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x64, x2apic/intr-remap: basic apic ops support
[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40
41 #include <asm/idle.h>
42 #include <asm/io.h>
43 #include <asm/smp.h>
44 #include <asm/desc.h>
45 #include <asm/proto.h>
46 #include <asm/acpi.h>
47 #include <asm/dma.h>
48 #include <asm/nmi.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
51
52 #include <mach_ipi.h>
53 #include <mach_apic.h>
54
55 struct irq_cfg {
56 cpumask_t domain;
57 cpumask_t old_domain;
58 unsigned move_cleanup_count;
59 u8 vector;
60 u8 move_in_progress : 1;
61 };
62
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
81 };
82
83 static int assign_irq_vector(int irq, cpumask_t mask);
84
85 int first_system_vector = 0xfe;
86
87 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
88
89 #define __apicdebuginit __init
90
91 int sis_apic_bug; /* not actually supported, dummy for compile */
92
93 static int no_timer_check;
94
95 static int disable_timer_pin_1 __initdata;
96
97 static bool mask_ioapic_irq_2 __initdata;
98
99 void __init force_mask_ioapic_irq_2(void)
100 {
101 mask_ioapic_irq_2 = true;
102 }
103
104 int timer_through_8259 __initdata;
105
106 /* Where if anywhere is the i8259 connect in external int mode */
107 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
108
109 static DEFINE_SPINLOCK(ioapic_lock);
110 DEFINE_SPINLOCK(vector_lock);
111
112 /*
113 * # of IRQ routing registers
114 */
115 int nr_ioapic_registers[MAX_IO_APICS];
116
117 /* I/O APIC RTE contents at the OS boot up */
118 struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
119
120 /* I/O APIC entries */
121 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
122 int nr_ioapics;
123
124 /* MP IRQ source entries */
125 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
126
127 /* # of MP IRQ source entries */
128 int mp_irq_entries;
129
130 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
131
132 /*
133 * Rough estimation of how many shared IRQs there are, can
134 * be changed anytime.
135 */
136 #define MAX_PLUS_SHARED_IRQS NR_IRQS
137 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
138
139 /*
140 * This is performance-critical, we want to do it O(1)
141 *
142 * the indexing order of this array favors 1:1 mappings
143 * between pins and IRQs.
144 */
145
146 static struct irq_pin_list {
147 short apic, pin, next;
148 } irq_2_pin[PIN_MAP_SIZE];
149
150 struct io_apic {
151 unsigned int index;
152 unsigned int unused[3];
153 unsigned int data;
154 };
155
156 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
157 {
158 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
159 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
160 }
161
162 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
163 {
164 struct io_apic __iomem *io_apic = io_apic_base(apic);
165 writel(reg, &io_apic->index);
166 return readl(&io_apic->data);
167 }
168
169 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
170 {
171 struct io_apic __iomem *io_apic = io_apic_base(apic);
172 writel(reg, &io_apic->index);
173 writel(value, &io_apic->data);
174 }
175
176 /*
177 * Re-write a value: to be used for read-modify-write
178 * cycles where the read already set up the index register.
179 */
180 static inline void io_apic_modify(unsigned int apic, unsigned int value)
181 {
182 struct io_apic __iomem *io_apic = io_apic_base(apic);
183 writel(value, &io_apic->data);
184 }
185
186 static bool io_apic_level_ack_pending(unsigned int irq)
187 {
188 struct irq_pin_list *entry;
189 unsigned long flags;
190
191 spin_lock_irqsave(&ioapic_lock, flags);
192 entry = irq_2_pin + irq;
193 for (;;) {
194 unsigned int reg;
195 int pin;
196
197 pin = entry->pin;
198 if (pin == -1)
199 break;
200 reg = io_apic_read(entry->apic, 0x10 + pin*2);
201 /* Is the remote IRR bit set? */
202 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
203 spin_unlock_irqrestore(&ioapic_lock, flags);
204 return true;
205 }
206 if (!entry->next)
207 break;
208 entry = irq_2_pin + entry->next;
209 }
210 spin_unlock_irqrestore(&ioapic_lock, flags);
211
212 return false;
213 }
214
215 /*
216 * Synchronize the IO-APIC and the CPU by doing
217 * a dummy read from the IO-APIC
218 */
219 static inline void io_apic_sync(unsigned int apic)
220 {
221 struct io_apic __iomem *io_apic = io_apic_base(apic);
222 readl(&io_apic->data);
223 }
224
225 #define __DO_ACTION(R, ACTION, FINAL) \
226 \
227 { \
228 int pin; \
229 struct irq_pin_list *entry = irq_2_pin + irq; \
230 \
231 BUG_ON(irq >= NR_IRQS); \
232 for (;;) { \
233 unsigned int reg; \
234 pin = entry->pin; \
235 if (pin == -1) \
236 break; \
237 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
238 reg ACTION; \
239 io_apic_modify(entry->apic, reg); \
240 FINAL; \
241 if (!entry->next) \
242 break; \
243 entry = irq_2_pin + entry->next; \
244 } \
245 }
246
247 union entry_union {
248 struct { u32 w1, w2; };
249 struct IO_APIC_route_entry entry;
250 };
251
252 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
253 {
254 union entry_union eu;
255 unsigned long flags;
256 spin_lock_irqsave(&ioapic_lock, flags);
257 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
258 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
259 spin_unlock_irqrestore(&ioapic_lock, flags);
260 return eu.entry;
261 }
262
263 /*
264 * When we write a new IO APIC routing entry, we need to write the high
265 * word first! If the mask bit in the low word is clear, we will enable
266 * the interrupt, and we need to make sure the entry is fully populated
267 * before that happens.
268 */
269 static void
270 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
271 {
272 union entry_union eu;
273 eu.entry = e;
274 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
275 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
276 }
277
278 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
279 {
280 unsigned long flags;
281 spin_lock_irqsave(&ioapic_lock, flags);
282 __ioapic_write_entry(apic, pin, e);
283 spin_unlock_irqrestore(&ioapic_lock, flags);
284 }
285
286 /*
287 * When we mask an IO APIC routing entry, we need to write the low
288 * word first, in order to set the mask bit before we change the
289 * high bits!
290 */
291 static void ioapic_mask_entry(int apic, int pin)
292 {
293 unsigned long flags;
294 union entry_union eu = { .entry.mask = 1 };
295
296 spin_lock_irqsave(&ioapic_lock, flags);
297 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
298 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
299 spin_unlock_irqrestore(&ioapic_lock, flags);
300 }
301
302 #ifdef CONFIG_SMP
303 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
304 {
305 int apic, pin;
306 struct irq_pin_list *entry = irq_2_pin + irq;
307
308 BUG_ON(irq >= NR_IRQS);
309 for (;;) {
310 unsigned int reg;
311 apic = entry->apic;
312 pin = entry->pin;
313 if (pin == -1)
314 break;
315 io_apic_write(apic, 0x11 + pin*2, dest);
316 reg = io_apic_read(apic, 0x10 + pin*2);
317 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
318 reg |= vector;
319 io_apic_modify(apic, reg);
320 if (!entry->next)
321 break;
322 entry = irq_2_pin + entry->next;
323 }
324 }
325
326 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
327 {
328 struct irq_cfg *cfg = irq_cfg + irq;
329 unsigned long flags;
330 unsigned int dest;
331 cpumask_t tmp;
332
333 cpus_and(tmp, mask, cpu_online_map);
334 if (cpus_empty(tmp))
335 return;
336
337 if (assign_irq_vector(irq, mask))
338 return;
339
340 cpus_and(tmp, cfg->domain, mask);
341 dest = cpu_mask_to_apicid(tmp);
342
343 /*
344 * Only the high 8 bits are valid.
345 */
346 dest = SET_APIC_LOGICAL_ID(dest);
347
348 spin_lock_irqsave(&ioapic_lock, flags);
349 __target_IO_APIC_irq(irq, dest, cfg->vector);
350 irq_desc[irq].affinity = mask;
351 spin_unlock_irqrestore(&ioapic_lock, flags);
352 }
353 #endif
354
355 /*
356 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
357 * shared ISA-space IRQs, so we have to support them. We are super
358 * fast in the common case, and fast for shared ISA-space IRQs.
359 */
360 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
361 {
362 static int first_free_entry = NR_IRQS;
363 struct irq_pin_list *entry = irq_2_pin + irq;
364
365 BUG_ON(irq >= NR_IRQS);
366 while (entry->next)
367 entry = irq_2_pin + entry->next;
368
369 if (entry->pin != -1) {
370 entry->next = first_free_entry;
371 entry = irq_2_pin + entry->next;
372 if (++first_free_entry >= PIN_MAP_SIZE)
373 panic("io_apic.c: ran out of irq_2_pin entries!");
374 }
375 entry->apic = apic;
376 entry->pin = pin;
377 }
378
379 /*
380 * Reroute an IRQ to a different pin.
381 */
382 static void __init replace_pin_at_irq(unsigned int irq,
383 int oldapic, int oldpin,
384 int newapic, int newpin)
385 {
386 struct irq_pin_list *entry = irq_2_pin + irq;
387
388 while (1) {
389 if (entry->apic == oldapic && entry->pin == oldpin) {
390 entry->apic = newapic;
391 entry->pin = newpin;
392 }
393 if (!entry->next)
394 break;
395 entry = irq_2_pin + entry->next;
396 }
397 }
398
399
400 #define DO_ACTION(name,R,ACTION, FINAL) \
401 \
402 static void name##_IO_APIC_irq (unsigned int irq) \
403 __DO_ACTION(R, ACTION, FINAL)
404
405 /* mask = 1 */
406 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
407
408 /* mask = 0 */
409 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
410
411 static void mask_IO_APIC_irq (unsigned int irq)
412 {
413 unsigned long flags;
414
415 spin_lock_irqsave(&ioapic_lock, flags);
416 __mask_IO_APIC_irq(irq);
417 spin_unlock_irqrestore(&ioapic_lock, flags);
418 }
419
420 static void unmask_IO_APIC_irq (unsigned int irq)
421 {
422 unsigned long flags;
423
424 spin_lock_irqsave(&ioapic_lock, flags);
425 __unmask_IO_APIC_irq(irq);
426 spin_unlock_irqrestore(&ioapic_lock, flags);
427 }
428
429 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
430 {
431 struct IO_APIC_route_entry entry;
432
433 /* Check delivery_mode to be sure we're not clearing an SMI pin */
434 entry = ioapic_read_entry(apic, pin);
435 if (entry.delivery_mode == dest_SMI)
436 return;
437 /*
438 * Disable it in the IO-APIC irq-routing table:
439 */
440 ioapic_mask_entry(apic, pin);
441 }
442
443 static void clear_IO_APIC (void)
444 {
445 int apic, pin;
446
447 for (apic = 0; apic < nr_ioapics; apic++)
448 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
449 clear_IO_APIC_pin(apic, pin);
450 }
451
452 /*
453 * Saves and masks all the unmasked IO-APIC RTE's
454 */
455 int save_mask_IO_APIC_setup(void)
456 {
457 union IO_APIC_reg_01 reg_01;
458 unsigned long flags;
459 int apic, pin;
460
461 /*
462 * The number of IO-APIC IRQ registers (== #pins):
463 */
464 for (apic = 0; apic < nr_ioapics; apic++) {
465 spin_lock_irqsave(&ioapic_lock, flags);
466 reg_01.raw = io_apic_read(apic, 1);
467 spin_unlock_irqrestore(&ioapic_lock, flags);
468 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
469 }
470
471 for (apic = 0; apic < nr_ioapics; apic++) {
472 early_ioapic_entries[apic] =
473 kzalloc(sizeof(struct IO_APIC_route_entry) *
474 nr_ioapic_registers[apic], GFP_KERNEL);
475 if (!early_ioapic_entries[apic])
476 return -ENOMEM;
477 }
478
479 for (apic = 0; apic < nr_ioapics; apic++)
480 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
481 struct IO_APIC_route_entry entry;
482
483 entry = early_ioapic_entries[apic][pin] =
484 ioapic_read_entry(apic, pin);
485 if (!entry.mask) {
486 entry.mask = 1;
487 ioapic_write_entry(apic, pin, entry);
488 }
489 }
490 return 0;
491 }
492
493 void restore_IO_APIC_setup(void)
494 {
495 int apic, pin;
496
497 for (apic = 0; apic < nr_ioapics; apic++)
498 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
499 ioapic_write_entry(apic, pin,
500 early_ioapic_entries[apic][pin]);
501 }
502
503 void reinit_intr_remapped_IO_APIC(int intr_remapping)
504 {
505 /*
506 * for now plain restore of previous settings.
507 * TBD: In the case of OS enabling interrupt-remapping,
508 * IO-APIC RTE's need to be setup to point to interrupt-remapping
509 * table entries. for now, do a plain restore, and wait for
510 * the setup_IO_APIC_irqs() to do proper initialization.
511 */
512 restore_IO_APIC_setup();
513 }
514
515 int skip_ioapic_setup;
516 int ioapic_force;
517
518 static int __init parse_noapic(char *str)
519 {
520 disable_ioapic_setup();
521 return 0;
522 }
523 early_param("noapic", parse_noapic);
524
525 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
526 static int __init disable_timer_pin_setup(char *arg)
527 {
528 disable_timer_pin_1 = 1;
529 return 1;
530 }
531 __setup("disable_timer_pin_1", disable_timer_pin_setup);
532
533
534 /*
535 * Find the IRQ entry number of a certain pin.
536 */
537 static int find_irq_entry(int apic, int pin, int type)
538 {
539 int i;
540
541 for (i = 0; i < mp_irq_entries; i++)
542 if (mp_irqs[i].mp_irqtype == type &&
543 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
544 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
545 mp_irqs[i].mp_dstirq == pin)
546 return i;
547
548 return -1;
549 }
550
551 /*
552 * Find the pin to which IRQ[irq] (ISA) is connected
553 */
554 static int __init find_isa_irq_pin(int irq, int type)
555 {
556 int i;
557
558 for (i = 0; i < mp_irq_entries; i++) {
559 int lbus = mp_irqs[i].mp_srcbus;
560
561 if (test_bit(lbus, mp_bus_not_pci) &&
562 (mp_irqs[i].mp_irqtype == type) &&
563 (mp_irqs[i].mp_srcbusirq == irq))
564
565 return mp_irqs[i].mp_dstirq;
566 }
567 return -1;
568 }
569
570 static int __init find_isa_irq_apic(int irq, int type)
571 {
572 int i;
573
574 for (i = 0; i < mp_irq_entries; i++) {
575 int lbus = mp_irqs[i].mp_srcbus;
576
577 if (test_bit(lbus, mp_bus_not_pci) &&
578 (mp_irqs[i].mp_irqtype == type) &&
579 (mp_irqs[i].mp_srcbusirq == irq))
580 break;
581 }
582 if (i < mp_irq_entries) {
583 int apic;
584 for(apic = 0; apic < nr_ioapics; apic++) {
585 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
586 return apic;
587 }
588 }
589
590 return -1;
591 }
592
593 /*
594 * Find a specific PCI IRQ entry.
595 * Not an __init, possibly needed by modules
596 */
597 static int pin_2_irq(int idx, int apic, int pin);
598
599 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
600 {
601 int apic, i, best_guess = -1;
602
603 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
604 bus, slot, pin);
605 if (test_bit(bus, mp_bus_not_pci)) {
606 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
607 return -1;
608 }
609 for (i = 0; i < mp_irq_entries; i++) {
610 int lbus = mp_irqs[i].mp_srcbus;
611
612 for (apic = 0; apic < nr_ioapics; apic++)
613 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
614 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
615 break;
616
617 if (!test_bit(lbus, mp_bus_not_pci) &&
618 !mp_irqs[i].mp_irqtype &&
619 (bus == lbus) &&
620 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
621 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
622
623 if (!(apic || IO_APIC_IRQ(irq)))
624 continue;
625
626 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
627 return irq;
628 /*
629 * Use the first all-but-pin matching entry as a
630 * best-guess fuzzy result for broken mptables.
631 */
632 if (best_guess < 0)
633 best_guess = irq;
634 }
635 }
636 BUG_ON(best_guess >= NR_IRQS);
637 return best_guess;
638 }
639
640 /* ISA interrupts are always polarity zero edge triggered,
641 * when listed as conforming in the MP table. */
642
643 #define default_ISA_trigger(idx) (0)
644 #define default_ISA_polarity(idx) (0)
645
646 /* PCI interrupts are always polarity one level triggered,
647 * when listed as conforming in the MP table. */
648
649 #define default_PCI_trigger(idx) (1)
650 #define default_PCI_polarity(idx) (1)
651
652 static int MPBIOS_polarity(int idx)
653 {
654 int bus = mp_irqs[idx].mp_srcbus;
655 int polarity;
656
657 /*
658 * Determine IRQ line polarity (high active or low active):
659 */
660 switch (mp_irqs[idx].mp_irqflag & 3)
661 {
662 case 0: /* conforms, ie. bus-type dependent polarity */
663 if (test_bit(bus, mp_bus_not_pci))
664 polarity = default_ISA_polarity(idx);
665 else
666 polarity = default_PCI_polarity(idx);
667 break;
668 case 1: /* high active */
669 {
670 polarity = 0;
671 break;
672 }
673 case 2: /* reserved */
674 {
675 printk(KERN_WARNING "broken BIOS!!\n");
676 polarity = 1;
677 break;
678 }
679 case 3: /* low active */
680 {
681 polarity = 1;
682 break;
683 }
684 default: /* invalid */
685 {
686 printk(KERN_WARNING "broken BIOS!!\n");
687 polarity = 1;
688 break;
689 }
690 }
691 return polarity;
692 }
693
694 static int MPBIOS_trigger(int idx)
695 {
696 int bus = mp_irqs[idx].mp_srcbus;
697 int trigger;
698
699 /*
700 * Determine IRQ trigger mode (edge or level sensitive):
701 */
702 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
703 {
704 case 0: /* conforms, ie. bus-type dependent */
705 if (test_bit(bus, mp_bus_not_pci))
706 trigger = default_ISA_trigger(idx);
707 else
708 trigger = default_PCI_trigger(idx);
709 break;
710 case 1: /* edge */
711 {
712 trigger = 0;
713 break;
714 }
715 case 2: /* reserved */
716 {
717 printk(KERN_WARNING "broken BIOS!!\n");
718 trigger = 1;
719 break;
720 }
721 case 3: /* level */
722 {
723 trigger = 1;
724 break;
725 }
726 default: /* invalid */
727 {
728 printk(KERN_WARNING "broken BIOS!!\n");
729 trigger = 0;
730 break;
731 }
732 }
733 return trigger;
734 }
735
736 static inline int irq_polarity(int idx)
737 {
738 return MPBIOS_polarity(idx);
739 }
740
741 static inline int irq_trigger(int idx)
742 {
743 return MPBIOS_trigger(idx);
744 }
745
746 static int pin_2_irq(int idx, int apic, int pin)
747 {
748 int irq, i;
749 int bus = mp_irqs[idx].mp_srcbus;
750
751 /*
752 * Debugging check, we are in big trouble if this message pops up!
753 */
754 if (mp_irqs[idx].mp_dstirq != pin)
755 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
756
757 if (test_bit(bus, mp_bus_not_pci)) {
758 irq = mp_irqs[idx].mp_srcbusirq;
759 } else {
760 /*
761 * PCI IRQs are mapped in order
762 */
763 i = irq = 0;
764 while (i < apic)
765 irq += nr_ioapic_registers[i++];
766 irq += pin;
767 }
768 BUG_ON(irq >= NR_IRQS);
769 return irq;
770 }
771
772 static int __assign_irq_vector(int irq, cpumask_t mask)
773 {
774 /*
775 * NOTE! The local APIC isn't very good at handling
776 * multiple interrupts at the same interrupt level.
777 * As the interrupt level is determined by taking the
778 * vector number and shifting that right by 4, we
779 * want to spread these out a bit so that they don't
780 * all fall in the same interrupt level.
781 *
782 * Also, we've got to be careful not to trash gate
783 * 0x80, because int 0x80 is hm, kind of importantish. ;)
784 */
785 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
786 unsigned int old_vector;
787 int cpu;
788 struct irq_cfg *cfg;
789
790 BUG_ON((unsigned)irq >= NR_IRQS);
791 cfg = &irq_cfg[irq];
792
793 /* Only try and allocate irqs on cpus that are present */
794 cpus_and(mask, mask, cpu_online_map);
795
796 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
797 return -EBUSY;
798
799 old_vector = cfg->vector;
800 if (old_vector) {
801 cpumask_t tmp;
802 cpus_and(tmp, cfg->domain, mask);
803 if (!cpus_empty(tmp))
804 return 0;
805 }
806
807 for_each_cpu_mask(cpu, mask) {
808 cpumask_t domain, new_mask;
809 int new_cpu;
810 int vector, offset;
811
812 domain = vector_allocation_domain(cpu);
813 cpus_and(new_mask, domain, cpu_online_map);
814
815 vector = current_vector;
816 offset = current_offset;
817 next:
818 vector += 8;
819 if (vector >= first_system_vector) {
820 /* If we run out of vectors on large boxen, must share them. */
821 offset = (offset + 1) % 8;
822 vector = FIRST_DEVICE_VECTOR + offset;
823 }
824 if (unlikely(current_vector == vector))
825 continue;
826 if (vector == IA32_SYSCALL_VECTOR)
827 goto next;
828 for_each_cpu_mask(new_cpu, new_mask)
829 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
830 goto next;
831 /* Found one! */
832 current_vector = vector;
833 current_offset = offset;
834 if (old_vector) {
835 cfg->move_in_progress = 1;
836 cfg->old_domain = cfg->domain;
837 }
838 for_each_cpu_mask(new_cpu, new_mask)
839 per_cpu(vector_irq, new_cpu)[vector] = irq;
840 cfg->vector = vector;
841 cfg->domain = domain;
842 return 0;
843 }
844 return -ENOSPC;
845 }
846
847 static int assign_irq_vector(int irq, cpumask_t mask)
848 {
849 int err;
850 unsigned long flags;
851
852 spin_lock_irqsave(&vector_lock, flags);
853 err = __assign_irq_vector(irq, mask);
854 spin_unlock_irqrestore(&vector_lock, flags);
855 return err;
856 }
857
858 static void __clear_irq_vector(int irq)
859 {
860 struct irq_cfg *cfg;
861 cpumask_t mask;
862 int cpu, vector;
863
864 BUG_ON((unsigned)irq >= NR_IRQS);
865 cfg = &irq_cfg[irq];
866 BUG_ON(!cfg->vector);
867
868 vector = cfg->vector;
869 cpus_and(mask, cfg->domain, cpu_online_map);
870 for_each_cpu_mask(cpu, mask)
871 per_cpu(vector_irq, cpu)[vector] = -1;
872
873 cfg->vector = 0;
874 cpus_clear(cfg->domain);
875 }
876
877 static void __setup_vector_irq(int cpu)
878 {
879 /* Initialize vector_irq on a new cpu */
880 /* This function must be called with vector_lock held */
881 int irq, vector;
882
883 /* Mark the inuse vectors */
884 for (irq = 0; irq < NR_IRQS; ++irq) {
885 if (!cpu_isset(cpu, irq_cfg[irq].domain))
886 continue;
887 vector = irq_cfg[irq].vector;
888 per_cpu(vector_irq, cpu)[vector] = irq;
889 }
890 /* Mark the free vectors */
891 for (vector = 0; vector < NR_VECTORS; ++vector) {
892 irq = per_cpu(vector_irq, cpu)[vector];
893 if (irq < 0)
894 continue;
895 if (!cpu_isset(cpu, irq_cfg[irq].domain))
896 per_cpu(vector_irq, cpu)[vector] = -1;
897 }
898 }
899
900 void setup_vector_irq(int cpu)
901 {
902 spin_lock(&vector_lock);
903 __setup_vector_irq(smp_processor_id());
904 spin_unlock(&vector_lock);
905 }
906
907
908 static struct irq_chip ioapic_chip;
909
910 static void ioapic_register_intr(int irq, unsigned long trigger)
911 {
912 if (trigger) {
913 irq_desc[irq].status |= IRQ_LEVEL;
914 set_irq_chip_and_handler_name(irq, &ioapic_chip,
915 handle_fasteoi_irq, "fasteoi");
916 } else {
917 irq_desc[irq].status &= ~IRQ_LEVEL;
918 set_irq_chip_and_handler_name(irq, &ioapic_chip,
919 handle_edge_irq, "edge");
920 }
921 }
922
923 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
924 int trigger, int polarity)
925 {
926 struct irq_cfg *cfg = irq_cfg + irq;
927 struct IO_APIC_route_entry entry;
928 cpumask_t mask;
929
930 if (!IO_APIC_IRQ(irq))
931 return;
932
933 mask = TARGET_CPUS;
934 if (assign_irq_vector(irq, mask))
935 return;
936
937 cpus_and(mask, cfg->domain, mask);
938
939 apic_printk(APIC_VERBOSE,KERN_DEBUG
940 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
941 "IRQ %d Mode:%i Active:%i)\n",
942 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
943 irq, trigger, polarity);
944
945 /*
946 * add it to the IO-APIC irq-routing table:
947 */
948 memset(&entry,0,sizeof(entry));
949
950 entry.delivery_mode = INT_DELIVERY_MODE;
951 entry.dest_mode = INT_DEST_MODE;
952 entry.dest = cpu_mask_to_apicid(mask);
953 entry.mask = 0; /* enable IRQ */
954 entry.trigger = trigger;
955 entry.polarity = polarity;
956 entry.vector = cfg->vector;
957
958 /* Mask level triggered irqs.
959 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
960 */
961 if (trigger)
962 entry.mask = 1;
963
964 ioapic_register_intr(irq, trigger);
965 if (irq < 16)
966 disable_8259A_irq(irq);
967
968 ioapic_write_entry(apic, pin, entry);
969 }
970
971 static void __init setup_IO_APIC_irqs(void)
972 {
973 int apic, pin, idx, irq, first_notcon = 1;
974
975 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
976
977 for (apic = 0; apic < nr_ioapics; apic++) {
978 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
979
980 idx = find_irq_entry(apic,pin,mp_INT);
981 if (idx == -1) {
982 if (first_notcon) {
983 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
984 first_notcon = 0;
985 } else
986 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
987 continue;
988 }
989 if (!first_notcon) {
990 apic_printk(APIC_VERBOSE, " not connected.\n");
991 first_notcon = 1;
992 }
993
994 irq = pin_2_irq(idx, apic, pin);
995 add_pin_to_irq(irq, apic, pin);
996
997 setup_IO_APIC_irq(apic, pin, irq,
998 irq_trigger(idx), irq_polarity(idx));
999 }
1000 }
1001
1002 if (!first_notcon)
1003 apic_printk(APIC_VERBOSE, " not connected.\n");
1004 }
1005
1006 /*
1007 * Set up the timer pin, possibly with the 8259A-master behind.
1008 */
1009 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1010 int vector)
1011 {
1012 struct IO_APIC_route_entry entry;
1013
1014 memset(&entry, 0, sizeof(entry));
1015
1016 /*
1017 * We use logical delivery to get the timer IRQ
1018 * to the first CPU.
1019 */
1020 entry.dest_mode = INT_DEST_MODE;
1021 entry.mask = 1; /* mask IRQ now */
1022 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1023 entry.delivery_mode = INT_DELIVERY_MODE;
1024 entry.polarity = 0;
1025 entry.trigger = 0;
1026 entry.vector = vector;
1027
1028 /*
1029 * The timer IRQ doesn't have to know that behind the
1030 * scene we may have a 8259A-master in AEOI mode ...
1031 */
1032 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1033
1034 /*
1035 * Add it to the IO-APIC irq-routing table:
1036 */
1037 ioapic_write_entry(apic, pin, entry);
1038 }
1039
1040 void __apicdebuginit print_IO_APIC(void)
1041 {
1042 int apic, i;
1043 union IO_APIC_reg_00 reg_00;
1044 union IO_APIC_reg_01 reg_01;
1045 union IO_APIC_reg_02 reg_02;
1046 unsigned long flags;
1047
1048 if (apic_verbosity == APIC_QUIET)
1049 return;
1050
1051 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1052 for (i = 0; i < nr_ioapics; i++)
1053 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1054 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1055
1056 /*
1057 * We are a bit conservative about what we expect. We have to
1058 * know about every hardware change ASAP.
1059 */
1060 printk(KERN_INFO "testing the IO APIC.......................\n");
1061
1062 for (apic = 0; apic < nr_ioapics; apic++) {
1063
1064 spin_lock_irqsave(&ioapic_lock, flags);
1065 reg_00.raw = io_apic_read(apic, 0);
1066 reg_01.raw = io_apic_read(apic, 1);
1067 if (reg_01.bits.version >= 0x10)
1068 reg_02.raw = io_apic_read(apic, 2);
1069 spin_unlock_irqrestore(&ioapic_lock, flags);
1070
1071 printk("\n");
1072 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1073 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1074 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1075
1076 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1077 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1078
1079 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1080 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1081
1082 if (reg_01.bits.version >= 0x10) {
1083 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1084 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1085 }
1086
1087 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1088
1089 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1090 " Stat Dmod Deli Vect: \n");
1091
1092 for (i = 0; i <= reg_01.bits.entries; i++) {
1093 struct IO_APIC_route_entry entry;
1094
1095 entry = ioapic_read_entry(apic, i);
1096
1097 printk(KERN_DEBUG " %02x %03X ",
1098 i,
1099 entry.dest
1100 );
1101
1102 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1103 entry.mask,
1104 entry.trigger,
1105 entry.irr,
1106 entry.polarity,
1107 entry.delivery_status,
1108 entry.dest_mode,
1109 entry.delivery_mode,
1110 entry.vector
1111 );
1112 }
1113 }
1114 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1115 for (i = 0; i < NR_IRQS; i++) {
1116 struct irq_pin_list *entry = irq_2_pin + i;
1117 if (entry->pin < 0)
1118 continue;
1119 printk(KERN_DEBUG "IRQ%d ", i);
1120 for (;;) {
1121 printk("-> %d:%d", entry->apic, entry->pin);
1122 if (!entry->next)
1123 break;
1124 entry = irq_2_pin + entry->next;
1125 }
1126 printk("\n");
1127 }
1128
1129 printk(KERN_INFO ".................................... done.\n");
1130
1131 return;
1132 }
1133
1134 #if 0
1135
1136 static __apicdebuginit void print_APIC_bitfield (int base)
1137 {
1138 unsigned int v;
1139 int i, j;
1140
1141 if (apic_verbosity == APIC_QUIET)
1142 return;
1143
1144 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1145 for (i = 0; i < 8; i++) {
1146 v = apic_read(base + i*0x10);
1147 for (j = 0; j < 32; j++) {
1148 if (v & (1<<j))
1149 printk("1");
1150 else
1151 printk("0");
1152 }
1153 printk("\n");
1154 }
1155 }
1156
1157 void __apicdebuginit print_local_APIC(void * dummy)
1158 {
1159 unsigned int v, ver, maxlvt;
1160 unsigned long icr;
1161
1162 if (apic_verbosity == APIC_QUIET)
1163 return;
1164
1165 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1166 smp_processor_id(), hard_smp_processor_id());
1167 v = apic_read(APIC_ID);
1168 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1169 v = apic_read(APIC_LVR);
1170 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1171 ver = GET_APIC_VERSION(v);
1172 maxlvt = lapic_get_maxlvt();
1173
1174 v = apic_read(APIC_TASKPRI);
1175 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1176
1177 v = apic_read(APIC_ARBPRI);
1178 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1179 v & APIC_ARBPRI_MASK);
1180 v = apic_read(APIC_PROCPRI);
1181 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1182
1183 v = apic_read(APIC_EOI);
1184 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1185 v = apic_read(APIC_RRR);
1186 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1187 v = apic_read(APIC_LDR);
1188 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1189 v = apic_read(APIC_DFR);
1190 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1191 v = apic_read(APIC_SPIV);
1192 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1193
1194 printk(KERN_DEBUG "... APIC ISR field:\n");
1195 print_APIC_bitfield(APIC_ISR);
1196 printk(KERN_DEBUG "... APIC TMR field:\n");
1197 print_APIC_bitfield(APIC_TMR);
1198 printk(KERN_DEBUG "... APIC IRR field:\n");
1199 print_APIC_bitfield(APIC_IRR);
1200
1201 v = apic_read(APIC_ESR);
1202 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1203
1204 icr = apic_icr_read();
1205 printk(KERN_DEBUG "... APIC ICR: %08x\n", icr);
1206 printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32);
1207
1208 v = apic_read(APIC_LVTT);
1209 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1210
1211 if (maxlvt > 3) { /* PC is LVT#4. */
1212 v = apic_read(APIC_LVTPC);
1213 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1214 }
1215 v = apic_read(APIC_LVT0);
1216 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1217 v = apic_read(APIC_LVT1);
1218 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1219
1220 if (maxlvt > 2) { /* ERR is LVT#3. */
1221 v = apic_read(APIC_LVTERR);
1222 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1223 }
1224
1225 v = apic_read(APIC_TMICT);
1226 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1227 v = apic_read(APIC_TMCCT);
1228 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1229 v = apic_read(APIC_TDCR);
1230 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1231 printk("\n");
1232 }
1233
1234 void print_all_local_APICs (void)
1235 {
1236 on_each_cpu(print_local_APIC, NULL, 1, 1);
1237 }
1238
1239 void __apicdebuginit print_PIC(void)
1240 {
1241 unsigned int v;
1242 unsigned long flags;
1243
1244 if (apic_verbosity == APIC_QUIET)
1245 return;
1246
1247 printk(KERN_DEBUG "\nprinting PIC contents\n");
1248
1249 spin_lock_irqsave(&i8259A_lock, flags);
1250
1251 v = inb(0xa1) << 8 | inb(0x21);
1252 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1253
1254 v = inb(0xa0) << 8 | inb(0x20);
1255 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1256
1257 outb(0x0b,0xa0);
1258 outb(0x0b,0x20);
1259 v = inb(0xa0) << 8 | inb(0x20);
1260 outb(0x0a,0xa0);
1261 outb(0x0a,0x20);
1262
1263 spin_unlock_irqrestore(&i8259A_lock, flags);
1264
1265 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1266
1267 v = inb(0x4d1) << 8 | inb(0x4d0);
1268 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1269 }
1270
1271 #endif /* 0 */
1272
1273 void __init enable_IO_APIC(void)
1274 {
1275 union IO_APIC_reg_01 reg_01;
1276 int i8259_apic, i8259_pin;
1277 int i, apic;
1278 unsigned long flags;
1279
1280 for (i = 0; i < PIN_MAP_SIZE; i++) {
1281 irq_2_pin[i].pin = -1;
1282 irq_2_pin[i].next = 0;
1283 }
1284
1285 /*
1286 * The number of IO-APIC IRQ registers (== #pins):
1287 */
1288 for (apic = 0; apic < nr_ioapics; apic++) {
1289 spin_lock_irqsave(&ioapic_lock, flags);
1290 reg_01.raw = io_apic_read(apic, 1);
1291 spin_unlock_irqrestore(&ioapic_lock, flags);
1292 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1293 }
1294 for(apic = 0; apic < nr_ioapics; apic++) {
1295 int pin;
1296 /* See if any of the pins is in ExtINT mode */
1297 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1298 struct IO_APIC_route_entry entry;
1299 entry = ioapic_read_entry(apic, pin);
1300
1301 /* If the interrupt line is enabled and in ExtInt mode
1302 * I have found the pin where the i8259 is connected.
1303 */
1304 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1305 ioapic_i8259.apic = apic;
1306 ioapic_i8259.pin = pin;
1307 goto found_i8259;
1308 }
1309 }
1310 }
1311 found_i8259:
1312 /* Look to see what if the MP table has reported the ExtINT */
1313 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1314 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1315 /* Trust the MP table if nothing is setup in the hardware */
1316 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1317 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1318 ioapic_i8259.pin = i8259_pin;
1319 ioapic_i8259.apic = i8259_apic;
1320 }
1321 /* Complain if the MP table and the hardware disagree */
1322 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1323 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1324 {
1325 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1326 }
1327
1328 /*
1329 * Do not trust the IO-APIC being empty at bootup
1330 */
1331 clear_IO_APIC();
1332 }
1333
1334 /*
1335 * Not an __init, needed by the reboot code
1336 */
1337 void disable_IO_APIC(void)
1338 {
1339 /*
1340 * Clear the IO-APIC before rebooting:
1341 */
1342 clear_IO_APIC();
1343
1344 /*
1345 * If the i8259 is routed through an IOAPIC
1346 * Put that IOAPIC in virtual wire mode
1347 * so legacy interrupts can be delivered.
1348 */
1349 if (ioapic_i8259.pin != -1) {
1350 struct IO_APIC_route_entry entry;
1351
1352 memset(&entry, 0, sizeof(entry));
1353 entry.mask = 0; /* Enabled */
1354 entry.trigger = 0; /* Edge */
1355 entry.irr = 0;
1356 entry.polarity = 0; /* High */
1357 entry.delivery_status = 0;
1358 entry.dest_mode = 0; /* Physical */
1359 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1360 entry.vector = 0;
1361 entry.dest = GET_APIC_ID(read_apic_id());
1362
1363 /*
1364 * Add it to the IO-APIC irq-routing table:
1365 */
1366 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1367 }
1368
1369 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1370 }
1371
1372 /*
1373 * There is a nasty bug in some older SMP boards, their mptable lies
1374 * about the timer IRQ. We do the following to work around the situation:
1375 *
1376 * - timer IRQ defaults to IO-APIC IRQ
1377 * - if this function detects that timer IRQs are defunct, then we fall
1378 * back to ISA timer IRQs
1379 */
1380 static int __init timer_irq_works(void)
1381 {
1382 unsigned long t1 = jiffies;
1383 unsigned long flags;
1384
1385 local_save_flags(flags);
1386 local_irq_enable();
1387 /* Let ten ticks pass... */
1388 mdelay((10 * 1000) / HZ);
1389 local_irq_restore(flags);
1390
1391 /*
1392 * Expect a few ticks at least, to be sure some possible
1393 * glue logic does not lock up after one or two first
1394 * ticks in a non-ExtINT mode. Also the local APIC
1395 * might have cached one ExtINT interrupt. Finally, at
1396 * least one tick may be lost due to delays.
1397 */
1398
1399 /* jiffies wrap? */
1400 if (time_after(jiffies, t1 + 4))
1401 return 1;
1402 return 0;
1403 }
1404
1405 /*
1406 * In the SMP+IOAPIC case it might happen that there are an unspecified
1407 * number of pending IRQ events unhandled. These cases are very rare,
1408 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1409 * better to do it this way as thus we do not have to be aware of
1410 * 'pending' interrupts in the IRQ path, except at this point.
1411 */
1412 /*
1413 * Edge triggered needs to resend any interrupt
1414 * that was delayed but this is now handled in the device
1415 * independent code.
1416 */
1417
1418 /*
1419 * Starting up a edge-triggered IO-APIC interrupt is
1420 * nasty - we need to make sure that we get the edge.
1421 * If it is already asserted for some reason, we need
1422 * return 1 to indicate that is was pending.
1423 *
1424 * This is not complete - we should be able to fake
1425 * an edge even if it isn't on the 8259A...
1426 */
1427
1428 static unsigned int startup_ioapic_irq(unsigned int irq)
1429 {
1430 int was_pending = 0;
1431 unsigned long flags;
1432
1433 spin_lock_irqsave(&ioapic_lock, flags);
1434 if (irq < 16) {
1435 disable_8259A_irq(irq);
1436 if (i8259A_irq_pending(irq))
1437 was_pending = 1;
1438 }
1439 __unmask_IO_APIC_irq(irq);
1440 spin_unlock_irqrestore(&ioapic_lock, flags);
1441
1442 return was_pending;
1443 }
1444
1445 static int ioapic_retrigger_irq(unsigned int irq)
1446 {
1447 struct irq_cfg *cfg = &irq_cfg[irq];
1448 cpumask_t mask;
1449 unsigned long flags;
1450
1451 spin_lock_irqsave(&vector_lock, flags);
1452 mask = cpumask_of_cpu(first_cpu(cfg->domain));
1453 send_IPI_mask(mask, cfg->vector);
1454 spin_unlock_irqrestore(&vector_lock, flags);
1455
1456 return 1;
1457 }
1458
1459 /*
1460 * Level and edge triggered IO-APIC interrupts need different handling,
1461 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1462 * handled with the level-triggered descriptor, but that one has slightly
1463 * more overhead. Level-triggered interrupts cannot be handled with the
1464 * edge-triggered handler, without risking IRQ storms and other ugly
1465 * races.
1466 */
1467
1468 #ifdef CONFIG_SMP
1469 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1470 {
1471 unsigned vector, me;
1472 ack_APIC_irq();
1473 exit_idle();
1474 irq_enter();
1475
1476 me = smp_processor_id();
1477 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1478 unsigned int irq;
1479 struct irq_desc *desc;
1480 struct irq_cfg *cfg;
1481 irq = __get_cpu_var(vector_irq)[vector];
1482 if (irq >= NR_IRQS)
1483 continue;
1484
1485 desc = irq_desc + irq;
1486 cfg = irq_cfg + irq;
1487 spin_lock(&desc->lock);
1488 if (!cfg->move_cleanup_count)
1489 goto unlock;
1490
1491 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1492 goto unlock;
1493
1494 __get_cpu_var(vector_irq)[vector] = -1;
1495 cfg->move_cleanup_count--;
1496 unlock:
1497 spin_unlock(&desc->lock);
1498 }
1499
1500 irq_exit();
1501 }
1502
1503 static void irq_complete_move(unsigned int irq)
1504 {
1505 struct irq_cfg *cfg = irq_cfg + irq;
1506 unsigned vector, me;
1507
1508 if (likely(!cfg->move_in_progress))
1509 return;
1510
1511 vector = ~get_irq_regs()->orig_ax;
1512 me = smp_processor_id();
1513 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1514 cpumask_t cleanup_mask;
1515
1516 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1517 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1518 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1519 cfg->move_in_progress = 0;
1520 }
1521 }
1522 #else
1523 static inline void irq_complete_move(unsigned int irq) {}
1524 #endif
1525
1526 static void ack_apic_edge(unsigned int irq)
1527 {
1528 irq_complete_move(irq);
1529 move_native_irq(irq);
1530 ack_APIC_irq();
1531 }
1532
1533 static void ack_apic_level(unsigned int irq)
1534 {
1535 int do_unmask_irq = 0;
1536
1537 irq_complete_move(irq);
1538 #ifdef CONFIG_GENERIC_PENDING_IRQ
1539 /* If we are moving the irq we need to mask it */
1540 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1541 do_unmask_irq = 1;
1542 mask_IO_APIC_irq(irq);
1543 }
1544 #endif
1545
1546 /*
1547 * We must acknowledge the irq before we move it or the acknowledge will
1548 * not propagate properly.
1549 */
1550 ack_APIC_irq();
1551
1552 /* Now we can move and renable the irq */
1553 if (unlikely(do_unmask_irq)) {
1554 /* Only migrate the irq if the ack has been received.
1555 *
1556 * On rare occasions the broadcast level triggered ack gets
1557 * delayed going to ioapics, and if we reprogram the
1558 * vector while Remote IRR is still set the irq will never
1559 * fire again.
1560 *
1561 * To prevent this scenario we read the Remote IRR bit
1562 * of the ioapic. This has two effects.
1563 * - On any sane system the read of the ioapic will
1564 * flush writes (and acks) going to the ioapic from
1565 * this cpu.
1566 * - We get to see if the ACK has actually been delivered.
1567 *
1568 * Based on failed experiments of reprogramming the
1569 * ioapic entry from outside of irq context starting
1570 * with masking the ioapic entry and then polling until
1571 * Remote IRR was clear before reprogramming the
1572 * ioapic I don't trust the Remote IRR bit to be
1573 * completey accurate.
1574 *
1575 * However there appears to be no other way to plug
1576 * this race, so if the Remote IRR bit is not
1577 * accurate and is causing problems then it is a hardware bug
1578 * and you can go talk to the chipset vendor about it.
1579 */
1580 if (!io_apic_level_ack_pending(irq))
1581 move_masked_irq(irq);
1582 unmask_IO_APIC_irq(irq);
1583 }
1584 }
1585
1586 static struct irq_chip ioapic_chip __read_mostly = {
1587 .name = "IO-APIC",
1588 .startup = startup_ioapic_irq,
1589 .mask = mask_IO_APIC_irq,
1590 .unmask = unmask_IO_APIC_irq,
1591 .ack = ack_apic_edge,
1592 .eoi = ack_apic_level,
1593 #ifdef CONFIG_SMP
1594 .set_affinity = set_ioapic_affinity_irq,
1595 #endif
1596 .retrigger = ioapic_retrigger_irq,
1597 };
1598
1599 static inline void init_IO_APIC_traps(void)
1600 {
1601 int irq;
1602
1603 /*
1604 * NOTE! The local APIC isn't very good at handling
1605 * multiple interrupts at the same interrupt level.
1606 * As the interrupt level is determined by taking the
1607 * vector number and shifting that right by 4, we
1608 * want to spread these out a bit so that they don't
1609 * all fall in the same interrupt level.
1610 *
1611 * Also, we've got to be careful not to trash gate
1612 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1613 */
1614 for (irq = 0; irq < NR_IRQS ; irq++) {
1615 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1616 /*
1617 * Hmm.. We don't have an entry for this,
1618 * so default to an old-fashioned 8259
1619 * interrupt if we can..
1620 */
1621 if (irq < 16)
1622 make_8259A_irq(irq);
1623 else
1624 /* Strange. Oh, well.. */
1625 irq_desc[irq].chip = &no_irq_chip;
1626 }
1627 }
1628 }
1629
1630 static void unmask_lapic_irq(unsigned int irq)
1631 {
1632 unsigned long v;
1633
1634 v = apic_read(APIC_LVT0);
1635 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1636 }
1637
1638 static void mask_lapic_irq(unsigned int irq)
1639 {
1640 unsigned long v;
1641
1642 v = apic_read(APIC_LVT0);
1643 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1644 }
1645
1646 static void ack_lapic_irq (unsigned int irq)
1647 {
1648 ack_APIC_irq();
1649 }
1650
1651 static struct irq_chip lapic_chip __read_mostly = {
1652 .name = "local-APIC",
1653 .mask = mask_lapic_irq,
1654 .unmask = unmask_lapic_irq,
1655 .ack = ack_lapic_irq,
1656 };
1657
1658 static void lapic_register_intr(int irq)
1659 {
1660 irq_desc[irq].status &= ~IRQ_LEVEL;
1661 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1662 "edge");
1663 }
1664
1665 static void __init setup_nmi(void)
1666 {
1667 /*
1668 * Dirty trick to enable the NMI watchdog ...
1669 * We put the 8259A master into AEOI mode and
1670 * unmask on all local APICs LVT0 as NMI.
1671 *
1672 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1673 * is from Maciej W. Rozycki - so we do not have to EOI from
1674 * the NMI handler or the timer interrupt.
1675 */
1676 printk(KERN_INFO "activating NMI Watchdog ...");
1677
1678 enable_NMI_through_LVT0();
1679
1680 printk(" done.\n");
1681 }
1682
1683 /*
1684 * This looks a bit hackish but it's about the only one way of sending
1685 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1686 * not support the ExtINT mode, unfortunately. We need to send these
1687 * cycles as some i82489DX-based boards have glue logic that keeps the
1688 * 8259A interrupt line asserted until INTA. --macro
1689 */
1690 static inline void __init unlock_ExtINT_logic(void)
1691 {
1692 int apic, pin, i;
1693 struct IO_APIC_route_entry entry0, entry1;
1694 unsigned char save_control, save_freq_select;
1695
1696 pin = find_isa_irq_pin(8, mp_INT);
1697 apic = find_isa_irq_apic(8, mp_INT);
1698 if (pin == -1)
1699 return;
1700
1701 entry0 = ioapic_read_entry(apic, pin);
1702
1703 clear_IO_APIC_pin(apic, pin);
1704
1705 memset(&entry1, 0, sizeof(entry1));
1706
1707 entry1.dest_mode = 0; /* physical delivery */
1708 entry1.mask = 0; /* unmask IRQ now */
1709 entry1.dest = hard_smp_processor_id();
1710 entry1.delivery_mode = dest_ExtINT;
1711 entry1.polarity = entry0.polarity;
1712 entry1.trigger = 0;
1713 entry1.vector = 0;
1714
1715 ioapic_write_entry(apic, pin, entry1);
1716
1717 save_control = CMOS_READ(RTC_CONTROL);
1718 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1719 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1720 RTC_FREQ_SELECT);
1721 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1722
1723 i = 100;
1724 while (i-- > 0) {
1725 mdelay(10);
1726 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1727 i -= 10;
1728 }
1729
1730 CMOS_WRITE(save_control, RTC_CONTROL);
1731 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1732 clear_IO_APIC_pin(apic, pin);
1733
1734 ioapic_write_entry(apic, pin, entry0);
1735 }
1736
1737 /*
1738 * This code may look a bit paranoid, but it's supposed to cooperate with
1739 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1740 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1741 * fanatically on his truly buggy board.
1742 *
1743 * FIXME: really need to revamp this for modern platforms only.
1744 */
1745 static inline void __init check_timer(void)
1746 {
1747 struct irq_cfg *cfg = irq_cfg + 0;
1748 int apic1, pin1, apic2, pin2;
1749 unsigned long flags;
1750 int no_pin1 = 0;
1751
1752 local_irq_save(flags);
1753
1754 /*
1755 * get/set the timer IRQ vector:
1756 */
1757 disable_8259A_irq(0);
1758 assign_irq_vector(0, TARGET_CPUS);
1759
1760 /*
1761 * As IRQ0 is to be enabled in the 8259A, the virtual
1762 * wire has to be disabled in the local APIC.
1763 */
1764 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1765 init_8259A(1);
1766
1767 pin1 = find_isa_irq_pin(0, mp_INT);
1768 apic1 = find_isa_irq_apic(0, mp_INT);
1769 pin2 = ioapic_i8259.pin;
1770 apic2 = ioapic_i8259.apic;
1771
1772 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1773 cfg->vector, apic1, pin1, apic2, pin2);
1774
1775 if (mask_ioapic_irq_2)
1776 mask_IO_APIC_irq(2);
1777
1778 /*
1779 * Some BIOS writers are clueless and report the ExtINTA
1780 * I/O APIC input from the cascaded 8259A as the timer
1781 * interrupt input. So just in case, if only one pin
1782 * was found above, try it both directly and through the
1783 * 8259A.
1784 */
1785 if (pin1 == -1) {
1786 pin1 = pin2;
1787 apic1 = apic2;
1788 no_pin1 = 1;
1789 } else if (pin2 == -1) {
1790 pin2 = pin1;
1791 apic2 = apic1;
1792 }
1793
1794 if (pin1 != -1) {
1795 /*
1796 * Ok, does IRQ0 through the IOAPIC work?
1797 */
1798 if (no_pin1) {
1799 add_pin_to_irq(0, apic1, pin1);
1800 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
1801 }
1802 unmask_IO_APIC_irq(0);
1803 if (!no_timer_check && timer_irq_works()) {
1804 if (nmi_watchdog == NMI_IO_APIC) {
1805 setup_nmi();
1806 enable_8259A_irq(0);
1807 }
1808 if (disable_timer_pin_1 > 0)
1809 clear_IO_APIC_pin(0, pin1);
1810 goto out;
1811 }
1812 clear_IO_APIC_pin(apic1, pin1);
1813 if (!no_pin1)
1814 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: "
1815 "8254 timer not connected to IO-APIC\n");
1816
1817 apic_printk(APIC_VERBOSE,KERN_INFO
1818 "...trying to set up timer (IRQ0) "
1819 "through the 8259A ... ");
1820 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1821 apic2, pin2);
1822 /*
1823 * legacy devices should be connected to IO APIC #0
1824 */
1825 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1826 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
1827 unmask_IO_APIC_irq(0);
1828 enable_8259A_irq(0);
1829 if (timer_irq_works()) {
1830 apic_printk(APIC_VERBOSE," works.\n");
1831 timer_through_8259 = 1;
1832 if (nmi_watchdog == NMI_IO_APIC) {
1833 disable_8259A_irq(0);
1834 setup_nmi();
1835 enable_8259A_irq(0);
1836 }
1837 goto out;
1838 }
1839 /*
1840 * Cleanup, just in case ...
1841 */
1842 disable_8259A_irq(0);
1843 clear_IO_APIC_pin(apic2, pin2);
1844 apic_printk(APIC_VERBOSE," failed.\n");
1845 }
1846
1847 if (nmi_watchdog == NMI_IO_APIC) {
1848 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1849 nmi_watchdog = NMI_NONE;
1850 }
1851
1852 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1853
1854 lapic_register_intr(0);
1855 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1856 enable_8259A_irq(0);
1857
1858 if (timer_irq_works()) {
1859 apic_printk(APIC_VERBOSE," works.\n");
1860 goto out;
1861 }
1862 disable_8259A_irq(0);
1863 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1864 apic_printk(APIC_VERBOSE," failed.\n");
1865
1866 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1867
1868 init_8259A(0);
1869 make_8259A_irq(0);
1870 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1871
1872 unlock_ExtINT_logic();
1873
1874 if (timer_irq_works()) {
1875 apic_printk(APIC_VERBOSE," works.\n");
1876 goto out;
1877 }
1878 apic_printk(APIC_VERBOSE," failed :(.\n");
1879 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1880 out:
1881 local_irq_restore(flags);
1882 }
1883
1884 static int __init notimercheck(char *s)
1885 {
1886 no_timer_check = 1;
1887 return 1;
1888 }
1889 __setup("no_timer_check", notimercheck);
1890
1891 /*
1892 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
1893 * to devices. However there may be an I/O APIC pin available for
1894 * this interrupt regardless. The pin may be left unconnected, but
1895 * typically it will be reused as an ExtINT cascade interrupt for
1896 * the master 8259A. In the MPS case such a pin will normally be
1897 * reported as an ExtINT interrupt in the MP table. With ACPI
1898 * there is no provision for ExtINT interrupts, and in the absence
1899 * of an override it would be treated as an ordinary ISA I/O APIC
1900 * interrupt, that is edge-triggered and unmasked by default. We
1901 * used to do this, but it caused problems on some systems because
1902 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
1903 * the same ExtINT cascade interrupt to drive the local APIC of the
1904 * bootstrap processor. Therefore we refrain from routing IRQ2 to
1905 * the I/O APIC in all cases now. No actual device should request
1906 * it anyway. --macro
1907 */
1908 #define PIC_IRQS (1<<2)
1909
1910 void __init setup_IO_APIC(void)
1911 {
1912
1913 /*
1914 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1915 */
1916
1917 io_apic_irqs = ~PIC_IRQS;
1918
1919 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1920
1921 sync_Arb_IDs();
1922 setup_IO_APIC_irqs();
1923 init_IO_APIC_traps();
1924 check_timer();
1925 if (!acpi_ioapic)
1926 print_IO_APIC();
1927 }
1928
1929 struct sysfs_ioapic_data {
1930 struct sys_device dev;
1931 struct IO_APIC_route_entry entry[0];
1932 };
1933 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1934
1935 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1936 {
1937 struct IO_APIC_route_entry *entry;
1938 struct sysfs_ioapic_data *data;
1939 int i;
1940
1941 data = container_of(dev, struct sysfs_ioapic_data, dev);
1942 entry = data->entry;
1943 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1944 *entry = ioapic_read_entry(dev->id, i);
1945
1946 return 0;
1947 }
1948
1949 static int ioapic_resume(struct sys_device *dev)
1950 {
1951 struct IO_APIC_route_entry *entry;
1952 struct sysfs_ioapic_data *data;
1953 unsigned long flags;
1954 union IO_APIC_reg_00 reg_00;
1955 int i;
1956
1957 data = container_of(dev, struct sysfs_ioapic_data, dev);
1958 entry = data->entry;
1959
1960 spin_lock_irqsave(&ioapic_lock, flags);
1961 reg_00.raw = io_apic_read(dev->id, 0);
1962 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
1963 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
1964 io_apic_write(dev->id, 0, reg_00.raw);
1965 }
1966 spin_unlock_irqrestore(&ioapic_lock, flags);
1967 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1968 ioapic_write_entry(dev->id, i, entry[i]);
1969
1970 return 0;
1971 }
1972
1973 static struct sysdev_class ioapic_sysdev_class = {
1974 .name = "ioapic",
1975 .suspend = ioapic_suspend,
1976 .resume = ioapic_resume,
1977 };
1978
1979 static int __init ioapic_init_sysfs(void)
1980 {
1981 struct sys_device * dev;
1982 int i, size, error;
1983
1984 error = sysdev_class_register(&ioapic_sysdev_class);
1985 if (error)
1986 return error;
1987
1988 for (i = 0; i < nr_ioapics; i++ ) {
1989 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1990 * sizeof(struct IO_APIC_route_entry);
1991 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1992 if (!mp_ioapic_data[i]) {
1993 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1994 continue;
1995 }
1996 dev = &mp_ioapic_data[i]->dev;
1997 dev->id = i;
1998 dev->cls = &ioapic_sysdev_class;
1999 error = sysdev_register(dev);
2000 if (error) {
2001 kfree(mp_ioapic_data[i]);
2002 mp_ioapic_data[i] = NULL;
2003 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2004 continue;
2005 }
2006 }
2007
2008 return 0;
2009 }
2010
2011 device_initcall(ioapic_init_sysfs);
2012
2013 /*
2014 * Dynamic irq allocate and deallocation
2015 */
2016 int create_irq(void)
2017 {
2018 /* Allocate an unused irq */
2019 int irq;
2020 int new;
2021 unsigned long flags;
2022
2023 irq = -ENOSPC;
2024 spin_lock_irqsave(&vector_lock, flags);
2025 for (new = (NR_IRQS - 1); new >= 0; new--) {
2026 if (platform_legacy_irq(new))
2027 continue;
2028 if (irq_cfg[new].vector != 0)
2029 continue;
2030 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
2031 irq = new;
2032 break;
2033 }
2034 spin_unlock_irqrestore(&vector_lock, flags);
2035
2036 if (irq >= 0) {
2037 dynamic_irq_init(irq);
2038 }
2039 return irq;
2040 }
2041
2042 void destroy_irq(unsigned int irq)
2043 {
2044 unsigned long flags;
2045
2046 dynamic_irq_cleanup(irq);
2047
2048 spin_lock_irqsave(&vector_lock, flags);
2049 __clear_irq_vector(irq);
2050 spin_unlock_irqrestore(&vector_lock, flags);
2051 }
2052
2053 /*
2054 * MSI message composition
2055 */
2056 #ifdef CONFIG_PCI_MSI
2057 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2058 {
2059 struct irq_cfg *cfg = irq_cfg + irq;
2060 int err;
2061 unsigned dest;
2062 cpumask_t tmp;
2063
2064 tmp = TARGET_CPUS;
2065 err = assign_irq_vector(irq, tmp);
2066 if (!err) {
2067 cpus_and(tmp, cfg->domain, tmp);
2068 dest = cpu_mask_to_apicid(tmp);
2069
2070 msg->address_hi = MSI_ADDR_BASE_HI;
2071 msg->address_lo =
2072 MSI_ADDR_BASE_LO |
2073 ((INT_DEST_MODE == 0) ?
2074 MSI_ADDR_DEST_MODE_PHYSICAL:
2075 MSI_ADDR_DEST_MODE_LOGICAL) |
2076 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2077 MSI_ADDR_REDIRECTION_CPU:
2078 MSI_ADDR_REDIRECTION_LOWPRI) |
2079 MSI_ADDR_DEST_ID(dest);
2080
2081 msg->data =
2082 MSI_DATA_TRIGGER_EDGE |
2083 MSI_DATA_LEVEL_ASSERT |
2084 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2085 MSI_DATA_DELIVERY_FIXED:
2086 MSI_DATA_DELIVERY_LOWPRI) |
2087 MSI_DATA_VECTOR(cfg->vector);
2088 }
2089 return err;
2090 }
2091
2092 #ifdef CONFIG_SMP
2093 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2094 {
2095 struct irq_cfg *cfg = irq_cfg + irq;
2096 struct msi_msg msg;
2097 unsigned int dest;
2098 cpumask_t tmp;
2099
2100 cpus_and(tmp, mask, cpu_online_map);
2101 if (cpus_empty(tmp))
2102 return;
2103
2104 if (assign_irq_vector(irq, mask))
2105 return;
2106
2107 cpus_and(tmp, cfg->domain, mask);
2108 dest = cpu_mask_to_apicid(tmp);
2109
2110 read_msi_msg(irq, &msg);
2111
2112 msg.data &= ~MSI_DATA_VECTOR_MASK;
2113 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2114 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2115 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2116
2117 write_msi_msg(irq, &msg);
2118 irq_desc[irq].affinity = mask;
2119 }
2120 #endif /* CONFIG_SMP */
2121
2122 /*
2123 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2124 * which implement the MSI or MSI-X Capability Structure.
2125 */
2126 static struct irq_chip msi_chip = {
2127 .name = "PCI-MSI",
2128 .unmask = unmask_msi_irq,
2129 .mask = mask_msi_irq,
2130 .ack = ack_apic_edge,
2131 #ifdef CONFIG_SMP
2132 .set_affinity = set_msi_irq_affinity,
2133 #endif
2134 .retrigger = ioapic_retrigger_irq,
2135 };
2136
2137 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2138 {
2139 struct msi_msg msg;
2140 int irq, ret;
2141 irq = create_irq();
2142 if (irq < 0)
2143 return irq;
2144
2145 ret = msi_compose_msg(dev, irq, &msg);
2146 if (ret < 0) {
2147 destroy_irq(irq);
2148 return ret;
2149 }
2150
2151 set_irq_msi(irq, desc);
2152 write_msi_msg(irq, &msg);
2153
2154 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2155
2156 return 0;
2157 }
2158
2159 void arch_teardown_msi_irq(unsigned int irq)
2160 {
2161 destroy_irq(irq);
2162 }
2163
2164 #ifdef CONFIG_DMAR
2165 #ifdef CONFIG_SMP
2166 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2167 {
2168 struct irq_cfg *cfg = irq_cfg + irq;
2169 struct msi_msg msg;
2170 unsigned int dest;
2171 cpumask_t tmp;
2172
2173 cpus_and(tmp, mask, cpu_online_map);
2174 if (cpus_empty(tmp))
2175 return;
2176
2177 if (assign_irq_vector(irq, mask))
2178 return;
2179
2180 cpus_and(tmp, cfg->domain, mask);
2181 dest = cpu_mask_to_apicid(tmp);
2182
2183 dmar_msi_read(irq, &msg);
2184
2185 msg.data &= ~MSI_DATA_VECTOR_MASK;
2186 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2187 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2188 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2189
2190 dmar_msi_write(irq, &msg);
2191 irq_desc[irq].affinity = mask;
2192 }
2193 #endif /* CONFIG_SMP */
2194
2195 struct irq_chip dmar_msi_type = {
2196 .name = "DMAR_MSI",
2197 .unmask = dmar_msi_unmask,
2198 .mask = dmar_msi_mask,
2199 .ack = ack_apic_edge,
2200 #ifdef CONFIG_SMP
2201 .set_affinity = dmar_msi_set_affinity,
2202 #endif
2203 .retrigger = ioapic_retrigger_irq,
2204 };
2205
2206 int arch_setup_dmar_msi(unsigned int irq)
2207 {
2208 int ret;
2209 struct msi_msg msg;
2210
2211 ret = msi_compose_msg(NULL, irq, &msg);
2212 if (ret < 0)
2213 return ret;
2214 dmar_msi_write(irq, &msg);
2215 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2216 "edge");
2217 return 0;
2218 }
2219 #endif
2220
2221 #endif /* CONFIG_PCI_MSI */
2222 /*
2223 * Hypertransport interrupt support
2224 */
2225 #ifdef CONFIG_HT_IRQ
2226
2227 #ifdef CONFIG_SMP
2228
2229 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2230 {
2231 struct ht_irq_msg msg;
2232 fetch_ht_irq_msg(irq, &msg);
2233
2234 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2235 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2236
2237 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2238 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2239
2240 write_ht_irq_msg(irq, &msg);
2241 }
2242
2243 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2244 {
2245 struct irq_cfg *cfg = irq_cfg + irq;
2246 unsigned int dest;
2247 cpumask_t tmp;
2248
2249 cpus_and(tmp, mask, cpu_online_map);
2250 if (cpus_empty(tmp))
2251 return;
2252
2253 if (assign_irq_vector(irq, mask))
2254 return;
2255
2256 cpus_and(tmp, cfg->domain, mask);
2257 dest = cpu_mask_to_apicid(tmp);
2258
2259 target_ht_irq(irq, dest, cfg->vector);
2260 irq_desc[irq].affinity = mask;
2261 }
2262 #endif
2263
2264 static struct irq_chip ht_irq_chip = {
2265 .name = "PCI-HT",
2266 .mask = mask_ht_irq,
2267 .unmask = unmask_ht_irq,
2268 .ack = ack_apic_edge,
2269 #ifdef CONFIG_SMP
2270 .set_affinity = set_ht_irq_affinity,
2271 #endif
2272 .retrigger = ioapic_retrigger_irq,
2273 };
2274
2275 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2276 {
2277 struct irq_cfg *cfg = irq_cfg + irq;
2278 int err;
2279 cpumask_t tmp;
2280
2281 tmp = TARGET_CPUS;
2282 err = assign_irq_vector(irq, tmp);
2283 if (!err) {
2284 struct ht_irq_msg msg;
2285 unsigned dest;
2286
2287 cpus_and(tmp, cfg->domain, tmp);
2288 dest = cpu_mask_to_apicid(tmp);
2289
2290 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2291
2292 msg.address_lo =
2293 HT_IRQ_LOW_BASE |
2294 HT_IRQ_LOW_DEST_ID(dest) |
2295 HT_IRQ_LOW_VECTOR(cfg->vector) |
2296 ((INT_DEST_MODE == 0) ?
2297 HT_IRQ_LOW_DM_PHYSICAL :
2298 HT_IRQ_LOW_DM_LOGICAL) |
2299 HT_IRQ_LOW_RQEOI_EDGE |
2300 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2301 HT_IRQ_LOW_MT_FIXED :
2302 HT_IRQ_LOW_MT_ARBITRATED) |
2303 HT_IRQ_LOW_IRQ_MASKED;
2304
2305 write_ht_irq_msg(irq, &msg);
2306
2307 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2308 handle_edge_irq, "edge");
2309 }
2310 return err;
2311 }
2312 #endif /* CONFIG_HT_IRQ */
2313
2314 /* --------------------------------------------------------------------------
2315 ACPI-based IOAPIC Configuration
2316 -------------------------------------------------------------------------- */
2317
2318 #ifdef CONFIG_ACPI
2319
2320 #define IO_APIC_MAX_ID 0xFE
2321
2322 int __init io_apic_get_redir_entries (int ioapic)
2323 {
2324 union IO_APIC_reg_01 reg_01;
2325 unsigned long flags;
2326
2327 spin_lock_irqsave(&ioapic_lock, flags);
2328 reg_01.raw = io_apic_read(ioapic, 1);
2329 spin_unlock_irqrestore(&ioapic_lock, flags);
2330
2331 return reg_01.bits.entries;
2332 }
2333
2334
2335 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2336 {
2337 if (!IO_APIC_IRQ(irq)) {
2338 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2339 ioapic);
2340 return -EINVAL;
2341 }
2342
2343 /*
2344 * IRQs < 16 are already in the irq_2_pin[] map
2345 */
2346 if (irq >= 16)
2347 add_pin_to_irq(irq, ioapic, pin);
2348
2349 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2350
2351 return 0;
2352 }
2353
2354
2355 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2356 {
2357 int i;
2358
2359 if (skip_ioapic_setup)
2360 return -1;
2361
2362 for (i = 0; i < mp_irq_entries; i++)
2363 if (mp_irqs[i].mp_irqtype == mp_INT &&
2364 mp_irqs[i].mp_srcbusirq == bus_irq)
2365 break;
2366 if (i >= mp_irq_entries)
2367 return -1;
2368
2369 *trigger = irq_trigger(i);
2370 *polarity = irq_polarity(i);
2371 return 0;
2372 }
2373
2374 #endif /* CONFIG_ACPI */
2375
2376 /*
2377 * This function currently is only a helper for the i386 smp boot process where
2378 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2379 * so mask in all cases should simply be TARGET_CPUS
2380 */
2381 #ifdef CONFIG_SMP
2382 void __init setup_ioapic_dest(void)
2383 {
2384 int pin, ioapic, irq, irq_entry;
2385
2386 if (skip_ioapic_setup == 1)
2387 return;
2388
2389 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2390 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2391 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2392 if (irq_entry == -1)
2393 continue;
2394 irq = pin_2_irq(irq_entry, ioapic, pin);
2395
2396 /* setup_IO_APIC_irqs could fail to get vector for some device
2397 * when you have too many devices, because at that time only boot
2398 * cpu is online.
2399 */
2400 if (!irq_cfg[irq].vector)
2401 setup_IO_APIC_irq(ioapic, pin, irq,
2402 irq_trigger(irq_entry),
2403 irq_polarity(irq_entry));
2404 else
2405 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2406 }
2407
2408 }
2409 }
2410 #endif
2411
2412 #define IOAPIC_RESOURCE_NAME_SIZE 11
2413
2414 static struct resource *ioapic_resources;
2415
2416 static struct resource * __init ioapic_setup_resources(void)
2417 {
2418 unsigned long n;
2419 struct resource *res;
2420 char *mem;
2421 int i;
2422
2423 if (nr_ioapics <= 0)
2424 return NULL;
2425
2426 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2427 n *= nr_ioapics;
2428
2429 mem = alloc_bootmem(n);
2430 res = (void *)mem;
2431
2432 if (mem != NULL) {
2433 mem += sizeof(struct resource) * nr_ioapics;
2434
2435 for (i = 0; i < nr_ioapics; i++) {
2436 res[i].name = mem;
2437 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2438 sprintf(mem, "IOAPIC %u", i);
2439 mem += IOAPIC_RESOURCE_NAME_SIZE;
2440 }
2441 }
2442
2443 ioapic_resources = res;
2444
2445 return res;
2446 }
2447
2448 void __init ioapic_init_mappings(void)
2449 {
2450 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2451 struct resource *ioapic_res;
2452 int i;
2453
2454 ioapic_res = ioapic_setup_resources();
2455 for (i = 0; i < nr_ioapics; i++) {
2456 if (smp_found_config) {
2457 ioapic_phys = mp_ioapics[i].mp_apicaddr;
2458 } else {
2459 ioapic_phys = (unsigned long)
2460 alloc_bootmem_pages(PAGE_SIZE);
2461 ioapic_phys = __pa(ioapic_phys);
2462 }
2463 set_fixmap_nocache(idx, ioapic_phys);
2464 apic_printk(APIC_VERBOSE,
2465 "mapped IOAPIC to %016lx (%016lx)\n",
2466 __fix_to_virt(idx), ioapic_phys);
2467 idx++;
2468
2469 if (ioapic_res != NULL) {
2470 ioapic_res->start = ioapic_phys;
2471 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2472 ioapic_res++;
2473 }
2474 }
2475 }
2476
2477 static int __init ioapic_insert_resources(void)
2478 {
2479 int i;
2480 struct resource *r = ioapic_resources;
2481
2482 if (!r) {
2483 printk(KERN_ERR
2484 "IO APIC resources could be not be allocated.\n");
2485 return -1;
2486 }
2487
2488 for (i = 0; i < nr_ioapics; i++) {
2489 insert_resource(&iomem_resource, r);
2490 r++;
2491 }
2492
2493 return 0;
2494 }
2495
2496 /* Insert the IO APIC resources after PCI initialization has occured to handle
2497 * IO APICS that are mapped in on a BAR in PCI space. */
2498 late_initcall(ioapic_insert_resources);
2499
Linux kernel - Deliverables
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