2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
40 #include <linux/dmar.h>
46 #include <asm/proto.h>
49 #include <asm/i8259.h>
51 #include <asm/msidef.h>
52 #include <asm/hypertransport.h>
53 #include <asm/irq_remapping.h>
56 #include <mach_apic.h>
58 #define __apicdebuginit(type) static type __init
63 unsigned move_cleanup_count
;
65 u8 move_in_progress
: 1;
68 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
69 static struct irq_cfg irq_cfg
[NR_IRQS
] __read_mostly
= {
70 [0] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
71 [1] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
72 [2] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
73 [3] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
74 [4] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
75 [5] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
76 [6] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
77 [7] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
78 [8] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
79 [9] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
80 [10] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
81 [11] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
82 [12] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
83 [13] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
84 [14] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
85 [15] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
88 static int assign_irq_vector(int irq
, cpumask_t mask
);
90 int first_system_vector
= 0xfe;
92 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
94 int sis_apic_bug
; /* not actually supported, dummy for compile */
96 static int no_timer_check
;
98 static int disable_timer_pin_1 __initdata
;
100 int timer_through_8259 __initdata
;
102 /* Where if anywhere is the i8259 connect in external int mode */
103 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
105 static DEFINE_SPINLOCK(ioapic_lock
);
106 static DEFINE_SPINLOCK(vector_lock
);
109 * # of IRQ routing registers
111 int nr_ioapic_registers
[MAX_IO_APICS
];
113 /* I/O APIC RTE contents at the OS boot up */
114 struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
116 /* I/O APIC entries */
117 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
120 /* MP IRQ source entries */
121 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
123 /* # of MP IRQ source entries */
126 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
129 * Rough estimation of how many shared IRQs there are, can
130 * be changed anytime.
132 #define MAX_PLUS_SHARED_IRQS NR_IRQS
133 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
136 * This is performance-critical, we want to do it O(1)
138 * the indexing order of this array favors 1:1 mappings
139 * between pins and IRQs.
142 static struct irq_pin_list
{
143 short apic
, pin
, next
;
144 } irq_2_pin
[PIN_MAP_SIZE
];
148 unsigned int unused
[3];
152 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
154 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
155 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
158 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
160 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
161 writel(reg
, &io_apic
->index
);
162 return readl(&io_apic
->data
);
165 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
167 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
168 writel(reg
, &io_apic
->index
);
169 writel(value
, &io_apic
->data
);
173 * Re-write a value: to be used for read-modify-write
174 * cycles where the read already set up the index register.
176 static inline void io_apic_modify(unsigned int apic
, unsigned int value
)
178 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
179 writel(value
, &io_apic
->data
);
182 static bool io_apic_level_ack_pending(unsigned int irq
)
184 struct irq_pin_list
*entry
;
187 spin_lock_irqsave(&ioapic_lock
, flags
);
188 entry
= irq_2_pin
+ irq
;
196 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
197 /* Is the remote IRR bit set? */
198 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
199 spin_unlock_irqrestore(&ioapic_lock
, flags
);
204 entry
= irq_2_pin
+ entry
->next
;
206 spin_unlock_irqrestore(&ioapic_lock
, flags
);
212 * Synchronize the IO-APIC and the CPU by doing
213 * a dummy read from the IO-APIC
215 static inline void io_apic_sync(unsigned int apic
)
217 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
218 readl(&io_apic
->data
);
221 #define __DO_ACTION(R, ACTION, FINAL) \
225 struct irq_pin_list *entry = irq_2_pin + irq; \
227 BUG_ON(irq >= NR_IRQS); \
233 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
235 io_apic_modify(entry->apic, reg); \
239 entry = irq_2_pin + entry->next; \
244 struct { u32 w1
, w2
; };
245 struct IO_APIC_route_entry entry
;
248 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
250 union entry_union eu
;
252 spin_lock_irqsave(&ioapic_lock
, flags
);
253 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
254 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
255 spin_unlock_irqrestore(&ioapic_lock
, flags
);
260 * When we write a new IO APIC routing entry, we need to write the high
261 * word first! If the mask bit in the low word is clear, we will enable
262 * the interrupt, and we need to make sure the entry is fully populated
263 * before that happens.
266 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
268 union entry_union eu
;
270 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
271 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
274 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
277 spin_lock_irqsave(&ioapic_lock
, flags
);
278 __ioapic_write_entry(apic
, pin
, e
);
279 spin_unlock_irqrestore(&ioapic_lock
, flags
);
283 * When we mask an IO APIC routing entry, we need to write the low
284 * word first, in order to set the mask bit before we change the
287 static void ioapic_mask_entry(int apic
, int pin
)
290 union entry_union eu
= { .entry
.mask
= 1 };
292 spin_lock_irqsave(&ioapic_lock
, flags
);
293 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
294 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
295 spin_unlock_irqrestore(&ioapic_lock
, flags
);
299 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
302 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
304 BUG_ON(irq
>= NR_IRQS
);
312 * With interrupt-remapping, destination information comes
313 * from interrupt-remapping table entry.
315 if (!irq_remapped(irq
))
316 io_apic_write(apic
, 0x11 + pin
*2, dest
);
317 reg
= io_apic_read(apic
, 0x10 + pin
*2);
318 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
320 io_apic_modify(apic
, reg
);
323 entry
= irq_2_pin
+ entry
->next
;
327 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
329 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
334 cpus_and(tmp
, mask
, cpu_online_map
);
338 if (assign_irq_vector(irq
, mask
))
341 cpus_and(tmp
, cfg
->domain
, mask
);
342 dest
= cpu_mask_to_apicid(tmp
);
345 * Only the high 8 bits are valid.
347 dest
= SET_APIC_LOGICAL_ID(dest
);
349 spin_lock_irqsave(&ioapic_lock
, flags
);
350 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
351 irq_desc
[irq
].affinity
= mask
;
352 spin_unlock_irqrestore(&ioapic_lock
, flags
);
357 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
358 * shared ISA-space IRQs, so we have to support them. We are super
359 * fast in the common case, and fast for shared ISA-space IRQs.
361 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
363 static int first_free_entry
= NR_IRQS
;
364 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
366 BUG_ON(irq
>= NR_IRQS
);
368 entry
= irq_2_pin
+ entry
->next
;
370 if (entry
->pin
!= -1) {
371 entry
->next
= first_free_entry
;
372 entry
= irq_2_pin
+ entry
->next
;
373 if (++first_free_entry
>= PIN_MAP_SIZE
)
374 panic("io_apic.c: ran out of irq_2_pin entries!");
381 * Reroute an IRQ to a different pin.
383 static void __init
replace_pin_at_irq(unsigned int irq
,
384 int oldapic
, int oldpin
,
385 int newapic
, int newpin
)
387 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
390 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
391 entry
->apic
= newapic
;
396 entry
= irq_2_pin
+ entry
->next
;
401 #define DO_ACTION(name,R,ACTION, FINAL) \
403 static void name##_IO_APIC_irq (unsigned int irq) \
404 __DO_ACTION(R, ACTION, FINAL)
407 DO_ACTION(__mask
, 0, |= IO_APIC_REDIR_MASKED
, io_apic_sync(entry
->apic
))
410 DO_ACTION(__unmask
, 0, &= ~IO_APIC_REDIR_MASKED
, )
412 static void mask_IO_APIC_irq (unsigned int irq
)
416 spin_lock_irqsave(&ioapic_lock
, flags
);
417 __mask_IO_APIC_irq(irq
);
418 spin_unlock_irqrestore(&ioapic_lock
, flags
);
421 static void unmask_IO_APIC_irq (unsigned int irq
)
425 spin_lock_irqsave(&ioapic_lock
, flags
);
426 __unmask_IO_APIC_irq(irq
);
427 spin_unlock_irqrestore(&ioapic_lock
, flags
);
430 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
432 struct IO_APIC_route_entry entry
;
434 /* Check delivery_mode to be sure we're not clearing an SMI pin */
435 entry
= ioapic_read_entry(apic
, pin
);
436 if (entry
.delivery_mode
== dest_SMI
)
439 * Disable it in the IO-APIC irq-routing table:
441 ioapic_mask_entry(apic
, pin
);
444 static void clear_IO_APIC (void)
448 for (apic
= 0; apic
< nr_ioapics
; apic
++)
449 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
450 clear_IO_APIC_pin(apic
, pin
);
454 * Saves and masks all the unmasked IO-APIC RTE's
456 int save_mask_IO_APIC_setup(void)
458 union IO_APIC_reg_01 reg_01
;
463 * The number of IO-APIC IRQ registers (== #pins):
465 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
466 spin_lock_irqsave(&ioapic_lock
, flags
);
467 reg_01
.raw
= io_apic_read(apic
, 1);
468 spin_unlock_irqrestore(&ioapic_lock
, flags
);
469 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
472 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
473 early_ioapic_entries
[apic
] =
474 kzalloc(sizeof(struct IO_APIC_route_entry
) *
475 nr_ioapic_registers
[apic
], GFP_KERNEL
);
476 if (!early_ioapic_entries
[apic
])
480 for (apic
= 0; apic
< nr_ioapics
; apic
++)
481 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
482 struct IO_APIC_route_entry entry
;
484 entry
= early_ioapic_entries
[apic
][pin
] =
485 ioapic_read_entry(apic
, pin
);
488 ioapic_write_entry(apic
, pin
, entry
);
494 void restore_IO_APIC_setup(void)
498 for (apic
= 0; apic
< nr_ioapics
; apic
++)
499 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
500 ioapic_write_entry(apic
, pin
,
501 early_ioapic_entries
[apic
][pin
]);
504 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
507 * for now plain restore of previous settings.
508 * TBD: In the case of OS enabling interrupt-remapping,
509 * IO-APIC RTE's need to be setup to point to interrupt-remapping
510 * table entries. for now, do a plain restore, and wait for
511 * the setup_IO_APIC_irqs() to do proper initialization.
513 restore_IO_APIC_setup();
516 int skip_ioapic_setup
;
519 static int __init
parse_noapic(char *str
)
521 disable_ioapic_setup();
524 early_param("noapic", parse_noapic
);
526 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
527 static int __init
disable_timer_pin_setup(char *arg
)
529 disable_timer_pin_1
= 1;
532 __setup("disable_timer_pin_1", disable_timer_pin_setup
);
536 * Find the IRQ entry number of a certain pin.
538 static int find_irq_entry(int apic
, int pin
, int type
)
542 for (i
= 0; i
< mp_irq_entries
; i
++)
543 if (mp_irqs
[i
].mp_irqtype
== type
&&
544 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
545 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
546 mp_irqs
[i
].mp_dstirq
== pin
)
553 * Find the pin to which IRQ[irq] (ISA) is connected
555 static int __init
find_isa_irq_pin(int irq
, int type
)
559 for (i
= 0; i
< mp_irq_entries
; i
++) {
560 int lbus
= mp_irqs
[i
].mp_srcbus
;
562 if (test_bit(lbus
, mp_bus_not_pci
) &&
563 (mp_irqs
[i
].mp_irqtype
== type
) &&
564 (mp_irqs
[i
].mp_srcbusirq
== irq
))
566 return mp_irqs
[i
].mp_dstirq
;
571 static int __init
find_isa_irq_apic(int irq
, int type
)
575 for (i
= 0; i
< mp_irq_entries
; i
++) {
576 int lbus
= mp_irqs
[i
].mp_srcbus
;
578 if (test_bit(lbus
, mp_bus_not_pci
) &&
579 (mp_irqs
[i
].mp_irqtype
== type
) &&
580 (mp_irqs
[i
].mp_srcbusirq
== irq
))
583 if (i
< mp_irq_entries
) {
585 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
586 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
595 * Find a specific PCI IRQ entry.
596 * Not an __init, possibly needed by modules
598 static int pin_2_irq(int idx
, int apic
, int pin
);
600 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
602 int apic
, i
, best_guess
= -1;
604 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
606 if (test_bit(bus
, mp_bus_not_pci
)) {
607 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
610 for (i
= 0; i
< mp_irq_entries
; i
++) {
611 int lbus
= mp_irqs
[i
].mp_srcbus
;
613 for (apic
= 0; apic
< nr_ioapics
; apic
++)
614 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
615 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
618 if (!test_bit(lbus
, mp_bus_not_pci
) &&
619 !mp_irqs
[i
].mp_irqtype
&&
621 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
622 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
624 if (!(apic
|| IO_APIC_IRQ(irq
)))
627 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
630 * Use the first all-but-pin matching entry as a
631 * best-guess fuzzy result for broken mptables.
637 BUG_ON(best_guess
>= NR_IRQS
);
641 /* ISA interrupts are always polarity zero edge triggered,
642 * when listed as conforming in the MP table. */
644 #define default_ISA_trigger(idx) (0)
645 #define default_ISA_polarity(idx) (0)
647 /* PCI interrupts are always polarity one level triggered,
648 * when listed as conforming in the MP table. */
650 #define default_PCI_trigger(idx) (1)
651 #define default_PCI_polarity(idx) (1)
653 static int MPBIOS_polarity(int idx
)
655 int bus
= mp_irqs
[idx
].mp_srcbus
;
659 * Determine IRQ line polarity (high active or low active):
661 switch (mp_irqs
[idx
].mp_irqflag
& 3)
663 case 0: /* conforms, ie. bus-type dependent polarity */
664 if (test_bit(bus
, mp_bus_not_pci
))
665 polarity
= default_ISA_polarity(idx
);
667 polarity
= default_PCI_polarity(idx
);
669 case 1: /* high active */
674 case 2: /* reserved */
676 printk(KERN_WARNING
"broken BIOS!!\n");
680 case 3: /* low active */
685 default: /* invalid */
687 printk(KERN_WARNING
"broken BIOS!!\n");
695 static int MPBIOS_trigger(int idx
)
697 int bus
= mp_irqs
[idx
].mp_srcbus
;
701 * Determine IRQ trigger mode (edge or level sensitive):
703 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
705 case 0: /* conforms, ie. bus-type dependent */
706 if (test_bit(bus
, mp_bus_not_pci
))
707 trigger
= default_ISA_trigger(idx
);
709 trigger
= default_PCI_trigger(idx
);
716 case 2: /* reserved */
718 printk(KERN_WARNING
"broken BIOS!!\n");
727 default: /* invalid */
729 printk(KERN_WARNING
"broken BIOS!!\n");
737 static inline int irq_polarity(int idx
)
739 return MPBIOS_polarity(idx
);
742 static inline int irq_trigger(int idx
)
744 return MPBIOS_trigger(idx
);
747 static int pin_2_irq(int idx
, int apic
, int pin
)
750 int bus
= mp_irqs
[idx
].mp_srcbus
;
753 * Debugging check, we are in big trouble if this message pops up!
755 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
756 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
758 if (test_bit(bus
, mp_bus_not_pci
)) {
759 irq
= mp_irqs
[idx
].mp_srcbusirq
;
762 * PCI IRQs are mapped in order
766 irq
+= nr_ioapic_registers
[i
++];
769 BUG_ON(irq
>= NR_IRQS
);
773 void lock_vector_lock(void)
775 /* Used to the online set of cpus does not change
776 * during assign_irq_vector.
778 spin_lock(&vector_lock
);
781 void unlock_vector_lock(void)
783 spin_unlock(&vector_lock
);
786 static int __assign_irq_vector(int irq
, cpumask_t mask
)
789 * NOTE! The local APIC isn't very good at handling
790 * multiple interrupts at the same interrupt level.
791 * As the interrupt level is determined by taking the
792 * vector number and shifting that right by 4, we
793 * want to spread these out a bit so that they don't
794 * all fall in the same interrupt level.
796 * Also, we've got to be careful not to trash gate
797 * 0x80, because int 0x80 is hm, kind of importantish. ;)
799 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
800 unsigned int old_vector
;
804 BUG_ON((unsigned)irq
>= NR_IRQS
);
807 /* Only try and allocate irqs on cpus that are present */
808 cpus_and(mask
, mask
, cpu_online_map
);
810 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
813 old_vector
= cfg
->vector
;
816 cpus_and(tmp
, cfg
->domain
, mask
);
817 if (!cpus_empty(tmp
))
821 for_each_cpu_mask_nr(cpu
, mask
) {
822 cpumask_t domain
, new_mask
;
826 domain
= vector_allocation_domain(cpu
);
827 cpus_and(new_mask
, domain
, cpu_online_map
);
829 vector
= current_vector
;
830 offset
= current_offset
;
833 if (vector
>= first_system_vector
) {
834 /* If we run out of vectors on large boxen, must share them. */
835 offset
= (offset
+ 1) % 8;
836 vector
= FIRST_DEVICE_VECTOR
+ offset
;
838 if (unlikely(current_vector
== vector
))
840 if (vector
== IA32_SYSCALL_VECTOR
)
842 for_each_cpu_mask_nr(new_cpu
, new_mask
)
843 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
846 current_vector
= vector
;
847 current_offset
= offset
;
849 cfg
->move_in_progress
= 1;
850 cfg
->old_domain
= cfg
->domain
;
852 for_each_cpu_mask_nr(new_cpu
, new_mask
)
853 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
854 cfg
->vector
= vector
;
855 cfg
->domain
= domain
;
861 static int assign_irq_vector(int irq
, cpumask_t mask
)
866 spin_lock_irqsave(&vector_lock
, flags
);
867 err
= __assign_irq_vector(irq
, mask
);
868 spin_unlock_irqrestore(&vector_lock
, flags
);
872 static void __clear_irq_vector(int irq
)
878 BUG_ON((unsigned)irq
>= NR_IRQS
);
880 BUG_ON(!cfg
->vector
);
882 vector
= cfg
->vector
;
883 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
884 for_each_cpu_mask_nr(cpu
, mask
)
885 per_cpu(vector_irq
, cpu
)[vector
] = -1;
888 cpus_clear(cfg
->domain
);
891 void __setup_vector_irq(int cpu
)
893 /* Initialize vector_irq on a new cpu */
894 /* This function must be called with vector_lock held */
897 /* Mark the inuse vectors */
898 for (irq
= 0; irq
< NR_IRQS
; ++irq
) {
899 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
901 vector
= irq_cfg
[irq
].vector
;
902 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
904 /* Mark the free vectors */
905 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
906 irq
= per_cpu(vector_irq
, cpu
)[vector
];
909 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
910 per_cpu(vector_irq
, cpu
)[vector
] = -1;
914 static struct irq_chip ioapic_chip
;
915 #ifdef CONFIG_INTR_REMAP
916 static struct irq_chip ir_ioapic_chip
;
919 static void ioapic_register_intr(int irq
, unsigned long trigger
)
922 irq_desc
[irq
].status
|= IRQ_LEVEL
;
924 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
926 #ifdef CONFIG_INTR_REMAP
927 if (irq_remapped(irq
)) {
928 irq_desc
[irq
].status
|= IRQ_MOVE_PCNTXT
;
930 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
934 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
935 handle_edge_irq
, "edge");
940 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
944 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
945 handle_edge_irq
, "edge");
948 static int setup_ioapic_entry(int apic
, int irq
,
949 struct IO_APIC_route_entry
*entry
,
950 unsigned int destination
, int trigger
,
951 int polarity
, int vector
)
954 * add it to the IO-APIC irq-routing table:
956 memset(entry
,0,sizeof(*entry
));
958 #ifdef CONFIG_INTR_REMAP
959 if (intr_remapping_enabled
) {
960 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
962 struct IR_IO_APIC_route_entry
*ir_entry
=
963 (struct IR_IO_APIC_route_entry
*) entry
;
967 panic("No mapping iommu for ioapic %d\n", apic
);
969 index
= alloc_irte(iommu
, irq
, 1);
971 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
973 memset(&irte
, 0, sizeof(irte
));
976 irte
.dst_mode
= INT_DEST_MODE
;
977 irte
.trigger_mode
= trigger
;
978 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
979 irte
.vector
= vector
;
980 irte
.dest_id
= IRTE_DEST(destination
);
982 modify_irte(irq
, &irte
);
984 ir_entry
->index2
= (index
>> 15) & 0x1;
986 ir_entry
->format
= 1;
987 ir_entry
->index
= (index
& 0x7fff);
991 entry
->delivery_mode
= INT_DELIVERY_MODE
;
992 entry
->dest_mode
= INT_DEST_MODE
;
993 entry
->dest
= destination
;
996 entry
->mask
= 0; /* enable IRQ */
997 entry
->trigger
= trigger
;
998 entry
->polarity
= polarity
;
999 entry
->vector
= vector
;
1001 /* Mask level triggered irqs.
1002 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1009 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
1010 int trigger
, int polarity
)
1012 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1013 struct IO_APIC_route_entry entry
;
1016 if (!IO_APIC_IRQ(irq
))
1020 if (assign_irq_vector(irq
, mask
))
1023 cpus_and(mask
, cfg
->domain
, mask
);
1025 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1026 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1027 "IRQ %d Mode:%i Active:%i)\n",
1028 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1029 irq
, trigger
, polarity
);
1032 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1033 cpu_mask_to_apicid(mask
), trigger
, polarity
,
1035 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1036 mp_ioapics
[apic
].mp_apicid
, pin
);
1037 __clear_irq_vector(irq
);
1041 ioapic_register_intr(irq
, trigger
);
1043 disable_8259A_irq(irq
);
1045 ioapic_write_entry(apic
, pin
, entry
);
1048 static void __init
setup_IO_APIC_irqs(void)
1050 int apic
, pin
, idx
, irq
, first_notcon
= 1;
1052 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1054 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1055 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1057 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1060 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1063 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1066 if (!first_notcon
) {
1067 apic_printk(APIC_VERBOSE
, " not connected.\n");
1071 irq
= pin_2_irq(idx
, apic
, pin
);
1072 add_pin_to_irq(irq
, apic
, pin
);
1074 setup_IO_APIC_irq(apic
, pin
, irq
,
1075 irq_trigger(idx
), irq_polarity(idx
));
1080 apic_printk(APIC_VERBOSE
, " not connected.\n");
1084 * Set up the timer pin, possibly with the 8259A-master behind.
1086 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1089 struct IO_APIC_route_entry entry
;
1091 if (intr_remapping_enabled
)
1094 memset(&entry
, 0, sizeof(entry
));
1097 * We use logical delivery to get the timer IRQ
1100 entry
.dest_mode
= INT_DEST_MODE
;
1101 entry
.mask
= 1; /* mask IRQ now */
1102 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1103 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1106 entry
.vector
= vector
;
1109 * The timer IRQ doesn't have to know that behind the
1110 * scene we may have a 8259A-master in AEOI mode ...
1112 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1115 * Add it to the IO-APIC irq-routing table:
1117 ioapic_write_entry(apic
, pin
, entry
);
1121 __apicdebuginit(void) print_IO_APIC(void)
1124 union IO_APIC_reg_00 reg_00
;
1125 union IO_APIC_reg_01 reg_01
;
1126 union IO_APIC_reg_02 reg_02
;
1127 unsigned long flags
;
1129 if (apic_verbosity
== APIC_QUIET
)
1132 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1133 for (i
= 0; i
< nr_ioapics
; i
++)
1134 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1135 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1138 * We are a bit conservative about what we expect. We have to
1139 * know about every hardware change ASAP.
1141 printk(KERN_INFO
"testing the IO APIC.......................\n");
1143 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1145 spin_lock_irqsave(&ioapic_lock
, flags
);
1146 reg_00
.raw
= io_apic_read(apic
, 0);
1147 reg_01
.raw
= io_apic_read(apic
, 1);
1148 if (reg_01
.bits
.version
>= 0x10)
1149 reg_02
.raw
= io_apic_read(apic
, 2);
1150 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1153 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1154 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1155 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1157 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1158 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1160 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1161 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1163 if (reg_01
.bits
.version
>= 0x10) {
1164 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1165 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1168 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1170 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1171 " Stat Dmod Deli Vect: \n");
1173 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1174 struct IO_APIC_route_entry entry
;
1176 entry
= ioapic_read_entry(apic
, i
);
1178 printk(KERN_DEBUG
" %02x %03X ",
1183 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1188 entry
.delivery_status
,
1190 entry
.delivery_mode
,
1195 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1196 for (i
= 0; i
< NR_IRQS
; i
++) {
1197 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1200 printk(KERN_DEBUG
"IRQ%d ", i
);
1202 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1205 entry
= irq_2_pin
+ entry
->next
;
1210 printk(KERN_INFO
".................................... done.\n");
1215 __apicdebuginit(void) print_APIC_bitfield(int base
)
1220 if (apic_verbosity
== APIC_QUIET
)
1223 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1224 for (i
= 0; i
< 8; i
++) {
1225 v
= apic_read(base
+ i
*0x10);
1226 for (j
= 0; j
< 32; j
++) {
1236 __apicdebuginit(void) print_local_APIC(void *dummy
)
1238 unsigned int v
, ver
, maxlvt
;
1241 if (apic_verbosity
== APIC_QUIET
)
1244 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1245 smp_processor_id(), hard_smp_processor_id());
1246 v
= apic_read(APIC_ID
);
1247 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1248 v
= apic_read(APIC_LVR
);
1249 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1250 ver
= GET_APIC_VERSION(v
);
1251 maxlvt
= lapic_get_maxlvt();
1253 v
= apic_read(APIC_TASKPRI
);
1254 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1256 v
= apic_read(APIC_ARBPRI
);
1257 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1258 v
& APIC_ARBPRI_MASK
);
1259 v
= apic_read(APIC_PROCPRI
);
1260 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1262 v
= apic_read(APIC_EOI
);
1263 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1264 v
= apic_read(APIC_RRR
);
1265 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1266 v
= apic_read(APIC_LDR
);
1267 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1268 v
= apic_read(APIC_DFR
);
1269 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1270 v
= apic_read(APIC_SPIV
);
1271 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1273 printk(KERN_DEBUG
"... APIC ISR field:\n");
1274 print_APIC_bitfield(APIC_ISR
);
1275 printk(KERN_DEBUG
"... APIC TMR field:\n");
1276 print_APIC_bitfield(APIC_TMR
);
1277 printk(KERN_DEBUG
"... APIC IRR field:\n");
1278 print_APIC_bitfield(APIC_IRR
);
1280 v
= apic_read(APIC_ESR
);
1281 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1283 icr
= apic_icr_read();
1284 printk(KERN_DEBUG
"... APIC ICR: %08x\n", icr
);
1285 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", icr
>> 32);
1287 v
= apic_read(APIC_LVTT
);
1288 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1290 if (maxlvt
> 3) { /* PC is LVT#4. */
1291 v
= apic_read(APIC_LVTPC
);
1292 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1294 v
= apic_read(APIC_LVT0
);
1295 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1296 v
= apic_read(APIC_LVT1
);
1297 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1299 if (maxlvt
> 2) { /* ERR is LVT#3. */
1300 v
= apic_read(APIC_LVTERR
);
1301 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1304 v
= apic_read(APIC_TMICT
);
1305 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1306 v
= apic_read(APIC_TMCCT
);
1307 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1308 v
= apic_read(APIC_TDCR
);
1309 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1313 __apicdebuginit(void) print_all_local_APICs(void)
1315 on_each_cpu(print_local_APIC
, NULL
, 1);
1318 __apicdebuginit(void) print_PIC(void)
1321 unsigned long flags
;
1323 if (apic_verbosity
== APIC_QUIET
)
1326 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1328 spin_lock_irqsave(&i8259A_lock
, flags
);
1330 v
= inb(0xa1) << 8 | inb(0x21);
1331 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1333 v
= inb(0xa0) << 8 | inb(0x20);
1334 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1338 v
= inb(0xa0) << 8 | inb(0x20);
1342 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1344 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1346 v
= inb(0x4d1) << 8 | inb(0x4d0);
1347 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1350 __apicdebuginit(int) print_all_ICs(void)
1353 print_all_local_APICs();
1359 fs_initcall(print_all_ICs
);
1362 void __init
enable_IO_APIC(void)
1364 union IO_APIC_reg_01 reg_01
;
1365 int i8259_apic
, i8259_pin
;
1367 unsigned long flags
;
1369 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1370 irq_2_pin
[i
].pin
= -1;
1371 irq_2_pin
[i
].next
= 0;
1375 * The number of IO-APIC IRQ registers (== #pins):
1377 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1378 spin_lock_irqsave(&ioapic_lock
, flags
);
1379 reg_01
.raw
= io_apic_read(apic
, 1);
1380 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1381 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1383 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1385 /* See if any of the pins is in ExtINT mode */
1386 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1387 struct IO_APIC_route_entry entry
;
1388 entry
= ioapic_read_entry(apic
, pin
);
1390 /* If the interrupt line is enabled and in ExtInt mode
1391 * I have found the pin where the i8259 is connected.
1393 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1394 ioapic_i8259
.apic
= apic
;
1395 ioapic_i8259
.pin
= pin
;
1401 /* Look to see what if the MP table has reported the ExtINT */
1402 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1403 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1404 /* Trust the MP table if nothing is setup in the hardware */
1405 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1406 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1407 ioapic_i8259
.pin
= i8259_pin
;
1408 ioapic_i8259
.apic
= i8259_apic
;
1410 /* Complain if the MP table and the hardware disagree */
1411 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1412 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1414 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1418 * Do not trust the IO-APIC being empty at bootup
1424 * Not an __init, needed by the reboot code
1426 void disable_IO_APIC(void)
1429 * Clear the IO-APIC before rebooting:
1434 * If the i8259 is routed through an IOAPIC
1435 * Put that IOAPIC in virtual wire mode
1436 * so legacy interrupts can be delivered.
1438 if (ioapic_i8259
.pin
!= -1) {
1439 struct IO_APIC_route_entry entry
;
1441 memset(&entry
, 0, sizeof(entry
));
1442 entry
.mask
= 0; /* Enabled */
1443 entry
.trigger
= 0; /* Edge */
1445 entry
.polarity
= 0; /* High */
1446 entry
.delivery_status
= 0;
1447 entry
.dest_mode
= 0; /* Physical */
1448 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1450 entry
.dest
= read_apic_id();
1453 * Add it to the IO-APIC irq-routing table:
1455 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1458 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1462 * There is a nasty bug in some older SMP boards, their mptable lies
1463 * about the timer IRQ. We do the following to work around the situation:
1465 * - timer IRQ defaults to IO-APIC IRQ
1466 * - if this function detects that timer IRQs are defunct, then we fall
1467 * back to ISA timer IRQs
1469 static int __init
timer_irq_works(void)
1471 unsigned long t1
= jiffies
;
1472 unsigned long flags
;
1474 local_save_flags(flags
);
1476 /* Let ten ticks pass... */
1477 mdelay((10 * 1000) / HZ
);
1478 local_irq_restore(flags
);
1481 * Expect a few ticks at least, to be sure some possible
1482 * glue logic does not lock up after one or two first
1483 * ticks in a non-ExtINT mode. Also the local APIC
1484 * might have cached one ExtINT interrupt. Finally, at
1485 * least one tick may be lost due to delays.
1489 if (time_after(jiffies
, t1
+ 4))
1495 * In the SMP+IOAPIC case it might happen that there are an unspecified
1496 * number of pending IRQ events unhandled. These cases are very rare,
1497 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1498 * better to do it this way as thus we do not have to be aware of
1499 * 'pending' interrupts in the IRQ path, except at this point.
1502 * Edge triggered needs to resend any interrupt
1503 * that was delayed but this is now handled in the device
1508 * Starting up a edge-triggered IO-APIC interrupt is
1509 * nasty - we need to make sure that we get the edge.
1510 * If it is already asserted for some reason, we need
1511 * return 1 to indicate that is was pending.
1513 * This is not complete - we should be able to fake
1514 * an edge even if it isn't on the 8259A...
1517 static unsigned int startup_ioapic_irq(unsigned int irq
)
1519 int was_pending
= 0;
1520 unsigned long flags
;
1522 spin_lock_irqsave(&ioapic_lock
, flags
);
1524 disable_8259A_irq(irq
);
1525 if (i8259A_irq_pending(irq
))
1528 __unmask_IO_APIC_irq(irq
);
1529 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1534 static int ioapic_retrigger_irq(unsigned int irq
)
1536 struct irq_cfg
*cfg
= &irq_cfg
[irq
];
1537 unsigned long flags
;
1539 spin_lock_irqsave(&vector_lock
, flags
);
1540 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg
->domain
)), cfg
->vector
);
1541 spin_unlock_irqrestore(&vector_lock
, flags
);
1547 * Level and edge triggered IO-APIC interrupts need different handling,
1548 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1549 * handled with the level-triggered descriptor, but that one has slightly
1550 * more overhead. Level-triggered interrupts cannot be handled with the
1551 * edge-triggered handler, without risking IRQ storms and other ugly
1557 #ifdef CONFIG_INTR_REMAP
1558 static void ir_irq_migration(struct work_struct
*work
);
1560 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
1563 * Migrate the IO-APIC irq in the presence of intr-remapping.
1565 * For edge triggered, irq migration is a simple atomic update(of vector
1566 * and cpu destination) of IRTE and flush the hardware cache.
1568 * For level triggered, we need to modify the io-apic RTE aswell with the update
1569 * vector information, along with modifying IRTE with vector and destination.
1570 * So irq migration for level triggered is little bit more complex compared to
1571 * edge triggered migration. But the good news is, we use the same algorithm
1572 * for level triggered migration as we have today, only difference being,
1573 * we now initiate the irq migration from process context instead of the
1574 * interrupt context.
1576 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1577 * suppression) to the IO-APIC, level triggered irq migration will also be
1578 * as simple as edge triggered migration and we can do the irq migration
1579 * with a simple atomic update to IO-APIC RTE.
1581 static void migrate_ioapic_irq(int irq
, cpumask_t mask
)
1583 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1584 struct irq_desc
*desc
= irq_desc
+ irq
;
1585 cpumask_t tmp
, cleanup_mask
;
1587 int modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
1589 unsigned long flags
;
1591 cpus_and(tmp
, mask
, cpu_online_map
);
1592 if (cpus_empty(tmp
))
1595 if (get_irte(irq
, &irte
))
1598 if (assign_irq_vector(irq
, mask
))
1601 cpus_and(tmp
, cfg
->domain
, mask
);
1602 dest
= cpu_mask_to_apicid(tmp
);
1604 if (modify_ioapic_rte
) {
1605 spin_lock_irqsave(&ioapic_lock
, flags
);
1606 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
1607 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1610 irte
.vector
= cfg
->vector
;
1611 irte
.dest_id
= IRTE_DEST(dest
);
1614 * Modified the IRTE and flushes the Interrupt entry cache.
1616 modify_irte(irq
, &irte
);
1618 if (cfg
->move_in_progress
) {
1619 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1620 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1621 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1622 cfg
->move_in_progress
= 0;
1625 irq_desc
[irq
].affinity
= mask
;
1628 static int migrate_irq_remapped_level(int irq
)
1632 mask_IO_APIC_irq(irq
);
1634 if (io_apic_level_ack_pending(irq
)) {
1636 * Interrupt in progress. Migrating irq now will change the
1637 * vector information in the IO-APIC RTE and that will confuse
1638 * the EOI broadcast performed by cpu.
1639 * So, delay the irq migration to the next instance.
1641 schedule_delayed_work(&ir_migration_work
, 1);
1645 /* everthing is clear. we have right of way */
1646 migrate_ioapic_irq(irq
, irq_desc
[irq
].pending_mask
);
1649 irq_desc
[irq
].status
&= ~IRQ_MOVE_PENDING
;
1650 cpus_clear(irq_desc
[irq
].pending_mask
);
1653 unmask_IO_APIC_irq(irq
);
1657 static void ir_irq_migration(struct work_struct
*work
)
1661 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1662 struct irq_desc
*desc
= irq_desc
+ irq
;
1663 if (desc
->status
& IRQ_MOVE_PENDING
) {
1664 unsigned long flags
;
1666 spin_lock_irqsave(&desc
->lock
, flags
);
1667 if (!desc
->chip
->set_affinity
||
1668 !(desc
->status
& IRQ_MOVE_PENDING
)) {
1669 desc
->status
&= ~IRQ_MOVE_PENDING
;
1670 spin_unlock_irqrestore(&desc
->lock
, flags
);
1674 desc
->chip
->set_affinity(irq
,
1675 irq_desc
[irq
].pending_mask
);
1676 spin_unlock_irqrestore(&desc
->lock
, flags
);
1682 * Migrates the IRQ destination in the process context.
1684 static void set_ir_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
1686 if (irq_desc
[irq
].status
& IRQ_LEVEL
) {
1687 irq_desc
[irq
].status
|= IRQ_MOVE_PENDING
;
1688 irq_desc
[irq
].pending_mask
= mask
;
1689 migrate_irq_remapped_level(irq
);
1693 migrate_ioapic_irq(irq
, mask
);
1697 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
1699 unsigned vector
, me
;
1704 me
= smp_processor_id();
1705 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
1707 struct irq_desc
*desc
;
1708 struct irq_cfg
*cfg
;
1709 irq
= __get_cpu_var(vector_irq
)[vector
];
1713 desc
= irq_desc
+ irq
;
1714 cfg
= irq_cfg
+ irq
;
1715 spin_lock(&desc
->lock
);
1716 if (!cfg
->move_cleanup_count
)
1719 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
1722 __get_cpu_var(vector_irq
)[vector
] = -1;
1723 cfg
->move_cleanup_count
--;
1725 spin_unlock(&desc
->lock
);
1731 static void irq_complete_move(unsigned int irq
)
1733 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1734 unsigned vector
, me
;
1736 if (likely(!cfg
->move_in_progress
))
1739 vector
= ~get_irq_regs()->orig_ax
;
1740 me
= smp_processor_id();
1741 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
1742 cpumask_t cleanup_mask
;
1744 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1745 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1746 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1747 cfg
->move_in_progress
= 0;
1751 static inline void irq_complete_move(unsigned int irq
) {}
1753 #ifdef CONFIG_INTR_REMAP
1754 static void ack_x2apic_level(unsigned int irq
)
1759 static void ack_x2apic_edge(unsigned int irq
)
1765 static void ack_apic_edge(unsigned int irq
)
1767 irq_complete_move(irq
);
1768 move_native_irq(irq
);
1772 static void ack_apic_level(unsigned int irq
)
1774 int do_unmask_irq
= 0;
1776 irq_complete_move(irq
);
1777 #ifdef CONFIG_GENERIC_PENDING_IRQ
1778 /* If we are moving the irq we need to mask it */
1779 if (unlikely(irq_desc
[irq
].status
& IRQ_MOVE_PENDING
)) {
1781 mask_IO_APIC_irq(irq
);
1786 * We must acknowledge the irq before we move it or the acknowledge will
1787 * not propagate properly.
1791 /* Now we can move and renable the irq */
1792 if (unlikely(do_unmask_irq
)) {
1793 /* Only migrate the irq if the ack has been received.
1795 * On rare occasions the broadcast level triggered ack gets
1796 * delayed going to ioapics, and if we reprogram the
1797 * vector while Remote IRR is still set the irq will never
1800 * To prevent this scenario we read the Remote IRR bit
1801 * of the ioapic. This has two effects.
1802 * - On any sane system the read of the ioapic will
1803 * flush writes (and acks) going to the ioapic from
1805 * - We get to see if the ACK has actually been delivered.
1807 * Based on failed experiments of reprogramming the
1808 * ioapic entry from outside of irq context starting
1809 * with masking the ioapic entry and then polling until
1810 * Remote IRR was clear before reprogramming the
1811 * ioapic I don't trust the Remote IRR bit to be
1812 * completey accurate.
1814 * However there appears to be no other way to plug
1815 * this race, so if the Remote IRR bit is not
1816 * accurate and is causing problems then it is a hardware bug
1817 * and you can go talk to the chipset vendor about it.
1819 if (!io_apic_level_ack_pending(irq
))
1820 move_masked_irq(irq
);
1821 unmask_IO_APIC_irq(irq
);
1825 static struct irq_chip ioapic_chip __read_mostly
= {
1827 .startup
= startup_ioapic_irq
,
1828 .mask
= mask_IO_APIC_irq
,
1829 .unmask
= unmask_IO_APIC_irq
,
1830 .ack
= ack_apic_edge
,
1831 .eoi
= ack_apic_level
,
1833 .set_affinity
= set_ioapic_affinity_irq
,
1835 .retrigger
= ioapic_retrigger_irq
,
1838 #ifdef CONFIG_INTR_REMAP
1839 static struct irq_chip ir_ioapic_chip __read_mostly
= {
1840 .name
= "IR-IO-APIC",
1841 .startup
= startup_ioapic_irq
,
1842 .mask
= mask_IO_APIC_irq
,
1843 .unmask
= unmask_IO_APIC_irq
,
1844 .ack
= ack_x2apic_edge
,
1845 .eoi
= ack_x2apic_level
,
1847 .set_affinity
= set_ir_ioapic_affinity_irq
,
1849 .retrigger
= ioapic_retrigger_irq
,
1853 static inline void init_IO_APIC_traps(void)
1858 * NOTE! The local APIC isn't very good at handling
1859 * multiple interrupts at the same interrupt level.
1860 * As the interrupt level is determined by taking the
1861 * vector number and shifting that right by 4, we
1862 * want to spread these out a bit so that they don't
1863 * all fall in the same interrupt level.
1865 * Also, we've got to be careful not to trash gate
1866 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1868 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1869 if (IO_APIC_IRQ(irq
) && !irq_cfg
[irq
].vector
) {
1871 * Hmm.. We don't have an entry for this,
1872 * so default to an old-fashioned 8259
1873 * interrupt if we can..
1876 make_8259A_irq(irq
);
1878 /* Strange. Oh, well.. */
1879 irq_desc
[irq
].chip
= &no_irq_chip
;
1884 static void unmask_lapic_irq(unsigned int irq
)
1888 v
= apic_read(APIC_LVT0
);
1889 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
1892 static void mask_lapic_irq(unsigned int irq
)
1896 v
= apic_read(APIC_LVT0
);
1897 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1900 static void ack_lapic_irq (unsigned int irq
)
1905 static struct irq_chip lapic_chip __read_mostly
= {
1906 .name
= "local-APIC",
1907 .mask
= mask_lapic_irq
,
1908 .unmask
= unmask_lapic_irq
,
1909 .ack
= ack_lapic_irq
,
1912 static void lapic_register_intr(int irq
)
1914 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
1915 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
1919 static void __init
setup_nmi(void)
1922 * Dirty trick to enable the NMI watchdog ...
1923 * We put the 8259A master into AEOI mode and
1924 * unmask on all local APICs LVT0 as NMI.
1926 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1927 * is from Maciej W. Rozycki - so we do not have to EOI from
1928 * the NMI handler or the timer interrupt.
1930 printk(KERN_INFO
"activating NMI Watchdog ...");
1932 enable_NMI_through_LVT0();
1938 * This looks a bit hackish but it's about the only one way of sending
1939 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1940 * not support the ExtINT mode, unfortunately. We need to send these
1941 * cycles as some i82489DX-based boards have glue logic that keeps the
1942 * 8259A interrupt line asserted until INTA. --macro
1944 static inline void __init
unlock_ExtINT_logic(void)
1947 struct IO_APIC_route_entry entry0
, entry1
;
1948 unsigned char save_control
, save_freq_select
;
1950 pin
= find_isa_irq_pin(8, mp_INT
);
1951 apic
= find_isa_irq_apic(8, mp_INT
);
1955 entry0
= ioapic_read_entry(apic
, pin
);
1957 clear_IO_APIC_pin(apic
, pin
);
1959 memset(&entry1
, 0, sizeof(entry1
));
1961 entry1
.dest_mode
= 0; /* physical delivery */
1962 entry1
.mask
= 0; /* unmask IRQ now */
1963 entry1
.dest
= hard_smp_processor_id();
1964 entry1
.delivery_mode
= dest_ExtINT
;
1965 entry1
.polarity
= entry0
.polarity
;
1969 ioapic_write_entry(apic
, pin
, entry1
);
1971 save_control
= CMOS_READ(RTC_CONTROL
);
1972 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
1973 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
1975 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
1980 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
1984 CMOS_WRITE(save_control
, RTC_CONTROL
);
1985 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
1986 clear_IO_APIC_pin(apic
, pin
);
1988 ioapic_write_entry(apic
, pin
, entry0
);
1992 * This code may look a bit paranoid, but it's supposed to cooperate with
1993 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1994 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1995 * fanatically on his truly buggy board.
1997 * FIXME: really need to revamp this for modern platforms only.
1999 static inline void __init
check_timer(void)
2001 struct irq_cfg
*cfg
= irq_cfg
+ 0;
2002 int apic1
, pin1
, apic2
, pin2
;
2003 unsigned long flags
;
2006 local_irq_save(flags
);
2009 * get/set the timer IRQ vector:
2011 disable_8259A_irq(0);
2012 assign_irq_vector(0, TARGET_CPUS
);
2015 * As IRQ0 is to be enabled in the 8259A, the virtual
2016 * wire has to be disabled in the local APIC.
2018 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2021 pin1
= find_isa_irq_pin(0, mp_INT
);
2022 apic1
= find_isa_irq_apic(0, mp_INT
);
2023 pin2
= ioapic_i8259
.pin
;
2024 apic2
= ioapic_i8259
.apic
;
2026 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2027 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2028 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2031 * Some BIOS writers are clueless and report the ExtINTA
2032 * I/O APIC input from the cascaded 8259A as the timer
2033 * interrupt input. So just in case, if only one pin
2034 * was found above, try it both directly and through the
2038 if (intr_remapping_enabled
)
2039 panic("BIOS bug: timer not connected to IO-APIC");
2043 } else if (pin2
== -1) {
2050 * Ok, does IRQ0 through the IOAPIC work?
2053 add_pin_to_irq(0, apic1
, pin1
);
2054 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2056 unmask_IO_APIC_irq(0);
2057 if (!no_timer_check
&& timer_irq_works()) {
2058 if (nmi_watchdog
== NMI_IO_APIC
) {
2060 enable_8259A_irq(0);
2062 if (disable_timer_pin_1
> 0)
2063 clear_IO_APIC_pin(0, pin1
);
2066 if (intr_remapping_enabled
)
2067 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2068 clear_IO_APIC_pin(apic1
, pin1
);
2070 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2071 "8254 timer not connected to IO-APIC\n");
2073 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2074 "(IRQ0) through the 8259A ...\n");
2075 apic_printk(APIC_QUIET
, KERN_INFO
2076 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2078 * legacy devices should be connected to IO APIC #0
2080 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2081 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2082 unmask_IO_APIC_irq(0);
2083 enable_8259A_irq(0);
2084 if (timer_irq_works()) {
2085 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2086 timer_through_8259
= 1;
2087 if (nmi_watchdog
== NMI_IO_APIC
) {
2088 disable_8259A_irq(0);
2090 enable_8259A_irq(0);
2095 * Cleanup, just in case ...
2097 disable_8259A_irq(0);
2098 clear_IO_APIC_pin(apic2
, pin2
);
2099 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2102 if (nmi_watchdog
== NMI_IO_APIC
) {
2103 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2104 "through the IO-APIC - disabling NMI Watchdog!\n");
2105 nmi_watchdog
= NMI_NONE
;
2108 apic_printk(APIC_QUIET
, KERN_INFO
2109 "...trying to set up timer as Virtual Wire IRQ...\n");
2111 lapic_register_intr(0);
2112 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2113 enable_8259A_irq(0);
2115 if (timer_irq_works()) {
2116 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2119 disable_8259A_irq(0);
2120 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2121 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2123 apic_printk(APIC_QUIET
, KERN_INFO
2124 "...trying to set up timer as ExtINT IRQ...\n");
2128 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2130 unlock_ExtINT_logic();
2132 if (timer_irq_works()) {
2133 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2136 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2137 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2138 "report. Then try booting with the 'noapic' option.\n");
2140 local_irq_restore(flags
);
2143 static int __init
notimercheck(char *s
)
2148 __setup("no_timer_check", notimercheck
);
2151 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2152 * to devices. However there may be an I/O APIC pin available for
2153 * this interrupt regardless. The pin may be left unconnected, but
2154 * typically it will be reused as an ExtINT cascade interrupt for
2155 * the master 8259A. In the MPS case such a pin will normally be
2156 * reported as an ExtINT interrupt in the MP table. With ACPI
2157 * there is no provision for ExtINT interrupts, and in the absence
2158 * of an override it would be treated as an ordinary ISA I/O APIC
2159 * interrupt, that is edge-triggered and unmasked by default. We
2160 * used to do this, but it caused problems on some systems because
2161 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2162 * the same ExtINT cascade interrupt to drive the local APIC of the
2163 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2164 * the I/O APIC in all cases now. No actual device should request
2165 * it anyway. --macro
2167 #define PIC_IRQS (1<<2)
2169 void __init
setup_IO_APIC(void)
2173 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2176 io_apic_irqs
= ~PIC_IRQS
;
2178 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2181 setup_IO_APIC_irqs();
2182 init_IO_APIC_traps();
2186 struct sysfs_ioapic_data
{
2187 struct sys_device dev
;
2188 struct IO_APIC_route_entry entry
[0];
2190 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2192 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2194 struct IO_APIC_route_entry
*entry
;
2195 struct sysfs_ioapic_data
*data
;
2198 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2199 entry
= data
->entry
;
2200 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
2201 *entry
= ioapic_read_entry(dev
->id
, i
);
2206 static int ioapic_resume(struct sys_device
*dev
)
2208 struct IO_APIC_route_entry
*entry
;
2209 struct sysfs_ioapic_data
*data
;
2210 unsigned long flags
;
2211 union IO_APIC_reg_00 reg_00
;
2214 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2215 entry
= data
->entry
;
2217 spin_lock_irqsave(&ioapic_lock
, flags
);
2218 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2219 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2220 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2221 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2223 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2224 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2225 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2230 static struct sysdev_class ioapic_sysdev_class
= {
2232 .suspend
= ioapic_suspend
,
2233 .resume
= ioapic_resume
,
2236 static int __init
ioapic_init_sysfs(void)
2238 struct sys_device
* dev
;
2241 error
= sysdev_class_register(&ioapic_sysdev_class
);
2245 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2246 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2247 * sizeof(struct IO_APIC_route_entry
);
2248 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2249 if (!mp_ioapic_data
[i
]) {
2250 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2253 dev
= &mp_ioapic_data
[i
]->dev
;
2255 dev
->cls
= &ioapic_sysdev_class
;
2256 error
= sysdev_register(dev
);
2258 kfree(mp_ioapic_data
[i
]);
2259 mp_ioapic_data
[i
] = NULL
;
2260 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2268 device_initcall(ioapic_init_sysfs
);
2271 * Dynamic irq allocate and deallocation
2273 int create_irq(void)
2275 /* Allocate an unused irq */
2278 unsigned long flags
;
2281 spin_lock_irqsave(&vector_lock
, flags
);
2282 for (new = (NR_IRQS
- 1); new >= 0; new--) {
2283 if (platform_legacy_irq(new))
2285 if (irq_cfg
[new].vector
!= 0)
2287 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
2291 spin_unlock_irqrestore(&vector_lock
, flags
);
2294 dynamic_irq_init(irq
);
2299 void destroy_irq(unsigned int irq
)
2301 unsigned long flags
;
2303 dynamic_irq_cleanup(irq
);
2305 #ifdef CONFIG_INTR_REMAP
2308 spin_lock_irqsave(&vector_lock
, flags
);
2309 __clear_irq_vector(irq
);
2310 spin_unlock_irqrestore(&vector_lock
, flags
);
2314 * MSI message composition
2316 #ifdef CONFIG_PCI_MSI
2317 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2319 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2325 err
= assign_irq_vector(irq
, tmp
);
2329 cpus_and(tmp
, cfg
->domain
, tmp
);
2330 dest
= cpu_mask_to_apicid(tmp
);
2332 #ifdef CONFIG_INTR_REMAP
2333 if (irq_remapped(irq
)) {
2338 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
2339 BUG_ON(ir_index
== -1);
2341 memset (&irte
, 0, sizeof(irte
));
2344 irte
.dst_mode
= INT_DEST_MODE
;
2345 irte
.trigger_mode
= 0; /* edge */
2346 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
2347 irte
.vector
= cfg
->vector
;
2348 irte
.dest_id
= IRTE_DEST(dest
);
2350 modify_irte(irq
, &irte
);
2352 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2353 msg
->data
= sub_handle
;
2354 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
2356 MSI_ADDR_IR_INDEX1(ir_index
) |
2357 MSI_ADDR_IR_INDEX2(ir_index
);
2361 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2364 ((INT_DEST_MODE
== 0) ?
2365 MSI_ADDR_DEST_MODE_PHYSICAL
:
2366 MSI_ADDR_DEST_MODE_LOGICAL
) |
2367 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2368 MSI_ADDR_REDIRECTION_CPU
:
2369 MSI_ADDR_REDIRECTION_LOWPRI
) |
2370 MSI_ADDR_DEST_ID(dest
);
2373 MSI_DATA_TRIGGER_EDGE
|
2374 MSI_DATA_LEVEL_ASSERT
|
2375 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2376 MSI_DATA_DELIVERY_FIXED
:
2377 MSI_DATA_DELIVERY_LOWPRI
) |
2378 MSI_DATA_VECTOR(cfg
->vector
);
2384 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2386 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2391 cpus_and(tmp
, mask
, cpu_online_map
);
2392 if (cpus_empty(tmp
))
2395 if (assign_irq_vector(irq
, mask
))
2398 cpus_and(tmp
, cfg
->domain
, mask
);
2399 dest
= cpu_mask_to_apicid(tmp
);
2401 read_msi_msg(irq
, &msg
);
2403 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2404 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2405 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2406 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2408 write_msi_msg(irq
, &msg
);
2409 irq_desc
[irq
].affinity
= mask
;
2412 #ifdef CONFIG_INTR_REMAP
2414 * Migrate the MSI irq to another cpumask. This migration is
2415 * done in the process context using interrupt-remapping hardware.
2417 static void ir_set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2419 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2421 cpumask_t tmp
, cleanup_mask
;
2424 cpus_and(tmp
, mask
, cpu_online_map
);
2425 if (cpus_empty(tmp
))
2428 if (get_irte(irq
, &irte
))
2431 if (assign_irq_vector(irq
, mask
))
2434 cpus_and(tmp
, cfg
->domain
, mask
);
2435 dest
= cpu_mask_to_apicid(tmp
);
2437 irte
.vector
= cfg
->vector
;
2438 irte
.dest_id
= IRTE_DEST(dest
);
2441 * atomically update the IRTE with the new destination and vector.
2443 modify_irte(irq
, &irte
);
2446 * After this point, all the interrupts will start arriving
2447 * at the new destination. So, time to cleanup the previous
2448 * vector allocation.
2450 if (cfg
->move_in_progress
) {
2451 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2452 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2453 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2454 cfg
->move_in_progress
= 0;
2457 irq_desc
[irq
].affinity
= mask
;
2460 #endif /* CONFIG_SMP */
2463 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2464 * which implement the MSI or MSI-X Capability Structure.
2466 static struct irq_chip msi_chip
= {
2468 .unmask
= unmask_msi_irq
,
2469 .mask
= mask_msi_irq
,
2470 .ack
= ack_apic_edge
,
2472 .set_affinity
= set_msi_irq_affinity
,
2474 .retrigger
= ioapic_retrigger_irq
,
2477 #ifdef CONFIG_INTR_REMAP
2478 static struct irq_chip msi_ir_chip
= {
2479 .name
= "IR-PCI-MSI",
2480 .unmask
= unmask_msi_irq
,
2481 .mask
= mask_msi_irq
,
2482 .ack
= ack_x2apic_edge
,
2484 .set_affinity
= ir_set_msi_irq_affinity
,
2486 .retrigger
= ioapic_retrigger_irq
,
2490 * Map the PCI dev to the corresponding remapping hardware unit
2491 * and allocate 'nvec' consecutive interrupt-remapping table entries
2494 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
2496 struct intel_iommu
*iommu
;
2499 iommu
= map_dev_to_ir(dev
);
2502 "Unable to map PCI %s to iommu\n", pci_name(dev
));
2506 index
= alloc_irte(iommu
, irq
, nvec
);
2509 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
2517 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
, int irq
)
2522 ret
= msi_compose_msg(dev
, irq
, &msg
);
2526 set_irq_msi(irq
, desc
);
2527 write_msi_msg(irq
, &msg
);
2529 #ifdef CONFIG_INTR_REMAP
2530 if (irq_remapped(irq
)) {
2531 struct irq_desc
*desc
= irq_desc
+ irq
;
2533 * irq migration in process context
2535 desc
->status
|= IRQ_MOVE_PCNTXT
;
2536 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
2539 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
2544 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2552 #ifdef CONFIG_INTR_REMAP
2553 if (!intr_remapping_enabled
)
2556 ret
= msi_alloc_irte(dev
, irq
, 1);
2561 ret
= setup_msi_irq(dev
, desc
, irq
);
2568 #ifdef CONFIG_INTR_REMAP
2575 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
2577 int irq
, ret
, sub_handle
;
2578 struct msi_desc
*desc
;
2579 #ifdef CONFIG_INTR_REMAP
2580 struct intel_iommu
*iommu
= 0;
2585 list_for_each_entry(desc
, &dev
->msi_list
, list
) {
2589 #ifdef CONFIG_INTR_REMAP
2590 if (!intr_remapping_enabled
)
2595 * allocate the consecutive block of IRTE's
2598 index
= msi_alloc_irte(dev
, irq
, nvec
);
2604 iommu
= map_dev_to_ir(dev
);
2610 * setup the mapping between the irq and the IRTE
2611 * base index, the sub_handle pointing to the
2612 * appropriate interrupt remap table entry.
2614 set_irte_irq(irq
, iommu
, index
, sub_handle
);
2618 ret
= setup_msi_irq(dev
, desc
, irq
);
2630 void arch_teardown_msi_irq(unsigned int irq
)
2637 static void dmar_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
2639 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2644 cpus_and(tmp
, mask
, cpu_online_map
);
2645 if (cpus_empty(tmp
))
2648 if (assign_irq_vector(irq
, mask
))
2651 cpus_and(tmp
, cfg
->domain
, mask
);
2652 dest
= cpu_mask_to_apicid(tmp
);
2654 dmar_msi_read(irq
, &msg
);
2656 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2657 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2658 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2659 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2661 dmar_msi_write(irq
, &msg
);
2662 irq_desc
[irq
].affinity
= mask
;
2664 #endif /* CONFIG_SMP */
2666 struct irq_chip dmar_msi_type
= {
2668 .unmask
= dmar_msi_unmask
,
2669 .mask
= dmar_msi_mask
,
2670 .ack
= ack_apic_edge
,
2672 .set_affinity
= dmar_msi_set_affinity
,
2674 .retrigger
= ioapic_retrigger_irq
,
2677 int arch_setup_dmar_msi(unsigned int irq
)
2682 ret
= msi_compose_msg(NULL
, irq
, &msg
);
2685 dmar_msi_write(irq
, &msg
);
2686 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
2692 #endif /* CONFIG_PCI_MSI */
2694 * Hypertransport interrupt support
2696 #ifdef CONFIG_HT_IRQ
2700 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
2702 struct ht_irq_msg msg
;
2703 fetch_ht_irq_msg(irq
, &msg
);
2705 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
2706 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2708 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
2709 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2711 write_ht_irq_msg(irq
, &msg
);
2714 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2716 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2720 cpus_and(tmp
, mask
, cpu_online_map
);
2721 if (cpus_empty(tmp
))
2724 if (assign_irq_vector(irq
, mask
))
2727 cpus_and(tmp
, cfg
->domain
, mask
);
2728 dest
= cpu_mask_to_apicid(tmp
);
2730 target_ht_irq(irq
, dest
, cfg
->vector
);
2731 irq_desc
[irq
].affinity
= mask
;
2735 static struct irq_chip ht_irq_chip
= {
2737 .mask
= mask_ht_irq
,
2738 .unmask
= unmask_ht_irq
,
2739 .ack
= ack_apic_edge
,
2741 .set_affinity
= set_ht_irq_affinity
,
2743 .retrigger
= ioapic_retrigger_irq
,
2746 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2748 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2753 err
= assign_irq_vector(irq
, tmp
);
2755 struct ht_irq_msg msg
;
2758 cpus_and(tmp
, cfg
->domain
, tmp
);
2759 dest
= cpu_mask_to_apicid(tmp
);
2761 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2765 HT_IRQ_LOW_DEST_ID(dest
) |
2766 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
2767 ((INT_DEST_MODE
== 0) ?
2768 HT_IRQ_LOW_DM_PHYSICAL
:
2769 HT_IRQ_LOW_DM_LOGICAL
) |
2770 HT_IRQ_LOW_RQEOI_EDGE
|
2771 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2772 HT_IRQ_LOW_MT_FIXED
:
2773 HT_IRQ_LOW_MT_ARBITRATED
) |
2774 HT_IRQ_LOW_IRQ_MASKED
;
2776 write_ht_irq_msg(irq
, &msg
);
2778 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2779 handle_edge_irq
, "edge");
2783 #endif /* CONFIG_HT_IRQ */
2785 /* --------------------------------------------------------------------------
2786 ACPI-based IOAPIC Configuration
2787 -------------------------------------------------------------------------- */
2791 #define IO_APIC_MAX_ID 0xFE
2793 int __init
io_apic_get_redir_entries (int ioapic
)
2795 union IO_APIC_reg_01 reg_01
;
2796 unsigned long flags
;
2798 spin_lock_irqsave(&ioapic_lock
, flags
);
2799 reg_01
.raw
= io_apic_read(ioapic
, 1);
2800 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2802 return reg_01
.bits
.entries
;
2806 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
2808 if (!IO_APIC_IRQ(irq
)) {
2809 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2815 * IRQs < 16 are already in the irq_2_pin[] map
2818 add_pin_to_irq(irq
, ioapic
, pin
);
2820 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
2826 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2830 if (skip_ioapic_setup
)
2833 for (i
= 0; i
< mp_irq_entries
; i
++)
2834 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
2835 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
2837 if (i
>= mp_irq_entries
)
2840 *trigger
= irq_trigger(i
);
2841 *polarity
= irq_polarity(i
);
2845 #endif /* CONFIG_ACPI */
2848 * This function currently is only a helper for the i386 smp boot process where
2849 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2850 * so mask in all cases should simply be TARGET_CPUS
2853 void __init
setup_ioapic_dest(void)
2855 int pin
, ioapic
, irq
, irq_entry
;
2857 if (skip_ioapic_setup
== 1)
2860 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
2861 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
2862 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
2863 if (irq_entry
== -1)
2865 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
2867 /* setup_IO_APIC_irqs could fail to get vector for some device
2868 * when you have too many devices, because at that time only boot
2871 if (!irq_cfg
[irq
].vector
)
2872 setup_IO_APIC_irq(ioapic
, pin
, irq
,
2873 irq_trigger(irq_entry
),
2874 irq_polarity(irq_entry
));
2875 #ifdef CONFIG_INTR_REMAP
2876 else if (intr_remapping_enabled
)
2877 set_ir_ioapic_affinity_irq(irq
, TARGET_CPUS
);
2880 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
2887 #define IOAPIC_RESOURCE_NAME_SIZE 11
2889 static struct resource
*ioapic_resources
;
2891 static struct resource
* __init
ioapic_setup_resources(void)
2894 struct resource
*res
;
2898 if (nr_ioapics
<= 0)
2901 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
2904 mem
= alloc_bootmem(n
);
2908 mem
+= sizeof(struct resource
) * nr_ioapics
;
2910 for (i
= 0; i
< nr_ioapics
; i
++) {
2912 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
2913 sprintf(mem
, "IOAPIC %u", i
);
2914 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
2918 ioapic_resources
= res
;
2923 void __init
ioapic_init_mappings(void)
2925 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2926 struct resource
*ioapic_res
;
2929 ioapic_res
= ioapic_setup_resources();
2930 for (i
= 0; i
< nr_ioapics
; i
++) {
2931 if (smp_found_config
) {
2932 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
2934 ioapic_phys
= (unsigned long)
2935 alloc_bootmem_pages(PAGE_SIZE
);
2936 ioapic_phys
= __pa(ioapic_phys
);
2938 set_fixmap_nocache(idx
, ioapic_phys
);
2939 apic_printk(APIC_VERBOSE
,
2940 "mapped IOAPIC to %016lx (%016lx)\n",
2941 __fix_to_virt(idx
), ioapic_phys
);
2944 if (ioapic_res
!= NULL
) {
2945 ioapic_res
->start
= ioapic_phys
;
2946 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
2952 static int __init
ioapic_insert_resources(void)
2955 struct resource
*r
= ioapic_resources
;
2959 "IO APIC resources could be not be allocated.\n");
2963 for (i
= 0; i
< nr_ioapics
; i
++) {
2964 insert_resource(&iomem_resource
, r
);
2971 /* Insert the IO APIC resources after PCI initialization has occured to handle
2972 * IO APICS that are mapped in on a BAR in PCI space. */
2973 late_initcall(ioapic_insert_resources
);