2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
40 #include <linux/dmar.h>
46 #include <asm/proto.h>
49 #include <asm/i8259.h>
51 #include <asm/msidef.h>
52 #include <asm/hypertransport.h>
53 #include <asm/irq_remapping.h>
56 #include <mach_apic.h>
58 #define __apicdebuginit(type) static type __init
63 unsigned move_cleanup_count
;
65 u8 move_in_progress
: 1;
68 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
69 static struct irq_cfg irq_cfg
[NR_IRQS
] __read_mostly
= {
70 [0] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
71 [1] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
72 [2] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
73 [3] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
74 [4] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
75 [5] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
76 [6] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
77 [7] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
78 [8] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
79 [9] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
80 [10] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
81 [11] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
82 [12] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
83 [13] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
84 [14] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
85 [15] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
88 static int assign_irq_vector(int irq
, cpumask_t mask
);
90 int first_system_vector
= 0xfe;
92 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
94 int sis_apic_bug
; /* not actually supported, dummy for compile */
96 static int no_timer_check
;
98 static int disable_timer_pin_1 __initdata
;
100 int timer_through_8259 __initdata
;
102 /* Where if anywhere is the i8259 connect in external int mode */
103 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
105 static DEFINE_SPINLOCK(ioapic_lock
);
106 static DEFINE_SPINLOCK(vector_lock
);
109 * # of IRQ routing registers
111 int nr_ioapic_registers
[MAX_IO_APICS
];
113 /* I/O APIC RTE contents at the OS boot up */
114 struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
116 /* I/O APIC entries */
117 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
120 /* MP IRQ source entries */
121 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
123 /* # of MP IRQ source entries */
126 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
129 * Rough estimation of how many shared IRQs there are, can
130 * be changed anytime.
132 #define MAX_PLUS_SHARED_IRQS NR_IRQS
133 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
135 int pin_map_size
= PIN_MAP_SIZE
;
137 * This is performance-critical, we want to do it O(1)
139 * the indexing order of this array favors 1:1 mappings
140 * between pins and IRQs.
143 static struct irq_pin_list
{
144 short apic
, pin
, next
;
145 } irq_2_pin
[PIN_MAP_SIZE
];
149 unsigned int unused
[3];
153 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
155 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
156 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
159 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
161 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
162 writel(reg
, &io_apic
->index
);
163 return readl(&io_apic
->data
);
166 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
168 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
169 writel(reg
, &io_apic
->index
);
170 writel(value
, &io_apic
->data
);
174 * Re-write a value: to be used for read-modify-write
175 * cycles where the read already set up the index register.
177 static inline void io_apic_modify(unsigned int apic
, unsigned int value
)
179 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
180 writel(value
, &io_apic
->data
);
183 static bool io_apic_level_ack_pending(unsigned int irq
)
185 struct irq_pin_list
*entry
;
188 spin_lock_irqsave(&ioapic_lock
, flags
);
189 entry
= irq_2_pin
+ irq
;
197 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
198 /* Is the remote IRR bit set? */
199 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
200 spin_unlock_irqrestore(&ioapic_lock
, flags
);
205 entry
= irq_2_pin
+ entry
->next
;
207 spin_unlock_irqrestore(&ioapic_lock
, flags
);
213 * Synchronize the IO-APIC and the CPU by doing
214 * a dummy read from the IO-APIC
216 static inline void io_apic_sync(unsigned int apic
)
218 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
219 readl(&io_apic
->data
);
222 #define __DO_ACTION(R, ACTION, FINAL) \
226 struct irq_pin_list *entry = irq_2_pin + irq; \
228 BUG_ON(irq >= nr_irqs); \
234 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
236 io_apic_modify(entry->apic, reg); \
240 entry = irq_2_pin + entry->next; \
245 struct { u32 w1
, w2
; };
246 struct IO_APIC_route_entry entry
;
249 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
251 union entry_union eu
;
253 spin_lock_irqsave(&ioapic_lock
, flags
);
254 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
255 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
256 spin_unlock_irqrestore(&ioapic_lock
, flags
);
261 * When we write a new IO APIC routing entry, we need to write the high
262 * word first! If the mask bit in the low word is clear, we will enable
263 * the interrupt, and we need to make sure the entry is fully populated
264 * before that happens.
267 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
269 union entry_union eu
;
271 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
272 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
275 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
278 spin_lock_irqsave(&ioapic_lock
, flags
);
279 __ioapic_write_entry(apic
, pin
, e
);
280 spin_unlock_irqrestore(&ioapic_lock
, flags
);
284 * When we mask an IO APIC routing entry, we need to write the low
285 * word first, in order to set the mask bit before we change the
288 static void ioapic_mask_entry(int apic
, int pin
)
291 union entry_union eu
= { .entry
.mask
= 1 };
293 spin_lock_irqsave(&ioapic_lock
, flags
);
294 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
295 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
296 spin_unlock_irqrestore(&ioapic_lock
, flags
);
300 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
303 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
305 BUG_ON(irq
>= nr_irqs
);
313 * With interrupt-remapping, destination information comes
314 * from interrupt-remapping table entry.
316 if (!irq_remapped(irq
))
317 io_apic_write(apic
, 0x11 + pin
*2, dest
);
318 reg
= io_apic_read(apic
, 0x10 + pin
*2);
319 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
321 io_apic_modify(apic
, reg
);
324 entry
= irq_2_pin
+ entry
->next
;
328 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
330 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
335 cpus_and(tmp
, mask
, cpu_online_map
);
339 if (assign_irq_vector(irq
, mask
))
342 cpus_and(tmp
, cfg
->domain
, mask
);
343 dest
= cpu_mask_to_apicid(tmp
);
346 * Only the high 8 bits are valid.
348 dest
= SET_APIC_LOGICAL_ID(dest
);
350 spin_lock_irqsave(&ioapic_lock
, flags
);
351 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
352 irq_desc
[irq
].affinity
= mask
;
353 spin_unlock_irqrestore(&ioapic_lock
, flags
);
358 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
359 * shared ISA-space IRQs, so we have to support them. We are super
360 * fast in the common case, and fast for shared ISA-space IRQs.
362 int first_free_entry
= NR_IRQS
;
363 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
365 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
367 BUG_ON(irq
>= nr_irqs
);
369 entry
= irq_2_pin
+ entry
->next
;
371 if (entry
->pin
!= -1) {
372 entry
->next
= first_free_entry
;
373 entry
= irq_2_pin
+ entry
->next
;
374 if (++first_free_entry
>= pin_map_size
)
375 panic("io_apic.c: ran out of irq_2_pin entries!");
382 * Reroute an IRQ to a different pin.
384 static void __init
replace_pin_at_irq(unsigned int irq
,
385 int oldapic
, int oldpin
,
386 int newapic
, int newpin
)
388 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
391 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
392 entry
->apic
= newapic
;
397 entry
= irq_2_pin
+ entry
->next
;
402 #define DO_ACTION(name,R,ACTION, FINAL) \
404 static void name##_IO_APIC_irq (unsigned int irq) \
405 __DO_ACTION(R, ACTION, FINAL)
408 DO_ACTION(__mask
, 0, |= IO_APIC_REDIR_MASKED
, io_apic_sync(entry
->apic
))
411 DO_ACTION(__unmask
, 0, &= ~IO_APIC_REDIR_MASKED
, )
413 static void mask_IO_APIC_irq (unsigned int irq
)
417 spin_lock_irqsave(&ioapic_lock
, flags
);
418 __mask_IO_APIC_irq(irq
);
419 spin_unlock_irqrestore(&ioapic_lock
, flags
);
422 static void unmask_IO_APIC_irq (unsigned int irq
)
426 spin_lock_irqsave(&ioapic_lock
, flags
);
427 __unmask_IO_APIC_irq(irq
);
428 spin_unlock_irqrestore(&ioapic_lock
, flags
);
431 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
433 struct IO_APIC_route_entry entry
;
435 /* Check delivery_mode to be sure we're not clearing an SMI pin */
436 entry
= ioapic_read_entry(apic
, pin
);
437 if (entry
.delivery_mode
== dest_SMI
)
440 * Disable it in the IO-APIC irq-routing table:
442 ioapic_mask_entry(apic
, pin
);
445 static void clear_IO_APIC (void)
449 for (apic
= 0; apic
< nr_ioapics
; apic
++)
450 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
451 clear_IO_APIC_pin(apic
, pin
);
455 * Saves and masks all the unmasked IO-APIC RTE's
457 int save_mask_IO_APIC_setup(void)
459 union IO_APIC_reg_01 reg_01
;
464 * The number of IO-APIC IRQ registers (== #pins):
466 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
467 spin_lock_irqsave(&ioapic_lock
, flags
);
468 reg_01
.raw
= io_apic_read(apic
, 1);
469 spin_unlock_irqrestore(&ioapic_lock
, flags
);
470 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
473 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
474 early_ioapic_entries
[apic
] =
475 kzalloc(sizeof(struct IO_APIC_route_entry
) *
476 nr_ioapic_registers
[apic
], GFP_KERNEL
);
477 if (!early_ioapic_entries
[apic
])
481 for (apic
= 0; apic
< nr_ioapics
; apic
++)
482 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
483 struct IO_APIC_route_entry entry
;
485 entry
= early_ioapic_entries
[apic
][pin
] =
486 ioapic_read_entry(apic
, pin
);
489 ioapic_write_entry(apic
, pin
, entry
);
495 void restore_IO_APIC_setup(void)
499 for (apic
= 0; apic
< nr_ioapics
; apic
++)
500 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
501 ioapic_write_entry(apic
, pin
,
502 early_ioapic_entries
[apic
][pin
]);
505 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
508 * for now plain restore of previous settings.
509 * TBD: In the case of OS enabling interrupt-remapping,
510 * IO-APIC RTE's need to be setup to point to interrupt-remapping
511 * table entries. for now, do a plain restore, and wait for
512 * the setup_IO_APIC_irqs() to do proper initialization.
514 restore_IO_APIC_setup();
517 int skip_ioapic_setup
;
520 static int __init
parse_noapic(char *str
)
522 disable_ioapic_setup();
525 early_param("noapic", parse_noapic
);
527 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
528 static int __init
disable_timer_pin_setup(char *arg
)
530 disable_timer_pin_1
= 1;
533 __setup("disable_timer_pin_1", disable_timer_pin_setup
);
537 * Find the IRQ entry number of a certain pin.
539 static int find_irq_entry(int apic
, int pin
, int type
)
543 for (i
= 0; i
< mp_irq_entries
; i
++)
544 if (mp_irqs
[i
].mp_irqtype
== type
&&
545 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
546 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
547 mp_irqs
[i
].mp_dstirq
== pin
)
554 * Find the pin to which IRQ[irq] (ISA) is connected
556 static int __init
find_isa_irq_pin(int irq
, int type
)
560 for (i
= 0; i
< mp_irq_entries
; i
++) {
561 int lbus
= mp_irqs
[i
].mp_srcbus
;
563 if (test_bit(lbus
, mp_bus_not_pci
) &&
564 (mp_irqs
[i
].mp_irqtype
== type
) &&
565 (mp_irqs
[i
].mp_srcbusirq
== irq
))
567 return mp_irqs
[i
].mp_dstirq
;
572 static int __init
find_isa_irq_apic(int irq
, int type
)
576 for (i
= 0; i
< mp_irq_entries
; i
++) {
577 int lbus
= mp_irqs
[i
].mp_srcbus
;
579 if (test_bit(lbus
, mp_bus_not_pci
) &&
580 (mp_irqs
[i
].mp_irqtype
== type
) &&
581 (mp_irqs
[i
].mp_srcbusirq
== irq
))
584 if (i
< mp_irq_entries
) {
586 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
587 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
596 * Find a specific PCI IRQ entry.
597 * Not an __init, possibly needed by modules
599 static int pin_2_irq(int idx
, int apic
, int pin
);
601 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
603 int apic
, i
, best_guess
= -1;
605 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
607 if (test_bit(bus
, mp_bus_not_pci
)) {
608 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
611 for (i
= 0; i
< mp_irq_entries
; i
++) {
612 int lbus
= mp_irqs
[i
].mp_srcbus
;
614 for (apic
= 0; apic
< nr_ioapics
; apic
++)
615 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
616 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
619 if (!test_bit(lbus
, mp_bus_not_pci
) &&
620 !mp_irqs
[i
].mp_irqtype
&&
622 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
623 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
625 if (!(apic
|| IO_APIC_IRQ(irq
)))
628 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
631 * Use the first all-but-pin matching entry as a
632 * best-guess fuzzy result for broken mptables.
638 BUG_ON(best_guess
>= nr_irqs
);
642 /* ISA interrupts are always polarity zero edge triggered,
643 * when listed as conforming in the MP table. */
645 #define default_ISA_trigger(idx) (0)
646 #define default_ISA_polarity(idx) (0)
648 /* PCI interrupts are always polarity one level triggered,
649 * when listed as conforming in the MP table. */
651 #define default_PCI_trigger(idx) (1)
652 #define default_PCI_polarity(idx) (1)
654 static int MPBIOS_polarity(int idx
)
656 int bus
= mp_irqs
[idx
].mp_srcbus
;
660 * Determine IRQ line polarity (high active or low active):
662 switch (mp_irqs
[idx
].mp_irqflag
& 3)
664 case 0: /* conforms, ie. bus-type dependent polarity */
665 if (test_bit(bus
, mp_bus_not_pci
))
666 polarity
= default_ISA_polarity(idx
);
668 polarity
= default_PCI_polarity(idx
);
670 case 1: /* high active */
675 case 2: /* reserved */
677 printk(KERN_WARNING
"broken BIOS!!\n");
681 case 3: /* low active */
686 default: /* invalid */
688 printk(KERN_WARNING
"broken BIOS!!\n");
696 static int MPBIOS_trigger(int idx
)
698 int bus
= mp_irqs
[idx
].mp_srcbus
;
702 * Determine IRQ trigger mode (edge or level sensitive):
704 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
706 case 0: /* conforms, ie. bus-type dependent */
707 if (test_bit(bus
, mp_bus_not_pci
))
708 trigger
= default_ISA_trigger(idx
);
710 trigger
= default_PCI_trigger(idx
);
717 case 2: /* reserved */
719 printk(KERN_WARNING
"broken BIOS!!\n");
728 default: /* invalid */
730 printk(KERN_WARNING
"broken BIOS!!\n");
738 static inline int irq_polarity(int idx
)
740 return MPBIOS_polarity(idx
);
743 static inline int irq_trigger(int idx
)
745 return MPBIOS_trigger(idx
);
748 static int pin_2_irq(int idx
, int apic
, int pin
)
751 int bus
= mp_irqs
[idx
].mp_srcbus
;
754 * Debugging check, we are in big trouble if this message pops up!
756 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
757 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
759 if (test_bit(bus
, mp_bus_not_pci
)) {
760 irq
= mp_irqs
[idx
].mp_srcbusirq
;
763 * PCI IRQs are mapped in order
767 irq
+= nr_ioapic_registers
[i
++];
770 BUG_ON(irq
>= nr_irqs
);
774 void lock_vector_lock(void)
776 /* Used to the online set of cpus does not change
777 * during assign_irq_vector.
779 spin_lock(&vector_lock
);
782 void unlock_vector_lock(void)
784 spin_unlock(&vector_lock
);
787 static int __assign_irq_vector(int irq
, cpumask_t mask
)
790 * NOTE! The local APIC isn't very good at handling
791 * multiple interrupts at the same interrupt level.
792 * As the interrupt level is determined by taking the
793 * vector number and shifting that right by 4, we
794 * want to spread these out a bit so that they don't
795 * all fall in the same interrupt level.
797 * Also, we've got to be careful not to trash gate
798 * 0x80, because int 0x80 is hm, kind of importantish. ;)
800 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
801 unsigned int old_vector
;
805 BUG_ON((unsigned)irq
>= nr_irqs
);
808 /* Only try and allocate irqs on cpus that are present */
809 cpus_and(mask
, mask
, cpu_online_map
);
811 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
814 old_vector
= cfg
->vector
;
817 cpus_and(tmp
, cfg
->domain
, mask
);
818 if (!cpus_empty(tmp
))
822 for_each_cpu_mask_nr(cpu
, mask
) {
823 cpumask_t domain
, new_mask
;
827 domain
= vector_allocation_domain(cpu
);
828 cpus_and(new_mask
, domain
, cpu_online_map
);
830 vector
= current_vector
;
831 offset
= current_offset
;
834 if (vector
>= first_system_vector
) {
835 /* If we run out of vectors on large boxen, must share them. */
836 offset
= (offset
+ 1) % 8;
837 vector
= FIRST_DEVICE_VECTOR
+ offset
;
839 if (unlikely(current_vector
== vector
))
841 if (vector
== IA32_SYSCALL_VECTOR
)
843 for_each_cpu_mask_nr(new_cpu
, new_mask
)
844 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
847 current_vector
= vector
;
848 current_offset
= offset
;
850 cfg
->move_in_progress
= 1;
851 cfg
->old_domain
= cfg
->domain
;
853 for_each_cpu_mask_nr(new_cpu
, new_mask
)
854 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
855 cfg
->vector
= vector
;
856 cfg
->domain
= domain
;
862 static int assign_irq_vector(int irq
, cpumask_t mask
)
867 spin_lock_irqsave(&vector_lock
, flags
);
868 err
= __assign_irq_vector(irq
, mask
);
869 spin_unlock_irqrestore(&vector_lock
, flags
);
873 static void __clear_irq_vector(int irq
)
879 BUG_ON((unsigned)irq
>= nr_irqs
);
881 BUG_ON(!cfg
->vector
);
883 vector
= cfg
->vector
;
884 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
885 for_each_cpu_mask_nr(cpu
, mask
)
886 per_cpu(vector_irq
, cpu
)[vector
] = -1;
889 cpus_clear(cfg
->domain
);
892 void __setup_vector_irq(int cpu
)
894 /* Initialize vector_irq on a new cpu */
895 /* This function must be called with vector_lock held */
898 /* Mark the inuse vectors */
899 for (irq
= 0; irq
< nr_irqs
; ++irq
) {
900 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
902 vector
= irq_cfg
[irq
].vector
;
903 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
905 /* Mark the free vectors */
906 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
907 irq
= per_cpu(vector_irq
, cpu
)[vector
];
910 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
911 per_cpu(vector_irq
, cpu
)[vector
] = -1;
915 static struct irq_chip ioapic_chip
;
916 #ifdef CONFIG_INTR_REMAP
917 static struct irq_chip ir_ioapic_chip
;
920 static void ioapic_register_intr(int irq
, unsigned long trigger
)
923 irq_desc
[irq
].status
|= IRQ_LEVEL
;
925 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
927 #ifdef CONFIG_INTR_REMAP
928 if (irq_remapped(irq
)) {
929 irq_desc
[irq
].status
|= IRQ_MOVE_PCNTXT
;
931 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
935 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
936 handle_edge_irq
, "edge");
941 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
945 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
946 handle_edge_irq
, "edge");
949 static int setup_ioapic_entry(int apic
, int irq
,
950 struct IO_APIC_route_entry
*entry
,
951 unsigned int destination
, int trigger
,
952 int polarity
, int vector
)
955 * add it to the IO-APIC irq-routing table:
957 memset(entry
,0,sizeof(*entry
));
959 #ifdef CONFIG_INTR_REMAP
960 if (intr_remapping_enabled
) {
961 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
963 struct IR_IO_APIC_route_entry
*ir_entry
=
964 (struct IR_IO_APIC_route_entry
*) entry
;
968 panic("No mapping iommu for ioapic %d\n", apic
);
970 index
= alloc_irte(iommu
, irq
, 1);
972 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
974 memset(&irte
, 0, sizeof(irte
));
977 irte
.dst_mode
= INT_DEST_MODE
;
978 irte
.trigger_mode
= trigger
;
979 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
980 irte
.vector
= vector
;
981 irte
.dest_id
= IRTE_DEST(destination
);
983 modify_irte(irq
, &irte
);
985 ir_entry
->index2
= (index
>> 15) & 0x1;
987 ir_entry
->format
= 1;
988 ir_entry
->index
= (index
& 0x7fff);
992 entry
->delivery_mode
= INT_DELIVERY_MODE
;
993 entry
->dest_mode
= INT_DEST_MODE
;
994 entry
->dest
= destination
;
997 entry
->mask
= 0; /* enable IRQ */
998 entry
->trigger
= trigger
;
999 entry
->polarity
= polarity
;
1000 entry
->vector
= vector
;
1002 /* Mask level triggered irqs.
1003 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1010 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
1011 int trigger
, int polarity
)
1013 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1014 struct IO_APIC_route_entry entry
;
1017 if (!IO_APIC_IRQ(irq
))
1021 if (assign_irq_vector(irq
, mask
))
1024 cpus_and(mask
, cfg
->domain
, mask
);
1026 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1027 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1028 "IRQ %d Mode:%i Active:%i)\n",
1029 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1030 irq
, trigger
, polarity
);
1033 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1034 cpu_mask_to_apicid(mask
), trigger
, polarity
,
1036 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1037 mp_ioapics
[apic
].mp_apicid
, pin
);
1038 __clear_irq_vector(irq
);
1042 ioapic_register_intr(irq
, trigger
);
1044 disable_8259A_irq(irq
);
1046 ioapic_write_entry(apic
, pin
, entry
);
1049 static void __init
setup_IO_APIC_irqs(void)
1051 int apic
, pin
, idx
, irq
, first_notcon
= 1;
1053 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1055 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1056 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1058 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1061 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1064 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1067 if (!first_notcon
) {
1068 apic_printk(APIC_VERBOSE
, " not connected.\n");
1072 irq
= pin_2_irq(idx
, apic
, pin
);
1073 add_pin_to_irq(irq
, apic
, pin
);
1075 setup_IO_APIC_irq(apic
, pin
, irq
,
1076 irq_trigger(idx
), irq_polarity(idx
));
1081 apic_printk(APIC_VERBOSE
, " not connected.\n");
1085 * Set up the timer pin, possibly with the 8259A-master behind.
1087 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1090 struct IO_APIC_route_entry entry
;
1092 if (intr_remapping_enabled
)
1095 memset(&entry
, 0, sizeof(entry
));
1098 * We use logical delivery to get the timer IRQ
1101 entry
.dest_mode
= INT_DEST_MODE
;
1102 entry
.mask
= 1; /* mask IRQ now */
1103 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1104 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1107 entry
.vector
= vector
;
1110 * The timer IRQ doesn't have to know that behind the
1111 * scene we may have a 8259A-master in AEOI mode ...
1113 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1116 * Add it to the IO-APIC irq-routing table:
1118 ioapic_write_entry(apic
, pin
, entry
);
1122 __apicdebuginit(void) print_IO_APIC(void)
1125 union IO_APIC_reg_00 reg_00
;
1126 union IO_APIC_reg_01 reg_01
;
1127 union IO_APIC_reg_02 reg_02
;
1128 unsigned long flags
;
1130 if (apic_verbosity
== APIC_QUIET
)
1133 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1134 for (i
= 0; i
< nr_ioapics
; i
++)
1135 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1136 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1139 * We are a bit conservative about what we expect. We have to
1140 * know about every hardware change ASAP.
1142 printk(KERN_INFO
"testing the IO APIC.......................\n");
1144 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1146 spin_lock_irqsave(&ioapic_lock
, flags
);
1147 reg_00
.raw
= io_apic_read(apic
, 0);
1148 reg_01
.raw
= io_apic_read(apic
, 1);
1149 if (reg_01
.bits
.version
>= 0x10)
1150 reg_02
.raw
= io_apic_read(apic
, 2);
1151 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1154 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1155 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1156 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1158 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1159 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1161 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1162 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1164 if (reg_01
.bits
.version
>= 0x10) {
1165 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1166 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1169 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1171 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1172 " Stat Dmod Deli Vect: \n");
1174 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1175 struct IO_APIC_route_entry entry
;
1177 entry
= ioapic_read_entry(apic
, i
);
1179 printk(KERN_DEBUG
" %02x %03X ",
1184 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1189 entry
.delivery_status
,
1191 entry
.delivery_mode
,
1196 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1197 for (i
= 0; i
< nr_irqs
; i
++) {
1198 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1201 printk(KERN_DEBUG
"IRQ%d ", i
);
1203 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1206 entry
= irq_2_pin
+ entry
->next
;
1211 printk(KERN_INFO
".................................... done.\n");
1216 __apicdebuginit(void) print_APIC_bitfield(int base
)
1221 if (apic_verbosity
== APIC_QUIET
)
1224 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1225 for (i
= 0; i
< 8; i
++) {
1226 v
= apic_read(base
+ i
*0x10);
1227 for (j
= 0; j
< 32; j
++) {
1237 __apicdebuginit(void) print_local_APIC(void *dummy
)
1239 unsigned int v
, ver
, maxlvt
;
1242 if (apic_verbosity
== APIC_QUIET
)
1245 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1246 smp_processor_id(), hard_smp_processor_id());
1247 v
= apic_read(APIC_ID
);
1248 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1249 v
= apic_read(APIC_LVR
);
1250 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1251 ver
= GET_APIC_VERSION(v
);
1252 maxlvt
= lapic_get_maxlvt();
1254 v
= apic_read(APIC_TASKPRI
);
1255 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1257 v
= apic_read(APIC_ARBPRI
);
1258 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1259 v
& APIC_ARBPRI_MASK
);
1260 v
= apic_read(APIC_PROCPRI
);
1261 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1263 v
= apic_read(APIC_EOI
);
1264 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1265 v
= apic_read(APIC_RRR
);
1266 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1267 v
= apic_read(APIC_LDR
);
1268 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1269 v
= apic_read(APIC_DFR
);
1270 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1271 v
= apic_read(APIC_SPIV
);
1272 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1274 printk(KERN_DEBUG
"... APIC ISR field:\n");
1275 print_APIC_bitfield(APIC_ISR
);
1276 printk(KERN_DEBUG
"... APIC TMR field:\n");
1277 print_APIC_bitfield(APIC_TMR
);
1278 printk(KERN_DEBUG
"... APIC IRR field:\n");
1279 print_APIC_bitfield(APIC_IRR
);
1281 v
= apic_read(APIC_ESR
);
1282 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1284 icr
= apic_icr_read();
1285 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1286 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1288 v
= apic_read(APIC_LVTT
);
1289 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1291 if (maxlvt
> 3) { /* PC is LVT#4. */
1292 v
= apic_read(APIC_LVTPC
);
1293 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1295 v
= apic_read(APIC_LVT0
);
1296 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1297 v
= apic_read(APIC_LVT1
);
1298 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1300 if (maxlvt
> 2) { /* ERR is LVT#3. */
1301 v
= apic_read(APIC_LVTERR
);
1302 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1305 v
= apic_read(APIC_TMICT
);
1306 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1307 v
= apic_read(APIC_TMCCT
);
1308 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1309 v
= apic_read(APIC_TDCR
);
1310 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1314 __apicdebuginit(void) print_all_local_APICs(void)
1316 on_each_cpu(print_local_APIC
, NULL
, 1);
1319 __apicdebuginit(void) print_PIC(void)
1322 unsigned long flags
;
1324 if (apic_verbosity
== APIC_QUIET
)
1327 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1329 spin_lock_irqsave(&i8259A_lock
, flags
);
1331 v
= inb(0xa1) << 8 | inb(0x21);
1332 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1334 v
= inb(0xa0) << 8 | inb(0x20);
1335 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1339 v
= inb(0xa0) << 8 | inb(0x20);
1343 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1345 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1347 v
= inb(0x4d1) << 8 | inb(0x4d0);
1348 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1351 __apicdebuginit(int) print_all_ICs(void)
1354 print_all_local_APICs();
1360 fs_initcall(print_all_ICs
);
1363 void __init
enable_IO_APIC(void)
1365 union IO_APIC_reg_01 reg_01
;
1366 int i8259_apic
, i8259_pin
;
1368 unsigned long flags
;
1370 for (i
= 0; i
< pin_map_size
; i
++) {
1371 irq_2_pin
[i
].pin
= -1;
1372 irq_2_pin
[i
].next
= 0;
1376 * The number of IO-APIC IRQ registers (== #pins):
1378 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1379 spin_lock_irqsave(&ioapic_lock
, flags
);
1380 reg_01
.raw
= io_apic_read(apic
, 1);
1381 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1382 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1384 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1386 /* See if any of the pins is in ExtINT mode */
1387 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1388 struct IO_APIC_route_entry entry
;
1389 entry
= ioapic_read_entry(apic
, pin
);
1391 /* If the interrupt line is enabled and in ExtInt mode
1392 * I have found the pin where the i8259 is connected.
1394 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1395 ioapic_i8259
.apic
= apic
;
1396 ioapic_i8259
.pin
= pin
;
1402 /* Look to see what if the MP table has reported the ExtINT */
1403 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1404 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1405 /* Trust the MP table if nothing is setup in the hardware */
1406 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1407 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1408 ioapic_i8259
.pin
= i8259_pin
;
1409 ioapic_i8259
.apic
= i8259_apic
;
1411 /* Complain if the MP table and the hardware disagree */
1412 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1413 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1415 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1419 * Do not trust the IO-APIC being empty at bootup
1425 * Not an __init, needed by the reboot code
1427 void disable_IO_APIC(void)
1430 * Clear the IO-APIC before rebooting:
1435 * If the i8259 is routed through an IOAPIC
1436 * Put that IOAPIC in virtual wire mode
1437 * so legacy interrupts can be delivered.
1439 if (ioapic_i8259
.pin
!= -1) {
1440 struct IO_APIC_route_entry entry
;
1442 memset(&entry
, 0, sizeof(entry
));
1443 entry
.mask
= 0; /* Enabled */
1444 entry
.trigger
= 0; /* Edge */
1446 entry
.polarity
= 0; /* High */
1447 entry
.delivery_status
= 0;
1448 entry
.dest_mode
= 0; /* Physical */
1449 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1451 entry
.dest
= read_apic_id();
1454 * Add it to the IO-APIC irq-routing table:
1456 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1459 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1463 * There is a nasty bug in some older SMP boards, their mptable lies
1464 * about the timer IRQ. We do the following to work around the situation:
1466 * - timer IRQ defaults to IO-APIC IRQ
1467 * - if this function detects that timer IRQs are defunct, then we fall
1468 * back to ISA timer IRQs
1470 static int __init
timer_irq_works(void)
1472 unsigned long t1
= jiffies
;
1473 unsigned long flags
;
1475 local_save_flags(flags
);
1477 /* Let ten ticks pass... */
1478 mdelay((10 * 1000) / HZ
);
1479 local_irq_restore(flags
);
1482 * Expect a few ticks at least, to be sure some possible
1483 * glue logic does not lock up after one or two first
1484 * ticks in a non-ExtINT mode. Also the local APIC
1485 * might have cached one ExtINT interrupt. Finally, at
1486 * least one tick may be lost due to delays.
1490 if (time_after(jiffies
, t1
+ 4))
1496 * In the SMP+IOAPIC case it might happen that there are an unspecified
1497 * number of pending IRQ events unhandled. These cases are very rare,
1498 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1499 * better to do it this way as thus we do not have to be aware of
1500 * 'pending' interrupts in the IRQ path, except at this point.
1503 * Edge triggered needs to resend any interrupt
1504 * that was delayed but this is now handled in the device
1509 * Starting up a edge-triggered IO-APIC interrupt is
1510 * nasty - we need to make sure that we get the edge.
1511 * If it is already asserted for some reason, we need
1512 * return 1 to indicate that is was pending.
1514 * This is not complete - we should be able to fake
1515 * an edge even if it isn't on the 8259A...
1518 static unsigned int startup_ioapic_irq(unsigned int irq
)
1520 int was_pending
= 0;
1521 unsigned long flags
;
1523 spin_lock_irqsave(&ioapic_lock
, flags
);
1525 disable_8259A_irq(irq
);
1526 if (i8259A_irq_pending(irq
))
1529 __unmask_IO_APIC_irq(irq
);
1530 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1535 static int ioapic_retrigger_irq(unsigned int irq
)
1537 struct irq_cfg
*cfg
= &irq_cfg
[irq
];
1538 unsigned long flags
;
1540 spin_lock_irqsave(&vector_lock
, flags
);
1541 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg
->domain
)), cfg
->vector
);
1542 spin_unlock_irqrestore(&vector_lock
, flags
);
1548 * Level and edge triggered IO-APIC interrupts need different handling,
1549 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1550 * handled with the level-triggered descriptor, but that one has slightly
1551 * more overhead. Level-triggered interrupts cannot be handled with the
1552 * edge-triggered handler, without risking IRQ storms and other ugly
1558 #ifdef CONFIG_INTR_REMAP
1559 static void ir_irq_migration(struct work_struct
*work
);
1561 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
1564 * Migrate the IO-APIC irq in the presence of intr-remapping.
1566 * For edge triggered, irq migration is a simple atomic update(of vector
1567 * and cpu destination) of IRTE and flush the hardware cache.
1569 * For level triggered, we need to modify the io-apic RTE aswell with the update
1570 * vector information, along with modifying IRTE with vector and destination.
1571 * So irq migration for level triggered is little bit more complex compared to
1572 * edge triggered migration. But the good news is, we use the same algorithm
1573 * for level triggered migration as we have today, only difference being,
1574 * we now initiate the irq migration from process context instead of the
1575 * interrupt context.
1577 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1578 * suppression) to the IO-APIC, level triggered irq migration will also be
1579 * as simple as edge triggered migration and we can do the irq migration
1580 * with a simple atomic update to IO-APIC RTE.
1582 static void migrate_ioapic_irq(int irq
, cpumask_t mask
)
1584 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1585 struct irq_desc
*desc
= irq_desc
+ irq
;
1586 cpumask_t tmp
, cleanup_mask
;
1588 int modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
1590 unsigned long flags
;
1592 cpus_and(tmp
, mask
, cpu_online_map
);
1593 if (cpus_empty(tmp
))
1596 if (get_irte(irq
, &irte
))
1599 if (assign_irq_vector(irq
, mask
))
1602 cpus_and(tmp
, cfg
->domain
, mask
);
1603 dest
= cpu_mask_to_apicid(tmp
);
1605 if (modify_ioapic_rte
) {
1606 spin_lock_irqsave(&ioapic_lock
, flags
);
1607 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
1608 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1611 irte
.vector
= cfg
->vector
;
1612 irte
.dest_id
= IRTE_DEST(dest
);
1615 * Modified the IRTE and flushes the Interrupt entry cache.
1617 modify_irte(irq
, &irte
);
1619 if (cfg
->move_in_progress
) {
1620 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1621 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1622 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1623 cfg
->move_in_progress
= 0;
1626 irq_desc
[irq
].affinity
= mask
;
1629 static int migrate_irq_remapped_level(int irq
)
1633 mask_IO_APIC_irq(irq
);
1635 if (io_apic_level_ack_pending(irq
)) {
1637 * Interrupt in progress. Migrating irq now will change the
1638 * vector information in the IO-APIC RTE and that will confuse
1639 * the EOI broadcast performed by cpu.
1640 * So, delay the irq migration to the next instance.
1642 schedule_delayed_work(&ir_migration_work
, 1);
1646 /* everthing is clear. we have right of way */
1647 migrate_ioapic_irq(irq
, irq_desc
[irq
].pending_mask
);
1650 irq_desc
[irq
].status
&= ~IRQ_MOVE_PENDING
;
1651 cpus_clear(irq_desc
[irq
].pending_mask
);
1654 unmask_IO_APIC_irq(irq
);
1658 static void ir_irq_migration(struct work_struct
*work
)
1662 for (irq
= 0; irq
< nr_irqs
; irq
++) {
1663 struct irq_desc
*desc
= irq_desc
+ irq
;
1664 if (desc
->status
& IRQ_MOVE_PENDING
) {
1665 unsigned long flags
;
1667 spin_lock_irqsave(&desc
->lock
, flags
);
1668 if (!desc
->chip
->set_affinity
||
1669 !(desc
->status
& IRQ_MOVE_PENDING
)) {
1670 desc
->status
&= ~IRQ_MOVE_PENDING
;
1671 spin_unlock_irqrestore(&desc
->lock
, flags
);
1675 desc
->chip
->set_affinity(irq
,
1676 irq_desc
[irq
].pending_mask
);
1677 spin_unlock_irqrestore(&desc
->lock
, flags
);
1683 * Migrates the IRQ destination in the process context.
1685 static void set_ir_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
1687 if (irq_desc
[irq
].status
& IRQ_LEVEL
) {
1688 irq_desc
[irq
].status
|= IRQ_MOVE_PENDING
;
1689 irq_desc
[irq
].pending_mask
= mask
;
1690 migrate_irq_remapped_level(irq
);
1694 migrate_ioapic_irq(irq
, mask
);
1698 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
1700 unsigned vector
, me
;
1705 me
= smp_processor_id();
1706 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
1708 struct irq_desc
*desc
;
1709 struct irq_cfg
*cfg
;
1710 irq
= __get_cpu_var(vector_irq
)[vector
];
1714 desc
= irq_desc
+ irq
;
1715 cfg
= irq_cfg
+ irq
;
1716 spin_lock(&desc
->lock
);
1717 if (!cfg
->move_cleanup_count
)
1720 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
1723 __get_cpu_var(vector_irq
)[vector
] = -1;
1724 cfg
->move_cleanup_count
--;
1726 spin_unlock(&desc
->lock
);
1732 static void irq_complete_move(unsigned int irq
)
1734 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1735 unsigned vector
, me
;
1737 if (likely(!cfg
->move_in_progress
))
1740 vector
= ~get_irq_regs()->orig_ax
;
1741 me
= smp_processor_id();
1742 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
1743 cpumask_t cleanup_mask
;
1745 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1746 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1747 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1748 cfg
->move_in_progress
= 0;
1752 static inline void irq_complete_move(unsigned int irq
) {}
1754 #ifdef CONFIG_INTR_REMAP
1755 static void ack_x2apic_level(unsigned int irq
)
1760 static void ack_x2apic_edge(unsigned int irq
)
1766 static void ack_apic_edge(unsigned int irq
)
1768 irq_complete_move(irq
);
1769 move_native_irq(irq
);
1773 static void ack_apic_level(unsigned int irq
)
1775 int do_unmask_irq
= 0;
1777 irq_complete_move(irq
);
1778 #ifdef CONFIG_GENERIC_PENDING_IRQ
1779 /* If we are moving the irq we need to mask it */
1780 if (unlikely(irq_desc
[irq
].status
& IRQ_MOVE_PENDING
)) {
1782 mask_IO_APIC_irq(irq
);
1787 * We must acknowledge the irq before we move it or the acknowledge will
1788 * not propagate properly.
1792 /* Now we can move and renable the irq */
1793 if (unlikely(do_unmask_irq
)) {
1794 /* Only migrate the irq if the ack has been received.
1796 * On rare occasions the broadcast level triggered ack gets
1797 * delayed going to ioapics, and if we reprogram the
1798 * vector while Remote IRR is still set the irq will never
1801 * To prevent this scenario we read the Remote IRR bit
1802 * of the ioapic. This has two effects.
1803 * - On any sane system the read of the ioapic will
1804 * flush writes (and acks) going to the ioapic from
1806 * - We get to see if the ACK has actually been delivered.
1808 * Based on failed experiments of reprogramming the
1809 * ioapic entry from outside of irq context starting
1810 * with masking the ioapic entry and then polling until
1811 * Remote IRR was clear before reprogramming the
1812 * ioapic I don't trust the Remote IRR bit to be
1813 * completey accurate.
1815 * However there appears to be no other way to plug
1816 * this race, so if the Remote IRR bit is not
1817 * accurate and is causing problems then it is a hardware bug
1818 * and you can go talk to the chipset vendor about it.
1820 if (!io_apic_level_ack_pending(irq
))
1821 move_masked_irq(irq
);
1822 unmask_IO_APIC_irq(irq
);
1826 static struct irq_chip ioapic_chip __read_mostly
= {
1828 .startup
= startup_ioapic_irq
,
1829 .mask
= mask_IO_APIC_irq
,
1830 .unmask
= unmask_IO_APIC_irq
,
1831 .ack
= ack_apic_edge
,
1832 .eoi
= ack_apic_level
,
1834 .set_affinity
= set_ioapic_affinity_irq
,
1836 .retrigger
= ioapic_retrigger_irq
,
1839 #ifdef CONFIG_INTR_REMAP
1840 static struct irq_chip ir_ioapic_chip __read_mostly
= {
1841 .name
= "IR-IO-APIC",
1842 .startup
= startup_ioapic_irq
,
1843 .mask
= mask_IO_APIC_irq
,
1844 .unmask
= unmask_IO_APIC_irq
,
1845 .ack
= ack_x2apic_edge
,
1846 .eoi
= ack_x2apic_level
,
1848 .set_affinity
= set_ir_ioapic_affinity_irq
,
1850 .retrigger
= ioapic_retrigger_irq
,
1854 static inline void init_IO_APIC_traps(void)
1859 * NOTE! The local APIC isn't very good at handling
1860 * multiple interrupts at the same interrupt level.
1861 * As the interrupt level is determined by taking the
1862 * vector number and shifting that right by 4, we
1863 * want to spread these out a bit so that they don't
1864 * all fall in the same interrupt level.
1866 * Also, we've got to be careful not to trash gate
1867 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1869 for (irq
= 0; irq
< nr_irqs
; irq
++) {
1870 if (IO_APIC_IRQ(irq
) && !irq_cfg
[irq
].vector
) {
1872 * Hmm.. We don't have an entry for this,
1873 * so default to an old-fashioned 8259
1874 * interrupt if we can..
1877 make_8259A_irq(irq
);
1879 /* Strange. Oh, well.. */
1880 irq_desc
[irq
].chip
= &no_irq_chip
;
1885 static void unmask_lapic_irq(unsigned int irq
)
1889 v
= apic_read(APIC_LVT0
);
1890 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
1893 static void mask_lapic_irq(unsigned int irq
)
1897 v
= apic_read(APIC_LVT0
);
1898 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1901 static void ack_lapic_irq (unsigned int irq
)
1906 static struct irq_chip lapic_chip __read_mostly
= {
1907 .name
= "local-APIC",
1908 .mask
= mask_lapic_irq
,
1909 .unmask
= unmask_lapic_irq
,
1910 .ack
= ack_lapic_irq
,
1913 static void lapic_register_intr(int irq
)
1915 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
1916 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
1920 static void __init
setup_nmi(void)
1923 * Dirty trick to enable the NMI watchdog ...
1924 * We put the 8259A master into AEOI mode and
1925 * unmask on all local APICs LVT0 as NMI.
1927 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1928 * is from Maciej W. Rozycki - so we do not have to EOI from
1929 * the NMI handler or the timer interrupt.
1931 printk(KERN_INFO
"activating NMI Watchdog ...");
1933 enable_NMI_through_LVT0();
1939 * This looks a bit hackish but it's about the only one way of sending
1940 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1941 * not support the ExtINT mode, unfortunately. We need to send these
1942 * cycles as some i82489DX-based boards have glue logic that keeps the
1943 * 8259A interrupt line asserted until INTA. --macro
1945 static inline void __init
unlock_ExtINT_logic(void)
1948 struct IO_APIC_route_entry entry0
, entry1
;
1949 unsigned char save_control
, save_freq_select
;
1951 pin
= find_isa_irq_pin(8, mp_INT
);
1952 apic
= find_isa_irq_apic(8, mp_INT
);
1956 entry0
= ioapic_read_entry(apic
, pin
);
1958 clear_IO_APIC_pin(apic
, pin
);
1960 memset(&entry1
, 0, sizeof(entry1
));
1962 entry1
.dest_mode
= 0; /* physical delivery */
1963 entry1
.mask
= 0; /* unmask IRQ now */
1964 entry1
.dest
= hard_smp_processor_id();
1965 entry1
.delivery_mode
= dest_ExtINT
;
1966 entry1
.polarity
= entry0
.polarity
;
1970 ioapic_write_entry(apic
, pin
, entry1
);
1972 save_control
= CMOS_READ(RTC_CONTROL
);
1973 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
1974 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
1976 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
1981 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
1985 CMOS_WRITE(save_control
, RTC_CONTROL
);
1986 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
1987 clear_IO_APIC_pin(apic
, pin
);
1989 ioapic_write_entry(apic
, pin
, entry0
);
1993 * This code may look a bit paranoid, but it's supposed to cooperate with
1994 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1995 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1996 * fanatically on his truly buggy board.
1998 * FIXME: really need to revamp this for modern platforms only.
2000 static inline void __init
check_timer(void)
2002 struct irq_cfg
*cfg
= irq_cfg
+ 0;
2003 int apic1
, pin1
, apic2
, pin2
;
2004 unsigned long flags
;
2007 local_irq_save(flags
);
2010 * get/set the timer IRQ vector:
2012 disable_8259A_irq(0);
2013 assign_irq_vector(0, TARGET_CPUS
);
2016 * As IRQ0 is to be enabled in the 8259A, the virtual
2017 * wire has to be disabled in the local APIC.
2019 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2022 pin1
= find_isa_irq_pin(0, mp_INT
);
2023 apic1
= find_isa_irq_apic(0, mp_INT
);
2024 pin2
= ioapic_i8259
.pin
;
2025 apic2
= ioapic_i8259
.apic
;
2027 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2028 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2029 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2032 * Some BIOS writers are clueless and report the ExtINTA
2033 * I/O APIC input from the cascaded 8259A as the timer
2034 * interrupt input. So just in case, if only one pin
2035 * was found above, try it both directly and through the
2039 if (intr_remapping_enabled
)
2040 panic("BIOS bug: timer not connected to IO-APIC");
2044 } else if (pin2
== -1) {
2051 * Ok, does IRQ0 through the IOAPIC work?
2054 add_pin_to_irq(0, apic1
, pin1
);
2055 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2057 unmask_IO_APIC_irq(0);
2058 if (!no_timer_check
&& timer_irq_works()) {
2059 if (nmi_watchdog
== NMI_IO_APIC
) {
2061 enable_8259A_irq(0);
2063 if (disable_timer_pin_1
> 0)
2064 clear_IO_APIC_pin(0, pin1
);
2067 if (intr_remapping_enabled
)
2068 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2069 clear_IO_APIC_pin(apic1
, pin1
);
2071 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2072 "8254 timer not connected to IO-APIC\n");
2074 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2075 "(IRQ0) through the 8259A ...\n");
2076 apic_printk(APIC_QUIET
, KERN_INFO
2077 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2079 * legacy devices should be connected to IO APIC #0
2081 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2082 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2083 unmask_IO_APIC_irq(0);
2084 enable_8259A_irq(0);
2085 if (timer_irq_works()) {
2086 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2087 timer_through_8259
= 1;
2088 if (nmi_watchdog
== NMI_IO_APIC
) {
2089 disable_8259A_irq(0);
2091 enable_8259A_irq(0);
2096 * Cleanup, just in case ...
2098 disable_8259A_irq(0);
2099 clear_IO_APIC_pin(apic2
, pin2
);
2100 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2103 if (nmi_watchdog
== NMI_IO_APIC
) {
2104 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2105 "through the IO-APIC - disabling NMI Watchdog!\n");
2106 nmi_watchdog
= NMI_NONE
;
2109 apic_printk(APIC_QUIET
, KERN_INFO
2110 "...trying to set up timer as Virtual Wire IRQ...\n");
2112 lapic_register_intr(0);
2113 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2114 enable_8259A_irq(0);
2116 if (timer_irq_works()) {
2117 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2120 disable_8259A_irq(0);
2121 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2122 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2124 apic_printk(APIC_QUIET
, KERN_INFO
2125 "...trying to set up timer as ExtINT IRQ...\n");
2129 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2131 unlock_ExtINT_logic();
2133 if (timer_irq_works()) {
2134 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2137 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2138 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2139 "report. Then try booting with the 'noapic' option.\n");
2141 local_irq_restore(flags
);
2144 static int __init
notimercheck(char *s
)
2149 __setup("no_timer_check", notimercheck
);
2152 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2153 * to devices. However there may be an I/O APIC pin available for
2154 * this interrupt regardless. The pin may be left unconnected, but
2155 * typically it will be reused as an ExtINT cascade interrupt for
2156 * the master 8259A. In the MPS case such a pin will normally be
2157 * reported as an ExtINT interrupt in the MP table. With ACPI
2158 * there is no provision for ExtINT interrupts, and in the absence
2159 * of an override it would be treated as an ordinary ISA I/O APIC
2160 * interrupt, that is edge-triggered and unmasked by default. We
2161 * used to do this, but it caused problems on some systems because
2162 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2163 * the same ExtINT cascade interrupt to drive the local APIC of the
2164 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2165 * the I/O APIC in all cases now. No actual device should request
2166 * it anyway. --macro
2168 #define PIC_IRQS (1<<2)
2170 void __init
setup_IO_APIC(void)
2174 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2177 io_apic_irqs
= ~PIC_IRQS
;
2179 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2182 setup_IO_APIC_irqs();
2183 init_IO_APIC_traps();
2187 struct sysfs_ioapic_data
{
2188 struct sys_device dev
;
2189 struct IO_APIC_route_entry entry
[0];
2191 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2193 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2195 struct IO_APIC_route_entry
*entry
;
2196 struct sysfs_ioapic_data
*data
;
2199 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2200 entry
= data
->entry
;
2201 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
2202 *entry
= ioapic_read_entry(dev
->id
, i
);
2207 static int ioapic_resume(struct sys_device
*dev
)
2209 struct IO_APIC_route_entry
*entry
;
2210 struct sysfs_ioapic_data
*data
;
2211 unsigned long flags
;
2212 union IO_APIC_reg_00 reg_00
;
2215 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2216 entry
= data
->entry
;
2218 spin_lock_irqsave(&ioapic_lock
, flags
);
2219 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2220 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2221 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2222 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2224 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2225 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2226 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2231 static struct sysdev_class ioapic_sysdev_class
= {
2233 .suspend
= ioapic_suspend
,
2234 .resume
= ioapic_resume
,
2237 static int __init
ioapic_init_sysfs(void)
2239 struct sys_device
* dev
;
2242 error
= sysdev_class_register(&ioapic_sysdev_class
);
2246 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2247 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2248 * sizeof(struct IO_APIC_route_entry
);
2249 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2250 if (!mp_ioapic_data
[i
]) {
2251 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2254 dev
= &mp_ioapic_data
[i
]->dev
;
2256 dev
->cls
= &ioapic_sysdev_class
;
2257 error
= sysdev_register(dev
);
2259 kfree(mp_ioapic_data
[i
]);
2260 mp_ioapic_data
[i
] = NULL
;
2261 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2269 device_initcall(ioapic_init_sysfs
);
2272 * Dynamic irq allocate and deallocation
2274 int create_irq(void)
2276 /* Allocate an unused irq */
2279 unsigned long flags
;
2282 spin_lock_irqsave(&vector_lock
, flags
);
2283 for (new = (nr_irqs
- 1); new >= 0; new--) {
2284 if (platform_legacy_irq(new))
2286 if (irq_cfg
[new].vector
!= 0)
2288 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
2292 spin_unlock_irqrestore(&vector_lock
, flags
);
2295 dynamic_irq_init(irq
);
2300 void destroy_irq(unsigned int irq
)
2302 unsigned long flags
;
2304 dynamic_irq_cleanup(irq
);
2306 #ifdef CONFIG_INTR_REMAP
2309 spin_lock_irqsave(&vector_lock
, flags
);
2310 __clear_irq_vector(irq
);
2311 spin_unlock_irqrestore(&vector_lock
, flags
);
2315 * MSI message composition
2317 #ifdef CONFIG_PCI_MSI
2318 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2320 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2326 err
= assign_irq_vector(irq
, tmp
);
2330 cpus_and(tmp
, cfg
->domain
, tmp
);
2331 dest
= cpu_mask_to_apicid(tmp
);
2333 #ifdef CONFIG_INTR_REMAP
2334 if (irq_remapped(irq
)) {
2339 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
2340 BUG_ON(ir_index
== -1);
2342 memset (&irte
, 0, sizeof(irte
));
2345 irte
.dst_mode
= INT_DEST_MODE
;
2346 irte
.trigger_mode
= 0; /* edge */
2347 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
2348 irte
.vector
= cfg
->vector
;
2349 irte
.dest_id
= IRTE_DEST(dest
);
2351 modify_irte(irq
, &irte
);
2353 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2354 msg
->data
= sub_handle
;
2355 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
2357 MSI_ADDR_IR_INDEX1(ir_index
) |
2358 MSI_ADDR_IR_INDEX2(ir_index
);
2362 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2365 ((INT_DEST_MODE
== 0) ?
2366 MSI_ADDR_DEST_MODE_PHYSICAL
:
2367 MSI_ADDR_DEST_MODE_LOGICAL
) |
2368 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2369 MSI_ADDR_REDIRECTION_CPU
:
2370 MSI_ADDR_REDIRECTION_LOWPRI
) |
2371 MSI_ADDR_DEST_ID(dest
);
2374 MSI_DATA_TRIGGER_EDGE
|
2375 MSI_DATA_LEVEL_ASSERT
|
2376 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2377 MSI_DATA_DELIVERY_FIXED
:
2378 MSI_DATA_DELIVERY_LOWPRI
) |
2379 MSI_DATA_VECTOR(cfg
->vector
);
2385 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2387 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2392 cpus_and(tmp
, mask
, cpu_online_map
);
2393 if (cpus_empty(tmp
))
2396 if (assign_irq_vector(irq
, mask
))
2399 cpus_and(tmp
, cfg
->domain
, mask
);
2400 dest
= cpu_mask_to_apicid(tmp
);
2402 read_msi_msg(irq
, &msg
);
2404 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2405 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2406 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2407 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2409 write_msi_msg(irq
, &msg
);
2410 irq_desc
[irq
].affinity
= mask
;
2413 #ifdef CONFIG_INTR_REMAP
2415 * Migrate the MSI irq to another cpumask. This migration is
2416 * done in the process context using interrupt-remapping hardware.
2418 static void ir_set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2420 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2422 cpumask_t tmp
, cleanup_mask
;
2425 cpus_and(tmp
, mask
, cpu_online_map
);
2426 if (cpus_empty(tmp
))
2429 if (get_irte(irq
, &irte
))
2432 if (assign_irq_vector(irq
, mask
))
2435 cpus_and(tmp
, cfg
->domain
, mask
);
2436 dest
= cpu_mask_to_apicid(tmp
);
2438 irte
.vector
= cfg
->vector
;
2439 irte
.dest_id
= IRTE_DEST(dest
);
2442 * atomically update the IRTE with the new destination and vector.
2444 modify_irte(irq
, &irte
);
2447 * After this point, all the interrupts will start arriving
2448 * at the new destination. So, time to cleanup the previous
2449 * vector allocation.
2451 if (cfg
->move_in_progress
) {
2452 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2453 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2454 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2455 cfg
->move_in_progress
= 0;
2458 irq_desc
[irq
].affinity
= mask
;
2461 #endif /* CONFIG_SMP */
2464 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2465 * which implement the MSI or MSI-X Capability Structure.
2467 static struct irq_chip msi_chip
= {
2469 .unmask
= unmask_msi_irq
,
2470 .mask
= mask_msi_irq
,
2471 .ack
= ack_apic_edge
,
2473 .set_affinity
= set_msi_irq_affinity
,
2475 .retrigger
= ioapic_retrigger_irq
,
2478 #ifdef CONFIG_INTR_REMAP
2479 static struct irq_chip msi_ir_chip
= {
2480 .name
= "IR-PCI-MSI",
2481 .unmask
= unmask_msi_irq
,
2482 .mask
= mask_msi_irq
,
2483 .ack
= ack_x2apic_edge
,
2485 .set_affinity
= ir_set_msi_irq_affinity
,
2487 .retrigger
= ioapic_retrigger_irq
,
2491 * Map the PCI dev to the corresponding remapping hardware unit
2492 * and allocate 'nvec' consecutive interrupt-remapping table entries
2495 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
2497 struct intel_iommu
*iommu
;
2500 iommu
= map_dev_to_ir(dev
);
2503 "Unable to map PCI %s to iommu\n", pci_name(dev
));
2507 index
= alloc_irte(iommu
, irq
, nvec
);
2510 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
2518 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
, int irq
)
2523 ret
= msi_compose_msg(dev
, irq
, &msg
);
2527 set_irq_msi(irq
, desc
);
2528 write_msi_msg(irq
, &msg
);
2530 #ifdef CONFIG_INTR_REMAP
2531 if (irq_remapped(irq
)) {
2532 struct irq_desc
*desc
= irq_desc
+ irq
;
2534 * irq migration in process context
2536 desc
->status
|= IRQ_MOVE_PCNTXT
;
2537 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
2540 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
2545 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2553 #ifdef CONFIG_INTR_REMAP
2554 if (!intr_remapping_enabled
)
2557 ret
= msi_alloc_irte(dev
, irq
, 1);
2562 ret
= setup_msi_irq(dev
, desc
, irq
);
2569 #ifdef CONFIG_INTR_REMAP
2576 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
2578 int irq
, ret
, sub_handle
;
2579 struct msi_desc
*desc
;
2580 #ifdef CONFIG_INTR_REMAP
2581 struct intel_iommu
*iommu
= 0;
2586 list_for_each_entry(desc
, &dev
->msi_list
, list
) {
2590 #ifdef CONFIG_INTR_REMAP
2591 if (!intr_remapping_enabled
)
2596 * allocate the consecutive block of IRTE's
2599 index
= msi_alloc_irte(dev
, irq
, nvec
);
2605 iommu
= map_dev_to_ir(dev
);
2611 * setup the mapping between the irq and the IRTE
2612 * base index, the sub_handle pointing to the
2613 * appropriate interrupt remap table entry.
2615 set_irte_irq(irq
, iommu
, index
, sub_handle
);
2619 ret
= setup_msi_irq(dev
, desc
, irq
);
2631 void arch_teardown_msi_irq(unsigned int irq
)
2638 static void dmar_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
2640 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2645 cpus_and(tmp
, mask
, cpu_online_map
);
2646 if (cpus_empty(tmp
))
2649 if (assign_irq_vector(irq
, mask
))
2652 cpus_and(tmp
, cfg
->domain
, mask
);
2653 dest
= cpu_mask_to_apicid(tmp
);
2655 dmar_msi_read(irq
, &msg
);
2657 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2658 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2659 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2660 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2662 dmar_msi_write(irq
, &msg
);
2663 irq_desc
[irq
].affinity
= mask
;
2665 #endif /* CONFIG_SMP */
2667 struct irq_chip dmar_msi_type
= {
2669 .unmask
= dmar_msi_unmask
,
2670 .mask
= dmar_msi_mask
,
2671 .ack
= ack_apic_edge
,
2673 .set_affinity
= dmar_msi_set_affinity
,
2675 .retrigger
= ioapic_retrigger_irq
,
2678 int arch_setup_dmar_msi(unsigned int irq
)
2683 ret
= msi_compose_msg(NULL
, irq
, &msg
);
2686 dmar_msi_write(irq
, &msg
);
2687 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
2693 #endif /* CONFIG_PCI_MSI */
2695 * Hypertransport interrupt support
2697 #ifdef CONFIG_HT_IRQ
2701 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
2703 struct ht_irq_msg msg
;
2704 fetch_ht_irq_msg(irq
, &msg
);
2706 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
2707 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2709 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
2710 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2712 write_ht_irq_msg(irq
, &msg
);
2715 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2717 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2721 cpus_and(tmp
, mask
, cpu_online_map
);
2722 if (cpus_empty(tmp
))
2725 if (assign_irq_vector(irq
, mask
))
2728 cpus_and(tmp
, cfg
->domain
, mask
);
2729 dest
= cpu_mask_to_apicid(tmp
);
2731 target_ht_irq(irq
, dest
, cfg
->vector
);
2732 irq_desc
[irq
].affinity
= mask
;
2736 static struct irq_chip ht_irq_chip
= {
2738 .mask
= mask_ht_irq
,
2739 .unmask
= unmask_ht_irq
,
2740 .ack
= ack_apic_edge
,
2742 .set_affinity
= set_ht_irq_affinity
,
2744 .retrigger
= ioapic_retrigger_irq
,
2747 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2749 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2754 err
= assign_irq_vector(irq
, tmp
);
2756 struct ht_irq_msg msg
;
2759 cpus_and(tmp
, cfg
->domain
, tmp
);
2760 dest
= cpu_mask_to_apicid(tmp
);
2762 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2766 HT_IRQ_LOW_DEST_ID(dest
) |
2767 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
2768 ((INT_DEST_MODE
== 0) ?
2769 HT_IRQ_LOW_DM_PHYSICAL
:
2770 HT_IRQ_LOW_DM_LOGICAL
) |
2771 HT_IRQ_LOW_RQEOI_EDGE
|
2772 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2773 HT_IRQ_LOW_MT_FIXED
:
2774 HT_IRQ_LOW_MT_ARBITRATED
) |
2775 HT_IRQ_LOW_IRQ_MASKED
;
2777 write_ht_irq_msg(irq
, &msg
);
2779 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2780 handle_edge_irq
, "edge");
2784 #endif /* CONFIG_HT_IRQ */
2786 /* --------------------------------------------------------------------------
2787 ACPI-based IOAPIC Configuration
2788 -------------------------------------------------------------------------- */
2792 #define IO_APIC_MAX_ID 0xFE
2794 int __init
io_apic_get_redir_entries (int ioapic
)
2796 union IO_APIC_reg_01 reg_01
;
2797 unsigned long flags
;
2799 spin_lock_irqsave(&ioapic_lock
, flags
);
2800 reg_01
.raw
= io_apic_read(ioapic
, 1);
2801 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2803 return reg_01
.bits
.entries
;
2807 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
2809 if (!IO_APIC_IRQ(irq
)) {
2810 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2816 * IRQs < 16 are already in the irq_2_pin[] map
2819 add_pin_to_irq(irq
, ioapic
, pin
);
2821 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
2827 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2831 if (skip_ioapic_setup
)
2834 for (i
= 0; i
< mp_irq_entries
; i
++)
2835 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
2836 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
2838 if (i
>= mp_irq_entries
)
2841 *trigger
= irq_trigger(i
);
2842 *polarity
= irq_polarity(i
);
2846 #endif /* CONFIG_ACPI */
2849 * This function currently is only a helper for the i386 smp boot process where
2850 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2851 * so mask in all cases should simply be TARGET_CPUS
2854 void __init
setup_ioapic_dest(void)
2856 int pin
, ioapic
, irq
, irq_entry
;
2858 if (skip_ioapic_setup
== 1)
2861 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
2862 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
2863 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
2864 if (irq_entry
== -1)
2866 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
2868 /* setup_IO_APIC_irqs could fail to get vector for some device
2869 * when you have too many devices, because at that time only boot
2872 if (!irq_cfg
[irq
].vector
)
2873 setup_IO_APIC_irq(ioapic
, pin
, irq
,
2874 irq_trigger(irq_entry
),
2875 irq_polarity(irq_entry
));
2876 #ifdef CONFIG_INTR_REMAP
2877 else if (intr_remapping_enabled
)
2878 set_ir_ioapic_affinity_irq(irq
, TARGET_CPUS
);
2881 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
2888 #define IOAPIC_RESOURCE_NAME_SIZE 11
2890 static struct resource
*ioapic_resources
;
2892 static struct resource
* __init
ioapic_setup_resources(void)
2895 struct resource
*res
;
2899 if (nr_ioapics
<= 0)
2902 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
2905 mem
= alloc_bootmem(n
);
2909 mem
+= sizeof(struct resource
) * nr_ioapics
;
2911 for (i
= 0; i
< nr_ioapics
; i
++) {
2913 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
2914 sprintf(mem
, "IOAPIC %u", i
);
2915 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
2919 ioapic_resources
= res
;
2924 void __init
ioapic_init_mappings(void)
2926 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2927 struct resource
*ioapic_res
;
2930 ioapic_res
= ioapic_setup_resources();
2931 for (i
= 0; i
< nr_ioapics
; i
++) {
2932 if (smp_found_config
) {
2933 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
2935 ioapic_phys
= (unsigned long)
2936 alloc_bootmem_pages(PAGE_SIZE
);
2937 ioapic_phys
= __pa(ioapic_phys
);
2939 set_fixmap_nocache(idx
, ioapic_phys
);
2940 apic_printk(APIC_VERBOSE
,
2941 "mapped IOAPIC to %016lx (%016lx)\n",
2942 __fix_to_virt(idx
), ioapic_phys
);
2945 if (ioapic_res
!= NULL
) {
2946 ioapic_res
->start
= ioapic_phys
;
2947 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
2953 static int __init
ioapic_insert_resources(void)
2956 struct resource
*r
= ioapic_resources
;
2960 "IO APIC resources could be not be allocated.\n");
2964 for (i
= 0; i
< nr_ioapics
; i
++) {
2965 insert_resource(&iomem_resource
, r
);
2972 /* Insert the IO APIC resources after PCI initialization has occured to handle
2973 * IO APICS that are mapped in on a BAR in PCI space. */
2974 late_initcall(ioapic_insert_resources
);