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Merge branch 'x86/cleanups' into x86/signal
[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40 #include <linux/dmar.h>
41
42 #include <asm/idle.h>
43 #include <asm/io.h>
44 #include <asm/smp.h>
45 #include <asm/desc.h>
46 #include <asm/proto.h>
47 #include <asm/acpi.h>
48 #include <asm/dma.h>
49 #include <asm/i8259.h>
50 #include <asm/nmi.h>
51 #include <asm/msidef.h>
52 #include <asm/hypertransport.h>
53 #include <asm/irq_remapping.h>
54
55 #include <mach_ipi.h>
56 #include <mach_apic.h>
57
58 struct irq_cfg {
59 cpumask_t domain;
60 cpumask_t old_domain;
61 unsigned move_cleanup_count;
62 u8 vector;
63 u8 move_in_progress : 1;
64 };
65
66 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
67 static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
68 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
69 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
70 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
71 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
72 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
73 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
74 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
75 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
76 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
77 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
78 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
79 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
80 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
81 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
82 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
83 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
84 };
85
86 static int assign_irq_vector(int irq, cpumask_t mask);
87
88 int first_system_vector = 0xfe;
89
90 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
91
92 #define __apicdebuginit __init
93
94 int sis_apic_bug; /* not actually supported, dummy for compile */
95
96 static int no_timer_check;
97
98 static int disable_timer_pin_1 __initdata;
99
100 int timer_through_8259 __initdata;
101
102 /* Where if anywhere is the i8259 connect in external int mode */
103 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
104
105 static DEFINE_SPINLOCK(ioapic_lock);
106 static DEFINE_SPINLOCK(vector_lock);
107
108 /*
109 * # of IRQ routing registers
110 */
111 int nr_ioapic_registers[MAX_IO_APICS];
112
113 /* I/O APIC RTE contents at the OS boot up */
114 struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
115
116 /* I/O APIC entries */
117 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
118 int nr_ioapics;
119
120 /* MP IRQ source entries */
121 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
122
123 /* # of MP IRQ source entries */
124 int mp_irq_entries;
125
126 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
127
128 /*
129 * Rough estimation of how many shared IRQs there are, can
130 * be changed anytime.
131 */
132 #define MAX_PLUS_SHARED_IRQS NR_IRQS
133 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
134
135 /*
136 * This is performance-critical, we want to do it O(1)
137 *
138 * the indexing order of this array favors 1:1 mappings
139 * between pins and IRQs.
140 */
141
142 static struct irq_pin_list {
143 short apic, pin, next;
144 } irq_2_pin[PIN_MAP_SIZE];
145
146 struct io_apic {
147 unsigned int index;
148 unsigned int unused[3];
149 unsigned int data;
150 };
151
152 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
153 {
154 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
155 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
156 }
157
158 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
159 {
160 struct io_apic __iomem *io_apic = io_apic_base(apic);
161 writel(reg, &io_apic->index);
162 return readl(&io_apic->data);
163 }
164
165 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
166 {
167 struct io_apic __iomem *io_apic = io_apic_base(apic);
168 writel(reg, &io_apic->index);
169 writel(value, &io_apic->data);
170 }
171
172 /*
173 * Re-write a value: to be used for read-modify-write
174 * cycles where the read already set up the index register.
175 */
176 static inline void io_apic_modify(unsigned int apic, unsigned int value)
177 {
178 struct io_apic __iomem *io_apic = io_apic_base(apic);
179 writel(value, &io_apic->data);
180 }
181
182 static bool io_apic_level_ack_pending(unsigned int irq)
183 {
184 struct irq_pin_list *entry;
185 unsigned long flags;
186
187 spin_lock_irqsave(&ioapic_lock, flags);
188 entry = irq_2_pin + irq;
189 for (;;) {
190 unsigned int reg;
191 int pin;
192
193 pin = entry->pin;
194 if (pin == -1)
195 break;
196 reg = io_apic_read(entry->apic, 0x10 + pin*2);
197 /* Is the remote IRR bit set? */
198 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
199 spin_unlock_irqrestore(&ioapic_lock, flags);
200 return true;
201 }
202 if (!entry->next)
203 break;
204 entry = irq_2_pin + entry->next;
205 }
206 spin_unlock_irqrestore(&ioapic_lock, flags);
207
208 return false;
209 }
210
211 /*
212 * Synchronize the IO-APIC and the CPU by doing
213 * a dummy read from the IO-APIC
214 */
215 static inline void io_apic_sync(unsigned int apic)
216 {
217 struct io_apic __iomem *io_apic = io_apic_base(apic);
218 readl(&io_apic->data);
219 }
220
221 #define __DO_ACTION(R, ACTION, FINAL) \
222 \
223 { \
224 int pin; \
225 struct irq_pin_list *entry = irq_2_pin + irq; \
226 \
227 BUG_ON(irq >= NR_IRQS); \
228 for (;;) { \
229 unsigned int reg; \
230 pin = entry->pin; \
231 if (pin == -1) \
232 break; \
233 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
234 reg ACTION; \
235 io_apic_modify(entry->apic, reg); \
236 FINAL; \
237 if (!entry->next) \
238 break; \
239 entry = irq_2_pin + entry->next; \
240 } \
241 }
242
243 union entry_union {
244 struct { u32 w1, w2; };
245 struct IO_APIC_route_entry entry;
246 };
247
248 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
249 {
250 union entry_union eu;
251 unsigned long flags;
252 spin_lock_irqsave(&ioapic_lock, flags);
253 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
254 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
255 spin_unlock_irqrestore(&ioapic_lock, flags);
256 return eu.entry;
257 }
258
259 /*
260 * When we write a new IO APIC routing entry, we need to write the high
261 * word first! If the mask bit in the low word is clear, we will enable
262 * the interrupt, and we need to make sure the entry is fully populated
263 * before that happens.
264 */
265 static void
266 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
267 {
268 union entry_union eu;
269 eu.entry = e;
270 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
271 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
272 }
273
274 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
275 {
276 unsigned long flags;
277 spin_lock_irqsave(&ioapic_lock, flags);
278 __ioapic_write_entry(apic, pin, e);
279 spin_unlock_irqrestore(&ioapic_lock, flags);
280 }
281
282 /*
283 * When we mask an IO APIC routing entry, we need to write the low
284 * word first, in order to set the mask bit before we change the
285 * high bits!
286 */
287 static void ioapic_mask_entry(int apic, int pin)
288 {
289 unsigned long flags;
290 union entry_union eu = { .entry.mask = 1 };
291
292 spin_lock_irqsave(&ioapic_lock, flags);
293 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
294 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
295 spin_unlock_irqrestore(&ioapic_lock, flags);
296 }
297
298 #ifdef CONFIG_SMP
299 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
300 {
301 int apic, pin;
302 struct irq_pin_list *entry = irq_2_pin + irq;
303
304 BUG_ON(irq >= NR_IRQS);
305 for (;;) {
306 unsigned int reg;
307 apic = entry->apic;
308 pin = entry->pin;
309 if (pin == -1)
310 break;
311 /*
312 * With interrupt-remapping, destination information comes
313 * from interrupt-remapping table entry.
314 */
315 if (!irq_remapped(irq))
316 io_apic_write(apic, 0x11 + pin*2, dest);
317 reg = io_apic_read(apic, 0x10 + pin*2);
318 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
319 reg |= vector;
320 io_apic_modify(apic, reg);
321 if (!entry->next)
322 break;
323 entry = irq_2_pin + entry->next;
324 }
325 }
326
327 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
328 {
329 struct irq_cfg *cfg = irq_cfg + irq;
330 unsigned long flags;
331 unsigned int dest;
332 cpumask_t tmp;
333
334 cpus_and(tmp, mask, cpu_online_map);
335 if (cpus_empty(tmp))
336 return;
337
338 if (assign_irq_vector(irq, mask))
339 return;
340
341 cpus_and(tmp, cfg->domain, mask);
342 dest = cpu_mask_to_apicid(tmp);
343
344 /*
345 * Only the high 8 bits are valid.
346 */
347 dest = SET_APIC_LOGICAL_ID(dest);
348
349 spin_lock_irqsave(&ioapic_lock, flags);
350 __target_IO_APIC_irq(irq, dest, cfg->vector);
351 irq_desc[irq].affinity = mask;
352 spin_unlock_irqrestore(&ioapic_lock, flags);
353 }
354 #endif
355
356 /*
357 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
358 * shared ISA-space IRQs, so we have to support them. We are super
359 * fast in the common case, and fast for shared ISA-space IRQs.
360 */
361 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
362 {
363 static int first_free_entry = NR_IRQS;
364 struct irq_pin_list *entry = irq_2_pin + irq;
365
366 BUG_ON(irq >= NR_IRQS);
367 while (entry->next)
368 entry = irq_2_pin + entry->next;
369
370 if (entry->pin != -1) {
371 entry->next = first_free_entry;
372 entry = irq_2_pin + entry->next;
373 if (++first_free_entry >= PIN_MAP_SIZE)
374 panic("io_apic.c: ran out of irq_2_pin entries!");
375 }
376 entry->apic = apic;
377 entry->pin = pin;
378 }
379
380 /*
381 * Reroute an IRQ to a different pin.
382 */
383 static void __init replace_pin_at_irq(unsigned int irq,
384 int oldapic, int oldpin,
385 int newapic, int newpin)
386 {
387 struct irq_pin_list *entry = irq_2_pin + irq;
388
389 while (1) {
390 if (entry->apic == oldapic && entry->pin == oldpin) {
391 entry->apic = newapic;
392 entry->pin = newpin;
393 }
394 if (!entry->next)
395 break;
396 entry = irq_2_pin + entry->next;
397 }
398 }
399
400
401 #define DO_ACTION(name,R,ACTION, FINAL) \
402 \
403 static void name##_IO_APIC_irq (unsigned int irq) \
404 __DO_ACTION(R, ACTION, FINAL)
405
406 /* mask = 1 */
407 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
408
409 /* mask = 0 */
410 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
411
412 static void mask_IO_APIC_irq (unsigned int irq)
413 {
414 unsigned long flags;
415
416 spin_lock_irqsave(&ioapic_lock, flags);
417 __mask_IO_APIC_irq(irq);
418 spin_unlock_irqrestore(&ioapic_lock, flags);
419 }
420
421 static void unmask_IO_APIC_irq (unsigned int irq)
422 {
423 unsigned long flags;
424
425 spin_lock_irqsave(&ioapic_lock, flags);
426 __unmask_IO_APIC_irq(irq);
427 spin_unlock_irqrestore(&ioapic_lock, flags);
428 }
429
430 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
431 {
432 struct IO_APIC_route_entry entry;
433
434 /* Check delivery_mode to be sure we're not clearing an SMI pin */
435 entry = ioapic_read_entry(apic, pin);
436 if (entry.delivery_mode == dest_SMI)
437 return;
438 /*
439 * Disable it in the IO-APIC irq-routing table:
440 */
441 ioapic_mask_entry(apic, pin);
442 }
443
444 static void clear_IO_APIC (void)
445 {
446 int apic, pin;
447
448 for (apic = 0; apic < nr_ioapics; apic++)
449 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
450 clear_IO_APIC_pin(apic, pin);
451 }
452
453 /*
454 * Saves and masks all the unmasked IO-APIC RTE's
455 */
456 int save_mask_IO_APIC_setup(void)
457 {
458 union IO_APIC_reg_01 reg_01;
459 unsigned long flags;
460 int apic, pin;
461
462 /*
463 * The number of IO-APIC IRQ registers (== #pins):
464 */
465 for (apic = 0; apic < nr_ioapics; apic++) {
466 spin_lock_irqsave(&ioapic_lock, flags);
467 reg_01.raw = io_apic_read(apic, 1);
468 spin_unlock_irqrestore(&ioapic_lock, flags);
469 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
470 }
471
472 for (apic = 0; apic < nr_ioapics; apic++) {
473 early_ioapic_entries[apic] =
474 kzalloc(sizeof(struct IO_APIC_route_entry) *
475 nr_ioapic_registers[apic], GFP_KERNEL);
476 if (!early_ioapic_entries[apic])
477 return -ENOMEM;
478 }
479
480 for (apic = 0; apic < nr_ioapics; apic++)
481 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
482 struct IO_APIC_route_entry entry;
483
484 entry = early_ioapic_entries[apic][pin] =
485 ioapic_read_entry(apic, pin);
486 if (!entry.mask) {
487 entry.mask = 1;
488 ioapic_write_entry(apic, pin, entry);
489 }
490 }
491 return 0;
492 }
493
494 void restore_IO_APIC_setup(void)
495 {
496 int apic, pin;
497
498 for (apic = 0; apic < nr_ioapics; apic++)
499 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
500 ioapic_write_entry(apic, pin,
501 early_ioapic_entries[apic][pin]);
502 }
503
504 void reinit_intr_remapped_IO_APIC(int intr_remapping)
505 {
506 /*
507 * for now plain restore of previous settings.
508 * TBD: In the case of OS enabling interrupt-remapping,
509 * IO-APIC RTE's need to be setup to point to interrupt-remapping
510 * table entries. for now, do a plain restore, and wait for
511 * the setup_IO_APIC_irqs() to do proper initialization.
512 */
513 restore_IO_APIC_setup();
514 }
515
516 int skip_ioapic_setup;
517 int ioapic_force;
518
519 static int __init parse_noapic(char *str)
520 {
521 disable_ioapic_setup();
522 return 0;
523 }
524 early_param("noapic", parse_noapic);
525
526 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
527 static int __init disable_timer_pin_setup(char *arg)
528 {
529 disable_timer_pin_1 = 1;
530 return 1;
531 }
532 __setup("disable_timer_pin_1", disable_timer_pin_setup);
533
534
535 /*
536 * Find the IRQ entry number of a certain pin.
537 */
538 static int find_irq_entry(int apic, int pin, int type)
539 {
540 int i;
541
542 for (i = 0; i < mp_irq_entries; i++)
543 if (mp_irqs[i].mp_irqtype == type &&
544 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
545 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
546 mp_irqs[i].mp_dstirq == pin)
547 return i;
548
549 return -1;
550 }
551
552 /*
553 * Find the pin to which IRQ[irq] (ISA) is connected
554 */
555 static int __init find_isa_irq_pin(int irq, int type)
556 {
557 int i;
558
559 for (i = 0; i < mp_irq_entries; i++) {
560 int lbus = mp_irqs[i].mp_srcbus;
561
562 if (test_bit(lbus, mp_bus_not_pci) &&
563 (mp_irqs[i].mp_irqtype == type) &&
564 (mp_irqs[i].mp_srcbusirq == irq))
565
566 return mp_irqs[i].mp_dstirq;
567 }
568 return -1;
569 }
570
571 static int __init find_isa_irq_apic(int irq, int type)
572 {
573 int i;
574
575 for (i = 0; i < mp_irq_entries; i++) {
576 int lbus = mp_irqs[i].mp_srcbus;
577
578 if (test_bit(lbus, mp_bus_not_pci) &&
579 (mp_irqs[i].mp_irqtype == type) &&
580 (mp_irqs[i].mp_srcbusirq == irq))
581 break;
582 }
583 if (i < mp_irq_entries) {
584 int apic;
585 for(apic = 0; apic < nr_ioapics; apic++) {
586 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
587 return apic;
588 }
589 }
590
591 return -1;
592 }
593
594 /*
595 * Find a specific PCI IRQ entry.
596 * Not an __init, possibly needed by modules
597 */
598 static int pin_2_irq(int idx, int apic, int pin);
599
600 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
601 {
602 int apic, i, best_guess = -1;
603
604 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
605 bus, slot, pin);
606 if (test_bit(bus, mp_bus_not_pci)) {
607 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
608 return -1;
609 }
610 for (i = 0; i < mp_irq_entries; i++) {
611 int lbus = mp_irqs[i].mp_srcbus;
612
613 for (apic = 0; apic < nr_ioapics; apic++)
614 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
615 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
616 break;
617
618 if (!test_bit(lbus, mp_bus_not_pci) &&
619 !mp_irqs[i].mp_irqtype &&
620 (bus == lbus) &&
621 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
622 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
623
624 if (!(apic || IO_APIC_IRQ(irq)))
625 continue;
626
627 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
628 return irq;
629 /*
630 * Use the first all-but-pin matching entry as a
631 * best-guess fuzzy result for broken mptables.
632 */
633 if (best_guess < 0)
634 best_guess = irq;
635 }
636 }
637 BUG_ON(best_guess >= NR_IRQS);
638 return best_guess;
639 }
640
641 /* ISA interrupts are always polarity zero edge triggered,
642 * when listed as conforming in the MP table. */
643
644 #define default_ISA_trigger(idx) (0)
645 #define default_ISA_polarity(idx) (0)
646
647 /* PCI interrupts are always polarity one level triggered,
648 * when listed as conforming in the MP table. */
649
650 #define default_PCI_trigger(idx) (1)
651 #define default_PCI_polarity(idx) (1)
652
653 static int MPBIOS_polarity(int idx)
654 {
655 int bus = mp_irqs[idx].mp_srcbus;
656 int polarity;
657
658 /*
659 * Determine IRQ line polarity (high active or low active):
660 */
661 switch (mp_irqs[idx].mp_irqflag & 3)
662 {
663 case 0: /* conforms, ie. bus-type dependent polarity */
664 if (test_bit(bus, mp_bus_not_pci))
665 polarity = default_ISA_polarity(idx);
666 else
667 polarity = default_PCI_polarity(idx);
668 break;
669 case 1: /* high active */
670 {
671 polarity = 0;
672 break;
673 }
674 case 2: /* reserved */
675 {
676 printk(KERN_WARNING "broken BIOS!!\n");
677 polarity = 1;
678 break;
679 }
680 case 3: /* low active */
681 {
682 polarity = 1;
683 break;
684 }
685 default: /* invalid */
686 {
687 printk(KERN_WARNING "broken BIOS!!\n");
688 polarity = 1;
689 break;
690 }
691 }
692 return polarity;
693 }
694
695 static int MPBIOS_trigger(int idx)
696 {
697 int bus = mp_irqs[idx].mp_srcbus;
698 int trigger;
699
700 /*
701 * Determine IRQ trigger mode (edge or level sensitive):
702 */
703 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
704 {
705 case 0: /* conforms, ie. bus-type dependent */
706 if (test_bit(bus, mp_bus_not_pci))
707 trigger = default_ISA_trigger(idx);
708 else
709 trigger = default_PCI_trigger(idx);
710 break;
711 case 1: /* edge */
712 {
713 trigger = 0;
714 break;
715 }
716 case 2: /* reserved */
717 {
718 printk(KERN_WARNING "broken BIOS!!\n");
719 trigger = 1;
720 break;
721 }
722 case 3: /* level */
723 {
724 trigger = 1;
725 break;
726 }
727 default: /* invalid */
728 {
729 printk(KERN_WARNING "broken BIOS!!\n");
730 trigger = 0;
731 break;
732 }
733 }
734 return trigger;
735 }
736
737 static inline int irq_polarity(int idx)
738 {
739 return MPBIOS_polarity(idx);
740 }
741
742 static inline int irq_trigger(int idx)
743 {
744 return MPBIOS_trigger(idx);
745 }
746
747 static int pin_2_irq(int idx, int apic, int pin)
748 {
749 int irq, i;
750 int bus = mp_irqs[idx].mp_srcbus;
751
752 /*
753 * Debugging check, we are in big trouble if this message pops up!
754 */
755 if (mp_irqs[idx].mp_dstirq != pin)
756 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
757
758 if (test_bit(bus, mp_bus_not_pci)) {
759 irq = mp_irqs[idx].mp_srcbusirq;
760 } else {
761 /*
762 * PCI IRQs are mapped in order
763 */
764 i = irq = 0;
765 while (i < apic)
766 irq += nr_ioapic_registers[i++];
767 irq += pin;
768 }
769 BUG_ON(irq >= NR_IRQS);
770 return irq;
771 }
772
773 void lock_vector_lock(void)
774 {
775 /* Used to the online set of cpus does not change
776 * during assign_irq_vector.
777 */
778 spin_lock(&vector_lock);
779 }
780
781 void unlock_vector_lock(void)
782 {
783 spin_unlock(&vector_lock);
784 }
785
786 static int __assign_irq_vector(int irq, cpumask_t mask)
787 {
788 /*
789 * NOTE! The local APIC isn't very good at handling
790 * multiple interrupts at the same interrupt level.
791 * As the interrupt level is determined by taking the
792 * vector number and shifting that right by 4, we
793 * want to spread these out a bit so that they don't
794 * all fall in the same interrupt level.
795 *
796 * Also, we've got to be careful not to trash gate
797 * 0x80, because int 0x80 is hm, kind of importantish. ;)
798 */
799 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
800 unsigned int old_vector;
801 int cpu;
802 struct irq_cfg *cfg;
803
804 BUG_ON((unsigned)irq >= NR_IRQS);
805 cfg = &irq_cfg[irq];
806
807 /* Only try and allocate irqs on cpus that are present */
808 cpus_and(mask, mask, cpu_online_map);
809
810 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
811 return -EBUSY;
812
813 old_vector = cfg->vector;
814 if (old_vector) {
815 cpumask_t tmp;
816 cpus_and(tmp, cfg->domain, mask);
817 if (!cpus_empty(tmp))
818 return 0;
819 }
820
821 for_each_cpu_mask_nr(cpu, mask) {
822 cpumask_t domain, new_mask;
823 int new_cpu;
824 int vector, offset;
825
826 domain = vector_allocation_domain(cpu);
827 cpus_and(new_mask, domain, cpu_online_map);
828
829 vector = current_vector;
830 offset = current_offset;
831 next:
832 vector += 8;
833 if (vector >= first_system_vector) {
834 /* If we run out of vectors on large boxen, must share them. */
835 offset = (offset + 1) % 8;
836 vector = FIRST_DEVICE_VECTOR + offset;
837 }
838 if (unlikely(current_vector == vector))
839 continue;
840 if (vector == IA32_SYSCALL_VECTOR)
841 goto next;
842 for_each_cpu_mask_nr(new_cpu, new_mask)
843 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
844 goto next;
845 /* Found one! */
846 current_vector = vector;
847 current_offset = offset;
848 if (old_vector) {
849 cfg->move_in_progress = 1;
850 cfg->old_domain = cfg->domain;
851 }
852 for_each_cpu_mask_nr(new_cpu, new_mask)
853 per_cpu(vector_irq, new_cpu)[vector] = irq;
854 cfg->vector = vector;
855 cfg->domain = domain;
856 return 0;
857 }
858 return -ENOSPC;
859 }
860
861 static int assign_irq_vector(int irq, cpumask_t mask)
862 {
863 int err;
864 unsigned long flags;
865
866 spin_lock_irqsave(&vector_lock, flags);
867 err = __assign_irq_vector(irq, mask);
868 spin_unlock_irqrestore(&vector_lock, flags);
869 return err;
870 }
871
872 static void __clear_irq_vector(int irq)
873 {
874 struct irq_cfg *cfg;
875 cpumask_t mask;
876 int cpu, vector;
877
878 BUG_ON((unsigned)irq >= NR_IRQS);
879 cfg = &irq_cfg[irq];
880 BUG_ON(!cfg->vector);
881
882 vector = cfg->vector;
883 cpus_and(mask, cfg->domain, cpu_online_map);
884 for_each_cpu_mask_nr(cpu, mask)
885 per_cpu(vector_irq, cpu)[vector] = -1;
886
887 cfg->vector = 0;
888 cpus_clear(cfg->domain);
889 }
890
891 void __setup_vector_irq(int cpu)
892 {
893 /* Initialize vector_irq on a new cpu */
894 /* This function must be called with vector_lock held */
895 int irq, vector;
896
897 /* Mark the inuse vectors */
898 for (irq = 0; irq < NR_IRQS; ++irq) {
899 if (!cpu_isset(cpu, irq_cfg[irq].domain))
900 continue;
901 vector = irq_cfg[irq].vector;
902 per_cpu(vector_irq, cpu)[vector] = irq;
903 }
904 /* Mark the free vectors */
905 for (vector = 0; vector < NR_VECTORS; ++vector) {
906 irq = per_cpu(vector_irq, cpu)[vector];
907 if (irq < 0)
908 continue;
909 if (!cpu_isset(cpu, irq_cfg[irq].domain))
910 per_cpu(vector_irq, cpu)[vector] = -1;
911 }
912 }
913
914 static struct irq_chip ioapic_chip;
915 #ifdef CONFIG_INTR_REMAP
916 static struct irq_chip ir_ioapic_chip;
917 #endif
918
919 static void ioapic_register_intr(int irq, unsigned long trigger)
920 {
921 if (trigger)
922 irq_desc[irq].status |= IRQ_LEVEL;
923 else
924 irq_desc[irq].status &= ~IRQ_LEVEL;
925
926 #ifdef CONFIG_INTR_REMAP
927 if (irq_remapped(irq)) {
928 irq_desc[irq].status |= IRQ_MOVE_PCNTXT;
929 if (trigger)
930 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
931 handle_fasteoi_irq,
932 "fasteoi");
933 else
934 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
935 handle_edge_irq, "edge");
936 return;
937 }
938 #endif
939 if (trigger)
940 set_irq_chip_and_handler_name(irq, &ioapic_chip,
941 handle_fasteoi_irq,
942 "fasteoi");
943 else
944 set_irq_chip_and_handler_name(irq, &ioapic_chip,
945 handle_edge_irq, "edge");
946 }
947
948 static int setup_ioapic_entry(int apic, int irq,
949 struct IO_APIC_route_entry *entry,
950 unsigned int destination, int trigger,
951 int polarity, int vector)
952 {
953 /*
954 * add it to the IO-APIC irq-routing table:
955 */
956 memset(entry,0,sizeof(*entry));
957
958 #ifdef CONFIG_INTR_REMAP
959 if (intr_remapping_enabled) {
960 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
961 struct irte irte;
962 struct IR_IO_APIC_route_entry *ir_entry =
963 (struct IR_IO_APIC_route_entry *) entry;
964 int index;
965
966 if (!iommu)
967 panic("No mapping iommu for ioapic %d\n", apic);
968
969 index = alloc_irte(iommu, irq, 1);
970 if (index < 0)
971 panic("Failed to allocate IRTE for ioapic %d\n", apic);
972
973 memset(&irte, 0, sizeof(irte));
974
975 irte.present = 1;
976 irte.dst_mode = INT_DEST_MODE;
977 irte.trigger_mode = trigger;
978 irte.dlvry_mode = INT_DELIVERY_MODE;
979 irte.vector = vector;
980 irte.dest_id = IRTE_DEST(destination);
981
982 modify_irte(irq, &irte);
983
984 ir_entry->index2 = (index >> 15) & 0x1;
985 ir_entry->zero = 0;
986 ir_entry->format = 1;
987 ir_entry->index = (index & 0x7fff);
988 } else
989 #endif
990 {
991 entry->delivery_mode = INT_DELIVERY_MODE;
992 entry->dest_mode = INT_DEST_MODE;
993 entry->dest = destination;
994 }
995
996 entry->mask = 0; /* enable IRQ */
997 entry->trigger = trigger;
998 entry->polarity = polarity;
999 entry->vector = vector;
1000
1001 /* Mask level triggered irqs.
1002 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1003 */
1004 if (trigger)
1005 entry->mask = 1;
1006 return 0;
1007 }
1008
1009 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1010 int trigger, int polarity)
1011 {
1012 struct irq_cfg *cfg = irq_cfg + irq;
1013 struct IO_APIC_route_entry entry;
1014 cpumask_t mask;
1015
1016 if (!IO_APIC_IRQ(irq))
1017 return;
1018
1019 mask = TARGET_CPUS;
1020 if (assign_irq_vector(irq, mask))
1021 return;
1022
1023 cpus_and(mask, cfg->domain, mask);
1024
1025 apic_printk(APIC_VERBOSE,KERN_DEBUG
1026 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1027 "IRQ %d Mode:%i Active:%i)\n",
1028 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1029 irq, trigger, polarity);
1030
1031
1032 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1033 cpu_mask_to_apicid(mask), trigger, polarity,
1034 cfg->vector)) {
1035 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1036 mp_ioapics[apic].mp_apicid, pin);
1037 __clear_irq_vector(irq);
1038 return;
1039 }
1040
1041 ioapic_register_intr(irq, trigger);
1042 if (irq < 16)
1043 disable_8259A_irq(irq);
1044
1045 ioapic_write_entry(apic, pin, entry);
1046 }
1047
1048 static void __init setup_IO_APIC_irqs(void)
1049 {
1050 int apic, pin, idx, irq, first_notcon = 1;
1051
1052 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1053
1054 for (apic = 0; apic < nr_ioapics; apic++) {
1055 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1056
1057 idx = find_irq_entry(apic,pin,mp_INT);
1058 if (idx == -1) {
1059 if (first_notcon) {
1060 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1061 first_notcon = 0;
1062 } else
1063 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1064 continue;
1065 }
1066 if (!first_notcon) {
1067 apic_printk(APIC_VERBOSE, " not connected.\n");
1068 first_notcon = 1;
1069 }
1070
1071 irq = pin_2_irq(idx, apic, pin);
1072 add_pin_to_irq(irq, apic, pin);
1073
1074 setup_IO_APIC_irq(apic, pin, irq,
1075 irq_trigger(idx), irq_polarity(idx));
1076 }
1077 }
1078
1079 if (!first_notcon)
1080 apic_printk(APIC_VERBOSE, " not connected.\n");
1081 }
1082
1083 /*
1084 * Set up the timer pin, possibly with the 8259A-master behind.
1085 */
1086 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1087 int vector)
1088 {
1089 struct IO_APIC_route_entry entry;
1090
1091 if (intr_remapping_enabled)
1092 return;
1093
1094 memset(&entry, 0, sizeof(entry));
1095
1096 /*
1097 * We use logical delivery to get the timer IRQ
1098 * to the first CPU.
1099 */
1100 entry.dest_mode = INT_DEST_MODE;
1101 entry.mask = 1; /* mask IRQ now */
1102 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1103 entry.delivery_mode = INT_DELIVERY_MODE;
1104 entry.polarity = 0;
1105 entry.trigger = 0;
1106 entry.vector = vector;
1107
1108 /*
1109 * The timer IRQ doesn't have to know that behind the
1110 * scene we may have a 8259A-master in AEOI mode ...
1111 */
1112 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1113
1114 /*
1115 * Add it to the IO-APIC irq-routing table:
1116 */
1117 ioapic_write_entry(apic, pin, entry);
1118 }
1119
1120 void __apicdebuginit print_IO_APIC(void)
1121 {
1122 int apic, i;
1123 union IO_APIC_reg_00 reg_00;
1124 union IO_APIC_reg_01 reg_01;
1125 union IO_APIC_reg_02 reg_02;
1126 unsigned long flags;
1127
1128 if (apic_verbosity == APIC_QUIET)
1129 return;
1130
1131 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1132 for (i = 0; i < nr_ioapics; i++)
1133 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1134 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1135
1136 /*
1137 * We are a bit conservative about what we expect. We have to
1138 * know about every hardware change ASAP.
1139 */
1140 printk(KERN_INFO "testing the IO APIC.......................\n");
1141
1142 for (apic = 0; apic < nr_ioapics; apic++) {
1143
1144 spin_lock_irqsave(&ioapic_lock, flags);
1145 reg_00.raw = io_apic_read(apic, 0);
1146 reg_01.raw = io_apic_read(apic, 1);
1147 if (reg_01.bits.version >= 0x10)
1148 reg_02.raw = io_apic_read(apic, 2);
1149 spin_unlock_irqrestore(&ioapic_lock, flags);
1150
1151 printk("\n");
1152 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1153 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1154 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1155
1156 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1157 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1158
1159 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1160 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1161
1162 if (reg_01.bits.version >= 0x10) {
1163 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1164 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1165 }
1166
1167 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1168
1169 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1170 " Stat Dmod Deli Vect: \n");
1171
1172 for (i = 0; i <= reg_01.bits.entries; i++) {
1173 struct IO_APIC_route_entry entry;
1174
1175 entry = ioapic_read_entry(apic, i);
1176
1177 printk(KERN_DEBUG " %02x %03X ",
1178 i,
1179 entry.dest
1180 );
1181
1182 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1183 entry.mask,
1184 entry.trigger,
1185 entry.irr,
1186 entry.polarity,
1187 entry.delivery_status,
1188 entry.dest_mode,
1189 entry.delivery_mode,
1190 entry.vector
1191 );
1192 }
1193 }
1194 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1195 for (i = 0; i < NR_IRQS; i++) {
1196 struct irq_pin_list *entry = irq_2_pin + i;
1197 if (entry->pin < 0)
1198 continue;
1199 printk(KERN_DEBUG "IRQ%d ", i);
1200 for (;;) {
1201 printk("-> %d:%d", entry->apic, entry->pin);
1202 if (!entry->next)
1203 break;
1204 entry = irq_2_pin + entry->next;
1205 }
1206 printk("\n");
1207 }
1208
1209 printk(KERN_INFO ".................................... done.\n");
1210
1211 return;
1212 }
1213
1214 #if 0
1215
1216 static __apicdebuginit void print_APIC_bitfield (int base)
1217 {
1218 unsigned int v;
1219 int i, j;
1220
1221 if (apic_verbosity == APIC_QUIET)
1222 return;
1223
1224 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1225 for (i = 0; i < 8; i++) {
1226 v = apic_read(base + i*0x10);
1227 for (j = 0; j < 32; j++) {
1228 if (v & (1<<j))
1229 printk("1");
1230 else
1231 printk("0");
1232 }
1233 printk("\n");
1234 }
1235 }
1236
1237 void __apicdebuginit print_local_APIC(void * dummy)
1238 {
1239 unsigned int v, ver, maxlvt;
1240 unsigned long icr;
1241
1242 if (apic_verbosity == APIC_QUIET)
1243 return;
1244
1245 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1246 smp_processor_id(), hard_smp_processor_id());
1247 v = apic_read(APIC_ID);
1248 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1249 v = apic_read(APIC_LVR);
1250 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1251 ver = GET_APIC_VERSION(v);
1252 maxlvt = lapic_get_maxlvt();
1253
1254 v = apic_read(APIC_TASKPRI);
1255 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1256
1257 v = apic_read(APIC_ARBPRI);
1258 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1259 v & APIC_ARBPRI_MASK);
1260 v = apic_read(APIC_PROCPRI);
1261 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1262
1263 v = apic_read(APIC_EOI);
1264 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1265 v = apic_read(APIC_RRR);
1266 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1267 v = apic_read(APIC_LDR);
1268 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1269 v = apic_read(APIC_DFR);
1270 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1271 v = apic_read(APIC_SPIV);
1272 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1273
1274 printk(KERN_DEBUG "... APIC ISR field:\n");
1275 print_APIC_bitfield(APIC_ISR);
1276 printk(KERN_DEBUG "... APIC TMR field:\n");
1277 print_APIC_bitfield(APIC_TMR);
1278 printk(KERN_DEBUG "... APIC IRR field:\n");
1279 print_APIC_bitfield(APIC_IRR);
1280
1281 v = apic_read(APIC_ESR);
1282 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1283
1284 icr = apic_icr_read();
1285 printk(KERN_DEBUG "... APIC ICR: %08x\n", icr);
1286 printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32);
1287
1288 v = apic_read(APIC_LVTT);
1289 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1290
1291 if (maxlvt > 3) { /* PC is LVT#4. */
1292 v = apic_read(APIC_LVTPC);
1293 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1294 }
1295 v = apic_read(APIC_LVT0);
1296 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1297 v = apic_read(APIC_LVT1);
1298 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1299
1300 if (maxlvt > 2) { /* ERR is LVT#3. */
1301 v = apic_read(APIC_LVTERR);
1302 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1303 }
1304
1305 v = apic_read(APIC_TMICT);
1306 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1307 v = apic_read(APIC_TMCCT);
1308 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1309 v = apic_read(APIC_TDCR);
1310 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1311 printk("\n");
1312 }
1313
1314 void print_all_local_APICs (void)
1315 {
1316 on_each_cpu(print_local_APIC, NULL, 1);
1317 }
1318
1319 void __apicdebuginit print_PIC(void)
1320 {
1321 unsigned int v;
1322 unsigned long flags;
1323
1324 if (apic_verbosity == APIC_QUIET)
1325 return;
1326
1327 printk(KERN_DEBUG "\nprinting PIC contents\n");
1328
1329 spin_lock_irqsave(&i8259A_lock, flags);
1330
1331 v = inb(0xa1) << 8 | inb(0x21);
1332 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1333
1334 v = inb(0xa0) << 8 | inb(0x20);
1335 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1336
1337 outb(0x0b,0xa0);
1338 outb(0x0b,0x20);
1339 v = inb(0xa0) << 8 | inb(0x20);
1340 outb(0x0a,0xa0);
1341 outb(0x0a,0x20);
1342
1343 spin_unlock_irqrestore(&i8259A_lock, flags);
1344
1345 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1346
1347 v = inb(0x4d1) << 8 | inb(0x4d0);
1348 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1349 }
1350
1351 #endif /* 0 */
1352
1353 void __init enable_IO_APIC(void)
1354 {
1355 union IO_APIC_reg_01 reg_01;
1356 int i8259_apic, i8259_pin;
1357 int i, apic;
1358 unsigned long flags;
1359
1360 for (i = 0; i < PIN_MAP_SIZE; i++) {
1361 irq_2_pin[i].pin = -1;
1362 irq_2_pin[i].next = 0;
1363 }
1364
1365 /*
1366 * The number of IO-APIC IRQ registers (== #pins):
1367 */
1368 for (apic = 0; apic < nr_ioapics; apic++) {
1369 spin_lock_irqsave(&ioapic_lock, flags);
1370 reg_01.raw = io_apic_read(apic, 1);
1371 spin_unlock_irqrestore(&ioapic_lock, flags);
1372 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1373 }
1374 for(apic = 0; apic < nr_ioapics; apic++) {
1375 int pin;
1376 /* See if any of the pins is in ExtINT mode */
1377 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1378 struct IO_APIC_route_entry entry;
1379 entry = ioapic_read_entry(apic, pin);
1380
1381 /* If the interrupt line is enabled and in ExtInt mode
1382 * I have found the pin where the i8259 is connected.
1383 */
1384 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1385 ioapic_i8259.apic = apic;
1386 ioapic_i8259.pin = pin;
1387 goto found_i8259;
1388 }
1389 }
1390 }
1391 found_i8259:
1392 /* Look to see what if the MP table has reported the ExtINT */
1393 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1394 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1395 /* Trust the MP table if nothing is setup in the hardware */
1396 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1397 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1398 ioapic_i8259.pin = i8259_pin;
1399 ioapic_i8259.apic = i8259_apic;
1400 }
1401 /* Complain if the MP table and the hardware disagree */
1402 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1403 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1404 {
1405 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1406 }
1407
1408 /*
1409 * Do not trust the IO-APIC being empty at bootup
1410 */
1411 clear_IO_APIC();
1412 }
1413
1414 /*
1415 * Not an __init, needed by the reboot code
1416 */
1417 void disable_IO_APIC(void)
1418 {
1419 /*
1420 * Clear the IO-APIC before rebooting:
1421 */
1422 clear_IO_APIC();
1423
1424 /*
1425 * If the i8259 is routed through an IOAPIC
1426 * Put that IOAPIC in virtual wire mode
1427 * so legacy interrupts can be delivered.
1428 */
1429 if (ioapic_i8259.pin != -1) {
1430 struct IO_APIC_route_entry entry;
1431
1432 memset(&entry, 0, sizeof(entry));
1433 entry.mask = 0; /* Enabled */
1434 entry.trigger = 0; /* Edge */
1435 entry.irr = 0;
1436 entry.polarity = 0; /* High */
1437 entry.delivery_status = 0;
1438 entry.dest_mode = 0; /* Physical */
1439 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1440 entry.vector = 0;
1441 entry.dest = read_apic_id();
1442
1443 /*
1444 * Add it to the IO-APIC irq-routing table:
1445 */
1446 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1447 }
1448
1449 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1450 }
1451
1452 /*
1453 * There is a nasty bug in some older SMP boards, their mptable lies
1454 * about the timer IRQ. We do the following to work around the situation:
1455 *
1456 * - timer IRQ defaults to IO-APIC IRQ
1457 * - if this function detects that timer IRQs are defunct, then we fall
1458 * back to ISA timer IRQs
1459 */
1460 static int __init timer_irq_works(void)
1461 {
1462 unsigned long t1 = jiffies;
1463 unsigned long flags;
1464
1465 local_save_flags(flags);
1466 local_irq_enable();
1467 /* Let ten ticks pass... */
1468 mdelay((10 * 1000) / HZ);
1469 local_irq_restore(flags);
1470
1471 /*
1472 * Expect a few ticks at least, to be sure some possible
1473 * glue logic does not lock up after one or two first
1474 * ticks in a non-ExtINT mode. Also the local APIC
1475 * might have cached one ExtINT interrupt. Finally, at
1476 * least one tick may be lost due to delays.
1477 */
1478
1479 /* jiffies wrap? */
1480 if (time_after(jiffies, t1 + 4))
1481 return 1;
1482 return 0;
1483 }
1484
1485 /*
1486 * In the SMP+IOAPIC case it might happen that there are an unspecified
1487 * number of pending IRQ events unhandled. These cases are very rare,
1488 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1489 * better to do it this way as thus we do not have to be aware of
1490 * 'pending' interrupts in the IRQ path, except at this point.
1491 */
1492 /*
1493 * Edge triggered needs to resend any interrupt
1494 * that was delayed but this is now handled in the device
1495 * independent code.
1496 */
1497
1498 /*
1499 * Starting up a edge-triggered IO-APIC interrupt is
1500 * nasty - we need to make sure that we get the edge.
1501 * If it is already asserted for some reason, we need
1502 * return 1 to indicate that is was pending.
1503 *
1504 * This is not complete - we should be able to fake
1505 * an edge even if it isn't on the 8259A...
1506 */
1507
1508 static unsigned int startup_ioapic_irq(unsigned int irq)
1509 {
1510 int was_pending = 0;
1511 unsigned long flags;
1512
1513 spin_lock_irqsave(&ioapic_lock, flags);
1514 if (irq < 16) {
1515 disable_8259A_irq(irq);
1516 if (i8259A_irq_pending(irq))
1517 was_pending = 1;
1518 }
1519 __unmask_IO_APIC_irq(irq);
1520 spin_unlock_irqrestore(&ioapic_lock, flags);
1521
1522 return was_pending;
1523 }
1524
1525 static int ioapic_retrigger_irq(unsigned int irq)
1526 {
1527 struct irq_cfg *cfg = &irq_cfg[irq];
1528 unsigned long flags;
1529
1530 spin_lock_irqsave(&vector_lock, flags);
1531 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
1532 spin_unlock_irqrestore(&vector_lock, flags);
1533
1534 return 1;
1535 }
1536
1537 /*
1538 * Level and edge triggered IO-APIC interrupts need different handling,
1539 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1540 * handled with the level-triggered descriptor, but that one has slightly
1541 * more overhead. Level-triggered interrupts cannot be handled with the
1542 * edge-triggered handler, without risking IRQ storms and other ugly
1543 * races.
1544 */
1545
1546 #ifdef CONFIG_SMP
1547
1548 #ifdef CONFIG_INTR_REMAP
1549 static void ir_irq_migration(struct work_struct *work);
1550
1551 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
1552
1553 /*
1554 * Migrate the IO-APIC irq in the presence of intr-remapping.
1555 *
1556 * For edge triggered, irq migration is a simple atomic update(of vector
1557 * and cpu destination) of IRTE and flush the hardware cache.
1558 *
1559 * For level triggered, we need to modify the io-apic RTE aswell with the update
1560 * vector information, along with modifying IRTE with vector and destination.
1561 * So irq migration for level triggered is little bit more complex compared to
1562 * edge triggered migration. But the good news is, we use the same algorithm
1563 * for level triggered migration as we have today, only difference being,
1564 * we now initiate the irq migration from process context instead of the
1565 * interrupt context.
1566 *
1567 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1568 * suppression) to the IO-APIC, level triggered irq migration will also be
1569 * as simple as edge triggered migration and we can do the irq migration
1570 * with a simple atomic update to IO-APIC RTE.
1571 */
1572 static void migrate_ioapic_irq(int irq, cpumask_t mask)
1573 {
1574 struct irq_cfg *cfg = irq_cfg + irq;
1575 struct irq_desc *desc = irq_desc + irq;
1576 cpumask_t tmp, cleanup_mask;
1577 struct irte irte;
1578 int modify_ioapic_rte = desc->status & IRQ_LEVEL;
1579 unsigned int dest;
1580 unsigned long flags;
1581
1582 cpus_and(tmp, mask, cpu_online_map);
1583 if (cpus_empty(tmp))
1584 return;
1585
1586 if (get_irte(irq, &irte))
1587 return;
1588
1589 if (assign_irq_vector(irq, mask))
1590 return;
1591
1592 cpus_and(tmp, cfg->domain, mask);
1593 dest = cpu_mask_to_apicid(tmp);
1594
1595 if (modify_ioapic_rte) {
1596 spin_lock_irqsave(&ioapic_lock, flags);
1597 __target_IO_APIC_irq(irq, dest, cfg->vector);
1598 spin_unlock_irqrestore(&ioapic_lock, flags);
1599 }
1600
1601 irte.vector = cfg->vector;
1602 irte.dest_id = IRTE_DEST(dest);
1603
1604 /*
1605 * Modified the IRTE and flushes the Interrupt entry cache.
1606 */
1607 modify_irte(irq, &irte);
1608
1609 if (cfg->move_in_progress) {
1610 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1611 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1612 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1613 cfg->move_in_progress = 0;
1614 }
1615
1616 irq_desc[irq].affinity = mask;
1617 }
1618
1619 static int migrate_irq_remapped_level(int irq)
1620 {
1621 int ret = -1;
1622
1623 mask_IO_APIC_irq(irq);
1624
1625 if (io_apic_level_ack_pending(irq)) {
1626 /*
1627 * Interrupt in progress. Migrating irq now will change the
1628 * vector information in the IO-APIC RTE and that will confuse
1629 * the EOI broadcast performed by cpu.
1630 * So, delay the irq migration to the next instance.
1631 */
1632 schedule_delayed_work(&ir_migration_work, 1);
1633 goto unmask;
1634 }
1635
1636 /* everthing is clear. we have right of way */
1637 migrate_ioapic_irq(irq, irq_desc[irq].pending_mask);
1638
1639 ret = 0;
1640 irq_desc[irq].status &= ~IRQ_MOVE_PENDING;
1641 cpus_clear(irq_desc[irq].pending_mask);
1642
1643 unmask:
1644 unmask_IO_APIC_irq(irq);
1645 return ret;
1646 }
1647
1648 static void ir_irq_migration(struct work_struct *work)
1649 {
1650 int irq;
1651
1652 for (irq = 0; irq < NR_IRQS; irq++) {
1653 struct irq_desc *desc = irq_desc + irq;
1654 if (desc->status & IRQ_MOVE_PENDING) {
1655 unsigned long flags;
1656
1657 spin_lock_irqsave(&desc->lock, flags);
1658 if (!desc->chip->set_affinity ||
1659 !(desc->status & IRQ_MOVE_PENDING)) {
1660 desc->status &= ~IRQ_MOVE_PENDING;
1661 spin_unlock_irqrestore(&desc->lock, flags);
1662 continue;
1663 }
1664
1665 desc->chip->set_affinity(irq,
1666 irq_desc[irq].pending_mask);
1667 spin_unlock_irqrestore(&desc->lock, flags);
1668 }
1669 }
1670 }
1671
1672 /*
1673 * Migrates the IRQ destination in the process context.
1674 */
1675 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1676 {
1677 if (irq_desc[irq].status & IRQ_LEVEL) {
1678 irq_desc[irq].status |= IRQ_MOVE_PENDING;
1679 irq_desc[irq].pending_mask = mask;
1680 migrate_irq_remapped_level(irq);
1681 return;
1682 }
1683
1684 migrate_ioapic_irq(irq, mask);
1685 }
1686 #endif
1687
1688 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1689 {
1690 unsigned vector, me;
1691 ack_APIC_irq();
1692 exit_idle();
1693 irq_enter();
1694
1695 me = smp_processor_id();
1696 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1697 unsigned int irq;
1698 struct irq_desc *desc;
1699 struct irq_cfg *cfg;
1700 irq = __get_cpu_var(vector_irq)[vector];
1701 if (irq >= NR_IRQS)
1702 continue;
1703
1704 desc = irq_desc + irq;
1705 cfg = irq_cfg + irq;
1706 spin_lock(&desc->lock);
1707 if (!cfg->move_cleanup_count)
1708 goto unlock;
1709
1710 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1711 goto unlock;
1712
1713 __get_cpu_var(vector_irq)[vector] = -1;
1714 cfg->move_cleanup_count--;
1715 unlock:
1716 spin_unlock(&desc->lock);
1717 }
1718
1719 irq_exit();
1720 }
1721
1722 static void irq_complete_move(unsigned int irq)
1723 {
1724 struct irq_cfg *cfg = irq_cfg + irq;
1725 unsigned vector, me;
1726
1727 if (likely(!cfg->move_in_progress))
1728 return;
1729
1730 vector = ~get_irq_regs()->orig_ax;
1731 me = smp_processor_id();
1732 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1733 cpumask_t cleanup_mask;
1734
1735 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1736 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1737 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1738 cfg->move_in_progress = 0;
1739 }
1740 }
1741 #else
1742 static inline void irq_complete_move(unsigned int irq) {}
1743 #endif
1744 #ifdef CONFIG_INTR_REMAP
1745 static void ack_x2apic_level(unsigned int irq)
1746 {
1747 ack_x2APIC_irq();
1748 }
1749
1750 static void ack_x2apic_edge(unsigned int irq)
1751 {
1752 ack_x2APIC_irq();
1753 }
1754 #endif
1755
1756 static void ack_apic_edge(unsigned int irq)
1757 {
1758 irq_complete_move(irq);
1759 move_native_irq(irq);
1760 ack_APIC_irq();
1761 }
1762
1763 static void ack_apic_level(unsigned int irq)
1764 {
1765 int do_unmask_irq = 0;
1766
1767 irq_complete_move(irq);
1768 #ifdef CONFIG_GENERIC_PENDING_IRQ
1769 /* If we are moving the irq we need to mask it */
1770 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1771 do_unmask_irq = 1;
1772 mask_IO_APIC_irq(irq);
1773 }
1774 #endif
1775
1776 /*
1777 * We must acknowledge the irq before we move it or the acknowledge will
1778 * not propagate properly.
1779 */
1780 ack_APIC_irq();
1781
1782 /* Now we can move and renable the irq */
1783 if (unlikely(do_unmask_irq)) {
1784 /* Only migrate the irq if the ack has been received.
1785 *
1786 * On rare occasions the broadcast level triggered ack gets
1787 * delayed going to ioapics, and if we reprogram the
1788 * vector while Remote IRR is still set the irq will never
1789 * fire again.
1790 *
1791 * To prevent this scenario we read the Remote IRR bit
1792 * of the ioapic. This has two effects.
1793 * - On any sane system the read of the ioapic will
1794 * flush writes (and acks) going to the ioapic from
1795 * this cpu.
1796 * - We get to see if the ACK has actually been delivered.
1797 *
1798 * Based on failed experiments of reprogramming the
1799 * ioapic entry from outside of irq context starting
1800 * with masking the ioapic entry and then polling until
1801 * Remote IRR was clear before reprogramming the
1802 * ioapic I don't trust the Remote IRR bit to be
1803 * completey accurate.
1804 *
1805 * However there appears to be no other way to plug
1806 * this race, so if the Remote IRR bit is not
1807 * accurate and is causing problems then it is a hardware bug
1808 * and you can go talk to the chipset vendor about it.
1809 */
1810 if (!io_apic_level_ack_pending(irq))
1811 move_masked_irq(irq);
1812 unmask_IO_APIC_irq(irq);
1813 }
1814 }
1815
1816 static struct irq_chip ioapic_chip __read_mostly = {
1817 .name = "IO-APIC",
1818 .startup = startup_ioapic_irq,
1819 .mask = mask_IO_APIC_irq,
1820 .unmask = unmask_IO_APIC_irq,
1821 .ack = ack_apic_edge,
1822 .eoi = ack_apic_level,
1823 #ifdef CONFIG_SMP
1824 .set_affinity = set_ioapic_affinity_irq,
1825 #endif
1826 .retrigger = ioapic_retrigger_irq,
1827 };
1828
1829 #ifdef CONFIG_INTR_REMAP
1830 static struct irq_chip ir_ioapic_chip __read_mostly = {
1831 .name = "IR-IO-APIC",
1832 .startup = startup_ioapic_irq,
1833 .mask = mask_IO_APIC_irq,
1834 .unmask = unmask_IO_APIC_irq,
1835 .ack = ack_x2apic_edge,
1836 .eoi = ack_x2apic_level,
1837 #ifdef CONFIG_SMP
1838 .set_affinity = set_ir_ioapic_affinity_irq,
1839 #endif
1840 .retrigger = ioapic_retrigger_irq,
1841 };
1842 #endif
1843
1844 static inline void init_IO_APIC_traps(void)
1845 {
1846 int irq;
1847
1848 /*
1849 * NOTE! The local APIC isn't very good at handling
1850 * multiple interrupts at the same interrupt level.
1851 * As the interrupt level is determined by taking the
1852 * vector number and shifting that right by 4, we
1853 * want to spread these out a bit so that they don't
1854 * all fall in the same interrupt level.
1855 *
1856 * Also, we've got to be careful not to trash gate
1857 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1858 */
1859 for (irq = 0; irq < NR_IRQS ; irq++) {
1860 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1861 /*
1862 * Hmm.. We don't have an entry for this,
1863 * so default to an old-fashioned 8259
1864 * interrupt if we can..
1865 */
1866 if (irq < 16)
1867 make_8259A_irq(irq);
1868 else
1869 /* Strange. Oh, well.. */
1870 irq_desc[irq].chip = &no_irq_chip;
1871 }
1872 }
1873 }
1874
1875 static void unmask_lapic_irq(unsigned int irq)
1876 {
1877 unsigned long v;
1878
1879 v = apic_read(APIC_LVT0);
1880 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1881 }
1882
1883 static void mask_lapic_irq(unsigned int irq)
1884 {
1885 unsigned long v;
1886
1887 v = apic_read(APIC_LVT0);
1888 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1889 }
1890
1891 static void ack_lapic_irq (unsigned int irq)
1892 {
1893 ack_APIC_irq();
1894 }
1895
1896 static struct irq_chip lapic_chip __read_mostly = {
1897 .name = "local-APIC",
1898 .mask = mask_lapic_irq,
1899 .unmask = unmask_lapic_irq,
1900 .ack = ack_lapic_irq,
1901 };
1902
1903 static void lapic_register_intr(int irq)
1904 {
1905 irq_desc[irq].status &= ~IRQ_LEVEL;
1906 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1907 "edge");
1908 }
1909
1910 static void __init setup_nmi(void)
1911 {
1912 /*
1913 * Dirty trick to enable the NMI watchdog ...
1914 * We put the 8259A master into AEOI mode and
1915 * unmask on all local APICs LVT0 as NMI.
1916 *
1917 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1918 * is from Maciej W. Rozycki - so we do not have to EOI from
1919 * the NMI handler or the timer interrupt.
1920 */
1921 printk(KERN_INFO "activating NMI Watchdog ...");
1922
1923 enable_NMI_through_LVT0();
1924
1925 printk(" done.\n");
1926 }
1927
1928 /*
1929 * This looks a bit hackish but it's about the only one way of sending
1930 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1931 * not support the ExtINT mode, unfortunately. We need to send these
1932 * cycles as some i82489DX-based boards have glue logic that keeps the
1933 * 8259A interrupt line asserted until INTA. --macro
1934 */
1935 static inline void __init unlock_ExtINT_logic(void)
1936 {
1937 int apic, pin, i;
1938 struct IO_APIC_route_entry entry0, entry1;
1939 unsigned char save_control, save_freq_select;
1940
1941 pin = find_isa_irq_pin(8, mp_INT);
1942 apic = find_isa_irq_apic(8, mp_INT);
1943 if (pin == -1)
1944 return;
1945
1946 entry0 = ioapic_read_entry(apic, pin);
1947
1948 clear_IO_APIC_pin(apic, pin);
1949
1950 memset(&entry1, 0, sizeof(entry1));
1951
1952 entry1.dest_mode = 0; /* physical delivery */
1953 entry1.mask = 0; /* unmask IRQ now */
1954 entry1.dest = hard_smp_processor_id();
1955 entry1.delivery_mode = dest_ExtINT;
1956 entry1.polarity = entry0.polarity;
1957 entry1.trigger = 0;
1958 entry1.vector = 0;
1959
1960 ioapic_write_entry(apic, pin, entry1);
1961
1962 save_control = CMOS_READ(RTC_CONTROL);
1963 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1964 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1965 RTC_FREQ_SELECT);
1966 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1967
1968 i = 100;
1969 while (i-- > 0) {
1970 mdelay(10);
1971 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1972 i -= 10;
1973 }
1974
1975 CMOS_WRITE(save_control, RTC_CONTROL);
1976 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1977 clear_IO_APIC_pin(apic, pin);
1978
1979 ioapic_write_entry(apic, pin, entry0);
1980 }
1981
1982 /*
1983 * This code may look a bit paranoid, but it's supposed to cooperate with
1984 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1985 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1986 * fanatically on his truly buggy board.
1987 *
1988 * FIXME: really need to revamp this for modern platforms only.
1989 */
1990 static inline void __init check_timer(void)
1991 {
1992 struct irq_cfg *cfg = irq_cfg + 0;
1993 int apic1, pin1, apic2, pin2;
1994 unsigned long flags;
1995 int no_pin1 = 0;
1996
1997 local_irq_save(flags);
1998
1999 /*
2000 * get/set the timer IRQ vector:
2001 */
2002 disable_8259A_irq(0);
2003 assign_irq_vector(0, TARGET_CPUS);
2004
2005 /*
2006 * As IRQ0 is to be enabled in the 8259A, the virtual
2007 * wire has to be disabled in the local APIC.
2008 */
2009 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2010 init_8259A(1);
2011
2012 pin1 = find_isa_irq_pin(0, mp_INT);
2013 apic1 = find_isa_irq_apic(0, mp_INT);
2014 pin2 = ioapic_i8259.pin;
2015 apic2 = ioapic_i8259.apic;
2016
2017 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2018 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2019 cfg->vector, apic1, pin1, apic2, pin2);
2020
2021 /*
2022 * Some BIOS writers are clueless and report the ExtINTA
2023 * I/O APIC input from the cascaded 8259A as the timer
2024 * interrupt input. So just in case, if only one pin
2025 * was found above, try it both directly and through the
2026 * 8259A.
2027 */
2028 if (pin1 == -1) {
2029 if (intr_remapping_enabled)
2030 panic("BIOS bug: timer not connected to IO-APIC");
2031 pin1 = pin2;
2032 apic1 = apic2;
2033 no_pin1 = 1;
2034 } else if (pin2 == -1) {
2035 pin2 = pin1;
2036 apic2 = apic1;
2037 }
2038
2039 if (pin1 != -1) {
2040 /*
2041 * Ok, does IRQ0 through the IOAPIC work?
2042 */
2043 if (no_pin1) {
2044 add_pin_to_irq(0, apic1, pin1);
2045 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2046 }
2047 unmask_IO_APIC_irq(0);
2048 if (!no_timer_check && timer_irq_works()) {
2049 if (nmi_watchdog == NMI_IO_APIC) {
2050 setup_nmi();
2051 enable_8259A_irq(0);
2052 }
2053 if (disable_timer_pin_1 > 0)
2054 clear_IO_APIC_pin(0, pin1);
2055 goto out;
2056 }
2057 if (intr_remapping_enabled)
2058 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2059 clear_IO_APIC_pin(apic1, pin1);
2060 if (!no_pin1)
2061 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2062 "8254 timer not connected to IO-APIC\n");
2063
2064 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2065 "(IRQ0) through the 8259A ...\n");
2066 apic_printk(APIC_QUIET, KERN_INFO
2067 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2068 /*
2069 * legacy devices should be connected to IO APIC #0
2070 */
2071 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2072 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2073 unmask_IO_APIC_irq(0);
2074 enable_8259A_irq(0);
2075 if (timer_irq_works()) {
2076 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2077 timer_through_8259 = 1;
2078 if (nmi_watchdog == NMI_IO_APIC) {
2079 disable_8259A_irq(0);
2080 setup_nmi();
2081 enable_8259A_irq(0);
2082 }
2083 goto out;
2084 }
2085 /*
2086 * Cleanup, just in case ...
2087 */
2088 disable_8259A_irq(0);
2089 clear_IO_APIC_pin(apic2, pin2);
2090 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2091 }
2092
2093 if (nmi_watchdog == NMI_IO_APIC) {
2094 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2095 "through the IO-APIC - disabling NMI Watchdog!\n");
2096 nmi_watchdog = NMI_NONE;
2097 }
2098
2099 apic_printk(APIC_QUIET, KERN_INFO
2100 "...trying to set up timer as Virtual Wire IRQ...\n");
2101
2102 lapic_register_intr(0);
2103 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2104 enable_8259A_irq(0);
2105
2106 if (timer_irq_works()) {
2107 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2108 goto out;
2109 }
2110 disable_8259A_irq(0);
2111 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2112 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2113
2114 apic_printk(APIC_QUIET, KERN_INFO
2115 "...trying to set up timer as ExtINT IRQ...\n");
2116
2117 init_8259A(0);
2118 make_8259A_irq(0);
2119 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2120
2121 unlock_ExtINT_logic();
2122
2123 if (timer_irq_works()) {
2124 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2125 goto out;
2126 }
2127 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2128 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2129 "report. Then try booting with the 'noapic' option.\n");
2130 out:
2131 local_irq_restore(flags);
2132 }
2133
2134 static int __init notimercheck(char *s)
2135 {
2136 no_timer_check = 1;
2137 return 1;
2138 }
2139 __setup("no_timer_check", notimercheck);
2140
2141 /*
2142 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2143 * to devices. However there may be an I/O APIC pin available for
2144 * this interrupt regardless. The pin may be left unconnected, but
2145 * typically it will be reused as an ExtINT cascade interrupt for
2146 * the master 8259A. In the MPS case such a pin will normally be
2147 * reported as an ExtINT interrupt in the MP table. With ACPI
2148 * there is no provision for ExtINT interrupts, and in the absence
2149 * of an override it would be treated as an ordinary ISA I/O APIC
2150 * interrupt, that is edge-triggered and unmasked by default. We
2151 * used to do this, but it caused problems on some systems because
2152 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2153 * the same ExtINT cascade interrupt to drive the local APIC of the
2154 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2155 * the I/O APIC in all cases now. No actual device should request
2156 * it anyway. --macro
2157 */
2158 #define PIC_IRQS (1<<2)
2159
2160 void __init setup_IO_APIC(void)
2161 {
2162
2163 /*
2164 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2165 */
2166
2167 io_apic_irqs = ~PIC_IRQS;
2168
2169 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2170
2171 sync_Arb_IDs();
2172 setup_IO_APIC_irqs();
2173 init_IO_APIC_traps();
2174 check_timer();
2175 if (!acpi_ioapic)
2176 print_IO_APIC();
2177 }
2178
2179 struct sysfs_ioapic_data {
2180 struct sys_device dev;
2181 struct IO_APIC_route_entry entry[0];
2182 };
2183 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2184
2185 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2186 {
2187 struct IO_APIC_route_entry *entry;
2188 struct sysfs_ioapic_data *data;
2189 int i;
2190
2191 data = container_of(dev, struct sysfs_ioapic_data, dev);
2192 entry = data->entry;
2193 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2194 *entry = ioapic_read_entry(dev->id, i);
2195
2196 return 0;
2197 }
2198
2199 static int ioapic_resume(struct sys_device *dev)
2200 {
2201 struct IO_APIC_route_entry *entry;
2202 struct sysfs_ioapic_data *data;
2203 unsigned long flags;
2204 union IO_APIC_reg_00 reg_00;
2205 int i;
2206
2207 data = container_of(dev, struct sysfs_ioapic_data, dev);
2208 entry = data->entry;
2209
2210 spin_lock_irqsave(&ioapic_lock, flags);
2211 reg_00.raw = io_apic_read(dev->id, 0);
2212 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2213 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2214 io_apic_write(dev->id, 0, reg_00.raw);
2215 }
2216 spin_unlock_irqrestore(&ioapic_lock, flags);
2217 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2218 ioapic_write_entry(dev->id, i, entry[i]);
2219
2220 return 0;
2221 }
2222
2223 static struct sysdev_class ioapic_sysdev_class = {
2224 .name = "ioapic",
2225 .suspend = ioapic_suspend,
2226 .resume = ioapic_resume,
2227 };
2228
2229 static int __init ioapic_init_sysfs(void)
2230 {
2231 struct sys_device * dev;
2232 int i, size, error;
2233
2234 error = sysdev_class_register(&ioapic_sysdev_class);
2235 if (error)
2236 return error;
2237
2238 for (i = 0; i < nr_ioapics; i++ ) {
2239 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2240 * sizeof(struct IO_APIC_route_entry);
2241 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2242 if (!mp_ioapic_data[i]) {
2243 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2244 continue;
2245 }
2246 dev = &mp_ioapic_data[i]->dev;
2247 dev->id = i;
2248 dev->cls = &ioapic_sysdev_class;
2249 error = sysdev_register(dev);
2250 if (error) {
2251 kfree(mp_ioapic_data[i]);
2252 mp_ioapic_data[i] = NULL;
2253 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2254 continue;
2255 }
2256 }
2257
2258 return 0;
2259 }
2260
2261 device_initcall(ioapic_init_sysfs);
2262
2263 /*
2264 * Dynamic irq allocate and deallocation
2265 */
2266 int create_irq(void)
2267 {
2268 /* Allocate an unused irq */
2269 int irq;
2270 int new;
2271 unsigned long flags;
2272
2273 irq = -ENOSPC;
2274 spin_lock_irqsave(&vector_lock, flags);
2275 for (new = (NR_IRQS - 1); new >= 0; new--) {
2276 if (platform_legacy_irq(new))
2277 continue;
2278 if (irq_cfg[new].vector != 0)
2279 continue;
2280 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
2281 irq = new;
2282 break;
2283 }
2284 spin_unlock_irqrestore(&vector_lock, flags);
2285
2286 if (irq >= 0) {
2287 dynamic_irq_init(irq);
2288 }
2289 return irq;
2290 }
2291
2292 void destroy_irq(unsigned int irq)
2293 {
2294 unsigned long flags;
2295
2296 dynamic_irq_cleanup(irq);
2297
2298 #ifdef CONFIG_INTR_REMAP
2299 free_irte(irq);
2300 #endif
2301 spin_lock_irqsave(&vector_lock, flags);
2302 __clear_irq_vector(irq);
2303 spin_unlock_irqrestore(&vector_lock, flags);
2304 }
2305
2306 /*
2307 * MSI message composition
2308 */
2309 #ifdef CONFIG_PCI_MSI
2310 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2311 {
2312 struct irq_cfg *cfg = irq_cfg + irq;
2313 int err;
2314 unsigned dest;
2315 cpumask_t tmp;
2316
2317 tmp = TARGET_CPUS;
2318 err = assign_irq_vector(irq, tmp);
2319 if (err)
2320 return err;
2321
2322 cpus_and(tmp, cfg->domain, tmp);
2323 dest = cpu_mask_to_apicid(tmp);
2324
2325 #ifdef CONFIG_INTR_REMAP
2326 if (irq_remapped(irq)) {
2327 struct irte irte;
2328 int ir_index;
2329 u16 sub_handle;
2330
2331 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
2332 BUG_ON(ir_index == -1);
2333
2334 memset (&irte, 0, sizeof(irte));
2335
2336 irte.present = 1;
2337 irte.dst_mode = INT_DEST_MODE;
2338 irte.trigger_mode = 0; /* edge */
2339 irte.dlvry_mode = INT_DELIVERY_MODE;
2340 irte.vector = cfg->vector;
2341 irte.dest_id = IRTE_DEST(dest);
2342
2343 modify_irte(irq, &irte);
2344
2345 msg->address_hi = MSI_ADDR_BASE_HI;
2346 msg->data = sub_handle;
2347 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
2348 MSI_ADDR_IR_SHV |
2349 MSI_ADDR_IR_INDEX1(ir_index) |
2350 MSI_ADDR_IR_INDEX2(ir_index);
2351 } else
2352 #endif
2353 {
2354 msg->address_hi = MSI_ADDR_BASE_HI;
2355 msg->address_lo =
2356 MSI_ADDR_BASE_LO |
2357 ((INT_DEST_MODE == 0) ?
2358 MSI_ADDR_DEST_MODE_PHYSICAL:
2359 MSI_ADDR_DEST_MODE_LOGICAL) |
2360 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2361 MSI_ADDR_REDIRECTION_CPU:
2362 MSI_ADDR_REDIRECTION_LOWPRI) |
2363 MSI_ADDR_DEST_ID(dest);
2364
2365 msg->data =
2366 MSI_DATA_TRIGGER_EDGE |
2367 MSI_DATA_LEVEL_ASSERT |
2368 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2369 MSI_DATA_DELIVERY_FIXED:
2370 MSI_DATA_DELIVERY_LOWPRI) |
2371 MSI_DATA_VECTOR(cfg->vector);
2372 }
2373 return err;
2374 }
2375
2376 #ifdef CONFIG_SMP
2377 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2378 {
2379 struct irq_cfg *cfg = irq_cfg + irq;
2380 struct msi_msg msg;
2381 unsigned int dest;
2382 cpumask_t tmp;
2383
2384 cpus_and(tmp, mask, cpu_online_map);
2385 if (cpus_empty(tmp))
2386 return;
2387
2388 if (assign_irq_vector(irq, mask))
2389 return;
2390
2391 cpus_and(tmp, cfg->domain, mask);
2392 dest = cpu_mask_to_apicid(tmp);
2393
2394 read_msi_msg(irq, &msg);
2395
2396 msg.data &= ~MSI_DATA_VECTOR_MASK;
2397 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2398 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2399 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2400
2401 write_msi_msg(irq, &msg);
2402 irq_desc[irq].affinity = mask;
2403 }
2404
2405 #ifdef CONFIG_INTR_REMAP
2406 /*
2407 * Migrate the MSI irq to another cpumask. This migration is
2408 * done in the process context using interrupt-remapping hardware.
2409 */
2410 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2411 {
2412 struct irq_cfg *cfg = irq_cfg + irq;
2413 unsigned int dest;
2414 cpumask_t tmp, cleanup_mask;
2415 struct irte irte;
2416
2417 cpus_and(tmp, mask, cpu_online_map);
2418 if (cpus_empty(tmp))
2419 return;
2420
2421 if (get_irte(irq, &irte))
2422 return;
2423
2424 if (assign_irq_vector(irq, mask))
2425 return;
2426
2427 cpus_and(tmp, cfg->domain, mask);
2428 dest = cpu_mask_to_apicid(tmp);
2429
2430 irte.vector = cfg->vector;
2431 irte.dest_id = IRTE_DEST(dest);
2432
2433 /*
2434 * atomically update the IRTE with the new destination and vector.
2435 */
2436 modify_irte(irq, &irte);
2437
2438 /*
2439 * After this point, all the interrupts will start arriving
2440 * at the new destination. So, time to cleanup the previous
2441 * vector allocation.
2442 */
2443 if (cfg->move_in_progress) {
2444 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2445 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2446 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2447 cfg->move_in_progress = 0;
2448 }
2449
2450 irq_desc[irq].affinity = mask;
2451 }
2452 #endif
2453 #endif /* CONFIG_SMP */
2454
2455 /*
2456 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2457 * which implement the MSI or MSI-X Capability Structure.
2458 */
2459 static struct irq_chip msi_chip = {
2460 .name = "PCI-MSI",
2461 .unmask = unmask_msi_irq,
2462 .mask = mask_msi_irq,
2463 .ack = ack_apic_edge,
2464 #ifdef CONFIG_SMP
2465 .set_affinity = set_msi_irq_affinity,
2466 #endif
2467 .retrigger = ioapic_retrigger_irq,
2468 };
2469
2470 #ifdef CONFIG_INTR_REMAP
2471 static struct irq_chip msi_ir_chip = {
2472 .name = "IR-PCI-MSI",
2473 .unmask = unmask_msi_irq,
2474 .mask = mask_msi_irq,
2475 .ack = ack_x2apic_edge,
2476 #ifdef CONFIG_SMP
2477 .set_affinity = ir_set_msi_irq_affinity,
2478 #endif
2479 .retrigger = ioapic_retrigger_irq,
2480 };
2481
2482 /*
2483 * Map the PCI dev to the corresponding remapping hardware unit
2484 * and allocate 'nvec' consecutive interrupt-remapping table entries
2485 * in it.
2486 */
2487 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
2488 {
2489 struct intel_iommu *iommu;
2490 int index;
2491
2492 iommu = map_dev_to_ir(dev);
2493 if (!iommu) {
2494 printk(KERN_ERR
2495 "Unable to map PCI %s to iommu\n", pci_name(dev));
2496 return -ENOENT;
2497 }
2498
2499 index = alloc_irte(iommu, irq, nvec);
2500 if (index < 0) {
2501 printk(KERN_ERR
2502 "Unable to allocate %d IRTE for PCI %s\n", nvec,
2503 pci_name(dev));
2504 return -ENOSPC;
2505 }
2506 return index;
2507 }
2508 #endif
2509
2510 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
2511 {
2512 int ret;
2513 struct msi_msg msg;
2514
2515 ret = msi_compose_msg(dev, irq, &msg);
2516 if (ret < 0)
2517 return ret;
2518
2519 set_irq_msi(irq, desc);
2520 write_msi_msg(irq, &msg);
2521
2522 #ifdef CONFIG_INTR_REMAP
2523 if (irq_remapped(irq)) {
2524 struct irq_desc *desc = irq_desc + irq;
2525 /*
2526 * irq migration in process context
2527 */
2528 desc->status |= IRQ_MOVE_PCNTXT;
2529 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
2530 } else
2531 #endif
2532 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2533
2534 return 0;
2535 }
2536
2537 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2538 {
2539 int irq, ret;
2540
2541 irq = create_irq();
2542 if (irq < 0)
2543 return irq;
2544
2545 #ifdef CONFIG_INTR_REMAP
2546 if (!intr_remapping_enabled)
2547 goto no_ir;
2548
2549 ret = msi_alloc_irte(dev, irq, 1);
2550 if (ret < 0)
2551 goto error;
2552 no_ir:
2553 #endif
2554 ret = setup_msi_irq(dev, desc, irq);
2555 if (ret < 0) {
2556 destroy_irq(irq);
2557 return ret;
2558 }
2559 return 0;
2560
2561 #ifdef CONFIG_INTR_REMAP
2562 error:
2563 destroy_irq(irq);
2564 return ret;
2565 #endif
2566 }
2567
2568 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
2569 {
2570 int irq, ret, sub_handle;
2571 struct msi_desc *desc;
2572 #ifdef CONFIG_INTR_REMAP
2573 struct intel_iommu *iommu = 0;
2574 int index = 0;
2575 #endif
2576
2577 sub_handle = 0;
2578 list_for_each_entry(desc, &dev->msi_list, list) {
2579 irq = create_irq();
2580 if (irq < 0)
2581 return irq;
2582 #ifdef CONFIG_INTR_REMAP
2583 if (!intr_remapping_enabled)
2584 goto no_ir;
2585
2586 if (!sub_handle) {
2587 /*
2588 * allocate the consecutive block of IRTE's
2589 * for 'nvec'
2590 */
2591 index = msi_alloc_irte(dev, irq, nvec);
2592 if (index < 0) {
2593 ret = index;
2594 goto error;
2595 }
2596 } else {
2597 iommu = map_dev_to_ir(dev);
2598 if (!iommu) {
2599 ret = -ENOENT;
2600 goto error;
2601 }
2602 /*
2603 * setup the mapping between the irq and the IRTE
2604 * base index, the sub_handle pointing to the
2605 * appropriate interrupt remap table entry.
2606 */
2607 set_irte_irq(irq, iommu, index, sub_handle);
2608 }
2609 no_ir:
2610 #endif
2611 ret = setup_msi_irq(dev, desc, irq);
2612 if (ret < 0)
2613 goto error;
2614 sub_handle++;
2615 }
2616 return 0;
2617
2618 error:
2619 destroy_irq(irq);
2620 return ret;
2621 }
2622
2623 void arch_teardown_msi_irq(unsigned int irq)
2624 {
2625 destroy_irq(irq);
2626 }
2627
2628 #ifdef CONFIG_DMAR
2629 #ifdef CONFIG_SMP
2630 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2631 {
2632 struct irq_cfg *cfg = irq_cfg + irq;
2633 struct msi_msg msg;
2634 unsigned int dest;
2635 cpumask_t tmp;
2636
2637 cpus_and(tmp, mask, cpu_online_map);
2638 if (cpus_empty(tmp))
2639 return;
2640
2641 if (assign_irq_vector(irq, mask))
2642 return;
2643
2644 cpus_and(tmp, cfg->domain, mask);
2645 dest = cpu_mask_to_apicid(tmp);
2646
2647 dmar_msi_read(irq, &msg);
2648
2649 msg.data &= ~MSI_DATA_VECTOR_MASK;
2650 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2651 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2652 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2653
2654 dmar_msi_write(irq, &msg);
2655 irq_desc[irq].affinity = mask;
2656 }
2657 #endif /* CONFIG_SMP */
2658
2659 struct irq_chip dmar_msi_type = {
2660 .name = "DMAR_MSI",
2661 .unmask = dmar_msi_unmask,
2662 .mask = dmar_msi_mask,
2663 .ack = ack_apic_edge,
2664 #ifdef CONFIG_SMP
2665 .set_affinity = dmar_msi_set_affinity,
2666 #endif
2667 .retrigger = ioapic_retrigger_irq,
2668 };
2669
2670 int arch_setup_dmar_msi(unsigned int irq)
2671 {
2672 int ret;
2673 struct msi_msg msg;
2674
2675 ret = msi_compose_msg(NULL, irq, &msg);
2676 if (ret < 0)
2677 return ret;
2678 dmar_msi_write(irq, &msg);
2679 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2680 "edge");
2681 return 0;
2682 }
2683 #endif
2684
2685 #endif /* CONFIG_PCI_MSI */
2686 /*
2687 * Hypertransport interrupt support
2688 */
2689 #ifdef CONFIG_HT_IRQ
2690
2691 #ifdef CONFIG_SMP
2692
2693 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2694 {
2695 struct ht_irq_msg msg;
2696 fetch_ht_irq_msg(irq, &msg);
2697
2698 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2699 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2700
2701 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2702 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2703
2704 write_ht_irq_msg(irq, &msg);
2705 }
2706
2707 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2708 {
2709 struct irq_cfg *cfg = irq_cfg + irq;
2710 unsigned int dest;
2711 cpumask_t tmp;
2712
2713 cpus_and(tmp, mask, cpu_online_map);
2714 if (cpus_empty(tmp))
2715 return;
2716
2717 if (assign_irq_vector(irq, mask))
2718 return;
2719
2720 cpus_and(tmp, cfg->domain, mask);
2721 dest = cpu_mask_to_apicid(tmp);
2722
2723 target_ht_irq(irq, dest, cfg->vector);
2724 irq_desc[irq].affinity = mask;
2725 }
2726 #endif
2727
2728 static struct irq_chip ht_irq_chip = {
2729 .name = "PCI-HT",
2730 .mask = mask_ht_irq,
2731 .unmask = unmask_ht_irq,
2732 .ack = ack_apic_edge,
2733 #ifdef CONFIG_SMP
2734 .set_affinity = set_ht_irq_affinity,
2735 #endif
2736 .retrigger = ioapic_retrigger_irq,
2737 };
2738
2739 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2740 {
2741 struct irq_cfg *cfg = irq_cfg + irq;
2742 int err;
2743 cpumask_t tmp;
2744
2745 tmp = TARGET_CPUS;
2746 err = assign_irq_vector(irq, tmp);
2747 if (!err) {
2748 struct ht_irq_msg msg;
2749 unsigned dest;
2750
2751 cpus_and(tmp, cfg->domain, tmp);
2752 dest = cpu_mask_to_apicid(tmp);
2753
2754 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2755
2756 msg.address_lo =
2757 HT_IRQ_LOW_BASE |
2758 HT_IRQ_LOW_DEST_ID(dest) |
2759 HT_IRQ_LOW_VECTOR(cfg->vector) |
2760 ((INT_DEST_MODE == 0) ?
2761 HT_IRQ_LOW_DM_PHYSICAL :
2762 HT_IRQ_LOW_DM_LOGICAL) |
2763 HT_IRQ_LOW_RQEOI_EDGE |
2764 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2765 HT_IRQ_LOW_MT_FIXED :
2766 HT_IRQ_LOW_MT_ARBITRATED) |
2767 HT_IRQ_LOW_IRQ_MASKED;
2768
2769 write_ht_irq_msg(irq, &msg);
2770
2771 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2772 handle_edge_irq, "edge");
2773 }
2774 return err;
2775 }
2776 #endif /* CONFIG_HT_IRQ */
2777
2778 /* --------------------------------------------------------------------------
2779 ACPI-based IOAPIC Configuration
2780 -------------------------------------------------------------------------- */
2781
2782 #ifdef CONFIG_ACPI
2783
2784 #define IO_APIC_MAX_ID 0xFE
2785
2786 int __init io_apic_get_redir_entries (int ioapic)
2787 {
2788 union IO_APIC_reg_01 reg_01;
2789 unsigned long flags;
2790
2791 spin_lock_irqsave(&ioapic_lock, flags);
2792 reg_01.raw = io_apic_read(ioapic, 1);
2793 spin_unlock_irqrestore(&ioapic_lock, flags);
2794
2795 return reg_01.bits.entries;
2796 }
2797
2798
2799 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2800 {
2801 if (!IO_APIC_IRQ(irq)) {
2802 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2803 ioapic);
2804 return -EINVAL;
2805 }
2806
2807 /*
2808 * IRQs < 16 are already in the irq_2_pin[] map
2809 */
2810 if (irq >= 16)
2811 add_pin_to_irq(irq, ioapic, pin);
2812
2813 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2814
2815 return 0;
2816 }
2817
2818
2819 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2820 {
2821 int i;
2822
2823 if (skip_ioapic_setup)
2824 return -1;
2825
2826 for (i = 0; i < mp_irq_entries; i++)
2827 if (mp_irqs[i].mp_irqtype == mp_INT &&
2828 mp_irqs[i].mp_srcbusirq == bus_irq)
2829 break;
2830 if (i >= mp_irq_entries)
2831 return -1;
2832
2833 *trigger = irq_trigger(i);
2834 *polarity = irq_polarity(i);
2835 return 0;
2836 }
2837
2838 #endif /* CONFIG_ACPI */
2839
2840 /*
2841 * This function currently is only a helper for the i386 smp boot process where
2842 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2843 * so mask in all cases should simply be TARGET_CPUS
2844 */
2845 #ifdef CONFIG_SMP
2846 void __init setup_ioapic_dest(void)
2847 {
2848 int pin, ioapic, irq, irq_entry;
2849
2850 if (skip_ioapic_setup == 1)
2851 return;
2852
2853 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2854 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2855 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2856 if (irq_entry == -1)
2857 continue;
2858 irq = pin_2_irq(irq_entry, ioapic, pin);
2859
2860 /* setup_IO_APIC_irqs could fail to get vector for some device
2861 * when you have too many devices, because at that time only boot
2862 * cpu is online.
2863 */
2864 if (!irq_cfg[irq].vector)
2865 setup_IO_APIC_irq(ioapic, pin, irq,
2866 irq_trigger(irq_entry),
2867 irq_polarity(irq_entry));
2868 #ifdef CONFIG_INTR_REMAP
2869 else if (intr_remapping_enabled)
2870 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
2871 #endif
2872 else
2873 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2874 }
2875
2876 }
2877 }
2878 #endif
2879
2880 #define IOAPIC_RESOURCE_NAME_SIZE 11
2881
2882 static struct resource *ioapic_resources;
2883
2884 static struct resource * __init ioapic_setup_resources(void)
2885 {
2886 unsigned long n;
2887 struct resource *res;
2888 char *mem;
2889 int i;
2890
2891 if (nr_ioapics <= 0)
2892 return NULL;
2893
2894 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2895 n *= nr_ioapics;
2896
2897 mem = alloc_bootmem(n);
2898 res = (void *)mem;
2899
2900 if (mem != NULL) {
2901 mem += sizeof(struct resource) * nr_ioapics;
2902
2903 for (i = 0; i < nr_ioapics; i++) {
2904 res[i].name = mem;
2905 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2906 sprintf(mem, "IOAPIC %u", i);
2907 mem += IOAPIC_RESOURCE_NAME_SIZE;
2908 }
2909 }
2910
2911 ioapic_resources = res;
2912
2913 return res;
2914 }
2915
2916 void __init ioapic_init_mappings(void)
2917 {
2918 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2919 struct resource *ioapic_res;
2920 int i;
2921
2922 ioapic_res = ioapic_setup_resources();
2923 for (i = 0; i < nr_ioapics; i++) {
2924 if (smp_found_config) {
2925 ioapic_phys = mp_ioapics[i].mp_apicaddr;
2926 } else {
2927 ioapic_phys = (unsigned long)
2928 alloc_bootmem_pages(PAGE_SIZE);
2929 ioapic_phys = __pa(ioapic_phys);
2930 }
2931 set_fixmap_nocache(idx, ioapic_phys);
2932 apic_printk(APIC_VERBOSE,
2933 "mapped IOAPIC to %016lx (%016lx)\n",
2934 __fix_to_virt(idx), ioapic_phys);
2935 idx++;
2936
2937 if (ioapic_res != NULL) {
2938 ioapic_res->start = ioapic_phys;
2939 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2940 ioapic_res++;
2941 }
2942 }
2943 }
2944
2945 static int __init ioapic_insert_resources(void)
2946 {
2947 int i;
2948 struct resource *r = ioapic_resources;
2949
2950 if (!r) {
2951 printk(KERN_ERR
2952 "IO APIC resources could be not be allocated.\n");
2953 return -1;
2954 }
2955
2956 for (i = 0; i < nr_ioapics; i++) {
2957 insert_resource(&iomem_resource, r);
2958 r++;
2959 }
2960
2961 return 0;
2962 }
2963
2964 /* Insert the IO APIC resources after PCI initialization has occured to handle
2965 * IO APICS that are mapped in on a BAR in PCI space. */
2966 late_initcall(ioapic_insert_resources);
2967
Linux kernel - Deliverables
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