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Merge git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6
[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40 #include <linux/dmar.h>
41
42 #include <asm/idle.h>
43 #include <asm/io.h>
44 #include <asm/smp.h>
45 #include <asm/desc.h>
46 #include <asm/proto.h>
47 #include <asm/acpi.h>
48 #include <asm/dma.h>
49 #include <asm/i8259.h>
50 #include <asm/nmi.h>
51 #include <asm/msidef.h>
52 #include <asm/hypertransport.h>
53 #include <asm/irq_remapping.h>
54
55 #include <mach_ipi.h>
56 #include <mach_apic.h>
57
58 #define __apicdebuginit(type) static type __init
59
60 struct irq_cfg {
61 cpumask_t domain;
62 cpumask_t old_domain;
63 unsigned move_cleanup_count;
64 u8 vector;
65 u8 move_in_progress : 1;
66 };
67
68 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
69 static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
70 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
71 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
72 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
73 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
74 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
75 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
76 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
77 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
78 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
79 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
80 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
81 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
82 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
83 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
84 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
85 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
86 };
87
88 static int assign_irq_vector(int irq, cpumask_t mask);
89
90 int first_system_vector = 0xfe;
91
92 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
93
94 int sis_apic_bug; /* not actually supported, dummy for compile */
95
96 static int no_timer_check;
97
98 static int disable_timer_pin_1 __initdata;
99
100 int timer_through_8259 __initdata;
101
102 /* Where if anywhere is the i8259 connect in external int mode */
103 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
104
105 static DEFINE_SPINLOCK(ioapic_lock);
106 static DEFINE_SPINLOCK(vector_lock);
107
108 /*
109 * # of IRQ routing registers
110 */
111 int nr_ioapic_registers[MAX_IO_APICS];
112
113 /* I/O APIC RTE contents at the OS boot up */
114 struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
115
116 /* I/O APIC entries */
117 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
118 int nr_ioapics;
119
120 /* MP IRQ source entries */
121 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
122
123 /* # of MP IRQ source entries */
124 int mp_irq_entries;
125
126 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
127
128 /*
129 * Rough estimation of how many shared IRQs there are, can
130 * be changed anytime.
131 */
132 #define MAX_PLUS_SHARED_IRQS NR_IRQS
133 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
134
135 /*
136 * This is performance-critical, we want to do it O(1)
137 *
138 * the indexing order of this array favors 1:1 mappings
139 * between pins and IRQs.
140 */
141
142 static struct irq_pin_list {
143 short apic, pin, next;
144 } irq_2_pin[PIN_MAP_SIZE];
145
146 struct io_apic {
147 unsigned int index;
148 unsigned int unused[3];
149 unsigned int data;
150 };
151
152 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
153 {
154 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
155 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
156 }
157
158 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
159 {
160 struct io_apic __iomem *io_apic = io_apic_base(apic);
161 writel(reg, &io_apic->index);
162 return readl(&io_apic->data);
163 }
164
165 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
166 {
167 struct io_apic __iomem *io_apic = io_apic_base(apic);
168 writel(reg, &io_apic->index);
169 writel(value, &io_apic->data);
170 }
171
172 /*
173 * Re-write a value: to be used for read-modify-write
174 * cycles where the read already set up the index register.
175 */
176 static inline void io_apic_modify(unsigned int apic, unsigned int value)
177 {
178 struct io_apic __iomem *io_apic = io_apic_base(apic);
179 writel(value, &io_apic->data);
180 }
181
182 static bool io_apic_level_ack_pending(unsigned int irq)
183 {
184 struct irq_pin_list *entry;
185 unsigned long flags;
186
187 spin_lock_irqsave(&ioapic_lock, flags);
188 entry = irq_2_pin + irq;
189 for (;;) {
190 unsigned int reg;
191 int pin;
192
193 pin = entry->pin;
194 if (pin == -1)
195 break;
196 reg = io_apic_read(entry->apic, 0x10 + pin*2);
197 /* Is the remote IRR bit set? */
198 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
199 spin_unlock_irqrestore(&ioapic_lock, flags);
200 return true;
201 }
202 if (!entry->next)
203 break;
204 entry = irq_2_pin + entry->next;
205 }
206 spin_unlock_irqrestore(&ioapic_lock, flags);
207
208 return false;
209 }
210
211 /*
212 * Synchronize the IO-APIC and the CPU by doing
213 * a dummy read from the IO-APIC
214 */
215 static inline void io_apic_sync(unsigned int apic)
216 {
217 struct io_apic __iomem *io_apic = io_apic_base(apic);
218 readl(&io_apic->data);
219 }
220
221 #define __DO_ACTION(R, ACTION, FINAL) \
222 \
223 { \
224 int pin; \
225 struct irq_pin_list *entry = irq_2_pin + irq; \
226 \
227 BUG_ON(irq >= NR_IRQS); \
228 for (;;) { \
229 unsigned int reg; \
230 pin = entry->pin; \
231 if (pin == -1) \
232 break; \
233 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
234 reg ACTION; \
235 io_apic_modify(entry->apic, reg); \
236 FINAL; \
237 if (!entry->next) \
238 break; \
239 entry = irq_2_pin + entry->next; \
240 } \
241 }
242
243 union entry_union {
244 struct { u32 w1, w2; };
245 struct IO_APIC_route_entry entry;
246 };
247
248 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
249 {
250 union entry_union eu;
251 unsigned long flags;
252 spin_lock_irqsave(&ioapic_lock, flags);
253 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
254 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
255 spin_unlock_irqrestore(&ioapic_lock, flags);
256 return eu.entry;
257 }
258
259 /*
260 * When we write a new IO APIC routing entry, we need to write the high
261 * word first! If the mask bit in the low word is clear, we will enable
262 * the interrupt, and we need to make sure the entry is fully populated
263 * before that happens.
264 */
265 static void
266 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
267 {
268 union entry_union eu;
269 eu.entry = e;
270 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
271 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
272 }
273
274 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
275 {
276 unsigned long flags;
277 spin_lock_irqsave(&ioapic_lock, flags);
278 __ioapic_write_entry(apic, pin, e);
279 spin_unlock_irqrestore(&ioapic_lock, flags);
280 }
281
282 /*
283 * When we mask an IO APIC routing entry, we need to write the low
284 * word first, in order to set the mask bit before we change the
285 * high bits!
286 */
287 static void ioapic_mask_entry(int apic, int pin)
288 {
289 unsigned long flags;
290 union entry_union eu = { .entry.mask = 1 };
291
292 spin_lock_irqsave(&ioapic_lock, flags);
293 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
294 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
295 spin_unlock_irqrestore(&ioapic_lock, flags);
296 }
297
298 #ifdef CONFIG_SMP
299 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
300 {
301 int apic, pin;
302 struct irq_pin_list *entry = irq_2_pin + irq;
303
304 BUG_ON(irq >= NR_IRQS);
305 for (;;) {
306 unsigned int reg;
307 apic = entry->apic;
308 pin = entry->pin;
309 if (pin == -1)
310 break;
311 /*
312 * With interrupt-remapping, destination information comes
313 * from interrupt-remapping table entry.
314 */
315 if (!irq_remapped(irq))
316 io_apic_write(apic, 0x11 + pin*2, dest);
317 reg = io_apic_read(apic, 0x10 + pin*2);
318 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
319 reg |= vector;
320 io_apic_modify(apic, reg);
321 if (!entry->next)
322 break;
323 entry = irq_2_pin + entry->next;
324 }
325 }
326
327 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
328 {
329 struct irq_cfg *cfg = irq_cfg + irq;
330 unsigned long flags;
331 unsigned int dest;
332 cpumask_t tmp;
333
334 cpus_and(tmp, mask, cpu_online_map);
335 if (cpus_empty(tmp))
336 return;
337
338 if (assign_irq_vector(irq, mask))
339 return;
340
341 cpus_and(tmp, cfg->domain, mask);
342 dest = cpu_mask_to_apicid(tmp);
343
344 /*
345 * Only the high 8 bits are valid.
346 */
347 dest = SET_APIC_LOGICAL_ID(dest);
348
349 spin_lock_irqsave(&ioapic_lock, flags);
350 __target_IO_APIC_irq(irq, dest, cfg->vector);
351 irq_desc[irq].affinity = mask;
352 spin_unlock_irqrestore(&ioapic_lock, flags);
353 }
354 #endif
355
356 /*
357 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
358 * shared ISA-space IRQs, so we have to support them. We are super
359 * fast in the common case, and fast for shared ISA-space IRQs.
360 */
361 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
362 {
363 static int first_free_entry = NR_IRQS;
364 struct irq_pin_list *entry = irq_2_pin + irq;
365
366 BUG_ON(irq >= NR_IRQS);
367 while (entry->next)
368 entry = irq_2_pin + entry->next;
369
370 if (entry->pin != -1) {
371 entry->next = first_free_entry;
372 entry = irq_2_pin + entry->next;
373 if (++first_free_entry >= PIN_MAP_SIZE)
374 panic("io_apic.c: ran out of irq_2_pin entries!");
375 }
376 entry->apic = apic;
377 entry->pin = pin;
378 }
379
380 /*
381 * Reroute an IRQ to a different pin.
382 */
383 static void __init replace_pin_at_irq(unsigned int irq,
384 int oldapic, int oldpin,
385 int newapic, int newpin)
386 {
387 struct irq_pin_list *entry = irq_2_pin + irq;
388
389 while (1) {
390 if (entry->apic == oldapic && entry->pin == oldpin) {
391 entry->apic = newapic;
392 entry->pin = newpin;
393 }
394 if (!entry->next)
395 break;
396 entry = irq_2_pin + entry->next;
397 }
398 }
399
400
401 #define DO_ACTION(name,R,ACTION, FINAL) \
402 \
403 static void name##_IO_APIC_irq (unsigned int irq) \
404 __DO_ACTION(R, ACTION, FINAL)
405
406 /* mask = 1 */
407 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
408
409 /* mask = 0 */
410 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
411
412 static void mask_IO_APIC_irq (unsigned int irq)
413 {
414 unsigned long flags;
415
416 spin_lock_irqsave(&ioapic_lock, flags);
417 __mask_IO_APIC_irq(irq);
418 spin_unlock_irqrestore(&ioapic_lock, flags);
419 }
420
421 static void unmask_IO_APIC_irq (unsigned int irq)
422 {
423 unsigned long flags;
424
425 spin_lock_irqsave(&ioapic_lock, flags);
426 __unmask_IO_APIC_irq(irq);
427 spin_unlock_irqrestore(&ioapic_lock, flags);
428 }
429
430 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
431 {
432 struct IO_APIC_route_entry entry;
433
434 /* Check delivery_mode to be sure we're not clearing an SMI pin */
435 entry = ioapic_read_entry(apic, pin);
436 if (entry.delivery_mode == dest_SMI)
437 return;
438 /*
439 * Disable it in the IO-APIC irq-routing table:
440 */
441 ioapic_mask_entry(apic, pin);
442 }
443
444 static void clear_IO_APIC (void)
445 {
446 int apic, pin;
447
448 for (apic = 0; apic < nr_ioapics; apic++)
449 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
450 clear_IO_APIC_pin(apic, pin);
451 }
452
453 /*
454 * Saves and masks all the unmasked IO-APIC RTE's
455 */
456 int save_mask_IO_APIC_setup(void)
457 {
458 union IO_APIC_reg_01 reg_01;
459 unsigned long flags;
460 int apic, pin;
461
462 /*
463 * The number of IO-APIC IRQ registers (== #pins):
464 */
465 for (apic = 0; apic < nr_ioapics; apic++) {
466 spin_lock_irqsave(&ioapic_lock, flags);
467 reg_01.raw = io_apic_read(apic, 1);
468 spin_unlock_irqrestore(&ioapic_lock, flags);
469 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
470 }
471
472 for (apic = 0; apic < nr_ioapics; apic++) {
473 early_ioapic_entries[apic] =
474 kzalloc(sizeof(struct IO_APIC_route_entry) *
475 nr_ioapic_registers[apic], GFP_KERNEL);
476 if (!early_ioapic_entries[apic])
477 return -ENOMEM;
478 }
479
480 for (apic = 0; apic < nr_ioapics; apic++)
481 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
482 struct IO_APIC_route_entry entry;
483
484 entry = early_ioapic_entries[apic][pin] =
485 ioapic_read_entry(apic, pin);
486 if (!entry.mask) {
487 entry.mask = 1;
488 ioapic_write_entry(apic, pin, entry);
489 }
490 }
491 return 0;
492 }
493
494 void restore_IO_APIC_setup(void)
495 {
496 int apic, pin;
497
498 for (apic = 0; apic < nr_ioapics; apic++)
499 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
500 ioapic_write_entry(apic, pin,
501 early_ioapic_entries[apic][pin]);
502 }
503
504 void reinit_intr_remapped_IO_APIC(int intr_remapping)
505 {
506 /*
507 * for now plain restore of previous settings.
508 * TBD: In the case of OS enabling interrupt-remapping,
509 * IO-APIC RTE's need to be setup to point to interrupt-remapping
510 * table entries. for now, do a plain restore, and wait for
511 * the setup_IO_APIC_irqs() to do proper initialization.
512 */
513 restore_IO_APIC_setup();
514 }
515
516 int skip_ioapic_setup;
517 int ioapic_force;
518
519 static int __init parse_noapic(char *str)
520 {
521 disable_ioapic_setup();
522 return 0;
523 }
524 early_param("noapic", parse_noapic);
525
526 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
527 static int __init disable_timer_pin_setup(char *arg)
528 {
529 disable_timer_pin_1 = 1;
530 return 1;
531 }
532 __setup("disable_timer_pin_1", disable_timer_pin_setup);
533
534
535 /*
536 * Find the IRQ entry number of a certain pin.
537 */
538 static int find_irq_entry(int apic, int pin, int type)
539 {
540 int i;
541
542 for (i = 0; i < mp_irq_entries; i++)
543 if (mp_irqs[i].mp_irqtype == type &&
544 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
545 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
546 mp_irqs[i].mp_dstirq == pin)
547 return i;
548
549 return -1;
550 }
551
552 /*
553 * Find the pin to which IRQ[irq] (ISA) is connected
554 */
555 static int __init find_isa_irq_pin(int irq, int type)
556 {
557 int i;
558
559 for (i = 0; i < mp_irq_entries; i++) {
560 int lbus = mp_irqs[i].mp_srcbus;
561
562 if (test_bit(lbus, mp_bus_not_pci) &&
563 (mp_irqs[i].mp_irqtype == type) &&
564 (mp_irqs[i].mp_srcbusirq == irq))
565
566 return mp_irqs[i].mp_dstirq;
567 }
568 return -1;
569 }
570
571 static int __init find_isa_irq_apic(int irq, int type)
572 {
573 int i;
574
575 for (i = 0; i < mp_irq_entries; i++) {
576 int lbus = mp_irqs[i].mp_srcbus;
577
578 if (test_bit(lbus, mp_bus_not_pci) &&
579 (mp_irqs[i].mp_irqtype == type) &&
580 (mp_irqs[i].mp_srcbusirq == irq))
581 break;
582 }
583 if (i < mp_irq_entries) {
584 int apic;
585 for(apic = 0; apic < nr_ioapics; apic++) {
586 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
587 return apic;
588 }
589 }
590
591 return -1;
592 }
593
594 /*
595 * Find a specific PCI IRQ entry.
596 * Not an __init, possibly needed by modules
597 */
598 static int pin_2_irq(int idx, int apic, int pin);
599
600 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
601 {
602 int apic, i, best_guess = -1;
603
604 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
605 bus, slot, pin);
606 if (test_bit(bus, mp_bus_not_pci)) {
607 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
608 return -1;
609 }
610 for (i = 0; i < mp_irq_entries; i++) {
611 int lbus = mp_irqs[i].mp_srcbus;
612
613 for (apic = 0; apic < nr_ioapics; apic++)
614 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
615 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
616 break;
617
618 if (!test_bit(lbus, mp_bus_not_pci) &&
619 !mp_irqs[i].mp_irqtype &&
620 (bus == lbus) &&
621 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
622 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
623
624 if (!(apic || IO_APIC_IRQ(irq)))
625 continue;
626
627 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
628 return irq;
629 /*
630 * Use the first all-but-pin matching entry as a
631 * best-guess fuzzy result for broken mptables.
632 */
633 if (best_guess < 0)
634 best_guess = irq;
635 }
636 }
637 BUG_ON(best_guess >= NR_IRQS);
638 return best_guess;
639 }
640
641 /* ISA interrupts are always polarity zero edge triggered,
642 * when listed as conforming in the MP table. */
643
644 #define default_ISA_trigger(idx) (0)
645 #define default_ISA_polarity(idx) (0)
646
647 /* PCI interrupts are always polarity one level triggered,
648 * when listed as conforming in the MP table. */
649
650 #define default_PCI_trigger(idx) (1)
651 #define default_PCI_polarity(idx) (1)
652
653 static int MPBIOS_polarity(int idx)
654 {
655 int bus = mp_irqs[idx].mp_srcbus;
656 int polarity;
657
658 /*
659 * Determine IRQ line polarity (high active or low active):
660 */
661 switch (mp_irqs[idx].mp_irqflag & 3)
662 {
663 case 0: /* conforms, ie. bus-type dependent polarity */
664 if (test_bit(bus, mp_bus_not_pci))
665 polarity = default_ISA_polarity(idx);
666 else
667 polarity = default_PCI_polarity(idx);
668 break;
669 case 1: /* high active */
670 {
671 polarity = 0;
672 break;
673 }
674 case 2: /* reserved */
675 {
676 printk(KERN_WARNING "broken BIOS!!\n");
677 polarity = 1;
678 break;
679 }
680 case 3: /* low active */
681 {
682 polarity = 1;
683 break;
684 }
685 default: /* invalid */
686 {
687 printk(KERN_WARNING "broken BIOS!!\n");
688 polarity = 1;
689 break;
690 }
691 }
692 return polarity;
693 }
694
695 static int MPBIOS_trigger(int idx)
696 {
697 int bus = mp_irqs[idx].mp_srcbus;
698 int trigger;
699
700 /*
701 * Determine IRQ trigger mode (edge or level sensitive):
702 */
703 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
704 {
705 case 0: /* conforms, ie. bus-type dependent */
706 if (test_bit(bus, mp_bus_not_pci))
707 trigger = default_ISA_trigger(idx);
708 else
709 trigger = default_PCI_trigger(idx);
710 break;
711 case 1: /* edge */
712 {
713 trigger = 0;
714 break;
715 }
716 case 2: /* reserved */
717 {
718 printk(KERN_WARNING "broken BIOS!!\n");
719 trigger = 1;
720 break;
721 }
722 case 3: /* level */
723 {
724 trigger = 1;
725 break;
726 }
727 default: /* invalid */
728 {
729 printk(KERN_WARNING "broken BIOS!!\n");
730 trigger = 0;
731 break;
732 }
733 }
734 return trigger;
735 }
736
737 static inline int irq_polarity(int idx)
738 {
739 return MPBIOS_polarity(idx);
740 }
741
742 static inline int irq_trigger(int idx)
743 {
744 return MPBIOS_trigger(idx);
745 }
746
747 static int pin_2_irq(int idx, int apic, int pin)
748 {
749 int irq, i;
750 int bus = mp_irqs[idx].mp_srcbus;
751
752 /*
753 * Debugging check, we are in big trouble if this message pops up!
754 */
755 if (mp_irqs[idx].mp_dstirq != pin)
756 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
757
758 if (test_bit(bus, mp_bus_not_pci)) {
759 irq = mp_irqs[idx].mp_srcbusirq;
760 } else {
761 /*
762 * PCI IRQs are mapped in order
763 */
764 i = irq = 0;
765 while (i < apic)
766 irq += nr_ioapic_registers[i++];
767 irq += pin;
768 }
769 BUG_ON(irq >= NR_IRQS);
770 return irq;
771 }
772
773 void lock_vector_lock(void)
774 {
775 /* Used to the online set of cpus does not change
776 * during assign_irq_vector.
777 */
778 spin_lock(&vector_lock);
779 }
780
781 void unlock_vector_lock(void)
782 {
783 spin_unlock(&vector_lock);
784 }
785
786 static int __assign_irq_vector(int irq, cpumask_t mask)
787 {
788 /*
789 * NOTE! The local APIC isn't very good at handling
790 * multiple interrupts at the same interrupt level.
791 * As the interrupt level is determined by taking the
792 * vector number and shifting that right by 4, we
793 * want to spread these out a bit so that they don't
794 * all fall in the same interrupt level.
795 *
796 * Also, we've got to be careful not to trash gate
797 * 0x80, because int 0x80 is hm, kind of importantish. ;)
798 */
799 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
800 unsigned int old_vector;
801 int cpu;
802 struct irq_cfg *cfg;
803
804 BUG_ON((unsigned)irq >= NR_IRQS);
805 cfg = &irq_cfg[irq];
806
807 /* Only try and allocate irqs on cpus that are present */
808 cpus_and(mask, mask, cpu_online_map);
809
810 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
811 return -EBUSY;
812
813 old_vector = cfg->vector;
814 if (old_vector) {
815 cpumask_t tmp;
816 cpus_and(tmp, cfg->domain, mask);
817 if (!cpus_empty(tmp))
818 return 0;
819 }
820
821 for_each_cpu_mask_nr(cpu, mask) {
822 cpumask_t domain, new_mask;
823 int new_cpu;
824 int vector, offset;
825
826 domain = vector_allocation_domain(cpu);
827 cpus_and(new_mask, domain, cpu_online_map);
828
829 vector = current_vector;
830 offset = current_offset;
831 next:
832 vector += 8;
833 if (vector >= first_system_vector) {
834 /* If we run out of vectors on large boxen, must share them. */
835 offset = (offset + 1) % 8;
836 vector = FIRST_DEVICE_VECTOR + offset;
837 }
838 if (unlikely(current_vector == vector))
839 continue;
840 if (vector == IA32_SYSCALL_VECTOR)
841 goto next;
842 for_each_cpu_mask_nr(new_cpu, new_mask)
843 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
844 goto next;
845 /* Found one! */
846 current_vector = vector;
847 current_offset = offset;
848 if (old_vector) {
849 cfg->move_in_progress = 1;
850 cfg->old_domain = cfg->domain;
851 }
852 for_each_cpu_mask_nr(new_cpu, new_mask)
853 per_cpu(vector_irq, new_cpu)[vector] = irq;
854 cfg->vector = vector;
855 cfg->domain = domain;
856 return 0;
857 }
858 return -ENOSPC;
859 }
860
861 static int assign_irq_vector(int irq, cpumask_t mask)
862 {
863 int err;
864 unsigned long flags;
865
866 spin_lock_irqsave(&vector_lock, flags);
867 err = __assign_irq_vector(irq, mask);
868 spin_unlock_irqrestore(&vector_lock, flags);
869 return err;
870 }
871
872 static void __clear_irq_vector(int irq)
873 {
874 struct irq_cfg *cfg;
875 cpumask_t mask;
876 int cpu, vector;
877
878 BUG_ON((unsigned)irq >= NR_IRQS);
879 cfg = &irq_cfg[irq];
880 BUG_ON(!cfg->vector);
881
882 vector = cfg->vector;
883 cpus_and(mask, cfg->domain, cpu_online_map);
884 for_each_cpu_mask_nr(cpu, mask)
885 per_cpu(vector_irq, cpu)[vector] = -1;
886
887 cfg->vector = 0;
888 cpus_clear(cfg->domain);
889 }
890
891 void __setup_vector_irq(int cpu)
892 {
893 /* Initialize vector_irq on a new cpu */
894 /* This function must be called with vector_lock held */
895 int irq, vector;
896
897 /* Mark the inuse vectors */
898 for (irq = 0; irq < NR_IRQS; ++irq) {
899 if (!cpu_isset(cpu, irq_cfg[irq].domain))
900 continue;
901 vector = irq_cfg[irq].vector;
902 per_cpu(vector_irq, cpu)[vector] = irq;
903 }
904 /* Mark the free vectors */
905 for (vector = 0; vector < NR_VECTORS; ++vector) {
906 irq = per_cpu(vector_irq, cpu)[vector];
907 if (irq < 0)
908 continue;
909 if (!cpu_isset(cpu, irq_cfg[irq].domain))
910 per_cpu(vector_irq, cpu)[vector] = -1;
911 }
912 }
913
914 static struct irq_chip ioapic_chip;
915 #ifdef CONFIG_INTR_REMAP
916 static struct irq_chip ir_ioapic_chip;
917 #endif
918
919 static void ioapic_register_intr(int irq, unsigned long trigger)
920 {
921 if (trigger)
922 irq_desc[irq].status |= IRQ_LEVEL;
923 else
924 irq_desc[irq].status &= ~IRQ_LEVEL;
925
926 #ifdef CONFIG_INTR_REMAP
927 if (irq_remapped(irq)) {
928 irq_desc[irq].status |= IRQ_MOVE_PCNTXT;
929 if (trigger)
930 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
931 handle_fasteoi_irq,
932 "fasteoi");
933 else
934 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
935 handle_edge_irq, "edge");
936 return;
937 }
938 #endif
939 if (trigger)
940 set_irq_chip_and_handler_name(irq, &ioapic_chip,
941 handle_fasteoi_irq,
942 "fasteoi");
943 else
944 set_irq_chip_and_handler_name(irq, &ioapic_chip,
945 handle_edge_irq, "edge");
946 }
947
948 static int setup_ioapic_entry(int apic, int irq,
949 struct IO_APIC_route_entry *entry,
950 unsigned int destination, int trigger,
951 int polarity, int vector)
952 {
953 /*
954 * add it to the IO-APIC irq-routing table:
955 */
956 memset(entry,0,sizeof(*entry));
957
958 #ifdef CONFIG_INTR_REMAP
959 if (intr_remapping_enabled) {
960 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
961 struct irte irte;
962 struct IR_IO_APIC_route_entry *ir_entry =
963 (struct IR_IO_APIC_route_entry *) entry;
964 int index;
965
966 if (!iommu)
967 panic("No mapping iommu for ioapic %d\n", apic);
968
969 index = alloc_irte(iommu, irq, 1);
970 if (index < 0)
971 panic("Failed to allocate IRTE for ioapic %d\n", apic);
972
973 memset(&irte, 0, sizeof(irte));
974
975 irte.present = 1;
976 irte.dst_mode = INT_DEST_MODE;
977 irte.trigger_mode = trigger;
978 irte.dlvry_mode = INT_DELIVERY_MODE;
979 irte.vector = vector;
980 irte.dest_id = IRTE_DEST(destination);
981
982 modify_irte(irq, &irte);
983
984 ir_entry->index2 = (index >> 15) & 0x1;
985 ir_entry->zero = 0;
986 ir_entry->format = 1;
987 ir_entry->index = (index & 0x7fff);
988 } else
989 #endif
990 {
991 entry->delivery_mode = INT_DELIVERY_MODE;
992 entry->dest_mode = INT_DEST_MODE;
993 entry->dest = destination;
994 }
995
996 entry->mask = 0; /* enable IRQ */
997 entry->trigger = trigger;
998 entry->polarity = polarity;
999 entry->vector = vector;
1000
1001 /* Mask level triggered irqs.
1002 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1003 */
1004 if (trigger)
1005 entry->mask = 1;
1006 return 0;
1007 }
1008
1009 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1010 int trigger, int polarity)
1011 {
1012 struct irq_cfg *cfg = irq_cfg + irq;
1013 struct IO_APIC_route_entry entry;
1014 cpumask_t mask;
1015
1016 if (!IO_APIC_IRQ(irq))
1017 return;
1018
1019 mask = TARGET_CPUS;
1020 if (assign_irq_vector(irq, mask))
1021 return;
1022
1023 cpus_and(mask, cfg->domain, mask);
1024
1025 apic_printk(APIC_VERBOSE,KERN_DEBUG
1026 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1027 "IRQ %d Mode:%i Active:%i)\n",
1028 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1029 irq, trigger, polarity);
1030
1031
1032 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1033 cpu_mask_to_apicid(mask), trigger, polarity,
1034 cfg->vector)) {
1035 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1036 mp_ioapics[apic].mp_apicid, pin);
1037 __clear_irq_vector(irq);
1038 return;
1039 }
1040
1041 ioapic_register_intr(irq, trigger);
1042 if (irq < 16)
1043 disable_8259A_irq(irq);
1044
1045 ioapic_write_entry(apic, pin, entry);
1046 }
1047
1048 static void __init setup_IO_APIC_irqs(void)
1049 {
1050 int apic, pin, idx, irq, first_notcon = 1;
1051
1052 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1053
1054 for (apic = 0; apic < nr_ioapics; apic++) {
1055 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1056
1057 idx = find_irq_entry(apic,pin,mp_INT);
1058 if (idx == -1) {
1059 if (first_notcon) {
1060 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1061 first_notcon = 0;
1062 } else
1063 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1064 continue;
1065 }
1066 if (!first_notcon) {
1067 apic_printk(APIC_VERBOSE, " not connected.\n");
1068 first_notcon = 1;
1069 }
1070
1071 irq = pin_2_irq(idx, apic, pin);
1072 add_pin_to_irq(irq, apic, pin);
1073
1074 setup_IO_APIC_irq(apic, pin, irq,
1075 irq_trigger(idx), irq_polarity(idx));
1076 }
1077 }
1078
1079 if (!first_notcon)
1080 apic_printk(APIC_VERBOSE, " not connected.\n");
1081 }
1082
1083 /*
1084 * Set up the timer pin, possibly with the 8259A-master behind.
1085 */
1086 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1087 int vector)
1088 {
1089 struct IO_APIC_route_entry entry;
1090
1091 if (intr_remapping_enabled)
1092 return;
1093
1094 memset(&entry, 0, sizeof(entry));
1095
1096 /*
1097 * We use logical delivery to get the timer IRQ
1098 * to the first CPU.
1099 */
1100 entry.dest_mode = INT_DEST_MODE;
1101 entry.mask = 1; /* mask IRQ now */
1102 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1103 entry.delivery_mode = INT_DELIVERY_MODE;
1104 entry.polarity = 0;
1105 entry.trigger = 0;
1106 entry.vector = vector;
1107
1108 /*
1109 * The timer IRQ doesn't have to know that behind the
1110 * scene we may have a 8259A-master in AEOI mode ...
1111 */
1112 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1113
1114 /*
1115 * Add it to the IO-APIC irq-routing table:
1116 */
1117 ioapic_write_entry(apic, pin, entry);
1118 }
1119
1120
1121 __apicdebuginit(void) print_IO_APIC(void)
1122 {
1123 int apic, i;
1124 union IO_APIC_reg_00 reg_00;
1125 union IO_APIC_reg_01 reg_01;
1126 union IO_APIC_reg_02 reg_02;
1127 unsigned long flags;
1128
1129 if (apic_verbosity == APIC_QUIET)
1130 return;
1131
1132 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1133 for (i = 0; i < nr_ioapics; i++)
1134 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1135 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1136
1137 /*
1138 * We are a bit conservative about what we expect. We have to
1139 * know about every hardware change ASAP.
1140 */
1141 printk(KERN_INFO "testing the IO APIC.......................\n");
1142
1143 for (apic = 0; apic < nr_ioapics; apic++) {
1144
1145 spin_lock_irqsave(&ioapic_lock, flags);
1146 reg_00.raw = io_apic_read(apic, 0);
1147 reg_01.raw = io_apic_read(apic, 1);
1148 if (reg_01.bits.version >= 0x10)
1149 reg_02.raw = io_apic_read(apic, 2);
1150 spin_unlock_irqrestore(&ioapic_lock, flags);
1151
1152 printk("\n");
1153 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1154 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1155 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1156
1157 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1158 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1159
1160 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1161 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1162
1163 if (reg_01.bits.version >= 0x10) {
1164 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1165 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1166 }
1167
1168 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1169
1170 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1171 " Stat Dmod Deli Vect: \n");
1172
1173 for (i = 0; i <= reg_01.bits.entries; i++) {
1174 struct IO_APIC_route_entry entry;
1175
1176 entry = ioapic_read_entry(apic, i);
1177
1178 printk(KERN_DEBUG " %02x %03X ",
1179 i,
1180 entry.dest
1181 );
1182
1183 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1184 entry.mask,
1185 entry.trigger,
1186 entry.irr,
1187 entry.polarity,
1188 entry.delivery_status,
1189 entry.dest_mode,
1190 entry.delivery_mode,
1191 entry.vector
1192 );
1193 }
1194 }
1195 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1196 for (i = 0; i < NR_IRQS; i++) {
1197 struct irq_pin_list *entry = irq_2_pin + i;
1198 if (entry->pin < 0)
1199 continue;
1200 printk(KERN_DEBUG "IRQ%d ", i);
1201 for (;;) {
1202 printk("-> %d:%d", entry->apic, entry->pin);
1203 if (!entry->next)
1204 break;
1205 entry = irq_2_pin + entry->next;
1206 }
1207 printk("\n");
1208 }
1209
1210 printk(KERN_INFO ".................................... done.\n");
1211
1212 return;
1213 }
1214
1215 __apicdebuginit(void) print_APIC_bitfield(int base)
1216 {
1217 unsigned int v;
1218 int i, j;
1219
1220 if (apic_verbosity == APIC_QUIET)
1221 return;
1222
1223 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1224 for (i = 0; i < 8; i++) {
1225 v = apic_read(base + i*0x10);
1226 for (j = 0; j < 32; j++) {
1227 if (v & (1<<j))
1228 printk("1");
1229 else
1230 printk("0");
1231 }
1232 printk("\n");
1233 }
1234 }
1235
1236 __apicdebuginit(void) print_local_APIC(void *dummy)
1237 {
1238 unsigned int v, ver, maxlvt;
1239 unsigned long icr;
1240
1241 if (apic_verbosity == APIC_QUIET)
1242 return;
1243
1244 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1245 smp_processor_id(), hard_smp_processor_id());
1246 v = apic_read(APIC_ID);
1247 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1248 v = apic_read(APIC_LVR);
1249 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1250 ver = GET_APIC_VERSION(v);
1251 maxlvt = lapic_get_maxlvt();
1252
1253 v = apic_read(APIC_TASKPRI);
1254 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1255
1256 v = apic_read(APIC_ARBPRI);
1257 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1258 v & APIC_ARBPRI_MASK);
1259 v = apic_read(APIC_PROCPRI);
1260 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1261
1262 v = apic_read(APIC_EOI);
1263 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1264 v = apic_read(APIC_RRR);
1265 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1266 v = apic_read(APIC_LDR);
1267 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1268 v = apic_read(APIC_DFR);
1269 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1270 v = apic_read(APIC_SPIV);
1271 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1272
1273 printk(KERN_DEBUG "... APIC ISR field:\n");
1274 print_APIC_bitfield(APIC_ISR);
1275 printk(KERN_DEBUG "... APIC TMR field:\n");
1276 print_APIC_bitfield(APIC_TMR);
1277 printk(KERN_DEBUG "... APIC IRR field:\n");
1278 print_APIC_bitfield(APIC_IRR);
1279
1280 v = apic_read(APIC_ESR);
1281 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1282
1283 icr = apic_icr_read();
1284 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1285 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1286
1287 v = apic_read(APIC_LVTT);
1288 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1289
1290 if (maxlvt > 3) { /* PC is LVT#4. */
1291 v = apic_read(APIC_LVTPC);
1292 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1293 }
1294 v = apic_read(APIC_LVT0);
1295 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1296 v = apic_read(APIC_LVT1);
1297 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1298
1299 if (maxlvt > 2) { /* ERR is LVT#3. */
1300 v = apic_read(APIC_LVTERR);
1301 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1302 }
1303
1304 v = apic_read(APIC_TMICT);
1305 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1306 v = apic_read(APIC_TMCCT);
1307 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1308 v = apic_read(APIC_TDCR);
1309 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1310 printk("\n");
1311 }
1312
1313 __apicdebuginit(void) print_all_local_APICs(void)
1314 {
1315 on_each_cpu(print_local_APIC, NULL, 1);
1316 }
1317
1318 __apicdebuginit(void) print_PIC(void)
1319 {
1320 unsigned int v;
1321 unsigned long flags;
1322
1323 if (apic_verbosity == APIC_QUIET)
1324 return;
1325
1326 printk(KERN_DEBUG "\nprinting PIC contents\n");
1327
1328 spin_lock_irqsave(&i8259A_lock, flags);
1329
1330 v = inb(0xa1) << 8 | inb(0x21);
1331 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1332
1333 v = inb(0xa0) << 8 | inb(0x20);
1334 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1335
1336 outb(0x0b,0xa0);
1337 outb(0x0b,0x20);
1338 v = inb(0xa0) << 8 | inb(0x20);
1339 outb(0x0a,0xa0);
1340 outb(0x0a,0x20);
1341
1342 spin_unlock_irqrestore(&i8259A_lock, flags);
1343
1344 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1345
1346 v = inb(0x4d1) << 8 | inb(0x4d0);
1347 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1348 }
1349
1350 __apicdebuginit(int) print_all_ICs(void)
1351 {
1352 print_PIC();
1353 print_all_local_APICs();
1354 print_IO_APIC();
1355
1356 return 0;
1357 }
1358
1359 fs_initcall(print_all_ICs);
1360
1361
1362 void __init enable_IO_APIC(void)
1363 {
1364 union IO_APIC_reg_01 reg_01;
1365 int i8259_apic, i8259_pin;
1366 int i, apic;
1367 unsigned long flags;
1368
1369 for (i = 0; i < PIN_MAP_SIZE; i++) {
1370 irq_2_pin[i].pin = -1;
1371 irq_2_pin[i].next = 0;
1372 }
1373
1374 /*
1375 * The number of IO-APIC IRQ registers (== #pins):
1376 */
1377 for (apic = 0; apic < nr_ioapics; apic++) {
1378 spin_lock_irqsave(&ioapic_lock, flags);
1379 reg_01.raw = io_apic_read(apic, 1);
1380 spin_unlock_irqrestore(&ioapic_lock, flags);
1381 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1382 }
1383 for(apic = 0; apic < nr_ioapics; apic++) {
1384 int pin;
1385 /* See if any of the pins is in ExtINT mode */
1386 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1387 struct IO_APIC_route_entry entry;
1388 entry = ioapic_read_entry(apic, pin);
1389
1390 /* If the interrupt line is enabled and in ExtInt mode
1391 * I have found the pin where the i8259 is connected.
1392 */
1393 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1394 ioapic_i8259.apic = apic;
1395 ioapic_i8259.pin = pin;
1396 goto found_i8259;
1397 }
1398 }
1399 }
1400 found_i8259:
1401 /* Look to see what if the MP table has reported the ExtINT */
1402 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1403 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1404 /* Trust the MP table if nothing is setup in the hardware */
1405 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1406 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1407 ioapic_i8259.pin = i8259_pin;
1408 ioapic_i8259.apic = i8259_apic;
1409 }
1410 /* Complain if the MP table and the hardware disagree */
1411 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1412 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1413 {
1414 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1415 }
1416
1417 /*
1418 * Do not trust the IO-APIC being empty at bootup
1419 */
1420 clear_IO_APIC();
1421 }
1422
1423 /*
1424 * Not an __init, needed by the reboot code
1425 */
1426 void disable_IO_APIC(void)
1427 {
1428 /*
1429 * Clear the IO-APIC before rebooting:
1430 */
1431 clear_IO_APIC();
1432
1433 /*
1434 * If the i8259 is routed through an IOAPIC
1435 * Put that IOAPIC in virtual wire mode
1436 * so legacy interrupts can be delivered.
1437 */
1438 if (ioapic_i8259.pin != -1) {
1439 struct IO_APIC_route_entry entry;
1440
1441 memset(&entry, 0, sizeof(entry));
1442 entry.mask = 0; /* Enabled */
1443 entry.trigger = 0; /* Edge */
1444 entry.irr = 0;
1445 entry.polarity = 0; /* High */
1446 entry.delivery_status = 0;
1447 entry.dest_mode = 0; /* Physical */
1448 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1449 entry.vector = 0;
1450 entry.dest = read_apic_id();
1451
1452 /*
1453 * Add it to the IO-APIC irq-routing table:
1454 */
1455 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1456 }
1457
1458 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1459 }
1460
1461 /*
1462 * There is a nasty bug in some older SMP boards, their mptable lies
1463 * about the timer IRQ. We do the following to work around the situation:
1464 *
1465 * - timer IRQ defaults to IO-APIC IRQ
1466 * - if this function detects that timer IRQs are defunct, then we fall
1467 * back to ISA timer IRQs
1468 */
1469 static int __init timer_irq_works(void)
1470 {
1471 unsigned long t1 = jiffies;
1472 unsigned long flags;
1473
1474 local_save_flags(flags);
1475 local_irq_enable();
1476 /* Let ten ticks pass... */
1477 mdelay((10 * 1000) / HZ);
1478 local_irq_restore(flags);
1479
1480 /*
1481 * Expect a few ticks at least, to be sure some possible
1482 * glue logic does not lock up after one or two first
1483 * ticks in a non-ExtINT mode. Also the local APIC
1484 * might have cached one ExtINT interrupt. Finally, at
1485 * least one tick may be lost due to delays.
1486 */
1487
1488 /* jiffies wrap? */
1489 if (time_after(jiffies, t1 + 4))
1490 return 1;
1491 return 0;
1492 }
1493
1494 /*
1495 * In the SMP+IOAPIC case it might happen that there are an unspecified
1496 * number of pending IRQ events unhandled. These cases are very rare,
1497 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1498 * better to do it this way as thus we do not have to be aware of
1499 * 'pending' interrupts in the IRQ path, except at this point.
1500 */
1501 /*
1502 * Edge triggered needs to resend any interrupt
1503 * that was delayed but this is now handled in the device
1504 * independent code.
1505 */
1506
1507 /*
1508 * Starting up a edge-triggered IO-APIC interrupt is
1509 * nasty - we need to make sure that we get the edge.
1510 * If it is already asserted for some reason, we need
1511 * return 1 to indicate that is was pending.
1512 *
1513 * This is not complete - we should be able to fake
1514 * an edge even if it isn't on the 8259A...
1515 */
1516
1517 static unsigned int startup_ioapic_irq(unsigned int irq)
1518 {
1519 int was_pending = 0;
1520 unsigned long flags;
1521
1522 spin_lock_irqsave(&ioapic_lock, flags);
1523 if (irq < 16) {
1524 disable_8259A_irq(irq);
1525 if (i8259A_irq_pending(irq))
1526 was_pending = 1;
1527 }
1528 __unmask_IO_APIC_irq(irq);
1529 spin_unlock_irqrestore(&ioapic_lock, flags);
1530
1531 return was_pending;
1532 }
1533
1534 static int ioapic_retrigger_irq(unsigned int irq)
1535 {
1536 struct irq_cfg *cfg = &irq_cfg[irq];
1537 unsigned long flags;
1538
1539 spin_lock_irqsave(&vector_lock, flags);
1540 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
1541 spin_unlock_irqrestore(&vector_lock, flags);
1542
1543 return 1;
1544 }
1545
1546 /*
1547 * Level and edge triggered IO-APIC interrupts need different handling,
1548 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1549 * handled with the level-triggered descriptor, but that one has slightly
1550 * more overhead. Level-triggered interrupts cannot be handled with the
1551 * edge-triggered handler, without risking IRQ storms and other ugly
1552 * races.
1553 */
1554
1555 #ifdef CONFIG_SMP
1556
1557 #ifdef CONFIG_INTR_REMAP
1558 static void ir_irq_migration(struct work_struct *work);
1559
1560 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
1561
1562 /*
1563 * Migrate the IO-APIC irq in the presence of intr-remapping.
1564 *
1565 * For edge triggered, irq migration is a simple atomic update(of vector
1566 * and cpu destination) of IRTE and flush the hardware cache.
1567 *
1568 * For level triggered, we need to modify the io-apic RTE aswell with the update
1569 * vector information, along with modifying IRTE with vector and destination.
1570 * So irq migration for level triggered is little bit more complex compared to
1571 * edge triggered migration. But the good news is, we use the same algorithm
1572 * for level triggered migration as we have today, only difference being,
1573 * we now initiate the irq migration from process context instead of the
1574 * interrupt context.
1575 *
1576 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1577 * suppression) to the IO-APIC, level triggered irq migration will also be
1578 * as simple as edge triggered migration and we can do the irq migration
1579 * with a simple atomic update to IO-APIC RTE.
1580 */
1581 static void migrate_ioapic_irq(int irq, cpumask_t mask)
1582 {
1583 struct irq_cfg *cfg = irq_cfg + irq;
1584 struct irq_desc *desc = irq_desc + irq;
1585 cpumask_t tmp, cleanup_mask;
1586 struct irte irte;
1587 int modify_ioapic_rte = desc->status & IRQ_LEVEL;
1588 unsigned int dest;
1589 unsigned long flags;
1590
1591 cpus_and(tmp, mask, cpu_online_map);
1592 if (cpus_empty(tmp))
1593 return;
1594
1595 if (get_irte(irq, &irte))
1596 return;
1597
1598 if (assign_irq_vector(irq, mask))
1599 return;
1600
1601 cpus_and(tmp, cfg->domain, mask);
1602 dest = cpu_mask_to_apicid(tmp);
1603
1604 if (modify_ioapic_rte) {
1605 spin_lock_irqsave(&ioapic_lock, flags);
1606 __target_IO_APIC_irq(irq, dest, cfg->vector);
1607 spin_unlock_irqrestore(&ioapic_lock, flags);
1608 }
1609
1610 irte.vector = cfg->vector;
1611 irte.dest_id = IRTE_DEST(dest);
1612
1613 /*
1614 * Modified the IRTE and flushes the Interrupt entry cache.
1615 */
1616 modify_irte(irq, &irte);
1617
1618 if (cfg->move_in_progress) {
1619 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1620 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1621 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1622 cfg->move_in_progress = 0;
1623 }
1624
1625 irq_desc[irq].affinity = mask;
1626 }
1627
1628 static int migrate_irq_remapped_level(int irq)
1629 {
1630 int ret = -1;
1631
1632 mask_IO_APIC_irq(irq);
1633
1634 if (io_apic_level_ack_pending(irq)) {
1635 /*
1636 * Interrupt in progress. Migrating irq now will change the
1637 * vector information in the IO-APIC RTE and that will confuse
1638 * the EOI broadcast performed by cpu.
1639 * So, delay the irq migration to the next instance.
1640 */
1641 schedule_delayed_work(&ir_migration_work, 1);
1642 goto unmask;
1643 }
1644
1645 /* everthing is clear. we have right of way */
1646 migrate_ioapic_irq(irq, irq_desc[irq].pending_mask);
1647
1648 ret = 0;
1649 irq_desc[irq].status &= ~IRQ_MOVE_PENDING;
1650 cpus_clear(irq_desc[irq].pending_mask);
1651
1652 unmask:
1653 unmask_IO_APIC_irq(irq);
1654 return ret;
1655 }
1656
1657 static void ir_irq_migration(struct work_struct *work)
1658 {
1659 int irq;
1660
1661 for (irq = 0; irq < NR_IRQS; irq++) {
1662 struct irq_desc *desc = irq_desc + irq;
1663 if (desc->status & IRQ_MOVE_PENDING) {
1664 unsigned long flags;
1665
1666 spin_lock_irqsave(&desc->lock, flags);
1667 if (!desc->chip->set_affinity ||
1668 !(desc->status & IRQ_MOVE_PENDING)) {
1669 desc->status &= ~IRQ_MOVE_PENDING;
1670 spin_unlock_irqrestore(&desc->lock, flags);
1671 continue;
1672 }
1673
1674 desc->chip->set_affinity(irq,
1675 irq_desc[irq].pending_mask);
1676 spin_unlock_irqrestore(&desc->lock, flags);
1677 }
1678 }
1679 }
1680
1681 /*
1682 * Migrates the IRQ destination in the process context.
1683 */
1684 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1685 {
1686 if (irq_desc[irq].status & IRQ_LEVEL) {
1687 irq_desc[irq].status |= IRQ_MOVE_PENDING;
1688 irq_desc[irq].pending_mask = mask;
1689 migrate_irq_remapped_level(irq);
1690 return;
1691 }
1692
1693 migrate_ioapic_irq(irq, mask);
1694 }
1695 #endif
1696
1697 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1698 {
1699 unsigned vector, me;
1700 ack_APIC_irq();
1701 exit_idle();
1702 irq_enter();
1703
1704 me = smp_processor_id();
1705 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1706 unsigned int irq;
1707 struct irq_desc *desc;
1708 struct irq_cfg *cfg;
1709 irq = __get_cpu_var(vector_irq)[vector];
1710 if (irq >= NR_IRQS)
1711 continue;
1712
1713 desc = irq_desc + irq;
1714 cfg = irq_cfg + irq;
1715 spin_lock(&desc->lock);
1716 if (!cfg->move_cleanup_count)
1717 goto unlock;
1718
1719 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1720 goto unlock;
1721
1722 __get_cpu_var(vector_irq)[vector] = -1;
1723 cfg->move_cleanup_count--;
1724 unlock:
1725 spin_unlock(&desc->lock);
1726 }
1727
1728 irq_exit();
1729 }
1730
1731 static void irq_complete_move(unsigned int irq)
1732 {
1733 struct irq_cfg *cfg = irq_cfg + irq;
1734 unsigned vector, me;
1735
1736 if (likely(!cfg->move_in_progress))
1737 return;
1738
1739 vector = ~get_irq_regs()->orig_ax;
1740 me = smp_processor_id();
1741 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1742 cpumask_t cleanup_mask;
1743
1744 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1745 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1746 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1747 cfg->move_in_progress = 0;
1748 }
1749 }
1750 #else
1751 static inline void irq_complete_move(unsigned int irq) {}
1752 #endif
1753 #ifdef CONFIG_INTR_REMAP
1754 static void ack_x2apic_level(unsigned int irq)
1755 {
1756 ack_x2APIC_irq();
1757 }
1758
1759 static void ack_x2apic_edge(unsigned int irq)
1760 {
1761 ack_x2APIC_irq();
1762 }
1763 #endif
1764
1765 static void ack_apic_edge(unsigned int irq)
1766 {
1767 irq_complete_move(irq);
1768 move_native_irq(irq);
1769 ack_APIC_irq();
1770 }
1771
1772 static void ack_apic_level(unsigned int irq)
1773 {
1774 int do_unmask_irq = 0;
1775
1776 irq_complete_move(irq);
1777 #ifdef CONFIG_GENERIC_PENDING_IRQ
1778 /* If we are moving the irq we need to mask it */
1779 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1780 do_unmask_irq = 1;
1781 mask_IO_APIC_irq(irq);
1782 }
1783 #endif
1784
1785 /*
1786 * We must acknowledge the irq before we move it or the acknowledge will
1787 * not propagate properly.
1788 */
1789 ack_APIC_irq();
1790
1791 /* Now we can move and renable the irq */
1792 if (unlikely(do_unmask_irq)) {
1793 /* Only migrate the irq if the ack has been received.
1794 *
1795 * On rare occasions the broadcast level triggered ack gets
1796 * delayed going to ioapics, and if we reprogram the
1797 * vector while Remote IRR is still set the irq will never
1798 * fire again.
1799 *
1800 * To prevent this scenario we read the Remote IRR bit
1801 * of the ioapic. This has two effects.
1802 * - On any sane system the read of the ioapic will
1803 * flush writes (and acks) going to the ioapic from
1804 * this cpu.
1805 * - We get to see if the ACK has actually been delivered.
1806 *
1807 * Based on failed experiments of reprogramming the
1808 * ioapic entry from outside of irq context starting
1809 * with masking the ioapic entry and then polling until
1810 * Remote IRR was clear before reprogramming the
1811 * ioapic I don't trust the Remote IRR bit to be
1812 * completey accurate.
1813 *
1814 * However there appears to be no other way to plug
1815 * this race, so if the Remote IRR bit is not
1816 * accurate and is causing problems then it is a hardware bug
1817 * and you can go talk to the chipset vendor about it.
1818 */
1819 if (!io_apic_level_ack_pending(irq))
1820 move_masked_irq(irq);
1821 unmask_IO_APIC_irq(irq);
1822 }
1823 }
1824
1825 static struct irq_chip ioapic_chip __read_mostly = {
1826 .name = "IO-APIC",
1827 .startup = startup_ioapic_irq,
1828 .mask = mask_IO_APIC_irq,
1829 .unmask = unmask_IO_APIC_irq,
1830 .ack = ack_apic_edge,
1831 .eoi = ack_apic_level,
1832 #ifdef CONFIG_SMP
1833 .set_affinity = set_ioapic_affinity_irq,
1834 #endif
1835 .retrigger = ioapic_retrigger_irq,
1836 };
1837
1838 #ifdef CONFIG_INTR_REMAP
1839 static struct irq_chip ir_ioapic_chip __read_mostly = {
1840 .name = "IR-IO-APIC",
1841 .startup = startup_ioapic_irq,
1842 .mask = mask_IO_APIC_irq,
1843 .unmask = unmask_IO_APIC_irq,
1844 .ack = ack_x2apic_edge,
1845 .eoi = ack_x2apic_level,
1846 #ifdef CONFIG_SMP
1847 .set_affinity = set_ir_ioapic_affinity_irq,
1848 #endif
1849 .retrigger = ioapic_retrigger_irq,
1850 };
1851 #endif
1852
1853 static inline void init_IO_APIC_traps(void)
1854 {
1855 int irq;
1856
1857 /*
1858 * NOTE! The local APIC isn't very good at handling
1859 * multiple interrupts at the same interrupt level.
1860 * As the interrupt level is determined by taking the
1861 * vector number and shifting that right by 4, we
1862 * want to spread these out a bit so that they don't
1863 * all fall in the same interrupt level.
1864 *
1865 * Also, we've got to be careful not to trash gate
1866 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1867 */
1868 for (irq = 0; irq < NR_IRQS ; irq++) {
1869 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1870 /*
1871 * Hmm.. We don't have an entry for this,
1872 * so default to an old-fashioned 8259
1873 * interrupt if we can..
1874 */
1875 if (irq < 16)
1876 make_8259A_irq(irq);
1877 else
1878 /* Strange. Oh, well.. */
1879 irq_desc[irq].chip = &no_irq_chip;
1880 }
1881 }
1882 }
1883
1884 static void unmask_lapic_irq(unsigned int irq)
1885 {
1886 unsigned long v;
1887
1888 v = apic_read(APIC_LVT0);
1889 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1890 }
1891
1892 static void mask_lapic_irq(unsigned int irq)
1893 {
1894 unsigned long v;
1895
1896 v = apic_read(APIC_LVT0);
1897 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1898 }
1899
1900 static void ack_lapic_irq (unsigned int irq)
1901 {
1902 ack_APIC_irq();
1903 }
1904
1905 static struct irq_chip lapic_chip __read_mostly = {
1906 .name = "local-APIC",
1907 .mask = mask_lapic_irq,
1908 .unmask = unmask_lapic_irq,
1909 .ack = ack_lapic_irq,
1910 };
1911
1912 static void lapic_register_intr(int irq)
1913 {
1914 irq_desc[irq].status &= ~IRQ_LEVEL;
1915 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1916 "edge");
1917 }
1918
1919 static void __init setup_nmi(void)
1920 {
1921 /*
1922 * Dirty trick to enable the NMI watchdog ...
1923 * We put the 8259A master into AEOI mode and
1924 * unmask on all local APICs LVT0 as NMI.
1925 *
1926 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1927 * is from Maciej W. Rozycki - so we do not have to EOI from
1928 * the NMI handler or the timer interrupt.
1929 */
1930 printk(KERN_INFO "activating NMI Watchdog ...");
1931
1932 enable_NMI_through_LVT0();
1933
1934 printk(" done.\n");
1935 }
1936
1937 /*
1938 * This looks a bit hackish but it's about the only one way of sending
1939 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1940 * not support the ExtINT mode, unfortunately. We need to send these
1941 * cycles as some i82489DX-based boards have glue logic that keeps the
1942 * 8259A interrupt line asserted until INTA. --macro
1943 */
1944 static inline void __init unlock_ExtINT_logic(void)
1945 {
1946 int apic, pin, i;
1947 struct IO_APIC_route_entry entry0, entry1;
1948 unsigned char save_control, save_freq_select;
1949
1950 pin = find_isa_irq_pin(8, mp_INT);
1951 apic = find_isa_irq_apic(8, mp_INT);
1952 if (pin == -1)
1953 return;
1954
1955 entry0 = ioapic_read_entry(apic, pin);
1956
1957 clear_IO_APIC_pin(apic, pin);
1958
1959 memset(&entry1, 0, sizeof(entry1));
1960
1961 entry1.dest_mode = 0; /* physical delivery */
1962 entry1.mask = 0; /* unmask IRQ now */
1963 entry1.dest = hard_smp_processor_id();
1964 entry1.delivery_mode = dest_ExtINT;
1965 entry1.polarity = entry0.polarity;
1966 entry1.trigger = 0;
1967 entry1.vector = 0;
1968
1969 ioapic_write_entry(apic, pin, entry1);
1970
1971 save_control = CMOS_READ(RTC_CONTROL);
1972 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1973 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1974 RTC_FREQ_SELECT);
1975 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1976
1977 i = 100;
1978 while (i-- > 0) {
1979 mdelay(10);
1980 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1981 i -= 10;
1982 }
1983
1984 CMOS_WRITE(save_control, RTC_CONTROL);
1985 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1986 clear_IO_APIC_pin(apic, pin);
1987
1988 ioapic_write_entry(apic, pin, entry0);
1989 }
1990
1991 /*
1992 * This code may look a bit paranoid, but it's supposed to cooperate with
1993 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1994 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1995 * fanatically on his truly buggy board.
1996 *
1997 * FIXME: really need to revamp this for modern platforms only.
1998 */
1999 static inline void __init check_timer(void)
2000 {
2001 struct irq_cfg *cfg = irq_cfg + 0;
2002 int apic1, pin1, apic2, pin2;
2003 unsigned long flags;
2004 int no_pin1 = 0;
2005
2006 local_irq_save(flags);
2007
2008 /*
2009 * get/set the timer IRQ vector:
2010 */
2011 disable_8259A_irq(0);
2012 assign_irq_vector(0, TARGET_CPUS);
2013
2014 /*
2015 * As IRQ0 is to be enabled in the 8259A, the virtual
2016 * wire has to be disabled in the local APIC.
2017 */
2018 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2019 init_8259A(1);
2020
2021 pin1 = find_isa_irq_pin(0, mp_INT);
2022 apic1 = find_isa_irq_apic(0, mp_INT);
2023 pin2 = ioapic_i8259.pin;
2024 apic2 = ioapic_i8259.apic;
2025
2026 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2027 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2028 cfg->vector, apic1, pin1, apic2, pin2);
2029
2030 /*
2031 * Some BIOS writers are clueless and report the ExtINTA
2032 * I/O APIC input from the cascaded 8259A as the timer
2033 * interrupt input. So just in case, if only one pin
2034 * was found above, try it both directly and through the
2035 * 8259A.
2036 */
2037 if (pin1 == -1) {
2038 if (intr_remapping_enabled)
2039 panic("BIOS bug: timer not connected to IO-APIC");
2040 pin1 = pin2;
2041 apic1 = apic2;
2042 no_pin1 = 1;
2043 } else if (pin2 == -1) {
2044 pin2 = pin1;
2045 apic2 = apic1;
2046 }
2047
2048 if (pin1 != -1) {
2049 /*
2050 * Ok, does IRQ0 through the IOAPIC work?
2051 */
2052 if (no_pin1) {
2053 add_pin_to_irq(0, apic1, pin1);
2054 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2055 }
2056 unmask_IO_APIC_irq(0);
2057 if (!no_timer_check && timer_irq_works()) {
2058 if (nmi_watchdog == NMI_IO_APIC) {
2059 setup_nmi();
2060 enable_8259A_irq(0);
2061 }
2062 if (disable_timer_pin_1 > 0)
2063 clear_IO_APIC_pin(0, pin1);
2064 goto out;
2065 }
2066 if (intr_remapping_enabled)
2067 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2068 clear_IO_APIC_pin(apic1, pin1);
2069 if (!no_pin1)
2070 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2071 "8254 timer not connected to IO-APIC\n");
2072
2073 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2074 "(IRQ0) through the 8259A ...\n");
2075 apic_printk(APIC_QUIET, KERN_INFO
2076 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2077 /*
2078 * legacy devices should be connected to IO APIC #0
2079 */
2080 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2081 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2082 unmask_IO_APIC_irq(0);
2083 enable_8259A_irq(0);
2084 if (timer_irq_works()) {
2085 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2086 timer_through_8259 = 1;
2087 if (nmi_watchdog == NMI_IO_APIC) {
2088 disable_8259A_irq(0);
2089 setup_nmi();
2090 enable_8259A_irq(0);
2091 }
2092 goto out;
2093 }
2094 /*
2095 * Cleanup, just in case ...
2096 */
2097 disable_8259A_irq(0);
2098 clear_IO_APIC_pin(apic2, pin2);
2099 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2100 }
2101
2102 if (nmi_watchdog == NMI_IO_APIC) {
2103 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2104 "through the IO-APIC - disabling NMI Watchdog!\n");
2105 nmi_watchdog = NMI_NONE;
2106 }
2107
2108 apic_printk(APIC_QUIET, KERN_INFO
2109 "...trying to set up timer as Virtual Wire IRQ...\n");
2110
2111 lapic_register_intr(0);
2112 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2113 enable_8259A_irq(0);
2114
2115 if (timer_irq_works()) {
2116 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2117 goto out;
2118 }
2119 disable_8259A_irq(0);
2120 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2121 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2122
2123 apic_printk(APIC_QUIET, KERN_INFO
2124 "...trying to set up timer as ExtINT IRQ...\n");
2125
2126 init_8259A(0);
2127 make_8259A_irq(0);
2128 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2129
2130 unlock_ExtINT_logic();
2131
2132 if (timer_irq_works()) {
2133 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2134 goto out;
2135 }
2136 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2137 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2138 "report. Then try booting with the 'noapic' option.\n");
2139 out:
2140 local_irq_restore(flags);
2141 }
2142
2143 static int __init notimercheck(char *s)
2144 {
2145 no_timer_check = 1;
2146 return 1;
2147 }
2148 __setup("no_timer_check", notimercheck);
2149
2150 /*
2151 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2152 * to devices. However there may be an I/O APIC pin available for
2153 * this interrupt regardless. The pin may be left unconnected, but
2154 * typically it will be reused as an ExtINT cascade interrupt for
2155 * the master 8259A. In the MPS case such a pin will normally be
2156 * reported as an ExtINT interrupt in the MP table. With ACPI
2157 * there is no provision for ExtINT interrupts, and in the absence
2158 * of an override it would be treated as an ordinary ISA I/O APIC
2159 * interrupt, that is edge-triggered and unmasked by default. We
2160 * used to do this, but it caused problems on some systems because
2161 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2162 * the same ExtINT cascade interrupt to drive the local APIC of the
2163 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2164 * the I/O APIC in all cases now. No actual device should request
2165 * it anyway. --macro
2166 */
2167 #define PIC_IRQS (1<<2)
2168
2169 void __init setup_IO_APIC(void)
2170 {
2171
2172 /*
2173 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2174 */
2175
2176 io_apic_irqs = ~PIC_IRQS;
2177
2178 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2179
2180 sync_Arb_IDs();
2181 setup_IO_APIC_irqs();
2182 init_IO_APIC_traps();
2183 check_timer();
2184 }
2185
2186 struct sysfs_ioapic_data {
2187 struct sys_device dev;
2188 struct IO_APIC_route_entry entry[0];
2189 };
2190 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2191
2192 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2193 {
2194 struct IO_APIC_route_entry *entry;
2195 struct sysfs_ioapic_data *data;
2196 int i;
2197
2198 data = container_of(dev, struct sysfs_ioapic_data, dev);
2199 entry = data->entry;
2200 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2201 *entry = ioapic_read_entry(dev->id, i);
2202
2203 return 0;
2204 }
2205
2206 static int ioapic_resume(struct sys_device *dev)
2207 {
2208 struct IO_APIC_route_entry *entry;
2209 struct sysfs_ioapic_data *data;
2210 unsigned long flags;
2211 union IO_APIC_reg_00 reg_00;
2212 int i;
2213
2214 data = container_of(dev, struct sysfs_ioapic_data, dev);
2215 entry = data->entry;
2216
2217 spin_lock_irqsave(&ioapic_lock, flags);
2218 reg_00.raw = io_apic_read(dev->id, 0);
2219 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2220 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2221 io_apic_write(dev->id, 0, reg_00.raw);
2222 }
2223 spin_unlock_irqrestore(&ioapic_lock, flags);
2224 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2225 ioapic_write_entry(dev->id, i, entry[i]);
2226
2227 return 0;
2228 }
2229
2230 static struct sysdev_class ioapic_sysdev_class = {
2231 .name = "ioapic",
2232 .suspend = ioapic_suspend,
2233 .resume = ioapic_resume,
2234 };
2235
2236 static int __init ioapic_init_sysfs(void)
2237 {
2238 struct sys_device * dev;
2239 int i, size, error;
2240
2241 error = sysdev_class_register(&ioapic_sysdev_class);
2242 if (error)
2243 return error;
2244
2245 for (i = 0; i < nr_ioapics; i++ ) {
2246 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2247 * sizeof(struct IO_APIC_route_entry);
2248 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2249 if (!mp_ioapic_data[i]) {
2250 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2251 continue;
2252 }
2253 dev = &mp_ioapic_data[i]->dev;
2254 dev->id = i;
2255 dev->cls = &ioapic_sysdev_class;
2256 error = sysdev_register(dev);
2257 if (error) {
2258 kfree(mp_ioapic_data[i]);
2259 mp_ioapic_data[i] = NULL;
2260 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2261 continue;
2262 }
2263 }
2264
2265 return 0;
2266 }
2267
2268 device_initcall(ioapic_init_sysfs);
2269
2270 /*
2271 * Dynamic irq allocate and deallocation
2272 */
2273 int create_irq(void)
2274 {
2275 /* Allocate an unused irq */
2276 int irq;
2277 int new;
2278 unsigned long flags;
2279
2280 irq = -ENOSPC;
2281 spin_lock_irqsave(&vector_lock, flags);
2282 for (new = (NR_IRQS - 1); new >= 0; new--) {
2283 if (platform_legacy_irq(new))
2284 continue;
2285 if (irq_cfg[new].vector != 0)
2286 continue;
2287 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
2288 irq = new;
2289 break;
2290 }
2291 spin_unlock_irqrestore(&vector_lock, flags);
2292
2293 if (irq >= 0) {
2294 dynamic_irq_init(irq);
2295 }
2296 return irq;
2297 }
2298
2299 void destroy_irq(unsigned int irq)
2300 {
2301 unsigned long flags;
2302
2303 dynamic_irq_cleanup(irq);
2304
2305 #ifdef CONFIG_INTR_REMAP
2306 free_irte(irq);
2307 #endif
2308 spin_lock_irqsave(&vector_lock, flags);
2309 __clear_irq_vector(irq);
2310 spin_unlock_irqrestore(&vector_lock, flags);
2311 }
2312
2313 /*
2314 * MSI message composition
2315 */
2316 #ifdef CONFIG_PCI_MSI
2317 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2318 {
2319 struct irq_cfg *cfg = irq_cfg + irq;
2320 int err;
2321 unsigned dest;
2322 cpumask_t tmp;
2323
2324 tmp = TARGET_CPUS;
2325 err = assign_irq_vector(irq, tmp);
2326 if (err)
2327 return err;
2328
2329 cpus_and(tmp, cfg->domain, tmp);
2330 dest = cpu_mask_to_apicid(tmp);
2331
2332 #ifdef CONFIG_INTR_REMAP
2333 if (irq_remapped(irq)) {
2334 struct irte irte;
2335 int ir_index;
2336 u16 sub_handle;
2337
2338 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
2339 BUG_ON(ir_index == -1);
2340
2341 memset (&irte, 0, sizeof(irte));
2342
2343 irte.present = 1;
2344 irte.dst_mode = INT_DEST_MODE;
2345 irte.trigger_mode = 0; /* edge */
2346 irte.dlvry_mode = INT_DELIVERY_MODE;
2347 irte.vector = cfg->vector;
2348 irte.dest_id = IRTE_DEST(dest);
2349
2350 modify_irte(irq, &irte);
2351
2352 msg->address_hi = MSI_ADDR_BASE_HI;
2353 msg->data = sub_handle;
2354 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
2355 MSI_ADDR_IR_SHV |
2356 MSI_ADDR_IR_INDEX1(ir_index) |
2357 MSI_ADDR_IR_INDEX2(ir_index);
2358 } else
2359 #endif
2360 {
2361 msg->address_hi = MSI_ADDR_BASE_HI;
2362 msg->address_lo =
2363 MSI_ADDR_BASE_LO |
2364 ((INT_DEST_MODE == 0) ?
2365 MSI_ADDR_DEST_MODE_PHYSICAL:
2366 MSI_ADDR_DEST_MODE_LOGICAL) |
2367 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2368 MSI_ADDR_REDIRECTION_CPU:
2369 MSI_ADDR_REDIRECTION_LOWPRI) |
2370 MSI_ADDR_DEST_ID(dest);
2371
2372 msg->data =
2373 MSI_DATA_TRIGGER_EDGE |
2374 MSI_DATA_LEVEL_ASSERT |
2375 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2376 MSI_DATA_DELIVERY_FIXED:
2377 MSI_DATA_DELIVERY_LOWPRI) |
2378 MSI_DATA_VECTOR(cfg->vector);
2379 }
2380 return err;
2381 }
2382
2383 #ifdef CONFIG_SMP
2384 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2385 {
2386 struct irq_cfg *cfg = irq_cfg + irq;
2387 struct msi_msg msg;
2388 unsigned int dest;
2389 cpumask_t tmp;
2390
2391 cpus_and(tmp, mask, cpu_online_map);
2392 if (cpus_empty(tmp))
2393 return;
2394
2395 if (assign_irq_vector(irq, mask))
2396 return;
2397
2398 cpus_and(tmp, cfg->domain, mask);
2399 dest = cpu_mask_to_apicid(tmp);
2400
2401 read_msi_msg(irq, &msg);
2402
2403 msg.data &= ~MSI_DATA_VECTOR_MASK;
2404 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2405 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2406 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2407
2408 write_msi_msg(irq, &msg);
2409 irq_desc[irq].affinity = mask;
2410 }
2411
2412 #ifdef CONFIG_INTR_REMAP
2413 /*
2414 * Migrate the MSI irq to another cpumask. This migration is
2415 * done in the process context using interrupt-remapping hardware.
2416 */
2417 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2418 {
2419 struct irq_cfg *cfg = irq_cfg + irq;
2420 unsigned int dest;
2421 cpumask_t tmp, cleanup_mask;
2422 struct irte irte;
2423
2424 cpus_and(tmp, mask, cpu_online_map);
2425 if (cpus_empty(tmp))
2426 return;
2427
2428 if (get_irte(irq, &irte))
2429 return;
2430
2431 if (assign_irq_vector(irq, mask))
2432 return;
2433
2434 cpus_and(tmp, cfg->domain, mask);
2435 dest = cpu_mask_to_apicid(tmp);
2436
2437 irte.vector = cfg->vector;
2438 irte.dest_id = IRTE_DEST(dest);
2439
2440 /*
2441 * atomically update the IRTE with the new destination and vector.
2442 */
2443 modify_irte(irq, &irte);
2444
2445 /*
2446 * After this point, all the interrupts will start arriving
2447 * at the new destination. So, time to cleanup the previous
2448 * vector allocation.
2449 */
2450 if (cfg->move_in_progress) {
2451 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2452 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2453 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2454 cfg->move_in_progress = 0;
2455 }
2456
2457 irq_desc[irq].affinity = mask;
2458 }
2459 #endif
2460 #endif /* CONFIG_SMP */
2461
2462 /*
2463 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2464 * which implement the MSI or MSI-X Capability Structure.
2465 */
2466 static struct irq_chip msi_chip = {
2467 .name = "PCI-MSI",
2468 .unmask = unmask_msi_irq,
2469 .mask = mask_msi_irq,
2470 .ack = ack_apic_edge,
2471 #ifdef CONFIG_SMP
2472 .set_affinity = set_msi_irq_affinity,
2473 #endif
2474 .retrigger = ioapic_retrigger_irq,
2475 };
2476
2477 #ifdef CONFIG_INTR_REMAP
2478 static struct irq_chip msi_ir_chip = {
2479 .name = "IR-PCI-MSI",
2480 .unmask = unmask_msi_irq,
2481 .mask = mask_msi_irq,
2482 .ack = ack_x2apic_edge,
2483 #ifdef CONFIG_SMP
2484 .set_affinity = ir_set_msi_irq_affinity,
2485 #endif
2486 .retrigger = ioapic_retrigger_irq,
2487 };
2488
2489 /*
2490 * Map the PCI dev to the corresponding remapping hardware unit
2491 * and allocate 'nvec' consecutive interrupt-remapping table entries
2492 * in it.
2493 */
2494 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
2495 {
2496 struct intel_iommu *iommu;
2497 int index;
2498
2499 iommu = map_dev_to_ir(dev);
2500 if (!iommu) {
2501 printk(KERN_ERR
2502 "Unable to map PCI %s to iommu\n", pci_name(dev));
2503 return -ENOENT;
2504 }
2505
2506 index = alloc_irte(iommu, irq, nvec);
2507 if (index < 0) {
2508 printk(KERN_ERR
2509 "Unable to allocate %d IRTE for PCI %s\n", nvec,
2510 pci_name(dev));
2511 return -ENOSPC;
2512 }
2513 return index;
2514 }
2515 #endif
2516
2517 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
2518 {
2519 int ret;
2520 struct msi_msg msg;
2521
2522 ret = msi_compose_msg(dev, irq, &msg);
2523 if (ret < 0)
2524 return ret;
2525
2526 set_irq_msi(irq, desc);
2527 write_msi_msg(irq, &msg);
2528
2529 #ifdef CONFIG_INTR_REMAP
2530 if (irq_remapped(irq)) {
2531 struct irq_desc *desc = irq_desc + irq;
2532 /*
2533 * irq migration in process context
2534 */
2535 desc->status |= IRQ_MOVE_PCNTXT;
2536 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
2537 } else
2538 #endif
2539 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2540
2541 return 0;
2542 }
2543
2544 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2545 {
2546 int irq, ret;
2547
2548 irq = create_irq();
2549 if (irq < 0)
2550 return irq;
2551
2552 #ifdef CONFIG_INTR_REMAP
2553 if (!intr_remapping_enabled)
2554 goto no_ir;
2555
2556 ret = msi_alloc_irte(dev, irq, 1);
2557 if (ret < 0)
2558 goto error;
2559 no_ir:
2560 #endif
2561 ret = setup_msi_irq(dev, desc, irq);
2562 if (ret < 0) {
2563 destroy_irq(irq);
2564 return ret;
2565 }
2566 return 0;
2567
2568 #ifdef CONFIG_INTR_REMAP
2569 error:
2570 destroy_irq(irq);
2571 return ret;
2572 #endif
2573 }
2574
2575 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
2576 {
2577 int irq, ret, sub_handle;
2578 struct msi_desc *desc;
2579 #ifdef CONFIG_INTR_REMAP
2580 struct intel_iommu *iommu = 0;
2581 int index = 0;
2582 #endif
2583
2584 sub_handle = 0;
2585 list_for_each_entry(desc, &dev->msi_list, list) {
2586 irq = create_irq();
2587 if (irq < 0)
2588 return irq;
2589 #ifdef CONFIG_INTR_REMAP
2590 if (!intr_remapping_enabled)
2591 goto no_ir;
2592
2593 if (!sub_handle) {
2594 /*
2595 * allocate the consecutive block of IRTE's
2596 * for 'nvec'
2597 */
2598 index = msi_alloc_irte(dev, irq, nvec);
2599 if (index < 0) {
2600 ret = index;
2601 goto error;
2602 }
2603 } else {
2604 iommu = map_dev_to_ir(dev);
2605 if (!iommu) {
2606 ret = -ENOENT;
2607 goto error;
2608 }
2609 /*
2610 * setup the mapping between the irq and the IRTE
2611 * base index, the sub_handle pointing to the
2612 * appropriate interrupt remap table entry.
2613 */
2614 set_irte_irq(irq, iommu, index, sub_handle);
2615 }
2616 no_ir:
2617 #endif
2618 ret = setup_msi_irq(dev, desc, irq);
2619 if (ret < 0)
2620 goto error;
2621 sub_handle++;
2622 }
2623 return 0;
2624
2625 error:
2626 destroy_irq(irq);
2627 return ret;
2628 }
2629
2630 void arch_teardown_msi_irq(unsigned int irq)
2631 {
2632 destroy_irq(irq);
2633 }
2634
2635 #ifdef CONFIG_DMAR
2636 #ifdef CONFIG_SMP
2637 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2638 {
2639 struct irq_cfg *cfg = irq_cfg + irq;
2640 struct msi_msg msg;
2641 unsigned int dest;
2642 cpumask_t tmp;
2643
2644 cpus_and(tmp, mask, cpu_online_map);
2645 if (cpus_empty(tmp))
2646 return;
2647
2648 if (assign_irq_vector(irq, mask))
2649 return;
2650
2651 cpus_and(tmp, cfg->domain, mask);
2652 dest = cpu_mask_to_apicid(tmp);
2653
2654 dmar_msi_read(irq, &msg);
2655
2656 msg.data &= ~MSI_DATA_VECTOR_MASK;
2657 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2658 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2659 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2660
2661 dmar_msi_write(irq, &msg);
2662 irq_desc[irq].affinity = mask;
2663 }
2664 #endif /* CONFIG_SMP */
2665
2666 struct irq_chip dmar_msi_type = {
2667 .name = "DMAR_MSI",
2668 .unmask = dmar_msi_unmask,
2669 .mask = dmar_msi_mask,
2670 .ack = ack_apic_edge,
2671 #ifdef CONFIG_SMP
2672 .set_affinity = dmar_msi_set_affinity,
2673 #endif
2674 .retrigger = ioapic_retrigger_irq,
2675 };
2676
2677 int arch_setup_dmar_msi(unsigned int irq)
2678 {
2679 int ret;
2680 struct msi_msg msg;
2681
2682 ret = msi_compose_msg(NULL, irq, &msg);
2683 if (ret < 0)
2684 return ret;
2685 dmar_msi_write(irq, &msg);
2686 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2687 "edge");
2688 return 0;
2689 }
2690 #endif
2691
2692 #endif /* CONFIG_PCI_MSI */
2693 /*
2694 * Hypertransport interrupt support
2695 */
2696 #ifdef CONFIG_HT_IRQ
2697
2698 #ifdef CONFIG_SMP
2699
2700 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2701 {
2702 struct ht_irq_msg msg;
2703 fetch_ht_irq_msg(irq, &msg);
2704
2705 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2706 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2707
2708 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2709 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2710
2711 write_ht_irq_msg(irq, &msg);
2712 }
2713
2714 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2715 {
2716 struct irq_cfg *cfg = irq_cfg + irq;
2717 unsigned int dest;
2718 cpumask_t tmp;
2719
2720 cpus_and(tmp, mask, cpu_online_map);
2721 if (cpus_empty(tmp))
2722 return;
2723
2724 if (assign_irq_vector(irq, mask))
2725 return;
2726
2727 cpus_and(tmp, cfg->domain, mask);
2728 dest = cpu_mask_to_apicid(tmp);
2729
2730 target_ht_irq(irq, dest, cfg->vector);
2731 irq_desc[irq].affinity = mask;
2732 }
2733 #endif
2734
2735 static struct irq_chip ht_irq_chip = {
2736 .name = "PCI-HT",
2737 .mask = mask_ht_irq,
2738 .unmask = unmask_ht_irq,
2739 .ack = ack_apic_edge,
2740 #ifdef CONFIG_SMP
2741 .set_affinity = set_ht_irq_affinity,
2742 #endif
2743 .retrigger = ioapic_retrigger_irq,
2744 };
2745
2746 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2747 {
2748 struct irq_cfg *cfg = irq_cfg + irq;
2749 int err;
2750 cpumask_t tmp;
2751
2752 tmp = TARGET_CPUS;
2753 err = assign_irq_vector(irq, tmp);
2754 if (!err) {
2755 struct ht_irq_msg msg;
2756 unsigned dest;
2757
2758 cpus_and(tmp, cfg->domain, tmp);
2759 dest = cpu_mask_to_apicid(tmp);
2760
2761 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2762
2763 msg.address_lo =
2764 HT_IRQ_LOW_BASE |
2765 HT_IRQ_LOW_DEST_ID(dest) |
2766 HT_IRQ_LOW_VECTOR(cfg->vector) |
2767 ((INT_DEST_MODE == 0) ?
2768 HT_IRQ_LOW_DM_PHYSICAL :
2769 HT_IRQ_LOW_DM_LOGICAL) |
2770 HT_IRQ_LOW_RQEOI_EDGE |
2771 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2772 HT_IRQ_LOW_MT_FIXED :
2773 HT_IRQ_LOW_MT_ARBITRATED) |
2774 HT_IRQ_LOW_IRQ_MASKED;
2775
2776 write_ht_irq_msg(irq, &msg);
2777
2778 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2779 handle_edge_irq, "edge");
2780 }
2781 return err;
2782 }
2783 #endif /* CONFIG_HT_IRQ */
2784
2785 /* --------------------------------------------------------------------------
2786 ACPI-based IOAPIC Configuration
2787 -------------------------------------------------------------------------- */
2788
2789 #ifdef CONFIG_ACPI
2790
2791 #define IO_APIC_MAX_ID 0xFE
2792
2793 int __init io_apic_get_redir_entries (int ioapic)
2794 {
2795 union IO_APIC_reg_01 reg_01;
2796 unsigned long flags;
2797
2798 spin_lock_irqsave(&ioapic_lock, flags);
2799 reg_01.raw = io_apic_read(ioapic, 1);
2800 spin_unlock_irqrestore(&ioapic_lock, flags);
2801
2802 return reg_01.bits.entries;
2803 }
2804
2805
2806 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2807 {
2808 if (!IO_APIC_IRQ(irq)) {
2809 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2810 ioapic);
2811 return -EINVAL;
2812 }
2813
2814 /*
2815 * IRQs < 16 are already in the irq_2_pin[] map
2816 */
2817 if (irq >= 16)
2818 add_pin_to_irq(irq, ioapic, pin);
2819
2820 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2821
2822 return 0;
2823 }
2824
2825
2826 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2827 {
2828 int i;
2829
2830 if (skip_ioapic_setup)
2831 return -1;
2832
2833 for (i = 0; i < mp_irq_entries; i++)
2834 if (mp_irqs[i].mp_irqtype == mp_INT &&
2835 mp_irqs[i].mp_srcbusirq == bus_irq)
2836 break;
2837 if (i >= mp_irq_entries)
2838 return -1;
2839
2840 *trigger = irq_trigger(i);
2841 *polarity = irq_polarity(i);
2842 return 0;
2843 }
2844
2845 #endif /* CONFIG_ACPI */
2846
2847 /*
2848 * This function currently is only a helper for the i386 smp boot process where
2849 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2850 * so mask in all cases should simply be TARGET_CPUS
2851 */
2852 #ifdef CONFIG_SMP
2853 void __init setup_ioapic_dest(void)
2854 {
2855 int pin, ioapic, irq, irq_entry;
2856
2857 if (skip_ioapic_setup == 1)
2858 return;
2859
2860 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2861 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2862 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2863 if (irq_entry == -1)
2864 continue;
2865 irq = pin_2_irq(irq_entry, ioapic, pin);
2866
2867 /* setup_IO_APIC_irqs could fail to get vector for some device
2868 * when you have too many devices, because at that time only boot
2869 * cpu is online.
2870 */
2871 if (!irq_cfg[irq].vector)
2872 setup_IO_APIC_irq(ioapic, pin, irq,
2873 irq_trigger(irq_entry),
2874 irq_polarity(irq_entry));
2875 #ifdef CONFIG_INTR_REMAP
2876 else if (intr_remapping_enabled)
2877 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
2878 #endif
2879 else
2880 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2881 }
2882
2883 }
2884 }
2885 #endif
2886
2887 #define IOAPIC_RESOURCE_NAME_SIZE 11
2888
2889 static struct resource *ioapic_resources;
2890
2891 static struct resource * __init ioapic_setup_resources(void)
2892 {
2893 unsigned long n;
2894 struct resource *res;
2895 char *mem;
2896 int i;
2897
2898 if (nr_ioapics <= 0)
2899 return NULL;
2900
2901 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2902 n *= nr_ioapics;
2903
2904 mem = alloc_bootmem(n);
2905 res = (void *)mem;
2906
2907 if (mem != NULL) {
2908 mem += sizeof(struct resource) * nr_ioapics;
2909
2910 for (i = 0; i < nr_ioapics; i++) {
2911 res[i].name = mem;
2912 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2913 sprintf(mem, "IOAPIC %u", i);
2914 mem += IOAPIC_RESOURCE_NAME_SIZE;
2915 }
2916 }
2917
2918 ioapic_resources = res;
2919
2920 return res;
2921 }
2922
2923 void __init ioapic_init_mappings(void)
2924 {
2925 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2926 struct resource *ioapic_res;
2927 int i;
2928
2929 ioapic_res = ioapic_setup_resources();
2930 for (i = 0; i < nr_ioapics; i++) {
2931 if (smp_found_config) {
2932 ioapic_phys = mp_ioapics[i].mp_apicaddr;
2933 } else {
2934 ioapic_phys = (unsigned long)
2935 alloc_bootmem_pages(PAGE_SIZE);
2936 ioapic_phys = __pa(ioapic_phys);
2937 }
2938 set_fixmap_nocache(idx, ioapic_phys);
2939 apic_printk(APIC_VERBOSE,
2940 "mapped IOAPIC to %016lx (%016lx)\n",
2941 __fix_to_virt(idx), ioapic_phys);
2942 idx++;
2943
2944 if (ioapic_res != NULL) {
2945 ioapic_res->start = ioapic_phys;
2946 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2947 ioapic_res++;
2948 }
2949 }
2950 }
2951
2952 static int __init ioapic_insert_resources(void)
2953 {
2954 int i;
2955 struct resource *r = ioapic_resources;
2956
2957 if (!r) {
2958 printk(KERN_ERR
2959 "IO APIC resources could be not be allocated.\n");
2960 return -1;
2961 }
2962
2963 for (i = 0; i < nr_ioapics; i++) {
2964 insert_resource(&iomem_resource, r);
2965 r++;
2966 }
2967
2968 return 0;
2969 }
2970
2971 /* Insert the IO APIC resources after PCI initialization has occured to handle
2972 * IO APICS that are mapped in on a BAR in PCI space. */
2973 late_initcall(ioapic_insert_resources);
2974
Linux kernel - Deliverables
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