2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
40 #include <linux/dmar.h>
46 #include <asm/proto.h>
49 #include <asm/i8259.h>
51 #include <asm/msidef.h>
52 #include <asm/hypertransport.h>
53 #include <asm/irq_remapping.h>
56 #include <mach_apic.h>
61 unsigned move_cleanup_count
;
63 u8 move_in_progress
: 1;
66 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
67 static struct irq_cfg irq_cfg
[NR_IRQS
] __read_mostly
= {
68 [0] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
69 [1] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
70 [2] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
71 [3] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
72 [4] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
73 [5] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
74 [6] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
75 [7] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
76 [8] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
77 [9] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
78 [10] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
79 [11] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
80 [12] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
81 [13] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
82 [14] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
83 [15] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
86 static int assign_irq_vector(int irq
, cpumask_t mask
);
88 int first_system_vector
= 0xfe;
90 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
92 #define __apicdebuginit __init
94 int sis_apic_bug
; /* not actually supported, dummy for compile */
96 static int no_timer_check
;
98 static int disable_timer_pin_1 __initdata
;
100 int timer_through_8259 __initdata
;
102 /* Where if anywhere is the i8259 connect in external int mode */
103 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
105 static DEFINE_SPINLOCK(ioapic_lock
);
106 static DEFINE_SPINLOCK(vector_lock
);
109 * # of IRQ routing registers
111 int nr_ioapic_registers
[MAX_IO_APICS
];
113 /* I/O APIC RTE contents at the OS boot up */
114 struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
116 /* I/O APIC entries */
117 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
120 /* MP IRQ source entries */
121 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
123 /* # of MP IRQ source entries */
126 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
129 * Rough estimation of how many shared IRQs there are, can
130 * be changed anytime.
132 #define MAX_PLUS_SHARED_IRQS NR_IRQS
133 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
136 * This is performance-critical, we want to do it O(1)
138 * the indexing order of this array favors 1:1 mappings
139 * between pins and IRQs.
142 static struct irq_pin_list
{
143 short apic
, pin
, next
;
144 } irq_2_pin
[PIN_MAP_SIZE
];
148 unsigned int unused
[3];
152 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
154 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
155 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
158 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
160 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
161 writel(reg
, &io_apic
->index
);
162 return readl(&io_apic
->data
);
165 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
167 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
168 writel(reg
, &io_apic
->index
);
169 writel(value
, &io_apic
->data
);
173 * Re-write a value: to be used for read-modify-write
174 * cycles where the read already set up the index register.
176 static inline void io_apic_modify(unsigned int apic
, unsigned int value
)
178 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
179 writel(value
, &io_apic
->data
);
182 static bool io_apic_level_ack_pending(unsigned int irq
)
184 struct irq_pin_list
*entry
;
187 spin_lock_irqsave(&ioapic_lock
, flags
);
188 entry
= irq_2_pin
+ irq
;
196 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
197 /* Is the remote IRR bit set? */
198 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
199 spin_unlock_irqrestore(&ioapic_lock
, flags
);
204 entry
= irq_2_pin
+ entry
->next
;
206 spin_unlock_irqrestore(&ioapic_lock
, flags
);
212 * Synchronize the IO-APIC and the CPU by doing
213 * a dummy read from the IO-APIC
215 static inline void io_apic_sync(unsigned int apic
)
217 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
218 readl(&io_apic
->data
);
221 #define __DO_ACTION(R, ACTION, FINAL) \
225 struct irq_pin_list *entry = irq_2_pin + irq; \
227 BUG_ON(irq >= NR_IRQS); \
233 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
235 io_apic_modify(entry->apic, reg); \
239 entry = irq_2_pin + entry->next; \
244 struct { u32 w1
, w2
; };
245 struct IO_APIC_route_entry entry
;
248 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
250 union entry_union eu
;
252 spin_lock_irqsave(&ioapic_lock
, flags
);
253 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
254 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
255 spin_unlock_irqrestore(&ioapic_lock
, flags
);
260 * When we write a new IO APIC routing entry, we need to write the high
261 * word first! If the mask bit in the low word is clear, we will enable
262 * the interrupt, and we need to make sure the entry is fully populated
263 * before that happens.
266 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
268 union entry_union eu
;
270 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
271 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
274 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
277 spin_lock_irqsave(&ioapic_lock
, flags
);
278 __ioapic_write_entry(apic
, pin
, e
);
279 spin_unlock_irqrestore(&ioapic_lock
, flags
);
283 * When we mask an IO APIC routing entry, we need to write the low
284 * word first, in order to set the mask bit before we change the
287 static void ioapic_mask_entry(int apic
, int pin
)
290 union entry_union eu
= { .entry
.mask
= 1 };
292 spin_lock_irqsave(&ioapic_lock
, flags
);
293 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
294 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
295 spin_unlock_irqrestore(&ioapic_lock
, flags
);
299 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
302 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
304 BUG_ON(irq
>= NR_IRQS
);
312 * With interrupt-remapping, destination information comes
313 * from interrupt-remapping table entry.
315 if (!irq_remapped(irq
))
316 io_apic_write(apic
, 0x11 + pin
*2, dest
);
317 reg
= io_apic_read(apic
, 0x10 + pin
*2);
318 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
320 io_apic_modify(apic
, reg
);
323 entry
= irq_2_pin
+ entry
->next
;
327 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
329 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
334 cpus_and(tmp
, mask
, cpu_online_map
);
338 if (assign_irq_vector(irq
, mask
))
341 cpus_and(tmp
, cfg
->domain
, mask
);
342 dest
= cpu_mask_to_apicid(tmp
);
345 * Only the high 8 bits are valid.
347 dest
= SET_APIC_LOGICAL_ID(dest
);
349 spin_lock_irqsave(&ioapic_lock
, flags
);
350 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
351 irq_desc
[irq
].affinity
= mask
;
352 spin_unlock_irqrestore(&ioapic_lock
, flags
);
357 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
358 * shared ISA-space IRQs, so we have to support them. We are super
359 * fast in the common case, and fast for shared ISA-space IRQs.
361 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
363 static int first_free_entry
= NR_IRQS
;
364 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
366 BUG_ON(irq
>= NR_IRQS
);
368 entry
= irq_2_pin
+ entry
->next
;
370 if (entry
->pin
!= -1) {
371 entry
->next
= first_free_entry
;
372 entry
= irq_2_pin
+ entry
->next
;
373 if (++first_free_entry
>= PIN_MAP_SIZE
)
374 panic("io_apic.c: ran out of irq_2_pin entries!");
381 * Reroute an IRQ to a different pin.
383 static void __init
replace_pin_at_irq(unsigned int irq
,
384 int oldapic
, int oldpin
,
385 int newapic
, int newpin
)
387 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
390 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
391 entry
->apic
= newapic
;
396 entry
= irq_2_pin
+ entry
->next
;
401 #define DO_ACTION(name,R,ACTION, FINAL) \
403 static void name##_IO_APIC_irq (unsigned int irq) \
404 __DO_ACTION(R, ACTION, FINAL)
407 DO_ACTION(__mask
, 0, |= IO_APIC_REDIR_MASKED
, io_apic_sync(entry
->apic
))
410 DO_ACTION(__unmask
, 0, &= ~IO_APIC_REDIR_MASKED
, )
412 static void mask_IO_APIC_irq (unsigned int irq
)
416 spin_lock_irqsave(&ioapic_lock
, flags
);
417 __mask_IO_APIC_irq(irq
);
418 spin_unlock_irqrestore(&ioapic_lock
, flags
);
421 static void unmask_IO_APIC_irq (unsigned int irq
)
425 spin_lock_irqsave(&ioapic_lock
, flags
);
426 __unmask_IO_APIC_irq(irq
);
427 spin_unlock_irqrestore(&ioapic_lock
, flags
);
430 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
432 struct IO_APIC_route_entry entry
;
434 /* Check delivery_mode to be sure we're not clearing an SMI pin */
435 entry
= ioapic_read_entry(apic
, pin
);
436 if (entry
.delivery_mode
== dest_SMI
)
439 * Disable it in the IO-APIC irq-routing table:
441 ioapic_mask_entry(apic
, pin
);
444 static void clear_IO_APIC (void)
448 for (apic
= 0; apic
< nr_ioapics
; apic
++)
449 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
450 clear_IO_APIC_pin(apic
, pin
);
454 * Saves and masks all the unmasked IO-APIC RTE's
456 int save_mask_IO_APIC_setup(void)
458 union IO_APIC_reg_01 reg_01
;
463 * The number of IO-APIC IRQ registers (== #pins):
465 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
466 spin_lock_irqsave(&ioapic_lock
, flags
);
467 reg_01
.raw
= io_apic_read(apic
, 1);
468 spin_unlock_irqrestore(&ioapic_lock
, flags
);
469 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
472 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
473 early_ioapic_entries
[apic
] =
474 kzalloc(sizeof(struct IO_APIC_route_entry
) *
475 nr_ioapic_registers
[apic
], GFP_KERNEL
);
476 if (!early_ioapic_entries
[apic
])
480 for (apic
= 0; apic
< nr_ioapics
; apic
++)
481 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
482 struct IO_APIC_route_entry entry
;
484 entry
= early_ioapic_entries
[apic
][pin
] =
485 ioapic_read_entry(apic
, pin
);
488 ioapic_write_entry(apic
, pin
, entry
);
494 void restore_IO_APIC_setup(void)
498 for (apic
= 0; apic
< nr_ioapics
; apic
++)
499 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
500 ioapic_write_entry(apic
, pin
,
501 early_ioapic_entries
[apic
][pin
]);
504 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
507 * for now plain restore of previous settings.
508 * TBD: In the case of OS enabling interrupt-remapping,
509 * IO-APIC RTE's need to be setup to point to interrupt-remapping
510 * table entries. for now, do a plain restore, and wait for
511 * the setup_IO_APIC_irqs() to do proper initialization.
513 restore_IO_APIC_setup();
516 int skip_ioapic_setup
;
519 static int __init
parse_noapic(char *str
)
521 disable_ioapic_setup();
524 early_param("noapic", parse_noapic
);
526 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
527 static int __init
disable_timer_pin_setup(char *arg
)
529 disable_timer_pin_1
= 1;
532 __setup("disable_timer_pin_1", disable_timer_pin_setup
);
536 * Find the IRQ entry number of a certain pin.
538 static int find_irq_entry(int apic
, int pin
, int type
)
542 for (i
= 0; i
< mp_irq_entries
; i
++)
543 if (mp_irqs
[i
].mp_irqtype
== type
&&
544 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
545 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
546 mp_irqs
[i
].mp_dstirq
== pin
)
553 * Find the pin to which IRQ[irq] (ISA) is connected
555 static int __init
find_isa_irq_pin(int irq
, int type
)
559 for (i
= 0; i
< mp_irq_entries
; i
++) {
560 int lbus
= mp_irqs
[i
].mp_srcbus
;
562 if (test_bit(lbus
, mp_bus_not_pci
) &&
563 (mp_irqs
[i
].mp_irqtype
== type
) &&
564 (mp_irqs
[i
].mp_srcbusirq
== irq
))
566 return mp_irqs
[i
].mp_dstirq
;
571 static int __init
find_isa_irq_apic(int irq
, int type
)
575 for (i
= 0; i
< mp_irq_entries
; i
++) {
576 int lbus
= mp_irqs
[i
].mp_srcbus
;
578 if (test_bit(lbus
, mp_bus_not_pci
) &&
579 (mp_irqs
[i
].mp_irqtype
== type
) &&
580 (mp_irqs
[i
].mp_srcbusirq
== irq
))
583 if (i
< mp_irq_entries
) {
585 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
586 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
595 * Find a specific PCI IRQ entry.
596 * Not an __init, possibly needed by modules
598 static int pin_2_irq(int idx
, int apic
, int pin
);
600 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
602 int apic
, i
, best_guess
= -1;
604 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
606 if (test_bit(bus
, mp_bus_not_pci
)) {
607 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
610 for (i
= 0; i
< mp_irq_entries
; i
++) {
611 int lbus
= mp_irqs
[i
].mp_srcbus
;
613 for (apic
= 0; apic
< nr_ioapics
; apic
++)
614 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
615 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
618 if (!test_bit(lbus
, mp_bus_not_pci
) &&
619 !mp_irqs
[i
].mp_irqtype
&&
621 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
622 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
624 if (!(apic
|| IO_APIC_IRQ(irq
)))
627 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
630 * Use the first all-but-pin matching entry as a
631 * best-guess fuzzy result for broken mptables.
637 BUG_ON(best_guess
>= NR_IRQS
);
641 /* ISA interrupts are always polarity zero edge triggered,
642 * when listed as conforming in the MP table. */
644 #define default_ISA_trigger(idx) (0)
645 #define default_ISA_polarity(idx) (0)
647 /* PCI interrupts are always polarity one level triggered,
648 * when listed as conforming in the MP table. */
650 #define default_PCI_trigger(idx) (1)
651 #define default_PCI_polarity(idx) (1)
653 static int MPBIOS_polarity(int idx
)
655 int bus
= mp_irqs
[idx
].mp_srcbus
;
659 * Determine IRQ line polarity (high active or low active):
661 switch (mp_irqs
[idx
].mp_irqflag
& 3)
663 case 0: /* conforms, ie. bus-type dependent polarity */
664 if (test_bit(bus
, mp_bus_not_pci
))
665 polarity
= default_ISA_polarity(idx
);
667 polarity
= default_PCI_polarity(idx
);
669 case 1: /* high active */
674 case 2: /* reserved */
676 printk(KERN_WARNING
"broken BIOS!!\n");
680 case 3: /* low active */
685 default: /* invalid */
687 printk(KERN_WARNING
"broken BIOS!!\n");
695 static int MPBIOS_trigger(int idx
)
697 int bus
= mp_irqs
[idx
].mp_srcbus
;
701 * Determine IRQ trigger mode (edge or level sensitive):
703 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
705 case 0: /* conforms, ie. bus-type dependent */
706 if (test_bit(bus
, mp_bus_not_pci
))
707 trigger
= default_ISA_trigger(idx
);
709 trigger
= default_PCI_trigger(idx
);
716 case 2: /* reserved */
718 printk(KERN_WARNING
"broken BIOS!!\n");
727 default: /* invalid */
729 printk(KERN_WARNING
"broken BIOS!!\n");
737 static inline int irq_polarity(int idx
)
739 return MPBIOS_polarity(idx
);
742 static inline int irq_trigger(int idx
)
744 return MPBIOS_trigger(idx
);
747 static int pin_2_irq(int idx
, int apic
, int pin
)
750 int bus
= mp_irqs
[idx
].mp_srcbus
;
753 * Debugging check, we are in big trouble if this message pops up!
755 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
756 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
758 if (test_bit(bus
, mp_bus_not_pci
)) {
759 irq
= mp_irqs
[idx
].mp_srcbusirq
;
762 * PCI IRQs are mapped in order
766 irq
+= nr_ioapic_registers
[i
++];
769 BUG_ON(irq
>= NR_IRQS
);
773 void lock_vector_lock(void)
775 /* Used to the online set of cpus does not change
776 * during assign_irq_vector.
778 spin_lock(&vector_lock
);
781 void unlock_vector_lock(void)
783 spin_unlock(&vector_lock
);
786 static int __assign_irq_vector(int irq
, cpumask_t mask
)
789 * NOTE! The local APIC isn't very good at handling
790 * multiple interrupts at the same interrupt level.
791 * As the interrupt level is determined by taking the
792 * vector number and shifting that right by 4, we
793 * want to spread these out a bit so that they don't
794 * all fall in the same interrupt level.
796 * Also, we've got to be careful not to trash gate
797 * 0x80, because int 0x80 is hm, kind of importantish. ;)
799 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
800 unsigned int old_vector
;
804 BUG_ON((unsigned)irq
>= NR_IRQS
);
807 /* Only try and allocate irqs on cpus that are present */
808 cpus_and(mask
, mask
, cpu_online_map
);
810 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
813 old_vector
= cfg
->vector
;
816 cpus_and(tmp
, cfg
->domain
, mask
);
817 if (!cpus_empty(tmp
))
821 for_each_cpu_mask_nr(cpu
, mask
) {
822 cpumask_t domain
, new_mask
;
826 domain
= vector_allocation_domain(cpu
);
827 cpus_and(new_mask
, domain
, cpu_online_map
);
829 vector
= current_vector
;
830 offset
= current_offset
;
833 if (vector
>= first_system_vector
) {
834 /* If we run out of vectors on large boxen, must share them. */
835 offset
= (offset
+ 1) % 8;
836 vector
= FIRST_DEVICE_VECTOR
+ offset
;
838 if (unlikely(current_vector
== vector
))
840 if (vector
== IA32_SYSCALL_VECTOR
)
842 for_each_cpu_mask_nr(new_cpu
, new_mask
)
843 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
846 current_vector
= vector
;
847 current_offset
= offset
;
849 cfg
->move_in_progress
= 1;
850 cfg
->old_domain
= cfg
->domain
;
852 for_each_cpu_mask_nr(new_cpu
, new_mask
)
853 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
854 cfg
->vector
= vector
;
855 cfg
->domain
= domain
;
861 static int assign_irq_vector(int irq
, cpumask_t mask
)
866 spin_lock_irqsave(&vector_lock
, flags
);
867 err
= __assign_irq_vector(irq
, mask
);
868 spin_unlock_irqrestore(&vector_lock
, flags
);
872 static void __clear_irq_vector(int irq
)
878 BUG_ON((unsigned)irq
>= NR_IRQS
);
880 BUG_ON(!cfg
->vector
);
882 vector
= cfg
->vector
;
883 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
884 for_each_cpu_mask_nr(cpu
, mask
)
885 per_cpu(vector_irq
, cpu
)[vector
] = -1;
888 cpus_clear(cfg
->domain
);
891 void __setup_vector_irq(int cpu
)
893 /* Initialize vector_irq on a new cpu */
894 /* This function must be called with vector_lock held */
897 /* Mark the inuse vectors */
898 for (irq
= 0; irq
< NR_IRQS
; ++irq
) {
899 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
901 vector
= irq_cfg
[irq
].vector
;
902 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
904 /* Mark the free vectors */
905 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
906 irq
= per_cpu(vector_irq
, cpu
)[vector
];
909 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
910 per_cpu(vector_irq
, cpu
)[vector
] = -1;
914 static struct irq_chip ioapic_chip
;
915 #ifdef CONFIG_INTR_REMAP
916 static struct irq_chip ir_ioapic_chip
;
919 static void ioapic_register_intr(int irq
, unsigned long trigger
)
922 irq_desc
[irq
].status
|= IRQ_LEVEL
;
924 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
926 #ifdef CONFIG_INTR_REMAP
927 if (irq_remapped(irq
)) {
928 irq_desc
[irq
].status
|= IRQ_MOVE_PCNTXT
;
930 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
934 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
935 handle_edge_irq
, "edge");
940 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
944 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
945 handle_edge_irq
, "edge");
948 static int setup_ioapic_entry(int apic
, int irq
,
949 struct IO_APIC_route_entry
*entry
,
950 unsigned int destination
, int trigger
,
951 int polarity
, int vector
)
954 * add it to the IO-APIC irq-routing table:
956 memset(entry
,0,sizeof(*entry
));
958 #ifdef CONFIG_INTR_REMAP
959 if (intr_remapping_enabled
) {
960 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
962 struct IR_IO_APIC_route_entry
*ir_entry
=
963 (struct IR_IO_APIC_route_entry
*) entry
;
967 panic("No mapping iommu for ioapic %d\n", apic
);
969 index
= alloc_irte(iommu
, irq
, 1);
971 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
973 memset(&irte
, 0, sizeof(irte
));
976 irte
.dst_mode
= INT_DEST_MODE
;
977 irte
.trigger_mode
= trigger
;
978 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
979 irte
.vector
= vector
;
980 irte
.dest_id
= IRTE_DEST(destination
);
982 modify_irte(irq
, &irte
);
984 ir_entry
->index2
= (index
>> 15) & 0x1;
986 ir_entry
->format
= 1;
987 ir_entry
->index
= (index
& 0x7fff);
991 entry
->delivery_mode
= INT_DELIVERY_MODE
;
992 entry
->dest_mode
= INT_DEST_MODE
;
993 entry
->dest
= destination
;
996 entry
->mask
= 0; /* enable IRQ */
997 entry
->trigger
= trigger
;
998 entry
->polarity
= polarity
;
999 entry
->vector
= vector
;
1001 /* Mask level triggered irqs.
1002 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1009 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
1010 int trigger
, int polarity
)
1012 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1013 struct IO_APIC_route_entry entry
;
1016 if (!IO_APIC_IRQ(irq
))
1020 if (assign_irq_vector(irq
, mask
))
1023 cpus_and(mask
, cfg
->domain
, mask
);
1025 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1026 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1027 "IRQ %d Mode:%i Active:%i)\n",
1028 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1029 irq
, trigger
, polarity
);
1032 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1033 cpu_mask_to_apicid(mask
), trigger
, polarity
,
1035 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1036 mp_ioapics
[apic
].mp_apicid
, pin
);
1037 __clear_irq_vector(irq
);
1041 ioapic_register_intr(irq
, trigger
);
1043 disable_8259A_irq(irq
);
1045 ioapic_write_entry(apic
, pin
, entry
);
1048 static void __init
setup_IO_APIC_irqs(void)
1050 int apic
, pin
, idx
, irq
, first_notcon
= 1;
1052 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1054 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1055 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1057 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1060 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1063 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1066 if (!first_notcon
) {
1067 apic_printk(APIC_VERBOSE
, " not connected.\n");
1071 irq
= pin_2_irq(idx
, apic
, pin
);
1072 add_pin_to_irq(irq
, apic
, pin
);
1074 setup_IO_APIC_irq(apic
, pin
, irq
,
1075 irq_trigger(idx
), irq_polarity(idx
));
1080 apic_printk(APIC_VERBOSE
, " not connected.\n");
1084 * Set up the timer pin, possibly with the 8259A-master behind.
1086 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1089 struct IO_APIC_route_entry entry
;
1091 if (intr_remapping_enabled
)
1094 memset(&entry
, 0, sizeof(entry
));
1097 * We use logical delivery to get the timer IRQ
1100 entry
.dest_mode
= INT_DEST_MODE
;
1101 entry
.mask
= 1; /* mask IRQ now */
1102 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1103 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1106 entry
.vector
= vector
;
1109 * The timer IRQ doesn't have to know that behind the
1110 * scene we may have a 8259A-master in AEOI mode ...
1112 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1115 * Add it to the IO-APIC irq-routing table:
1117 ioapic_write_entry(apic
, pin
, entry
);
1120 void __apicdebuginit
print_IO_APIC(void)
1123 union IO_APIC_reg_00 reg_00
;
1124 union IO_APIC_reg_01 reg_01
;
1125 union IO_APIC_reg_02 reg_02
;
1126 unsigned long flags
;
1128 if (apic_verbosity
== APIC_QUIET
)
1131 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1132 for (i
= 0; i
< nr_ioapics
; i
++)
1133 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1134 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1137 * We are a bit conservative about what we expect. We have to
1138 * know about every hardware change ASAP.
1140 printk(KERN_INFO
"testing the IO APIC.......................\n");
1142 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1144 spin_lock_irqsave(&ioapic_lock
, flags
);
1145 reg_00
.raw
= io_apic_read(apic
, 0);
1146 reg_01
.raw
= io_apic_read(apic
, 1);
1147 if (reg_01
.bits
.version
>= 0x10)
1148 reg_02
.raw
= io_apic_read(apic
, 2);
1149 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1152 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1153 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1154 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1156 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1157 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1159 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1160 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1162 if (reg_01
.bits
.version
>= 0x10) {
1163 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1164 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1167 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1169 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1170 " Stat Dmod Deli Vect: \n");
1172 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1173 struct IO_APIC_route_entry entry
;
1175 entry
= ioapic_read_entry(apic
, i
);
1177 printk(KERN_DEBUG
" %02x %03X ",
1182 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1187 entry
.delivery_status
,
1189 entry
.delivery_mode
,
1194 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1195 for (i
= 0; i
< NR_IRQS
; i
++) {
1196 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1199 printk(KERN_DEBUG
"IRQ%d ", i
);
1201 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1204 entry
= irq_2_pin
+ entry
->next
;
1209 printk(KERN_INFO
".................................... done.\n");
1216 static __apicdebuginit
void print_APIC_bitfield (int base
)
1221 if (apic_verbosity
== APIC_QUIET
)
1224 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1225 for (i
= 0; i
< 8; i
++) {
1226 v
= apic_read(base
+ i
*0x10);
1227 for (j
= 0; j
< 32; j
++) {
1237 void __apicdebuginit
print_local_APIC(void * dummy
)
1239 unsigned int v
, ver
, maxlvt
;
1242 if (apic_verbosity
== APIC_QUIET
)
1245 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1246 smp_processor_id(), hard_smp_processor_id());
1247 v
= apic_read(APIC_ID
);
1248 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1249 v
= apic_read(APIC_LVR
);
1250 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1251 ver
= GET_APIC_VERSION(v
);
1252 maxlvt
= lapic_get_maxlvt();
1254 v
= apic_read(APIC_TASKPRI
);
1255 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1257 v
= apic_read(APIC_ARBPRI
);
1258 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1259 v
& APIC_ARBPRI_MASK
);
1260 v
= apic_read(APIC_PROCPRI
);
1261 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1263 v
= apic_read(APIC_EOI
);
1264 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1265 v
= apic_read(APIC_RRR
);
1266 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1267 v
= apic_read(APIC_LDR
);
1268 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1269 v
= apic_read(APIC_DFR
);
1270 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1271 v
= apic_read(APIC_SPIV
);
1272 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1274 printk(KERN_DEBUG
"... APIC ISR field:\n");
1275 print_APIC_bitfield(APIC_ISR
);
1276 printk(KERN_DEBUG
"... APIC TMR field:\n");
1277 print_APIC_bitfield(APIC_TMR
);
1278 printk(KERN_DEBUG
"... APIC IRR field:\n");
1279 print_APIC_bitfield(APIC_IRR
);
1281 v
= apic_read(APIC_ESR
);
1282 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1284 icr
= apic_icr_read();
1285 printk(KERN_DEBUG
"... APIC ICR: %08x\n", icr
);
1286 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", icr
>> 32);
1288 v
= apic_read(APIC_LVTT
);
1289 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1291 if (maxlvt
> 3) { /* PC is LVT#4. */
1292 v
= apic_read(APIC_LVTPC
);
1293 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1295 v
= apic_read(APIC_LVT0
);
1296 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1297 v
= apic_read(APIC_LVT1
);
1298 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1300 if (maxlvt
> 2) { /* ERR is LVT#3. */
1301 v
= apic_read(APIC_LVTERR
);
1302 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1305 v
= apic_read(APIC_TMICT
);
1306 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1307 v
= apic_read(APIC_TMCCT
);
1308 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1309 v
= apic_read(APIC_TDCR
);
1310 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1314 void print_all_local_APICs (void)
1316 on_each_cpu(print_local_APIC
, NULL
, 1);
1319 void __apicdebuginit
print_PIC(void)
1322 unsigned long flags
;
1324 if (apic_verbosity
== APIC_QUIET
)
1327 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1329 spin_lock_irqsave(&i8259A_lock
, flags
);
1331 v
= inb(0xa1) << 8 | inb(0x21);
1332 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1334 v
= inb(0xa0) << 8 | inb(0x20);
1335 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1339 v
= inb(0xa0) << 8 | inb(0x20);
1343 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1345 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1347 v
= inb(0x4d1) << 8 | inb(0x4d0);
1348 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1353 void __init
enable_IO_APIC(void)
1355 union IO_APIC_reg_01 reg_01
;
1356 int i8259_apic
, i8259_pin
;
1358 unsigned long flags
;
1360 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1361 irq_2_pin
[i
].pin
= -1;
1362 irq_2_pin
[i
].next
= 0;
1366 * The number of IO-APIC IRQ registers (== #pins):
1368 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1369 spin_lock_irqsave(&ioapic_lock
, flags
);
1370 reg_01
.raw
= io_apic_read(apic
, 1);
1371 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1372 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1374 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1376 /* See if any of the pins is in ExtINT mode */
1377 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1378 struct IO_APIC_route_entry entry
;
1379 entry
= ioapic_read_entry(apic
, pin
);
1381 /* If the interrupt line is enabled and in ExtInt mode
1382 * I have found the pin where the i8259 is connected.
1384 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1385 ioapic_i8259
.apic
= apic
;
1386 ioapic_i8259
.pin
= pin
;
1392 /* Look to see what if the MP table has reported the ExtINT */
1393 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1394 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1395 /* Trust the MP table if nothing is setup in the hardware */
1396 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1397 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1398 ioapic_i8259
.pin
= i8259_pin
;
1399 ioapic_i8259
.apic
= i8259_apic
;
1401 /* Complain if the MP table and the hardware disagree */
1402 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1403 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1405 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1409 * Do not trust the IO-APIC being empty at bootup
1415 * Not an __init, needed by the reboot code
1417 void disable_IO_APIC(void)
1420 * Clear the IO-APIC before rebooting:
1425 * If the i8259 is routed through an IOAPIC
1426 * Put that IOAPIC in virtual wire mode
1427 * so legacy interrupts can be delivered.
1429 if (ioapic_i8259
.pin
!= -1) {
1430 struct IO_APIC_route_entry entry
;
1432 memset(&entry
, 0, sizeof(entry
));
1433 entry
.mask
= 0; /* Enabled */
1434 entry
.trigger
= 0; /* Edge */
1436 entry
.polarity
= 0; /* High */
1437 entry
.delivery_status
= 0;
1438 entry
.dest_mode
= 0; /* Physical */
1439 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1441 entry
.dest
= read_apic_id();
1444 * Add it to the IO-APIC irq-routing table:
1446 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1449 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1453 * There is a nasty bug in some older SMP boards, their mptable lies
1454 * about the timer IRQ. We do the following to work around the situation:
1456 * - timer IRQ defaults to IO-APIC IRQ
1457 * - if this function detects that timer IRQs are defunct, then we fall
1458 * back to ISA timer IRQs
1460 static int __init
timer_irq_works(void)
1462 unsigned long t1
= jiffies
;
1463 unsigned long flags
;
1465 local_save_flags(flags
);
1467 /* Let ten ticks pass... */
1468 mdelay((10 * 1000) / HZ
);
1469 local_irq_restore(flags
);
1472 * Expect a few ticks at least, to be sure some possible
1473 * glue logic does not lock up after one or two first
1474 * ticks in a non-ExtINT mode. Also the local APIC
1475 * might have cached one ExtINT interrupt. Finally, at
1476 * least one tick may be lost due to delays.
1480 if (time_after(jiffies
, t1
+ 4))
1486 * In the SMP+IOAPIC case it might happen that there are an unspecified
1487 * number of pending IRQ events unhandled. These cases are very rare,
1488 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1489 * better to do it this way as thus we do not have to be aware of
1490 * 'pending' interrupts in the IRQ path, except at this point.
1493 * Edge triggered needs to resend any interrupt
1494 * that was delayed but this is now handled in the device
1499 * Starting up a edge-triggered IO-APIC interrupt is
1500 * nasty - we need to make sure that we get the edge.
1501 * If it is already asserted for some reason, we need
1502 * return 1 to indicate that is was pending.
1504 * This is not complete - we should be able to fake
1505 * an edge even if it isn't on the 8259A...
1508 static unsigned int startup_ioapic_irq(unsigned int irq
)
1510 int was_pending
= 0;
1511 unsigned long flags
;
1513 spin_lock_irqsave(&ioapic_lock
, flags
);
1515 disable_8259A_irq(irq
);
1516 if (i8259A_irq_pending(irq
))
1519 __unmask_IO_APIC_irq(irq
);
1520 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1525 static int ioapic_retrigger_irq(unsigned int irq
)
1527 struct irq_cfg
*cfg
= &irq_cfg
[irq
];
1528 unsigned long flags
;
1530 spin_lock_irqsave(&vector_lock
, flags
);
1531 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg
->domain
)), cfg
->vector
);
1532 spin_unlock_irqrestore(&vector_lock
, flags
);
1538 * Level and edge triggered IO-APIC interrupts need different handling,
1539 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1540 * handled with the level-triggered descriptor, but that one has slightly
1541 * more overhead. Level-triggered interrupts cannot be handled with the
1542 * edge-triggered handler, without risking IRQ storms and other ugly
1548 #ifdef CONFIG_INTR_REMAP
1549 static void ir_irq_migration(struct work_struct
*work
);
1551 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
1554 * Migrate the IO-APIC irq in the presence of intr-remapping.
1556 * For edge triggered, irq migration is a simple atomic update(of vector
1557 * and cpu destination) of IRTE and flush the hardware cache.
1559 * For level triggered, we need to modify the io-apic RTE aswell with the update
1560 * vector information, along with modifying IRTE with vector and destination.
1561 * So irq migration for level triggered is little bit more complex compared to
1562 * edge triggered migration. But the good news is, we use the same algorithm
1563 * for level triggered migration as we have today, only difference being,
1564 * we now initiate the irq migration from process context instead of the
1565 * interrupt context.
1567 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1568 * suppression) to the IO-APIC, level triggered irq migration will also be
1569 * as simple as edge triggered migration and we can do the irq migration
1570 * with a simple atomic update to IO-APIC RTE.
1572 static void migrate_ioapic_irq(int irq
, cpumask_t mask
)
1574 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1575 struct irq_desc
*desc
= irq_desc
+ irq
;
1576 cpumask_t tmp
, cleanup_mask
;
1578 int modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
1580 unsigned long flags
;
1582 cpus_and(tmp
, mask
, cpu_online_map
);
1583 if (cpus_empty(tmp
))
1586 if (get_irte(irq
, &irte
))
1589 if (assign_irq_vector(irq
, mask
))
1592 cpus_and(tmp
, cfg
->domain
, mask
);
1593 dest
= cpu_mask_to_apicid(tmp
);
1595 if (modify_ioapic_rte
) {
1596 spin_lock_irqsave(&ioapic_lock
, flags
);
1597 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
1598 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1601 irte
.vector
= cfg
->vector
;
1602 irte
.dest_id
= IRTE_DEST(dest
);
1605 * Modified the IRTE and flushes the Interrupt entry cache.
1607 modify_irte(irq
, &irte
);
1609 if (cfg
->move_in_progress
) {
1610 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1611 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1612 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1613 cfg
->move_in_progress
= 0;
1616 irq_desc
[irq
].affinity
= mask
;
1619 static int migrate_irq_remapped_level(int irq
)
1623 mask_IO_APIC_irq(irq
);
1625 if (io_apic_level_ack_pending(irq
)) {
1627 * Interrupt in progress. Migrating irq now will change the
1628 * vector information in the IO-APIC RTE and that will confuse
1629 * the EOI broadcast performed by cpu.
1630 * So, delay the irq migration to the next instance.
1632 schedule_delayed_work(&ir_migration_work
, 1);
1636 /* everthing is clear. we have right of way */
1637 migrate_ioapic_irq(irq
, irq_desc
[irq
].pending_mask
);
1640 irq_desc
[irq
].status
&= ~IRQ_MOVE_PENDING
;
1641 cpus_clear(irq_desc
[irq
].pending_mask
);
1644 unmask_IO_APIC_irq(irq
);
1648 static void ir_irq_migration(struct work_struct
*work
)
1652 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1653 struct irq_desc
*desc
= irq_desc
+ irq
;
1654 if (desc
->status
& IRQ_MOVE_PENDING
) {
1655 unsigned long flags
;
1657 spin_lock_irqsave(&desc
->lock
, flags
);
1658 if (!desc
->chip
->set_affinity
||
1659 !(desc
->status
& IRQ_MOVE_PENDING
)) {
1660 desc
->status
&= ~IRQ_MOVE_PENDING
;
1661 spin_unlock_irqrestore(&desc
->lock
, flags
);
1665 desc
->chip
->set_affinity(irq
,
1666 irq_desc
[irq
].pending_mask
);
1667 spin_unlock_irqrestore(&desc
->lock
, flags
);
1673 * Migrates the IRQ destination in the process context.
1675 static void set_ir_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
1677 if (irq_desc
[irq
].status
& IRQ_LEVEL
) {
1678 irq_desc
[irq
].status
|= IRQ_MOVE_PENDING
;
1679 irq_desc
[irq
].pending_mask
= mask
;
1680 migrate_irq_remapped_level(irq
);
1684 migrate_ioapic_irq(irq
, mask
);
1688 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
1690 unsigned vector
, me
;
1695 me
= smp_processor_id();
1696 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
1698 struct irq_desc
*desc
;
1699 struct irq_cfg
*cfg
;
1700 irq
= __get_cpu_var(vector_irq
)[vector
];
1704 desc
= irq_desc
+ irq
;
1705 cfg
= irq_cfg
+ irq
;
1706 spin_lock(&desc
->lock
);
1707 if (!cfg
->move_cleanup_count
)
1710 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
1713 __get_cpu_var(vector_irq
)[vector
] = -1;
1714 cfg
->move_cleanup_count
--;
1716 spin_unlock(&desc
->lock
);
1722 static void irq_complete_move(unsigned int irq
)
1724 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1725 unsigned vector
, me
;
1727 if (likely(!cfg
->move_in_progress
))
1730 vector
= ~get_irq_regs()->orig_ax
;
1731 me
= smp_processor_id();
1732 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
1733 cpumask_t cleanup_mask
;
1735 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1736 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1737 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1738 cfg
->move_in_progress
= 0;
1742 static inline void irq_complete_move(unsigned int irq
) {}
1744 #ifdef CONFIG_INTR_REMAP
1745 static void ack_x2apic_level(unsigned int irq
)
1750 static void ack_x2apic_edge(unsigned int irq
)
1756 static void ack_apic_edge(unsigned int irq
)
1758 irq_complete_move(irq
);
1759 move_native_irq(irq
);
1763 static void ack_apic_level(unsigned int irq
)
1765 int do_unmask_irq
= 0;
1767 irq_complete_move(irq
);
1768 #ifdef CONFIG_GENERIC_PENDING_IRQ
1769 /* If we are moving the irq we need to mask it */
1770 if (unlikely(irq_desc
[irq
].status
& IRQ_MOVE_PENDING
)) {
1772 mask_IO_APIC_irq(irq
);
1777 * We must acknowledge the irq before we move it or the acknowledge will
1778 * not propagate properly.
1782 /* Now we can move and renable the irq */
1783 if (unlikely(do_unmask_irq
)) {
1784 /* Only migrate the irq if the ack has been received.
1786 * On rare occasions the broadcast level triggered ack gets
1787 * delayed going to ioapics, and if we reprogram the
1788 * vector while Remote IRR is still set the irq will never
1791 * To prevent this scenario we read the Remote IRR bit
1792 * of the ioapic. This has two effects.
1793 * - On any sane system the read of the ioapic will
1794 * flush writes (and acks) going to the ioapic from
1796 * - We get to see if the ACK has actually been delivered.
1798 * Based on failed experiments of reprogramming the
1799 * ioapic entry from outside of irq context starting
1800 * with masking the ioapic entry and then polling until
1801 * Remote IRR was clear before reprogramming the
1802 * ioapic I don't trust the Remote IRR bit to be
1803 * completey accurate.
1805 * However there appears to be no other way to plug
1806 * this race, so if the Remote IRR bit is not
1807 * accurate and is causing problems then it is a hardware bug
1808 * and you can go talk to the chipset vendor about it.
1810 if (!io_apic_level_ack_pending(irq
))
1811 move_masked_irq(irq
);
1812 unmask_IO_APIC_irq(irq
);
1816 static struct irq_chip ioapic_chip __read_mostly
= {
1818 .startup
= startup_ioapic_irq
,
1819 .mask
= mask_IO_APIC_irq
,
1820 .unmask
= unmask_IO_APIC_irq
,
1821 .ack
= ack_apic_edge
,
1822 .eoi
= ack_apic_level
,
1824 .set_affinity
= set_ioapic_affinity_irq
,
1826 .retrigger
= ioapic_retrigger_irq
,
1829 #ifdef CONFIG_INTR_REMAP
1830 static struct irq_chip ir_ioapic_chip __read_mostly
= {
1831 .name
= "IR-IO-APIC",
1832 .startup
= startup_ioapic_irq
,
1833 .mask
= mask_IO_APIC_irq
,
1834 .unmask
= unmask_IO_APIC_irq
,
1835 .ack
= ack_x2apic_edge
,
1836 .eoi
= ack_x2apic_level
,
1838 .set_affinity
= set_ir_ioapic_affinity_irq
,
1840 .retrigger
= ioapic_retrigger_irq
,
1844 static inline void init_IO_APIC_traps(void)
1849 * NOTE! The local APIC isn't very good at handling
1850 * multiple interrupts at the same interrupt level.
1851 * As the interrupt level is determined by taking the
1852 * vector number and shifting that right by 4, we
1853 * want to spread these out a bit so that they don't
1854 * all fall in the same interrupt level.
1856 * Also, we've got to be careful not to trash gate
1857 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1859 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1860 if (IO_APIC_IRQ(irq
) && !irq_cfg
[irq
].vector
) {
1862 * Hmm.. We don't have an entry for this,
1863 * so default to an old-fashioned 8259
1864 * interrupt if we can..
1867 make_8259A_irq(irq
);
1869 /* Strange. Oh, well.. */
1870 irq_desc
[irq
].chip
= &no_irq_chip
;
1875 static void unmask_lapic_irq(unsigned int irq
)
1879 v
= apic_read(APIC_LVT0
);
1880 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
1883 static void mask_lapic_irq(unsigned int irq
)
1887 v
= apic_read(APIC_LVT0
);
1888 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1891 static void ack_lapic_irq (unsigned int irq
)
1896 static struct irq_chip lapic_chip __read_mostly
= {
1897 .name
= "local-APIC",
1898 .mask
= mask_lapic_irq
,
1899 .unmask
= unmask_lapic_irq
,
1900 .ack
= ack_lapic_irq
,
1903 static void lapic_register_intr(int irq
)
1905 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
1906 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
1910 static void __init
setup_nmi(void)
1913 * Dirty trick to enable the NMI watchdog ...
1914 * We put the 8259A master into AEOI mode and
1915 * unmask on all local APICs LVT0 as NMI.
1917 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1918 * is from Maciej W. Rozycki - so we do not have to EOI from
1919 * the NMI handler or the timer interrupt.
1921 printk(KERN_INFO
"activating NMI Watchdog ...");
1923 enable_NMI_through_LVT0();
1929 * This looks a bit hackish but it's about the only one way of sending
1930 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1931 * not support the ExtINT mode, unfortunately. We need to send these
1932 * cycles as some i82489DX-based boards have glue logic that keeps the
1933 * 8259A interrupt line asserted until INTA. --macro
1935 static inline void __init
unlock_ExtINT_logic(void)
1938 struct IO_APIC_route_entry entry0
, entry1
;
1939 unsigned char save_control
, save_freq_select
;
1941 pin
= find_isa_irq_pin(8, mp_INT
);
1942 apic
= find_isa_irq_apic(8, mp_INT
);
1946 entry0
= ioapic_read_entry(apic
, pin
);
1948 clear_IO_APIC_pin(apic
, pin
);
1950 memset(&entry1
, 0, sizeof(entry1
));
1952 entry1
.dest_mode
= 0; /* physical delivery */
1953 entry1
.mask
= 0; /* unmask IRQ now */
1954 entry1
.dest
= hard_smp_processor_id();
1955 entry1
.delivery_mode
= dest_ExtINT
;
1956 entry1
.polarity
= entry0
.polarity
;
1960 ioapic_write_entry(apic
, pin
, entry1
);
1962 save_control
= CMOS_READ(RTC_CONTROL
);
1963 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
1964 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
1966 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
1971 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
1975 CMOS_WRITE(save_control
, RTC_CONTROL
);
1976 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
1977 clear_IO_APIC_pin(apic
, pin
);
1979 ioapic_write_entry(apic
, pin
, entry0
);
1983 * This code may look a bit paranoid, but it's supposed to cooperate with
1984 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1985 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1986 * fanatically on his truly buggy board.
1988 * FIXME: really need to revamp this for modern platforms only.
1990 static inline void __init
check_timer(void)
1992 struct irq_cfg
*cfg
= irq_cfg
+ 0;
1993 int apic1
, pin1
, apic2
, pin2
;
1994 unsigned long flags
;
1997 local_irq_save(flags
);
2000 * get/set the timer IRQ vector:
2002 disable_8259A_irq(0);
2003 assign_irq_vector(0, TARGET_CPUS
);
2006 * As IRQ0 is to be enabled in the 8259A, the virtual
2007 * wire has to be disabled in the local APIC.
2009 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2012 pin1
= find_isa_irq_pin(0, mp_INT
);
2013 apic1
= find_isa_irq_apic(0, mp_INT
);
2014 pin2
= ioapic_i8259
.pin
;
2015 apic2
= ioapic_i8259
.apic
;
2017 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2018 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2019 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2022 * Some BIOS writers are clueless and report the ExtINTA
2023 * I/O APIC input from the cascaded 8259A as the timer
2024 * interrupt input. So just in case, if only one pin
2025 * was found above, try it both directly and through the
2029 if (intr_remapping_enabled
)
2030 panic("BIOS bug: timer not connected to IO-APIC");
2034 } else if (pin2
== -1) {
2041 * Ok, does IRQ0 through the IOAPIC work?
2044 add_pin_to_irq(0, apic1
, pin1
);
2045 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2047 unmask_IO_APIC_irq(0);
2048 if (!no_timer_check
&& timer_irq_works()) {
2049 if (nmi_watchdog
== NMI_IO_APIC
) {
2051 enable_8259A_irq(0);
2053 if (disable_timer_pin_1
> 0)
2054 clear_IO_APIC_pin(0, pin1
);
2057 if (intr_remapping_enabled
)
2058 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2059 clear_IO_APIC_pin(apic1
, pin1
);
2061 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2062 "8254 timer not connected to IO-APIC\n");
2064 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2065 "(IRQ0) through the 8259A ...\n");
2066 apic_printk(APIC_QUIET
, KERN_INFO
2067 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2069 * legacy devices should be connected to IO APIC #0
2071 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2072 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2073 unmask_IO_APIC_irq(0);
2074 enable_8259A_irq(0);
2075 if (timer_irq_works()) {
2076 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2077 timer_through_8259
= 1;
2078 if (nmi_watchdog
== NMI_IO_APIC
) {
2079 disable_8259A_irq(0);
2081 enable_8259A_irq(0);
2086 * Cleanup, just in case ...
2088 disable_8259A_irq(0);
2089 clear_IO_APIC_pin(apic2
, pin2
);
2090 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2093 if (nmi_watchdog
== NMI_IO_APIC
) {
2094 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2095 "through the IO-APIC - disabling NMI Watchdog!\n");
2096 nmi_watchdog
= NMI_NONE
;
2099 apic_printk(APIC_QUIET
, KERN_INFO
2100 "...trying to set up timer as Virtual Wire IRQ...\n");
2102 lapic_register_intr(0);
2103 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2104 enable_8259A_irq(0);
2106 if (timer_irq_works()) {
2107 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2110 disable_8259A_irq(0);
2111 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2112 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2114 apic_printk(APIC_QUIET
, KERN_INFO
2115 "...trying to set up timer as ExtINT IRQ...\n");
2119 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2121 unlock_ExtINT_logic();
2123 if (timer_irq_works()) {
2124 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2127 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2128 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2129 "report. Then try booting with the 'noapic' option.\n");
2131 local_irq_restore(flags
);
2134 static int __init
notimercheck(char *s
)
2139 __setup("no_timer_check", notimercheck
);
2142 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2143 * to devices. However there may be an I/O APIC pin available for
2144 * this interrupt regardless. The pin may be left unconnected, but
2145 * typically it will be reused as an ExtINT cascade interrupt for
2146 * the master 8259A. In the MPS case such a pin will normally be
2147 * reported as an ExtINT interrupt in the MP table. With ACPI
2148 * there is no provision for ExtINT interrupts, and in the absence
2149 * of an override it would be treated as an ordinary ISA I/O APIC
2150 * interrupt, that is edge-triggered and unmasked by default. We
2151 * used to do this, but it caused problems on some systems because
2152 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2153 * the same ExtINT cascade interrupt to drive the local APIC of the
2154 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2155 * the I/O APIC in all cases now. No actual device should request
2156 * it anyway. --macro
2158 #define PIC_IRQS (1<<2)
2160 void __init
setup_IO_APIC(void)
2164 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2167 io_apic_irqs
= ~PIC_IRQS
;
2169 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2172 setup_IO_APIC_irqs();
2173 init_IO_APIC_traps();
2179 struct sysfs_ioapic_data
{
2180 struct sys_device dev
;
2181 struct IO_APIC_route_entry entry
[0];
2183 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2185 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2187 struct IO_APIC_route_entry
*entry
;
2188 struct sysfs_ioapic_data
*data
;
2191 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2192 entry
= data
->entry
;
2193 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
2194 *entry
= ioapic_read_entry(dev
->id
, i
);
2199 static int ioapic_resume(struct sys_device
*dev
)
2201 struct IO_APIC_route_entry
*entry
;
2202 struct sysfs_ioapic_data
*data
;
2203 unsigned long flags
;
2204 union IO_APIC_reg_00 reg_00
;
2207 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2208 entry
= data
->entry
;
2210 spin_lock_irqsave(&ioapic_lock
, flags
);
2211 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2212 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2213 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2214 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2216 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2217 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2218 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2223 static struct sysdev_class ioapic_sysdev_class
= {
2225 .suspend
= ioapic_suspend
,
2226 .resume
= ioapic_resume
,
2229 static int __init
ioapic_init_sysfs(void)
2231 struct sys_device
* dev
;
2234 error
= sysdev_class_register(&ioapic_sysdev_class
);
2238 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2239 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2240 * sizeof(struct IO_APIC_route_entry
);
2241 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2242 if (!mp_ioapic_data
[i
]) {
2243 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2246 dev
= &mp_ioapic_data
[i
]->dev
;
2248 dev
->cls
= &ioapic_sysdev_class
;
2249 error
= sysdev_register(dev
);
2251 kfree(mp_ioapic_data
[i
]);
2252 mp_ioapic_data
[i
] = NULL
;
2253 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2261 device_initcall(ioapic_init_sysfs
);
2264 * Dynamic irq allocate and deallocation
2266 int create_irq(void)
2268 /* Allocate an unused irq */
2271 unsigned long flags
;
2274 spin_lock_irqsave(&vector_lock
, flags
);
2275 for (new = (NR_IRQS
- 1); new >= 0; new--) {
2276 if (platform_legacy_irq(new))
2278 if (irq_cfg
[new].vector
!= 0)
2280 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
2284 spin_unlock_irqrestore(&vector_lock
, flags
);
2287 dynamic_irq_init(irq
);
2292 void destroy_irq(unsigned int irq
)
2294 unsigned long flags
;
2296 dynamic_irq_cleanup(irq
);
2298 #ifdef CONFIG_INTR_REMAP
2301 spin_lock_irqsave(&vector_lock
, flags
);
2302 __clear_irq_vector(irq
);
2303 spin_unlock_irqrestore(&vector_lock
, flags
);
2307 * MSI message composition
2309 #ifdef CONFIG_PCI_MSI
2310 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2312 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2318 err
= assign_irq_vector(irq
, tmp
);
2322 cpus_and(tmp
, cfg
->domain
, tmp
);
2323 dest
= cpu_mask_to_apicid(tmp
);
2325 #ifdef CONFIG_INTR_REMAP
2326 if (irq_remapped(irq
)) {
2331 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
2332 BUG_ON(ir_index
== -1);
2334 memset (&irte
, 0, sizeof(irte
));
2337 irte
.dst_mode
= INT_DEST_MODE
;
2338 irte
.trigger_mode
= 0; /* edge */
2339 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
2340 irte
.vector
= cfg
->vector
;
2341 irte
.dest_id
= IRTE_DEST(dest
);
2343 modify_irte(irq
, &irte
);
2345 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2346 msg
->data
= sub_handle
;
2347 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
2349 MSI_ADDR_IR_INDEX1(ir_index
) |
2350 MSI_ADDR_IR_INDEX2(ir_index
);
2354 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2357 ((INT_DEST_MODE
== 0) ?
2358 MSI_ADDR_DEST_MODE_PHYSICAL
:
2359 MSI_ADDR_DEST_MODE_LOGICAL
) |
2360 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2361 MSI_ADDR_REDIRECTION_CPU
:
2362 MSI_ADDR_REDIRECTION_LOWPRI
) |
2363 MSI_ADDR_DEST_ID(dest
);
2366 MSI_DATA_TRIGGER_EDGE
|
2367 MSI_DATA_LEVEL_ASSERT
|
2368 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2369 MSI_DATA_DELIVERY_FIXED
:
2370 MSI_DATA_DELIVERY_LOWPRI
) |
2371 MSI_DATA_VECTOR(cfg
->vector
);
2377 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2379 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2384 cpus_and(tmp
, mask
, cpu_online_map
);
2385 if (cpus_empty(tmp
))
2388 if (assign_irq_vector(irq
, mask
))
2391 cpus_and(tmp
, cfg
->domain
, mask
);
2392 dest
= cpu_mask_to_apicid(tmp
);
2394 read_msi_msg(irq
, &msg
);
2396 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2397 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2398 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2399 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2401 write_msi_msg(irq
, &msg
);
2402 irq_desc
[irq
].affinity
= mask
;
2405 #ifdef CONFIG_INTR_REMAP
2407 * Migrate the MSI irq to another cpumask. This migration is
2408 * done in the process context using interrupt-remapping hardware.
2410 static void ir_set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2412 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2414 cpumask_t tmp
, cleanup_mask
;
2417 cpus_and(tmp
, mask
, cpu_online_map
);
2418 if (cpus_empty(tmp
))
2421 if (get_irte(irq
, &irte
))
2424 if (assign_irq_vector(irq
, mask
))
2427 cpus_and(tmp
, cfg
->domain
, mask
);
2428 dest
= cpu_mask_to_apicid(tmp
);
2430 irte
.vector
= cfg
->vector
;
2431 irte
.dest_id
= IRTE_DEST(dest
);
2434 * atomically update the IRTE with the new destination and vector.
2436 modify_irte(irq
, &irte
);
2439 * After this point, all the interrupts will start arriving
2440 * at the new destination. So, time to cleanup the previous
2441 * vector allocation.
2443 if (cfg
->move_in_progress
) {
2444 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2445 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2446 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2447 cfg
->move_in_progress
= 0;
2450 irq_desc
[irq
].affinity
= mask
;
2453 #endif /* CONFIG_SMP */
2456 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2457 * which implement the MSI or MSI-X Capability Structure.
2459 static struct irq_chip msi_chip
= {
2461 .unmask
= unmask_msi_irq
,
2462 .mask
= mask_msi_irq
,
2463 .ack
= ack_apic_edge
,
2465 .set_affinity
= set_msi_irq_affinity
,
2467 .retrigger
= ioapic_retrigger_irq
,
2470 #ifdef CONFIG_INTR_REMAP
2471 static struct irq_chip msi_ir_chip
= {
2472 .name
= "IR-PCI-MSI",
2473 .unmask
= unmask_msi_irq
,
2474 .mask
= mask_msi_irq
,
2475 .ack
= ack_x2apic_edge
,
2477 .set_affinity
= ir_set_msi_irq_affinity
,
2479 .retrigger
= ioapic_retrigger_irq
,
2483 * Map the PCI dev to the corresponding remapping hardware unit
2484 * and allocate 'nvec' consecutive interrupt-remapping table entries
2487 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
2489 struct intel_iommu
*iommu
;
2492 iommu
= map_dev_to_ir(dev
);
2495 "Unable to map PCI %s to iommu\n", pci_name(dev
));
2499 index
= alloc_irte(iommu
, irq
, nvec
);
2502 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
2510 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
, int irq
)
2515 ret
= msi_compose_msg(dev
, irq
, &msg
);
2519 set_irq_msi(irq
, desc
);
2520 write_msi_msg(irq
, &msg
);
2522 #ifdef CONFIG_INTR_REMAP
2523 if (irq_remapped(irq
)) {
2524 struct irq_desc
*desc
= irq_desc
+ irq
;
2526 * irq migration in process context
2528 desc
->status
|= IRQ_MOVE_PCNTXT
;
2529 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
2532 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
2537 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2545 #ifdef CONFIG_INTR_REMAP
2546 if (!intr_remapping_enabled
)
2549 ret
= msi_alloc_irte(dev
, irq
, 1);
2554 ret
= setup_msi_irq(dev
, desc
, irq
);
2561 #ifdef CONFIG_INTR_REMAP
2568 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
2570 int irq
, ret
, sub_handle
;
2571 struct msi_desc
*desc
;
2572 #ifdef CONFIG_INTR_REMAP
2573 struct intel_iommu
*iommu
= 0;
2578 list_for_each_entry(desc
, &dev
->msi_list
, list
) {
2582 #ifdef CONFIG_INTR_REMAP
2583 if (!intr_remapping_enabled
)
2588 * allocate the consecutive block of IRTE's
2591 index
= msi_alloc_irte(dev
, irq
, nvec
);
2597 iommu
= map_dev_to_ir(dev
);
2603 * setup the mapping between the irq and the IRTE
2604 * base index, the sub_handle pointing to the
2605 * appropriate interrupt remap table entry.
2607 set_irte_irq(irq
, iommu
, index
, sub_handle
);
2611 ret
= setup_msi_irq(dev
, desc
, irq
);
2623 void arch_teardown_msi_irq(unsigned int irq
)
2630 static void dmar_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
2632 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2637 cpus_and(tmp
, mask
, cpu_online_map
);
2638 if (cpus_empty(tmp
))
2641 if (assign_irq_vector(irq
, mask
))
2644 cpus_and(tmp
, cfg
->domain
, mask
);
2645 dest
= cpu_mask_to_apicid(tmp
);
2647 dmar_msi_read(irq
, &msg
);
2649 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2650 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2651 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2652 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2654 dmar_msi_write(irq
, &msg
);
2655 irq_desc
[irq
].affinity
= mask
;
2657 #endif /* CONFIG_SMP */
2659 struct irq_chip dmar_msi_type
= {
2661 .unmask
= dmar_msi_unmask
,
2662 .mask
= dmar_msi_mask
,
2663 .ack
= ack_apic_edge
,
2665 .set_affinity
= dmar_msi_set_affinity
,
2667 .retrigger
= ioapic_retrigger_irq
,
2670 int arch_setup_dmar_msi(unsigned int irq
)
2675 ret
= msi_compose_msg(NULL
, irq
, &msg
);
2678 dmar_msi_write(irq
, &msg
);
2679 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
2685 #endif /* CONFIG_PCI_MSI */
2687 * Hypertransport interrupt support
2689 #ifdef CONFIG_HT_IRQ
2693 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
2695 struct ht_irq_msg msg
;
2696 fetch_ht_irq_msg(irq
, &msg
);
2698 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
2699 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2701 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
2702 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2704 write_ht_irq_msg(irq
, &msg
);
2707 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2709 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2713 cpus_and(tmp
, mask
, cpu_online_map
);
2714 if (cpus_empty(tmp
))
2717 if (assign_irq_vector(irq
, mask
))
2720 cpus_and(tmp
, cfg
->domain
, mask
);
2721 dest
= cpu_mask_to_apicid(tmp
);
2723 target_ht_irq(irq
, dest
, cfg
->vector
);
2724 irq_desc
[irq
].affinity
= mask
;
2728 static struct irq_chip ht_irq_chip
= {
2730 .mask
= mask_ht_irq
,
2731 .unmask
= unmask_ht_irq
,
2732 .ack
= ack_apic_edge
,
2734 .set_affinity
= set_ht_irq_affinity
,
2736 .retrigger
= ioapic_retrigger_irq
,
2739 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2741 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2746 err
= assign_irq_vector(irq
, tmp
);
2748 struct ht_irq_msg msg
;
2751 cpus_and(tmp
, cfg
->domain
, tmp
);
2752 dest
= cpu_mask_to_apicid(tmp
);
2754 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2758 HT_IRQ_LOW_DEST_ID(dest
) |
2759 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
2760 ((INT_DEST_MODE
== 0) ?
2761 HT_IRQ_LOW_DM_PHYSICAL
:
2762 HT_IRQ_LOW_DM_LOGICAL
) |
2763 HT_IRQ_LOW_RQEOI_EDGE
|
2764 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2765 HT_IRQ_LOW_MT_FIXED
:
2766 HT_IRQ_LOW_MT_ARBITRATED
) |
2767 HT_IRQ_LOW_IRQ_MASKED
;
2769 write_ht_irq_msg(irq
, &msg
);
2771 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2772 handle_edge_irq
, "edge");
2776 #endif /* CONFIG_HT_IRQ */
2778 /* --------------------------------------------------------------------------
2779 ACPI-based IOAPIC Configuration
2780 -------------------------------------------------------------------------- */
2784 #define IO_APIC_MAX_ID 0xFE
2786 int __init
io_apic_get_redir_entries (int ioapic
)
2788 union IO_APIC_reg_01 reg_01
;
2789 unsigned long flags
;
2791 spin_lock_irqsave(&ioapic_lock
, flags
);
2792 reg_01
.raw
= io_apic_read(ioapic
, 1);
2793 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2795 return reg_01
.bits
.entries
;
2799 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
2801 if (!IO_APIC_IRQ(irq
)) {
2802 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2808 * IRQs < 16 are already in the irq_2_pin[] map
2811 add_pin_to_irq(irq
, ioapic
, pin
);
2813 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
2819 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2823 if (skip_ioapic_setup
)
2826 for (i
= 0; i
< mp_irq_entries
; i
++)
2827 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
2828 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
2830 if (i
>= mp_irq_entries
)
2833 *trigger
= irq_trigger(i
);
2834 *polarity
= irq_polarity(i
);
2838 #endif /* CONFIG_ACPI */
2841 * This function currently is only a helper for the i386 smp boot process where
2842 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2843 * so mask in all cases should simply be TARGET_CPUS
2846 void __init
setup_ioapic_dest(void)
2848 int pin
, ioapic
, irq
, irq_entry
;
2850 if (skip_ioapic_setup
== 1)
2853 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
2854 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
2855 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
2856 if (irq_entry
== -1)
2858 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
2860 /* setup_IO_APIC_irqs could fail to get vector for some device
2861 * when you have too many devices, because at that time only boot
2864 if (!irq_cfg
[irq
].vector
)
2865 setup_IO_APIC_irq(ioapic
, pin
, irq
,
2866 irq_trigger(irq_entry
),
2867 irq_polarity(irq_entry
));
2868 #ifdef CONFIG_INTR_REMAP
2869 else if (intr_remapping_enabled
)
2870 set_ir_ioapic_affinity_irq(irq
, TARGET_CPUS
);
2873 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
2880 #define IOAPIC_RESOURCE_NAME_SIZE 11
2882 static struct resource
*ioapic_resources
;
2884 static struct resource
* __init
ioapic_setup_resources(void)
2887 struct resource
*res
;
2891 if (nr_ioapics
<= 0)
2894 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
2897 mem
= alloc_bootmem(n
);
2901 mem
+= sizeof(struct resource
) * nr_ioapics
;
2903 for (i
= 0; i
< nr_ioapics
; i
++) {
2905 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
2906 sprintf(mem
, "IOAPIC %u", i
);
2907 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
2911 ioapic_resources
= res
;
2916 void __init
ioapic_init_mappings(void)
2918 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2919 struct resource
*ioapic_res
;
2922 ioapic_res
= ioapic_setup_resources();
2923 for (i
= 0; i
< nr_ioapics
; i
++) {
2924 if (smp_found_config
) {
2925 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
2927 ioapic_phys
= (unsigned long)
2928 alloc_bootmem_pages(PAGE_SIZE
);
2929 ioapic_phys
= __pa(ioapic_phys
);
2931 set_fixmap_nocache(idx
, ioapic_phys
);
2932 apic_printk(APIC_VERBOSE
,
2933 "mapped IOAPIC to %016lx (%016lx)\n",
2934 __fix_to_virt(idx
), ioapic_phys
);
2937 if (ioapic_res
!= NULL
) {
2938 ioapic_res
->start
= ioapic_phys
;
2939 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
2945 static int __init
ioapic_insert_resources(void)
2948 struct resource
*r
= ioapic_resources
;
2952 "IO APIC resources could be not be allocated.\n");
2956 for (i
= 0; i
< nr_ioapics
; i
++) {
2957 insert_resource(&iomem_resource
, r
);
2964 /* Insert the IO APIC resources after PCI initialization has occured to handle
2965 * IO APICS that are mapped in on a BAR in PCI space. */
2966 late_initcall(ioapic_insert_resources
);