arch/x86/kernel/microcode_amd.c

   1 /*
   2  *  AMD CPU Microcode Update Driver for Linux
   3  *  Copyright (C) 2008-2011 Advanced Micro Devices Inc.
   4  *
   5  *  Author: Peter Oruba <peter.oruba@amd.com>
   6  *
   7  *  Based on work by:
   8  *  Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
   9  *
  10  *  Maintainers:
  11  *  Andreas Herrmann <herrmann.der.user@googlemail.com>
  12  *  Borislav Petkov <bp@alien8.de>
  13  *
  14  *  This driver allows to upgrade microcode on F10h AMD
  15  *  CPUs and later.
  16  *
  17  *  Licensed under the terms of the GNU General Public
  18  *  License version 2. See file COPYING for details.
  19  */
  20
  21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22
  23 #include <linux/firmware.h>
  24 #include <linux/pci_ids.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/pci.h>
  30
  31 #include <asm/microcode.h>
  32 #include <asm/processor.h>
  33 #include <asm/msr.h>
  34
  35 MODULE_DESCRIPTION("AMD Microcode Update Driver");
  36 MODULE_AUTHOR("Peter Oruba");
  37 MODULE_LICENSE("GPL v2");
  38
  39 #define UCODE_MAGIC                0x00414d44
  40 #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
  41 #define UCODE_UCODE_TYPE           0x00000001
  42
  43 struct equiv_cpu_entry {
  44         u32     installed_cpu;
  45         u32     fixed_errata_mask;
  46         u32     fixed_errata_compare;
  47         u16     equiv_cpu;
  48         u16     res;
  49 } __attribute__((packed));
  50
  51 struct microcode_header_amd {
  52         u32     data_code;
  53         u32     patch_id;
  54         u16     mc_patch_data_id;
  55         u8      mc_patch_data_len;
  56         u8      init_flag;
  57         u32     mc_patch_data_checksum;
  58         u32     nb_dev_id;
  59         u32     sb_dev_id;
  60         u16     processor_rev_id;
  61         u8      nb_rev_id;
  62         u8      sb_rev_id;
  63         u8      bios_api_rev;
  64         u8      reserved1[3];
  65         u32     match_reg[8];
  66 } __attribute__((packed));
  67
  68 struct microcode_amd {
  69         struct microcode_header_amd     hdr;
  70         unsigned int                    mpb[0];
  71 };
  72
  73 #define SECTION_HDR_SIZE        8
  74 #define CONTAINER_HDR_SZ        12
  75
  76 static struct equiv_cpu_entry *equiv_cpu_table;
  77
  78 struct ucode_patch {
  79         struct list_head plist;
  80         void *data;
  81         u32 patch_id;
  82         u16 equiv_cpu;
  83 };
  84
  85 static LIST_HEAD(pcache);
  86
  87 static u16 find_equiv_id(unsigned int cpu)
  88 {
  89         struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
  90         int i = 0;
  91
  92         if (!equiv_cpu_table)
  93                 return 0;
  94
  95         while (equiv_cpu_table[i].installed_cpu != 0) {
  96                 if (uci->cpu_sig.sig == equiv_cpu_table[i].installed_cpu)
  97                         return equiv_cpu_table[i].equiv_cpu;
  98
  99                 i++;
 100         }
 101         return 0;
 102 }
 103
 104 static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
 105 {
 106         int i = 0;
 107
 108         BUG_ON(!equiv_cpu_table);
 109
 110         while (equiv_cpu_table[i].equiv_cpu != 0) {
 111                 if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
 112                         return equiv_cpu_table[i].installed_cpu;
 113                 i++;
 114         }
 115         return 0;
 116 }
 117
 118 /*
 119  * a small, trivial cache of per-family ucode patches
 120  */
 121 static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
 122 {
 123         struct ucode_patch *p;
 124
 125         list_for_each_entry(p, &pcache, plist)
 126                 if (p->equiv_cpu == equiv_cpu)
 127                         return p;
 128         return NULL;
 129 }
 130
 131 static void update_cache(struct ucode_patch *new_patch)
 132 {
 133         struct ucode_patch *p;
 134
 135         list_for_each_entry(p, &pcache, plist) {
 136                 if (p->equiv_cpu == new_patch->equiv_cpu) {
 137                         if (p->patch_id >= new_patch->patch_id)
 138                                 /* we already have the latest patch */
 139                                 return;
 140
 141                         list_replace(&p->plist, &new_patch->plist);
 142                         kfree(p->data);
 143                         kfree(p);
 144                         return;
 145                 }
 146         }
 147         /* no patch found, add it */
 148         list_add_tail(&new_patch->plist, &pcache);
 149 }
 150
 151 static void free_cache(void)
 152 {
 153         struct ucode_patch *p, *tmp;
 154
 155         list_for_each_entry_safe(p, tmp, &pcache, plist) {
 156                 __list_del(p->plist.prev, p->plist.next);
 157                 kfree(p->data);
 158                 kfree(p);
 159         }
 160 }
 161
 162 static struct ucode_patch *find_patch(unsigned int cpu)
 163 {
 164         u16 equiv_id;
 165
 166         equiv_id = find_equiv_id(cpu);
 167         if (!equiv_id)
 168                 return NULL;
 169
 170         return cache_find_patch(equiv_id);
 171 }
 172
 173 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
 174 {
 175         struct cpuinfo_x86 *c = &cpu_data(cpu);
 176
 177         csig->sig = cpuid_eax(0x00000001);
 178         csig->rev = c->microcode;
 179         pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
 180
 181         return 0;
 182 }
 183
 184 static unsigned int verify_patch_size(int cpu, u32 patch_size,
 185                                       unsigned int size)
 186 {
 187         struct cpuinfo_x86 *c = &cpu_data(cpu);
 188         u32 max_size;
 189
 190 #define F1XH_MPB_MAX_SIZE 2048
 191 #define F14H_MPB_MAX_SIZE 1824
 192 #define F15H_MPB_MAX_SIZE 4096
 193 #define F16H_MPB_MAX_SIZE 3458
 194
 195         switch (c->x86) {
 196         case 0x14:
 197                 max_size = F14H_MPB_MAX_SIZE;
 198                 break;
 199         case 0x15:
 200                 max_size = F15H_MPB_MAX_SIZE;
 201                 break;
 202         case 0x16:
 203                 max_size = F16H_MPB_MAX_SIZE;
 204                 break;
 205         default:
 206                 max_size = F1XH_MPB_MAX_SIZE;
 207                 break;
 208         }
 209
 210         if (patch_size > min_t(u32, size, max_size)) {
 211                 pr_err("patch size mismatch\n");
 212                 return 0;
 213         }
 214
 215         return patch_size;
 216 }
 217
 218 static int apply_microcode_amd(int cpu)
 219 {
 220         struct cpuinfo_x86 *c = &cpu_data(cpu);
 221         struct microcode_amd *mc_amd;
 222         struct ucode_cpu_info *uci;
 223         struct ucode_patch *p;
 224         u32 rev, dummy;
 225
 226         BUG_ON(raw_smp_processor_id() != cpu);
 227
 228         uci = ucode_cpu_info + cpu;
 229
 230         p = find_patch(cpu);
 231         if (!p)
 232                 return 0;
 233
 234         mc_amd  = p->data;
 235         uci->mc = p->data;
 236
 237         rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
 238
 239         /* need to apply patch? */
 240         if (rev >= mc_amd->hdr.patch_id) {
 241                 c->microcode = rev;
 242                 return 0;
 243         }
 244
 245         wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
 246
 247         /* verify patch application was successful */
 248         rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
 249         if (rev != mc_amd->hdr.patch_id) {
 250                 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
 251                        cpu, mc_amd->hdr.patch_id);
 252                 return -1;
 253         }
 254
 255         pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
 256         uci->cpu_sig.rev = rev;
 257         c->microcode = rev;
 258
 259         return 0;
 260 }
 261
 262 static int install_equiv_cpu_table(const u8 *buf)
 263 {
 264         unsigned int *ibuf = (unsigned int *)buf;
 265         unsigned int type = ibuf[1];
 266         unsigned int size = ibuf[2];
 267
 268         if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
 269                 pr_err("empty section/"
 270                        "invalid type field in container file section header\n");
 271                 return -EINVAL;
 272         }
 273
 274         equiv_cpu_table = vmalloc(size);
 275         if (!equiv_cpu_table) {
 276                 pr_err("failed to allocate equivalent CPU table\n");
 277                 return -ENOMEM;
 278         }
 279
 280         memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
 281
 282         /* add header length */
 283         return size + CONTAINER_HDR_SZ;
 284 }
 285
 286 static void free_equiv_cpu_table(void)
 287 {
 288         vfree(equiv_cpu_table);
 289         equiv_cpu_table = NULL;
 290 }
 291
 292 static void cleanup(void)
 293 {
 294         free_equiv_cpu_table();
 295         free_cache();
 296 }
 297
 298 /*
 299  * We return the current size even if some of the checks failed so that
 300  * we can skip over the next patch. If we return a negative value, we
 301  * signal a grave error like a memory allocation has failed and the
 302  * driver cannot continue functioning normally. In such cases, we tear
 303  * down everything we've used up so far and exit.
 304  */
 305 static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover)
 306 {
 307         struct cpuinfo_x86 *c = &cpu_data(cpu);
 308         struct microcode_header_amd *mc_hdr;
 309         struct ucode_patch *patch;
 310         unsigned int patch_size, crnt_size, ret;
 311         u32 proc_fam;
 312         u16 proc_id;
 313
 314         patch_size  = *(u32 *)(fw + 4);
 315         crnt_size   = patch_size + SECTION_HDR_SIZE;
 316         mc_hdr      = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
 317         proc_id     = mc_hdr->processor_rev_id;
 318
 319         proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
 320         if (!proc_fam) {
 321                 pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
 322                 return crnt_size;
 323         }
 324
 325         /* check if patch is for the current family */
 326         proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
 327         if (proc_fam != c->x86)
 328                 return crnt_size;
 329
 330         if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
 331                 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
 332                         mc_hdr->patch_id);
 333                 return crnt_size;
 334         }
 335
 336         ret = verify_patch_size(cpu, patch_size, leftover);
 337         if (!ret) {
 338                 pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
 339                 return crnt_size;
 340         }
 341
 342         patch = kzalloc(sizeof(*patch), GFP_KERNEL);
 343         if (!patch) {
 344                 pr_err("Patch allocation failure.\n");
 345                 return -EINVAL;
 346         }
 347
 348         patch->data = kzalloc(patch_size, GFP_KERNEL);
 349         if (!patch->data) {
 350                 pr_err("Patch data allocation failure.\n");
 351                 kfree(patch);
 352                 return -EINVAL;
 353         }
 354
 355         /* All looks ok, copy patch... */
 356         memcpy(patch->data, fw + SECTION_HDR_SIZE, patch_size);
 357         INIT_LIST_HEAD(&patch->plist);
 358         patch->patch_id  = mc_hdr->patch_id;
 359         patch->equiv_cpu = proc_id;
 360
 361         /* ... and add to cache. */
 362         update_cache(patch);
 363
 364         return crnt_size;
 365 }
 366
 367 static enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
 368 {
 369         enum ucode_state ret = UCODE_ERROR;
 370         unsigned int leftover;
 371         u8 *fw = (u8 *)data;
 372         int crnt_size = 0;
 373         int offset;
 374
 375         offset = install_equiv_cpu_table(data);
 376         if (offset < 0) {
 377                 pr_err("failed to create equivalent cpu table\n");
 378                 return ret;
 379         }
 380         fw += offset;
 381         leftover = size - offset;
 382
 383         if (*(u32 *)fw != UCODE_UCODE_TYPE) {
 384                 pr_err("invalid type field in container file section header\n");
 385                 free_equiv_cpu_table();
 386                 return ret;
 387         }
 388
 389         while (leftover) {
 390                 crnt_size = verify_and_add_patch(cpu, fw, leftover);
 391                 if (crnt_size < 0)
 392                         return ret;
 393
 394                 fw       += crnt_size;
 395                 leftover -= crnt_size;
 396         }
 397
 398         return UCODE_OK;
 399 }
 400
 401 /*
 402  * AMD microcode firmware naming convention, up to family 15h they are in
 403  * the legacy file:
 404  *
 405  *    amd-ucode/microcode_amd.bin
 406  *
 407  * This legacy file is always smaller than 2K in size.
 408  *
 409  * Beginning with family 15h, they are in family-specific firmware files:
 410  *
 411  *    amd-ucode/microcode_amd_fam15h.bin
 412  *    amd-ucode/microcode_amd_fam16h.bin
 413  *    ...
 414  *
 415  * These might be larger than 2K.
 416  */
 417 static enum ucode_state request_microcode_amd(int cpu, struct device *device,
 418                                               bool refresh_fw)
 419 {
 420         char fw_name[36] = "amd-ucode/microcode_amd.bin";
 421         struct cpuinfo_x86 *c = &cpu_data(cpu);
 422         enum ucode_state ret = UCODE_NFOUND;
 423         const struct firmware *fw;
 424
 425         /* reload ucode container only on the boot cpu */
 426         if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index)
 427                 return UCODE_OK;
 428
 429         if (c->x86 >= 0x15)
 430                 snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
 431
 432         if (request_firmware(&fw, (const char *)fw_name, device)) {
 433                 pr_err("failed to load file %s\n", fw_name);
 434                 goto out;
 435         }
 436
 437         ret = UCODE_ERROR;
 438         if (*(u32 *)fw->data != UCODE_MAGIC) {
 439                 pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
 440                 goto fw_release;
 441         }
 442
 443         /* free old equiv table */
 444         free_equiv_cpu_table();
 445
 446         ret = load_microcode_amd(cpu, fw->data, fw->size);
 447         if (ret != UCODE_OK)
 448                 cleanup();
 449
 450  fw_release:
 451         release_firmware(fw);
 452
 453  out:
 454         return ret;
 455 }
 456
 457 static enum ucode_state
 458 request_microcode_user(int cpu, const void __user *buf, size_t size)
 459 {
 460         return UCODE_ERROR;
 461 }
 462
 463 static void microcode_fini_cpu_amd(int cpu)
 464 {
 465         struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
 466
 467         uci->mc = NULL;
 468 }
 469
 470 static struct microcode_ops microcode_amd_ops = {
 471         .request_microcode_user           = request_microcode_user,
 472         .request_microcode_fw             = request_microcode_amd,
 473         .collect_cpu_info                 = collect_cpu_info_amd,
 474         .apply_microcode                  = apply_microcode_amd,
 475         .microcode_fini_cpu               = microcode_fini_cpu_amd,
 476 };
 477
 478 struct microcode_ops * __init init_amd_microcode(void)
 479 {
 480         struct cpuinfo_x86 *c = &cpu_data(0);
 481
 482         if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
 483                 pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
 484                 return NULL;
 485         }
 486
 487         return &microcode_amd_ops;
 488 }
 489
 490 void __exit exit_amd_microcode(void)
 491 {
 492         cleanup();
 493 }