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x86, 32-bit: trim memory not covered by wb mtrrs
[deliverable/linux.git] / arch / x86 / kernel / mpparse_64.c
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/bootmem.h>
20 #include <linux/kernel_stat.h>
21 #include <linux/mc146818rtc.h>
22 #include <linux/acpi.h>
23 #include <linux/module.h>
24
25 #include <asm/smp.h>
26 #include <asm/mtrr.h>
27 #include <asm/mpspec.h>
28 #include <asm/pgalloc.h>
29 #include <asm/io_apic.h>
30 #include <asm/proto.h>
31 #include <asm/acpi.h>
32
33 /* Have we found an MP table */
34 int smp_found_config;
35
36 /*
37 * Various Linux-internal data structures created from the
38 * MP-table.
39 */
40 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
41 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
42
43 static int mp_current_pci_id = 0;
44 /* I/O APIC entries */
45 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
46
47 /* # of MP IRQ source entries */
48 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
49
50 /* MP IRQ source entries */
51 int mp_irq_entries;
52
53 int nr_ioapics;
54 unsigned long mp_lapic_addr = 0;
55
56
57
58 /* Processor that is doing the boot up */
59 unsigned int boot_cpu_id = -1U;
60 EXPORT_SYMBOL(boot_cpu_id);
61
62 /* Internal processor count */
63 unsigned int num_processors __cpuinitdata = 0;
64
65 unsigned disabled_cpus __cpuinitdata;
66
67 /* Bitmask of physically existing CPUs */
68 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
69
70 u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata
71 = { [0 ... NR_CPUS-1] = BAD_APICID };
72 void *x86_bios_cpu_apicid_early_ptr;
73 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
74 EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
75
76
77 /*
78 * Intel MP BIOS table parsing routines:
79 */
80
81 /*
82 * Checksum an MP configuration block.
83 */
84
85 static int __init mpf_checksum(unsigned char *mp, int len)
86 {
87 int sum = 0;
88
89 while (len--)
90 sum += *mp++;
91
92 return sum & 0xFF;
93 }
94
95 static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
96 {
97 int cpu;
98 cpumask_t tmp_map;
99 char *bootup_cpu = "";
100
101 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
102 disabled_cpus++;
103 return;
104 }
105 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
106 bootup_cpu = " (Bootup-CPU)";
107 boot_cpu_id = m->mpc_apicid;
108 }
109
110 printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu);
111
112 if (num_processors >= NR_CPUS) {
113 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
114 " Processor ignored.\n", NR_CPUS);
115 return;
116 }
117
118 num_processors++;
119 cpus_complement(tmp_map, cpu_present_map);
120 cpu = first_cpu(tmp_map);
121
122 physid_set(m->mpc_apicid, phys_cpu_present_map);
123 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
124 /*
125 * x86_bios_cpu_apicid is required to have processors listed
126 * in same order as logical cpu numbers. Hence the first
127 * entry is BSP, and so on.
128 */
129 cpu = 0;
130 }
131 /* are we being called early in kernel startup? */
132 if (x86_cpu_to_apicid_early_ptr) {
133 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
134 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
135
136 cpu_to_apicid[cpu] = m->mpc_apicid;
137 bios_cpu_apicid[cpu] = m->mpc_apicid;
138 } else {
139 per_cpu(x86_cpu_to_apicid, cpu) = m->mpc_apicid;
140 per_cpu(x86_bios_cpu_apicid, cpu) = m->mpc_apicid;
141 }
142
143 cpu_set(cpu, cpu_possible_map);
144 cpu_set(cpu, cpu_present_map);
145 }
146
147 static void __init MP_bus_info (struct mpc_config_bus *m)
148 {
149 char str[7];
150
151 memcpy(str, m->mpc_bustype, 6);
152 str[6] = 0;
153 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
154
155 if (strncmp(str, "ISA", 3) == 0) {
156 set_bit(m->mpc_busid, mp_bus_not_pci);
157 } else if (strncmp(str, "PCI", 3) == 0) {
158 clear_bit(m->mpc_busid, mp_bus_not_pci);
159 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
160 mp_current_pci_id++;
161 } else {
162 printk(KERN_ERR "Unknown bustype %s\n", str);
163 }
164 }
165
166 static int bad_ioapic(unsigned long address)
167 {
168 if (nr_ioapics >= MAX_IO_APICS) {
169 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
170 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
171 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
172 }
173 if (!address) {
174 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
175 " found in table, skipping!\n");
176 return 1;
177 }
178 return 0;
179 }
180
181 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
182 {
183 if (!(m->mpc_flags & MPC_APIC_USABLE))
184 return;
185
186 printk("I/O APIC #%d at 0x%X.\n",
187 m->mpc_apicid, m->mpc_apicaddr);
188
189 if (bad_ioapic(m->mpc_apicaddr))
190 return;
191
192 mp_ioapics[nr_ioapics] = *m;
193 nr_ioapics++;
194 }
195
196 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
197 {
198 mp_irqs [mp_irq_entries] = *m;
199 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
200 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
201 m->mpc_irqtype, m->mpc_irqflag & 3,
202 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
203 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
204 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
205 panic("Max # of irq sources exceeded!!\n");
206 }
207
208 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
209 {
210 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
211 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
212 m->mpc_irqtype, m->mpc_irqflag & 3,
213 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
214 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
215 }
216
217 /*
218 * Read/parse the MPC
219 */
220
221 static int __init smp_read_mpc(struct mp_config_table *mpc)
222 {
223 char str[16];
224 int count=sizeof(*mpc);
225 unsigned char *mpt=((unsigned char *)mpc)+count;
226
227 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
228 printk("MPTABLE: bad signature [%c%c%c%c]!\n",
229 mpc->mpc_signature[0],
230 mpc->mpc_signature[1],
231 mpc->mpc_signature[2],
232 mpc->mpc_signature[3]);
233 return 0;
234 }
235 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
236 printk("MPTABLE: checksum error!\n");
237 return 0;
238 }
239 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
240 printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n",
241 mpc->mpc_spec);
242 return 0;
243 }
244 if (!mpc->mpc_lapic) {
245 printk(KERN_ERR "MPTABLE: null local APIC address!\n");
246 return 0;
247 }
248 memcpy(str,mpc->mpc_oem,8);
249 str[8] = 0;
250 printk(KERN_INFO "MPTABLE: OEM ID: %s ",str);
251
252 memcpy(str,mpc->mpc_productid,12);
253 str[12] = 0;
254 printk("MPTABLE: Product ID: %s ",str);
255
256 printk("MPTABLE: APIC at: 0x%X\n",mpc->mpc_lapic);
257
258 /* save the local APIC address, it might be non-default */
259 if (!acpi_lapic)
260 mp_lapic_addr = mpc->mpc_lapic;
261
262 /*
263 * Now process the configuration blocks.
264 */
265 while (count < mpc->mpc_length) {
266 switch(*mpt) {
267 case MP_PROCESSOR:
268 {
269 struct mpc_config_processor *m=
270 (struct mpc_config_processor *)mpt;
271 if (!acpi_lapic)
272 MP_processor_info(m);
273 mpt += sizeof(*m);
274 count += sizeof(*m);
275 break;
276 }
277 case MP_BUS:
278 {
279 struct mpc_config_bus *m=
280 (struct mpc_config_bus *)mpt;
281 MP_bus_info(m);
282 mpt += sizeof(*m);
283 count += sizeof(*m);
284 break;
285 }
286 case MP_IOAPIC:
287 {
288 struct mpc_config_ioapic *m=
289 (struct mpc_config_ioapic *)mpt;
290 MP_ioapic_info(m);
291 mpt += sizeof(*m);
292 count += sizeof(*m);
293 break;
294 }
295 case MP_INTSRC:
296 {
297 struct mpc_config_intsrc *m=
298 (struct mpc_config_intsrc *)mpt;
299
300 MP_intsrc_info(m);
301 mpt += sizeof(*m);
302 count += sizeof(*m);
303 break;
304 }
305 case MP_LINTSRC:
306 {
307 struct mpc_config_lintsrc *m=
308 (struct mpc_config_lintsrc *)mpt;
309 MP_lintsrc_info(m);
310 mpt += sizeof(*m);
311 count += sizeof(*m);
312 break;
313 }
314 }
315 }
316 setup_apic_routing();
317 if (!num_processors)
318 printk(KERN_ERR "MPTABLE: no processors registered!\n");
319 return num_processors;
320 }
321
322 static int __init ELCR_trigger(unsigned int irq)
323 {
324 unsigned int port;
325
326 port = 0x4d0 + (irq >> 3);
327 return (inb(port) >> (irq & 7)) & 1;
328 }
329
330 static void __init construct_default_ioirq_mptable(int mpc_default_type)
331 {
332 struct mpc_config_intsrc intsrc;
333 int i;
334 int ELCR_fallback = 0;
335
336 intsrc.mpc_type = MP_INTSRC;
337 intsrc.mpc_irqflag = 0; /* conforming */
338 intsrc.mpc_srcbus = 0;
339 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
340
341 intsrc.mpc_irqtype = mp_INT;
342
343 /*
344 * If true, we have an ISA/PCI system with no IRQ entries
345 * in the MP table. To prevent the PCI interrupts from being set up
346 * incorrectly, we try to use the ELCR. The sanity check to see if
347 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
348 * never be level sensitive, so we simply see if the ELCR agrees.
349 * If it does, we assume it's valid.
350 */
351 if (mpc_default_type == 5) {
352 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
353
354 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
355 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
356 else {
357 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
358 ELCR_fallback = 1;
359 }
360 }
361
362 for (i = 0; i < 16; i++) {
363 switch (mpc_default_type) {
364 case 2:
365 if (i == 0 || i == 13)
366 continue; /* IRQ0 & IRQ13 not connected */
367 /* fall through */
368 default:
369 if (i == 2)
370 continue; /* IRQ2 is never connected */
371 }
372
373 if (ELCR_fallback) {
374 /*
375 * If the ELCR indicates a level-sensitive interrupt, we
376 * copy that information over to the MP table in the
377 * irqflag field (level sensitive, active high polarity).
378 */
379 if (ELCR_trigger(i))
380 intsrc.mpc_irqflag = 13;
381 else
382 intsrc.mpc_irqflag = 0;
383 }
384
385 intsrc.mpc_srcbusirq = i;
386 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
387 MP_intsrc_info(&intsrc);
388 }
389
390 intsrc.mpc_irqtype = mp_ExtINT;
391 intsrc.mpc_srcbusirq = 0;
392 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
393 MP_intsrc_info(&intsrc);
394 }
395
396 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
397 {
398 struct mpc_config_processor processor;
399 struct mpc_config_bus bus;
400 struct mpc_config_ioapic ioapic;
401 struct mpc_config_lintsrc lintsrc;
402 int linttypes[2] = { mp_ExtINT, mp_NMI };
403 int i;
404
405 /*
406 * local APIC has default address
407 */
408 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
409
410 /*
411 * 2 CPUs, numbered 0 & 1.
412 */
413 processor.mpc_type = MP_PROCESSOR;
414 processor.mpc_apicver = 0;
415 processor.mpc_cpuflag = CPU_ENABLED;
416 processor.mpc_cpufeature = 0;
417 processor.mpc_featureflag = 0;
418 processor.mpc_reserved[0] = 0;
419 processor.mpc_reserved[1] = 0;
420 for (i = 0; i < 2; i++) {
421 processor.mpc_apicid = i;
422 MP_processor_info(&processor);
423 }
424
425 bus.mpc_type = MP_BUS;
426 bus.mpc_busid = 0;
427 switch (mpc_default_type) {
428 default:
429 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
430 mpc_default_type);
431 /* fall through */
432 case 1:
433 case 5:
434 memcpy(bus.mpc_bustype, "ISA ", 6);
435 break;
436 }
437 MP_bus_info(&bus);
438 if (mpc_default_type > 4) {
439 bus.mpc_busid = 1;
440 memcpy(bus.mpc_bustype, "PCI ", 6);
441 MP_bus_info(&bus);
442 }
443
444 ioapic.mpc_type = MP_IOAPIC;
445 ioapic.mpc_apicid = 2;
446 ioapic.mpc_apicver = 0;
447 ioapic.mpc_flags = MPC_APIC_USABLE;
448 ioapic.mpc_apicaddr = 0xFEC00000;
449 MP_ioapic_info(&ioapic);
450
451 /*
452 * We set up most of the low 16 IO-APIC pins according to MPS rules.
453 */
454 construct_default_ioirq_mptable(mpc_default_type);
455
456 lintsrc.mpc_type = MP_LINTSRC;
457 lintsrc.mpc_irqflag = 0; /* conforming */
458 lintsrc.mpc_srcbusid = 0;
459 lintsrc.mpc_srcbusirq = 0;
460 lintsrc.mpc_destapic = MP_APIC_ALL;
461 for (i = 0; i < 2; i++) {
462 lintsrc.mpc_irqtype = linttypes[i];
463 lintsrc.mpc_destapiclint = i;
464 MP_lintsrc_info(&lintsrc);
465 }
466 }
467
468 static struct intel_mp_floating *mpf_found;
469
470 /*
471 * Scan the memory blocks for an SMP configuration block.
472 */
473 void __init get_smp_config (void)
474 {
475 struct intel_mp_floating *mpf = mpf_found;
476
477 /*
478 * ACPI supports both logical (e.g. Hyper-Threading) and physical
479 * processors, where MPS only supports physical.
480 */
481 if (acpi_lapic && acpi_ioapic) {
482 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
483 return;
484 }
485 else if (acpi_lapic)
486 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
487
488 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
489
490 /*
491 * Now see if we need to read further.
492 */
493 if (mpf->mpf_feature1 != 0) {
494
495 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
496 construct_default_ISA_mptable(mpf->mpf_feature1);
497
498 } else if (mpf->mpf_physptr) {
499
500 /*
501 * Read the physical hardware table. Anything here will
502 * override the defaults.
503 */
504 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
505 smp_found_config = 0;
506 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
507 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
508 return;
509 }
510 /*
511 * If there are no explicit MP IRQ entries, then we are
512 * broken. We set up most of the low 16 IO-APIC pins to
513 * ISA defaults and hope it will work.
514 */
515 if (!mp_irq_entries) {
516 struct mpc_config_bus bus;
517
518 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
519
520 bus.mpc_type = MP_BUS;
521 bus.mpc_busid = 0;
522 memcpy(bus.mpc_bustype, "ISA ", 6);
523 MP_bus_info(&bus);
524
525 construct_default_ioirq_mptable(0);
526 }
527
528 } else
529 BUG();
530
531 printk(KERN_INFO "Processors: %d\n", num_processors);
532 /*
533 * Only use the first configuration found.
534 */
535 }
536
537 static int __init smp_scan_config (unsigned long base, unsigned long length)
538 {
539 extern void __bad_mpf_size(void);
540 unsigned int *bp = phys_to_virt(base);
541 struct intel_mp_floating *mpf;
542
543 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
544 if (sizeof(*mpf) != 16)
545 __bad_mpf_size();
546
547 while (length > 0) {
548 mpf = (struct intel_mp_floating *)bp;
549 if ((*bp == SMP_MAGIC_IDENT) &&
550 (mpf->mpf_length == 1) &&
551 !mpf_checksum((unsigned char *)bp, 16) &&
552 ((mpf->mpf_specification == 1)
553 || (mpf->mpf_specification == 4)) ) {
554
555 smp_found_config = 1;
556 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
557 if (mpf->mpf_physptr)
558 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
559 mpf_found = mpf;
560 return 1;
561 }
562 bp += 4;
563 length -= 16;
564 }
565 return 0;
566 }
567
568 void __init find_smp_config(void)
569 {
570 unsigned int address;
571
572 /*
573 * FIXME: Linux assumes you have 640K of base ram..
574 * this continues the error...
575 *
576 * 1) Scan the bottom 1K for a signature
577 * 2) Scan the top 1K of base RAM
578 * 3) Scan the 64K of bios
579 */
580 if (smp_scan_config(0x0,0x400) ||
581 smp_scan_config(639*0x400,0x400) ||
582 smp_scan_config(0xF0000,0x10000))
583 return;
584 /*
585 * If it is an SMP machine we should know now.
586 *
587 * there is a real-mode segmented pointer pointing to the
588 * 4K EBDA area at 0x40E, calculate and scan it here.
589 *
590 * NOTE! There are Linux loaders that will corrupt the EBDA
591 * area, and as such this kind of SMP config may be less
592 * trustworthy, simply because the SMP table may have been
593 * stomped on during early boot. These loaders are buggy and
594 * should be fixed.
595 */
596
597 address = *(unsigned short *)phys_to_virt(0x40E);
598 address <<= 4;
599 if (smp_scan_config(address, 0x1000))
600 return;
601
602 /* If we have come this far, we did not find an MP table */
603 printk(KERN_INFO "No mptable found.\n");
604 }
605
606 /* --------------------------------------------------------------------------
607 ACPI-based MP Configuration
608 -------------------------------------------------------------------------- */
609
610 #ifdef CONFIG_ACPI
611
612 void __init mp_register_lapic_address(u64 address)
613 {
614 mp_lapic_addr = (unsigned long) address;
615 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
616 if (boot_cpu_id == -1U)
617 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
618 }
619
620 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
621 {
622 struct mpc_config_processor processor;
623 int boot_cpu = 0;
624
625 if (id == boot_cpu_id)
626 boot_cpu = 1;
627
628 processor.mpc_type = MP_PROCESSOR;
629 processor.mpc_apicid = id;
630 processor.mpc_apicver = 0;
631 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
632 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
633 processor.mpc_cpufeature = 0;
634 processor.mpc_featureflag = 0;
635 processor.mpc_reserved[0] = 0;
636 processor.mpc_reserved[1] = 0;
637
638 MP_processor_info(&processor);
639 }
640
641 #define MP_ISA_BUS 0
642 #define MP_MAX_IOAPIC_PIN 127
643
644 static struct mp_ioapic_routing {
645 int apic_id;
646 int gsi_start;
647 int gsi_end;
648 u32 pin_programmed[4];
649 } mp_ioapic_routing[MAX_IO_APICS];
650
651 static int mp_find_ioapic(int gsi)
652 {
653 int i = 0;
654
655 /* Find the IOAPIC that manages this GSI. */
656 for (i = 0; i < nr_ioapics; i++) {
657 if ((gsi >= mp_ioapic_routing[i].gsi_start)
658 && (gsi <= mp_ioapic_routing[i].gsi_end))
659 return i;
660 }
661
662 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
663 return -1;
664 }
665
666 static u8 uniq_ioapic_id(u8 id)
667 {
668 int i;
669 DECLARE_BITMAP(used, 256);
670 bitmap_zero(used, 256);
671 for (i = 0; i < nr_ioapics; i++) {
672 struct mpc_config_ioapic *ia = &mp_ioapics[i];
673 __set_bit(ia->mpc_apicid, used);
674 }
675 if (!test_bit(id, used))
676 return id;
677 return find_first_zero_bit(used, 256);
678 }
679
680 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
681 {
682 int idx = 0;
683
684 if (bad_ioapic(address))
685 return;
686
687 idx = nr_ioapics;
688
689 mp_ioapics[idx].mpc_type = MP_IOAPIC;
690 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
691 mp_ioapics[idx].mpc_apicaddr = address;
692
693 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
694 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
695 mp_ioapics[idx].mpc_apicver = 0;
696
697 /*
698 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
699 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
700 */
701 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
702 mp_ioapic_routing[idx].gsi_start = gsi_base;
703 mp_ioapic_routing[idx].gsi_end = gsi_base +
704 io_apic_get_redir_entries(idx);
705
706 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, "
707 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
708 mp_ioapics[idx].mpc_apicaddr,
709 mp_ioapic_routing[idx].gsi_start,
710 mp_ioapic_routing[idx].gsi_end);
711
712 nr_ioapics++;
713 }
714
715 void __init
716 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
717 {
718 struct mpc_config_intsrc intsrc;
719 int ioapic = -1;
720 int pin = -1;
721
722 /*
723 * Convert 'gsi' to 'ioapic.pin'.
724 */
725 ioapic = mp_find_ioapic(gsi);
726 if (ioapic < 0)
727 return;
728 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
729
730 /*
731 * TBD: This check is for faulty timer entries, where the override
732 * erroneously sets the trigger to level, resulting in a HUGE
733 * increase of timer interrupts!
734 */
735 if ((bus_irq == 0) && (trigger == 3))
736 trigger = 1;
737
738 intsrc.mpc_type = MP_INTSRC;
739 intsrc.mpc_irqtype = mp_INT;
740 intsrc.mpc_irqflag = (trigger << 2) | polarity;
741 intsrc.mpc_srcbus = MP_ISA_BUS;
742 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
743 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
744 intsrc.mpc_dstirq = pin; /* INTIN# */
745
746 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
747 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
748 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
749 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
750
751 mp_irqs[mp_irq_entries] = intsrc;
752 if (++mp_irq_entries == MAX_IRQ_SOURCES)
753 panic("Max # of irq sources exceeded!\n");
754 }
755
756 void __init mp_config_acpi_legacy_irqs(void)
757 {
758 struct mpc_config_intsrc intsrc;
759 int i = 0;
760 int ioapic = -1;
761
762 /*
763 * Fabricate the legacy ISA bus (bus #31).
764 */
765 set_bit(MP_ISA_BUS, mp_bus_not_pci);
766
767 /*
768 * Locate the IOAPIC that manages the ISA IRQs (0-15).
769 */
770 ioapic = mp_find_ioapic(0);
771 if (ioapic < 0)
772 return;
773
774 intsrc.mpc_type = MP_INTSRC;
775 intsrc.mpc_irqflag = 0; /* Conforming */
776 intsrc.mpc_srcbus = MP_ISA_BUS;
777 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
778
779 /*
780 * Use the default configuration for the IRQs 0-15. Unless
781 * overridden by (MADT) interrupt source override entries.
782 */
783 for (i = 0; i < 16; i++) {
784 int idx;
785
786 for (idx = 0; idx < mp_irq_entries; idx++) {
787 struct mpc_config_intsrc *irq = mp_irqs + idx;
788
789 /* Do we already have a mapping for this ISA IRQ? */
790 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
791 break;
792
793 /* Do we already have a mapping for this IOAPIC pin */
794 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
795 (irq->mpc_dstirq == i))
796 break;
797 }
798
799 if (idx != mp_irq_entries) {
800 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
801 continue; /* IRQ already used */
802 }
803
804 intsrc.mpc_irqtype = mp_INT;
805 intsrc.mpc_srcbusirq = i; /* Identity mapped */
806 intsrc.mpc_dstirq = i;
807
808 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
809 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
810 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
811 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
812 intsrc.mpc_dstirq);
813
814 mp_irqs[mp_irq_entries] = intsrc;
815 if (++mp_irq_entries == MAX_IRQ_SOURCES)
816 panic("Max # of irq sources exceeded!\n");
817 }
818 }
819
820 int mp_register_gsi(u32 gsi, int triggering, int polarity)
821 {
822 int ioapic = -1;
823 int ioapic_pin = 0;
824 int idx, bit = 0;
825
826 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
827 return gsi;
828
829 /* Don't set up the ACPI SCI because it's already set up */
830 if (acpi_gbl_FADT.sci_interrupt == gsi)
831 return gsi;
832
833 ioapic = mp_find_ioapic(gsi);
834 if (ioapic < 0) {
835 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
836 return gsi;
837 }
838
839 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
840
841 /*
842 * Avoid pin reprogramming. PRTs typically include entries
843 * with redundant pin->gsi mappings (but unique PCI devices);
844 * we only program the IOAPIC on the first.
845 */
846 bit = ioapic_pin % 32;
847 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
848 if (idx > 3) {
849 printk(KERN_ERR "Invalid reference to IOAPIC pin "
850 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
851 ioapic_pin);
852 return gsi;
853 }
854 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
855 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
856 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
857 return gsi;
858 }
859
860 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
861
862 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
863 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
864 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
865 return gsi;
866 }
867 #endif /*CONFIG_ACPI*/
Linux kernel - Deliverables
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