2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 * Copyright (C) 2011 Don Zickus Red Hat, Inc.
6 * Pentium III FXSR, SSE support
7 * Gareth Hughes <gareth@valinux.com>, May 2000
11 * Handle hardware traps and faults.
13 #include <linux/spinlock.h>
14 #include <linux/kprobes.h>
15 #include <linux/kdebug.h>
16 #include <linux/nmi.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/hardirq.h>
20 #include <linux/slab.h>
21 #include <linux/export.h>
23 #if defined(CONFIG_EDAC)
24 #include <linux/edac.h>
27 #include <linux/atomic.h>
28 #include <asm/traps.h>
29 #include <asm/mach_traps.h>
31 #include <asm/x86_init.h>
33 #define CREATE_TRACE_POINTS
34 #include <trace/events/nmi.h>
38 struct list_head head
;
41 static struct nmi_desc nmi_desc
[NMI_MAX
] =
44 .lock
= __SPIN_LOCK_UNLOCKED(&nmi_desc
[0].lock
),
45 .head
= LIST_HEAD_INIT(nmi_desc
[0].head
),
48 .lock
= __SPIN_LOCK_UNLOCKED(&nmi_desc
[1].lock
),
49 .head
= LIST_HEAD_INIT(nmi_desc
[1].head
),
52 .lock
= __SPIN_LOCK_UNLOCKED(&nmi_desc
[2].lock
),
53 .head
= LIST_HEAD_INIT(nmi_desc
[2].head
),
56 .lock
= __SPIN_LOCK_UNLOCKED(&nmi_desc
[3].lock
),
57 .head
= LIST_HEAD_INIT(nmi_desc
[3].head
),
65 unsigned int external
;
69 static DEFINE_PER_CPU(struct nmi_stats
, nmi_stats
);
71 static int ignore_nmis
;
73 int unknown_nmi_panic
;
75 * Prevent NMI reason port (0x61) being accessed simultaneously, can
76 * only be used in NMI handler.
78 static DEFINE_RAW_SPINLOCK(nmi_reason_lock
);
80 static int __init
setup_unknown_nmi_panic(char *str
)
82 unknown_nmi_panic
= 1;
85 __setup("unknown_nmi_panic", setup_unknown_nmi_panic
);
87 #define nmi_to_desc(type) (&nmi_desc[type])
89 static u64 nmi_longest_ns
= 1 * NSEC_PER_MSEC
;
91 static int __init
nmi_warning_debugfs(void)
93 debugfs_create_u64("nmi_longest_ns", 0644,
94 arch_debugfs_dir
, &nmi_longest_ns
);
97 fs_initcall(nmi_warning_debugfs
);
99 static void nmi_max_handler(struct irq_work
*w
)
101 struct nmiaction
*a
= container_of(w
, struct nmiaction
, irq_work
);
102 int remainder_ns
, decimal_msecs
;
103 u64 whole_msecs
= ACCESS_ONCE(a
->max_duration
);
105 remainder_ns
= do_div(whole_msecs
, (1000 * 1000));
106 decimal_msecs
= remainder_ns
/ 1000;
108 printk_ratelimited(KERN_INFO
109 "INFO: NMI handler (%ps) took too long to run: %lld.%03d msecs\n",
110 a
->handler
, whole_msecs
, decimal_msecs
);
113 static int nmi_handle(unsigned int type
, struct pt_regs
*regs
, bool b2b
)
115 struct nmi_desc
*desc
= nmi_to_desc(type
);
122 * NMIs are edge-triggered, which means if you have enough
123 * of them concurrently, you can lose some because only one
124 * can be latched at any given time. Walk the whole list
125 * to handle those situations.
127 list_for_each_entry_rcu(a
, &desc
->head
, list
) {
131 delta
= sched_clock();
132 thishandled
= a
->handler(type
, regs
);
133 handled
+= thishandled
;
134 delta
= sched_clock() - delta
;
135 trace_nmi_handler(a
->handler
, (int)delta
, thishandled
);
137 if (delta
< nmi_longest_ns
|| delta
< a
->max_duration
)
140 a
->max_duration
= delta
;
141 irq_work_queue(&a
->irq_work
);
146 /* return total number of NMI events handled */
149 NOKPROBE_SYMBOL(nmi_handle
);
151 int __register_nmi_handler(unsigned int type
, struct nmiaction
*action
)
153 struct nmi_desc
*desc
= nmi_to_desc(type
);
156 if (!action
->handler
)
159 init_irq_work(&action
->irq_work
, nmi_max_handler
);
161 spin_lock_irqsave(&desc
->lock
, flags
);
164 * most handlers of type NMI_UNKNOWN never return because
165 * they just assume the NMI is theirs. Just a sanity check
166 * to manage expectations
168 WARN_ON_ONCE(type
== NMI_UNKNOWN
&& !list_empty(&desc
->head
));
169 WARN_ON_ONCE(type
== NMI_SERR
&& !list_empty(&desc
->head
));
170 WARN_ON_ONCE(type
== NMI_IO_CHECK
&& !list_empty(&desc
->head
));
173 * some handlers need to be executed first otherwise a fake
174 * event confuses some handlers (kdump uses this flag)
176 if (action
->flags
& NMI_FLAG_FIRST
)
177 list_add_rcu(&action
->list
, &desc
->head
);
179 list_add_tail_rcu(&action
->list
, &desc
->head
);
181 spin_unlock_irqrestore(&desc
->lock
, flags
);
184 EXPORT_SYMBOL(__register_nmi_handler
);
186 void unregister_nmi_handler(unsigned int type
, const char *name
)
188 struct nmi_desc
*desc
= nmi_to_desc(type
);
192 spin_lock_irqsave(&desc
->lock
, flags
);
194 list_for_each_entry_rcu(n
, &desc
->head
, list
) {
196 * the name passed in to describe the nmi handler
197 * is used as the lookup key
199 if (!strcmp(n
->name
, name
)) {
201 "Trying to free NMI (%s) from NMI context!\n", n
->name
);
202 list_del_rcu(&n
->list
);
207 spin_unlock_irqrestore(&desc
->lock
, flags
);
210 EXPORT_SYMBOL_GPL(unregister_nmi_handler
);
213 pci_serr_error(unsigned char reason
, struct pt_regs
*regs
)
215 /* check to see if anyone registered against these types of errors */
216 if (nmi_handle(NMI_SERR
, regs
, false))
219 pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
220 reason
, smp_processor_id());
223 * On some machines, PCI SERR line is used to report memory
224 * errors. EDAC makes use of it.
226 #if defined(CONFIG_EDAC)
227 if (edac_handler_set()) {
228 edac_atomic_assert_error();
233 if (panic_on_unrecovered_nmi
)
234 panic("NMI: Not continuing");
236 pr_emerg("Dazed and confused, but trying to continue\n");
238 /* Clear and disable the PCI SERR error line. */
239 reason
= (reason
& NMI_REASON_CLEAR_MASK
) | NMI_REASON_CLEAR_SERR
;
240 outb(reason
, NMI_REASON_PORT
);
242 NOKPROBE_SYMBOL(pci_serr_error
);
245 io_check_error(unsigned char reason
, struct pt_regs
*regs
)
249 /* check to see if anyone registered against these types of errors */
250 if (nmi_handle(NMI_IO_CHECK
, regs
, false))
254 "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
255 reason
, smp_processor_id());
259 panic("NMI IOCK error: Not continuing");
261 /* Re-enable the IOCK line, wait for a few seconds */
262 reason
= (reason
& NMI_REASON_CLEAR_MASK
) | NMI_REASON_CLEAR_IOCHK
;
263 outb(reason
, NMI_REASON_PORT
);
267 touch_nmi_watchdog();
271 reason
&= ~NMI_REASON_CLEAR_IOCHK
;
272 outb(reason
, NMI_REASON_PORT
);
274 NOKPROBE_SYMBOL(io_check_error
);
277 unknown_nmi_error(unsigned char reason
, struct pt_regs
*regs
)
282 * Use 'false' as back-to-back NMIs are dealt with one level up.
283 * Of course this makes having multiple 'unknown' handlers useless
284 * as only the first one is ever run (unless it can actually determine
285 * if it caused the NMI)
287 handled
= nmi_handle(NMI_UNKNOWN
, regs
, false);
289 __this_cpu_add(nmi_stats
.unknown
, handled
);
293 __this_cpu_add(nmi_stats
.unknown
, 1);
295 pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
296 reason
, smp_processor_id());
298 pr_emerg("Do you have a strange power saving mode enabled?\n");
299 if (unknown_nmi_panic
|| panic_on_unrecovered_nmi
)
300 panic("NMI: Not continuing");
302 pr_emerg("Dazed and confused, but trying to continue\n");
304 NOKPROBE_SYMBOL(unknown_nmi_error
);
306 static DEFINE_PER_CPU(bool, swallow_nmi
);
307 static DEFINE_PER_CPU(unsigned long, last_nmi_rip
);
309 static void default_do_nmi(struct pt_regs
*regs
)
311 unsigned char reason
= 0;
316 * CPU-specific NMI must be processed before non-CPU-specific
317 * NMI, otherwise we may lose it, because the CPU-specific
318 * NMI can not be detected/processed on other CPUs.
322 * Back-to-back NMIs are interesting because they can either
323 * be two NMI or more than two NMIs (any thing over two is dropped
324 * due to NMI being edge-triggered). If this is the second half
325 * of the back-to-back NMI, assume we dropped things and process
326 * more handlers. Otherwise reset the 'swallow' NMI behaviour
328 if (regs
->ip
== __this_cpu_read(last_nmi_rip
))
331 __this_cpu_write(swallow_nmi
, false);
333 __this_cpu_write(last_nmi_rip
, regs
->ip
);
335 handled
= nmi_handle(NMI_LOCAL
, regs
, b2b
);
336 __this_cpu_add(nmi_stats
.normal
, handled
);
339 * There are cases when a NMI handler handles multiple
340 * events in the current NMI. One of these events may
341 * be queued for in the next NMI. Because the event is
342 * already handled, the next NMI will result in an unknown
343 * NMI. Instead lets flag this for a potential NMI to
347 __this_cpu_write(swallow_nmi
, true);
351 /* Non-CPU-specific NMI: NMI sources can be processed on any CPU */
352 raw_spin_lock(&nmi_reason_lock
);
353 reason
= x86_platform
.get_nmi_reason();
355 if (reason
& NMI_REASON_MASK
) {
356 if (reason
& NMI_REASON_SERR
)
357 pci_serr_error(reason
, regs
);
358 else if (reason
& NMI_REASON_IOCHK
)
359 io_check_error(reason
, regs
);
362 * Reassert NMI in case it became active
363 * meanwhile as it's edge-triggered:
367 __this_cpu_add(nmi_stats
.external
, 1);
368 raw_spin_unlock(&nmi_reason_lock
);
371 raw_spin_unlock(&nmi_reason_lock
);
374 * Only one NMI can be latched at a time. To handle
375 * this we may process multiple nmi handlers at once to
376 * cover the case where an NMI is dropped. The downside
377 * to this approach is we may process an NMI prematurely,
378 * while its real NMI is sitting latched. This will cause
379 * an unknown NMI on the next run of the NMI processing.
381 * We tried to flag that condition above, by setting the
382 * swallow_nmi flag when we process more than one event.
383 * This condition is also only present on the second half
384 * of a back-to-back NMI, so we flag that condition too.
386 * If both are true, we assume we already processed this
387 * NMI previously and we swallow it. Otherwise we reset
390 * There are scenarios where we may accidentally swallow
391 * a 'real' unknown NMI. For example, while processing
392 * a perf NMI another perf NMI comes in along with a
393 * 'real' unknown NMI. These two NMIs get combined into
394 * one (as descibed above). When the next NMI gets
395 * processed, it will be flagged by perf as handled, but
396 * noone will know that there was a 'real' unknown NMI sent
397 * also. As a result it gets swallowed. Or if the first
398 * perf NMI returns two events handled then the second
399 * NMI will get eaten by the logic below, again losing a
400 * 'real' unknown NMI. But this is the best we can do
403 if (b2b
&& __this_cpu_read(swallow_nmi
))
404 __this_cpu_add(nmi_stats
.swallow
, 1);
406 unknown_nmi_error(reason
, regs
);
408 NOKPROBE_SYMBOL(default_do_nmi
);
411 * NMIs can hit breakpoints which will cause it to lose its
412 * NMI context with the CPU when the breakpoint does an iret.
416 * For i386, NMIs use the same stack as the kernel, and we can
417 * add a workaround to the iret problem in C (preventing nested
418 * NMIs if an NMI takes a trap). Simply have 3 states the NMI
425 * When no NMI is in progress, it is in the "not running" state.
426 * When an NMI comes in, it goes into the "executing" state.
427 * Normally, if another NMI is triggered, it does not interrupt
428 * the running NMI and the HW will simply latch it so that when
429 * the first NMI finishes, it will restart the second NMI.
430 * (Note, the latch is binary, thus multiple NMIs triggering,
431 * when one is running, are ignored. Only one NMI is restarted.)
433 * If an NMI hits a breakpoint that executes an iret, another
434 * NMI can preempt it. We do not want to allow this new NMI
435 * to run, but we want to execute it when the first one finishes.
436 * We set the state to "latched", and the exit of the first NMI will
437 * perform a dec_return, if the result is zero (NOT_RUNNING), then
438 * it will simply exit the NMI handler. If not, the dec_return
439 * would have set the state to NMI_EXECUTING (what we want it to
440 * be when we are running). In this case, we simply jump back
441 * to rerun the NMI handler again, and restart the 'latched' NMI.
443 * No trap (breakpoint or page fault) should be hit before nmi_restart,
444 * thus there is no race between the first check of state for NOT_RUNNING
445 * and setting it to NMI_EXECUTING. The HW will prevent nested NMIs
448 * In case the NMI takes a page fault, we need to save off the CR2
449 * because the NMI could have preempted another page fault and corrupt
450 * the CR2 that is about to be read. As nested NMIs must be restarted
451 * and they can not take breakpoints or page faults, the update of the
452 * CR2 must be done before converting the nmi state back to NOT_RUNNING.
453 * Otherwise, there would be a race of another nested NMI coming in
454 * after setting state to NOT_RUNNING but before updating the nmi_cr2.
461 static DEFINE_PER_CPU(enum nmi_states
, nmi_state
);
462 static DEFINE_PER_CPU(unsigned long, nmi_cr2
);
464 #define nmi_nesting_preprocess(regs) \
466 if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) { \
467 this_cpu_write(nmi_state, NMI_LATCHED); \
470 this_cpu_write(nmi_state, NMI_EXECUTING); \
471 this_cpu_write(nmi_cr2, read_cr2()); \
475 #define nmi_nesting_postprocess() \
477 if (unlikely(this_cpu_read(nmi_cr2) != read_cr2())) \
478 write_cr2(this_cpu_read(nmi_cr2)); \
479 if (this_cpu_dec_return(nmi_state)) \
484 * In x86_64 things are a bit more difficult. This has the same problem
485 * where an NMI hitting a breakpoint that calls iret will remove the
486 * NMI context, allowing a nested NMI to enter. What makes this more
487 * difficult is that both NMIs and breakpoints have their own stack.
488 * When a new NMI or breakpoint is executed, the stack is set to a fixed
489 * point. If an NMI is nested, it will have its stack set at that same
490 * fixed address that the first NMI had, and will start corrupting the
491 * stack. This is handled in entry_64.S, but the same problem exists with
492 * the breakpoint stack.
494 * If a breakpoint is being processed, and the debug stack is being used,
495 * if an NMI comes in and also hits a breakpoint, the stack pointer
496 * will be set to the same fixed address as the breakpoint that was
497 * interrupted, causing that stack to be corrupted. To handle this case,
498 * check if the stack that was interrupted is the debug stack, and if
499 * so, change the IDT so that new breakpoints will use the current stack
500 * and not switch to the fixed address. On return of the NMI, switch back
501 * to the original IDT.
503 static DEFINE_PER_CPU(int, update_debug_stack
);
505 static inline void nmi_nesting_preprocess(struct pt_regs
*regs
)
508 * If we interrupted a breakpoint, it is possible that
509 * the nmi handler will have breakpoints too. We need to
510 * change the IDT such that breakpoints that happen here
511 * continue to use the NMI stack.
513 if (unlikely(is_debug_stack(regs
->sp
))) {
514 debug_stack_set_zero();
515 this_cpu_write(update_debug_stack
, 1);
519 static inline void nmi_nesting_postprocess(void)
521 if (unlikely(this_cpu_read(update_debug_stack
))) {
523 this_cpu_write(update_debug_stack
, 0);
528 dotraplinkage notrace
void
529 do_nmi(struct pt_regs
*regs
, long error_code
)
531 nmi_nesting_preprocess(regs
);
535 inc_irq_stat(__nmi_count
);
538 default_do_nmi(regs
);
542 /* On i386, may loop back to preprocess */
543 nmi_nesting_postprocess();
545 NOKPROBE_SYMBOL(do_nmi
);
552 void restart_nmi(void)
557 /* reset the back-to-back NMI logic */
558 void local_touch_nmi(void)
560 __this_cpu_write(last_nmi_rip
, 0);
562 EXPORT_SYMBOL_GPL(local_touch_nmi
);
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