arch/x86/kernel/pci-gart_64.c

   1 /*
   2  * Dynamic DMA mapping support for AMD Hammer.
   3  *
   4  * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
   5  * This allows to use PCI devices that only support 32bit addresses on systems
   6  * with more than 4GB.
   7  *
   8  * See Documentation/DMA-mapping.txt for the interface specification.
   9  *
  10  * Copyright 2002 Andi Kleen, SuSE Labs.
  11  * Subject to the GNU General Public License v2 only.
  12  */
  13
  14 #include <linux/types.h>
  15 #include <linux/ctype.h>
  16 #include <linux/agp_backend.h>
  17 #include <linux/init.h>
  18 #include <linux/mm.h>
  19 #include <linux/string.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/pci.h>
  22 #include <linux/module.h>
  23 #include <linux/topology.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/bitops.h>
  26 #include <linux/kdebug.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/iommu-helper.h>
  29 #include <linux/sysdev.h>
  30 #include <asm/atomic.h>
  31 #include <asm/io.h>
  32 #include <asm/mtrr.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/proto.h>
  35 #include <asm/iommu.h>
  36 #include <asm/gart.h>
  37 #include <asm/cacheflush.h>
  38 #include <asm/swiotlb.h>
  39 #include <asm/dma.h>
  40 #include <asm/k8.h>
  41
  42 static unsigned long iommu_bus_base;    /* GART remapping area (physical) */
  43 static unsigned long iommu_size;        /* size of remapping area bytes */
  44 static unsigned long iommu_pages;       /* .. and in pages */
  45
  46 static u32 *iommu_gatt_base;            /* Remapping table */
  47
  48 /*
  49  * If this is disabled the IOMMU will use an optimized flushing strategy
  50  * of only flushing when an mapping is reused. With it true the GART is
  51  * flushed for every mapping. Problem is that doing the lazy flush seems
  52  * to trigger bugs with some popular PCI cards, in particular 3ware (but
  53  * has been also also seen with Qlogic at least).
  54  */
  55 int iommu_fullflush = 1;
  56
  57 /* Allocation bitmap for the remapping area: */
  58 static DEFINE_SPINLOCK(iommu_bitmap_lock);
  59 /* Guarded by iommu_bitmap_lock: */
  60 static unsigned long *iommu_gart_bitmap;
  61
  62 static u32 gart_unmapped_entry;
  63
  64 #define GPTE_VALID    1
  65 #define GPTE_COHERENT 2
  66 #define GPTE_ENCODE(x) \
  67         (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
  68 #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
  69
  70 #define to_pages(addr, size) \
  71         (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT)
  72
  73 #define EMERGENCY_PAGES 32 /* = 128KB */
  74
  75 #ifdef CONFIG_AGP
  76 #define AGPEXTERN extern
  77 #else
  78 #define AGPEXTERN
  79 #endif
  80
  81 /* backdoor interface to AGP driver */
  82 AGPEXTERN int agp_memory_reserved;
  83 AGPEXTERN __u32 *agp_gatt_table;
  84
  85 static unsigned long next_bit;  /* protected by iommu_bitmap_lock */
  86 static int need_flush;          /* global flush state. set for each gart wrap */
  87
  88 static unsigned long alloc_iommu(struct device *dev, int size)
  89 {
  90         unsigned long offset, flags;
  91         unsigned long boundary_size;
  92         unsigned long base_index;
  93
  94         base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
  95                            PAGE_SIZE) >> PAGE_SHIFT;
  96         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
  97                               PAGE_SIZE) >> PAGE_SHIFT;
  98
  99         spin_lock_irqsave(&iommu_bitmap_lock, flags);
 100         offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit,
 101                                   size, base_index, boundary_size, 0);
 102         if (offset == -1) {
 103                 need_flush = 1;
 104                 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0,
 105                                           size, base_index, boundary_size, 0);
 106         }
 107         if (offset != -1) {
 108                 next_bit = offset+size;
 109                 if (next_bit >= iommu_pages) {
 110                         next_bit = 0;
 111                         need_flush = 1;
 112                 }
 113         }
 114         if (iommu_fullflush)
 115                 need_flush = 1;
 116         spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
 117
 118         return offset;
 119 }
 120
 121 static void free_iommu(unsigned long offset, int size)
 122 {
 123         unsigned long flags;
 124
 125         spin_lock_irqsave(&iommu_bitmap_lock, flags);
 126         iommu_area_free(iommu_gart_bitmap, offset, size);
 127         spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
 128 }
 129
 130 /*
 131  * Use global flush state to avoid races with multiple flushers.
 132  */
 133 static void flush_gart(void)
 134 {
 135         unsigned long flags;
 136
 137         spin_lock_irqsave(&iommu_bitmap_lock, flags);
 138         if (need_flush) {
 139                 k8_flush_garts();
 140                 need_flush = 0;
 141         }
 142         spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
 143 }
 144
 145 #ifdef CONFIG_IOMMU_LEAK
 146
 147 #define SET_LEAK(x)                                                     \
 148         do {                                                            \
 149                 if (iommu_leak_tab)                                     \
 150                         iommu_leak_tab[x] = __builtin_return_address(0);\
 151         } while (0)
 152
 153 #define CLEAR_LEAK(x)                                                   \
 154         do {                                                            \
 155                 if (iommu_leak_tab)                                     \
 156                         iommu_leak_tab[x] = NULL;                       \
 157         } while (0)
 158
 159 /* Debugging aid for drivers that don't free their IOMMU tables */
 160 static void **iommu_leak_tab;
 161 static int leak_trace;
 162 static int iommu_leak_pages = 20;
 163
 164 static void dump_leak(void)
 165 {
 166         int i;
 167         static int dump;
 168
 169         if (dump || !iommu_leak_tab)
 170                 return;
 171         dump = 1;
 172         show_stack(NULL, NULL);
 173
 174         /* Very crude. dump some from the end of the table too */
 175         printk(KERN_DEBUG "Dumping %d pages from end of IOMMU:\n",
 176                iommu_leak_pages);
 177         for (i = 0; i < iommu_leak_pages; i += 2) {
 178                 printk(KERN_DEBUG "%lu: ", iommu_pages-i);
 179                 printk_address((unsigned long) iommu_leak_tab[iommu_pages-i], 0);
 180                 printk(KERN_CONT "%c", (i+1)%2 == 0 ? '\n' : ' ');
 181         }
 182         printk(KERN_DEBUG "\n");
 183 }
 184 #else
 185 # define SET_LEAK(x)
 186 # define CLEAR_LEAK(x)
 187 #endif
 188
 189 static void iommu_full(struct device *dev, size_t size, int dir)
 190 {
 191         /*
 192          * Ran out of IOMMU space for this operation. This is very bad.
 193          * Unfortunately the drivers cannot handle this operation properly.
 194          * Return some non mapped prereserved space in the aperture and
 195          * let the Northbridge deal with it. This will result in garbage
 196          * in the IO operation. When the size exceeds the prereserved space
 197          * memory corruption will occur or random memory will be DMAed
 198          * out. Hopefully no network devices use single mappings that big.
 199          */
 200
 201         dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size);
 202
 203         if (size > PAGE_SIZE*EMERGENCY_PAGES) {
 204                 if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
 205                         panic("PCI-DMA: Memory would be corrupted\n");
 206                 if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
 207                         panic(KERN_ERR
 208                                 "PCI-DMA: Random memory would be DMAed\n");
 209         }
 210 #ifdef CONFIG_IOMMU_LEAK
 211         dump_leak();
 212 #endif
 213 }
 214
 215 static inline int
 216 need_iommu(struct device *dev, unsigned long addr, size_t size)
 217 {
 218         u64 mask = *dev->dma_mask;
 219         int high = addr + size > mask;
 220         int mmu = high;
 221
 222         if (force_iommu)
 223                 mmu = 1;
 224
 225         return mmu;
 226 }
 227
 228 static inline int
 229 nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
 230 {
 231         u64 mask = *dev->dma_mask;
 232         int high = addr + size > mask;
 233         int mmu = high;
 234
 235         return mmu;
 236 }
 237
 238 /* Map a single continuous physical area into the IOMMU.
 239  * Caller needs to check if the iommu is needed and flush.
 240  */
 241 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
 242                                 size_t size, int dir)
 243 {
 244         unsigned long npages = to_pages(phys_mem, size);
 245         unsigned long iommu_page = alloc_iommu(dev, npages);
 246         int i;
 247
 248         if (iommu_page == -1) {
 249                 if (!nonforced_iommu(dev, phys_mem, size))
 250                         return phys_mem;
 251                 if (panic_on_overflow)
 252                         panic("dma_map_area overflow %lu bytes\n", size);
 253                 iommu_full(dev, size, dir);
 254                 return bad_dma_address;
 255         }
 256
 257         for (i = 0; i < npages; i++) {
 258                 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
 259                 SET_LEAK(iommu_page + i);
 260                 phys_mem += PAGE_SIZE;
 261         }
 262         return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
 263 }
 264
 265 static dma_addr_t
 266 gart_map_simple(struct device *dev, phys_addr_t paddr, size_t size, int dir)
 267 {
 268         dma_addr_t map = dma_map_area(dev, paddr, size, dir);
 269
 270         flush_gart();
 271
 272         return map;
 273 }
 274
 275 /* Map a single area into the IOMMU */
 276 static dma_addr_t
 277 gart_map_single(struct device *dev, phys_addr_t paddr, size_t size, int dir)
 278 {
 279         unsigned long bus;
 280
 281         if (!dev)
 282                 dev = &fallback_dev;
 283
 284         if (!need_iommu(dev, paddr, size))
 285                 return paddr;
 286
 287         bus = gart_map_simple(dev, paddr, size, dir);
 288
 289         return bus;
 290 }
 291
 292 /*
 293  * Free a DMA mapping.
 294  */
 295 static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
 296                               size_t size, int direction)
 297 {
 298         unsigned long iommu_page;
 299         int npages;
 300         int i;
 301
 302         if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
 303             dma_addr >= iommu_bus_base + iommu_size)
 304                 return;
 305
 306         iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
 307         npages = to_pages(dma_addr, size);
 308         for (i = 0; i < npages; i++) {
 309                 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
 310                 CLEAR_LEAK(iommu_page + i);
 311         }
 312         free_iommu(iommu_page, npages);
 313 }
 314
 315 /*
 316  * Wrapper for pci_unmap_single working with scatterlists.
 317  */
 318 static void
 319 gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
 320 {
 321         struct scatterlist *s;
 322         int i;
 323
 324         for_each_sg(sg, s, nents, i) {
 325                 if (!s->dma_length || !s->length)
 326                         break;
 327                 gart_unmap_single(dev, s->dma_address, s->dma_length, dir);
 328         }
 329 }
 330
 331 /* Fallback for dma_map_sg in case of overflow */
 332 static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
 333                                int nents, int dir)
 334 {
 335         struct scatterlist *s;
 336         int i;
 337
 338 #ifdef CONFIG_IOMMU_DEBUG
 339         printk(KERN_DEBUG "dma_map_sg overflow\n");
 340 #endif
 341
 342         for_each_sg(sg, s, nents, i) {
 343                 unsigned long addr = sg_phys(s);
 344
 345                 if (nonforced_iommu(dev, addr, s->length)) {
 346                         addr = dma_map_area(dev, addr, s->length, dir);
 347                         if (addr == bad_dma_address) {
 348                                 if (i > 0)
 349                                         gart_unmap_sg(dev, sg, i, dir);
 350                                 nents = 0;
 351                                 sg[0].dma_length = 0;
 352                                 break;
 353                         }
 354                 }
 355                 s->dma_address = addr;
 356                 s->dma_length = s->length;
 357         }
 358         flush_gart();
 359
 360         return nents;
 361 }
 362
 363 /* Map multiple scatterlist entries continuous into the first. */
 364 static int __dma_map_cont(struct device *dev, struct scatterlist *start,
 365                           int nelems, struct scatterlist *sout,
 366                           unsigned long pages)
 367 {
 368         unsigned long iommu_start = alloc_iommu(dev, pages);
 369         unsigned long iommu_page = iommu_start;
 370         struct scatterlist *s;
 371         int i;
 372
 373         if (iommu_start == -1)
 374                 return -1;
 375
 376         for_each_sg(start, s, nelems, i) {
 377                 unsigned long pages, addr;
 378                 unsigned long phys_addr = s->dma_address;
 379
 380                 BUG_ON(s != start && s->offset);
 381                 if (s == start) {
 382                         sout->dma_address = iommu_bus_base;
 383                         sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
 384                         sout->dma_length = s->length;
 385                 } else {
 386                         sout->dma_length += s->length;
 387                 }
 388
 389                 addr = phys_addr;
 390                 pages = to_pages(s->offset, s->length);
 391                 while (pages--) {
 392                         iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
 393                         SET_LEAK(iommu_page);
 394                         addr += PAGE_SIZE;
 395                         iommu_page++;
 396                 }
 397         }
 398         BUG_ON(iommu_page - iommu_start != pages);
 399
 400         return 0;
 401 }
 402
 403 static inline int
 404 dma_map_cont(struct device *dev, struct scatterlist *start, int nelems,
 405              struct scatterlist *sout, unsigned long pages, int need)
 406 {
 407         if (!need) {
 408                 BUG_ON(nelems != 1);
 409                 sout->dma_address = start->dma_address;
 410                 sout->dma_length = start->length;
 411                 return 0;
 412         }
 413         return __dma_map_cont(dev, start, nelems, sout, pages);
 414 }
 415
 416 /*
 417  * DMA map all entries in a scatterlist.
 418  * Merge chunks that have page aligned sizes into a continuous mapping.
 419  */
 420 static int
 421 gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
 422 {
 423         struct scatterlist *s, *ps, *start_sg, *sgmap;
 424         int need = 0, nextneed, i, out, start;
 425         unsigned long pages = 0;
 426         unsigned int seg_size;
 427         unsigned int max_seg_size;
 428
 429         if (nents == 0)
 430                 return 0;
 431
 432         if (!dev)
 433                 dev = &fallback_dev;
 434
 435         out = 0;
 436         start = 0;
 437         start_sg = sgmap = sg;
 438         seg_size = 0;
 439         max_seg_size = dma_get_max_seg_size(dev);
 440         ps = NULL; /* shut up gcc */
 441         for_each_sg(sg, s, nents, i) {
 442                 dma_addr_t addr = sg_phys(s);
 443
 444                 s->dma_address = addr;
 445                 BUG_ON(s->length == 0);
 446
 447                 nextneed = need_iommu(dev, addr, s->length);
 448
 449                 /* Handle the previous not yet processed entries */
 450                 if (i > start) {
 451                         /*
 452                          * Can only merge when the last chunk ends on a
 453                          * page boundary and the new one doesn't have an
 454                          * offset.
 455                          */
 456                         if (!iommu_merge || !nextneed || !need || s->offset ||
 457                             (s->length + seg_size > max_seg_size) ||
 458                             (ps->offset + ps->length) % PAGE_SIZE) {
 459                                 if (dma_map_cont(dev, start_sg, i - start,
 460                                                  sgmap, pages, need) < 0)
 461                                         goto error;
 462                                 out++;
 463                                 seg_size = 0;
 464                                 sgmap = sg_next(sgmap);
 465                                 pages = 0;
 466                                 start = i;
 467                                 start_sg = s;
 468                         }
 469                 }
 470
 471                 seg_size += s->length;
 472                 need = nextneed;
 473                 pages += to_pages(s->offset, s->length);
 474                 ps = s;
 475         }
 476         if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
 477                 goto error;
 478         out++;
 479         flush_gart();
 480         if (out < nents) {
 481                 sgmap = sg_next(sgmap);
 482                 sgmap->dma_length = 0;
 483         }
 484         return out;
 485
 486 error:
 487         flush_gart();
 488         gart_unmap_sg(dev, sg, out, dir);
 489
 490         /* When it was forced or merged try again in a dumb way */
 491         if (force_iommu || iommu_merge) {
 492                 out = dma_map_sg_nonforce(dev, sg, nents, dir);
 493                 if (out > 0)
 494                         return out;
 495         }
 496         if (panic_on_overflow)
 497                 panic("dma_map_sg: overflow on %lu pages\n", pages);
 498
 499         iommu_full(dev, pages << PAGE_SHIFT, dir);
 500         for_each_sg(sg, s, nents, i)
 501                 s->dma_address = bad_dma_address;
 502         return 0;
 503 }
 504
 505 static int no_agp;
 506
 507 static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
 508 {
 509         unsigned long a;
 510
 511         if (!iommu_size) {
 512                 iommu_size = aper_size;
 513                 if (!no_agp)
 514                         iommu_size /= 2;
 515         }
 516
 517         a = aper + iommu_size;
 518         iommu_size -= round_up(a, PMD_PAGE_SIZE) - a;
 519
 520         if (iommu_size < 64*1024*1024) {
 521                 printk(KERN_WARNING
 522                         "PCI-DMA: Warning: Small IOMMU %luMB."
 523                         " Consider increasing the AGP aperture in BIOS\n",
 524                                 iommu_size >> 20);
 525         }
 526
 527         return iommu_size;
 528 }
 529
 530 static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
 531 {
 532         unsigned aper_size = 0, aper_base_32, aper_order;
 533         u64 aper_base;
 534
 535         pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
 536         pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
 537         aper_order = (aper_order >> 1) & 7;
 538
 539         aper_base = aper_base_32 & 0x7fff;
 540         aper_base <<= 25;
 541
 542         aper_size = (32 * 1024 * 1024) << aper_order;
 543         if (aper_base + aper_size > 0x100000000UL || !aper_size)
 544                 aper_base = 0;
 545
 546         *size = aper_size;
 547         return aper_base;
 548 }
 549
 550 static void enable_gart_translations(void)
 551 {
 552         int i;
 553
 554         for (i = 0; i < num_k8_northbridges; i++) {
 555                 struct pci_dev *dev = k8_northbridges[i];
 556
 557                 enable_gart_translation(dev, __pa(agp_gatt_table));
 558         }
 559 }
 560
 561 /*
 562  * If fix_up_north_bridges is set, the north bridges have to be fixed up on
 563  * resume in the same way as they are handled in gart_iommu_hole_init().
 564  */
 565 static bool fix_up_north_bridges;
 566 static u32 aperture_order;
 567 static u32 aperture_alloc;
 568
 569 void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
 570 {
 571         fix_up_north_bridges = true;
 572         aperture_order = aper_order;
 573         aperture_alloc = aper_alloc;
 574 }
 575
 576 static int gart_resume(struct sys_device *dev)
 577 {
 578         printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n");
 579
 580         if (fix_up_north_bridges) {
 581                 int i;
 582
 583                 printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n");
 584
 585                 for (i = 0; i < num_k8_northbridges; i++) {
 586                         struct pci_dev *dev = k8_northbridges[i];
 587
 588                         /*
 589                          * Don't enable translations just yet.  That is the next
 590                          * step.  Restore the pre-suspend aperture settings.
 591                          */
 592                         pci_write_config_dword(dev, AMD64_GARTAPERTURECTL,
 593                                                 aperture_order << 1);
 594                         pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE,
 595                                                 aperture_alloc >> 25);
 596                 }
 597         }
 598
 599         enable_gart_translations();
 600
 601         return 0;
 602 }
 603
 604 static int gart_suspend(struct sys_device *dev, pm_message_t state)
 605 {
 606         return 0;
 607 }
 608
 609 static struct sysdev_class gart_sysdev_class = {
 610         .name = "gart",
 611         .suspend = gart_suspend,
 612         .resume = gart_resume,
 613
 614 };
 615
 616 static struct sys_device device_gart = {
 617         .id     = 0,
 618         .cls    = &gart_sysdev_class,
 619 };
 620
 621 /*
 622  * Private Northbridge GATT initialization in case we cannot use the
 623  * AGP driver for some reason.
 624  */
 625 static __init int init_k8_gatt(struct agp_kern_info *info)
 626 {
 627         unsigned aper_size, gatt_size, new_aper_size;
 628         unsigned aper_base, new_aper_base;
 629         struct pci_dev *dev;
 630         void *gatt;
 631         int i, error;
 632         unsigned long start_pfn, end_pfn;
 633
 634         printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
 635         aper_size = aper_base = info->aper_size = 0;
 636         dev = NULL;
 637         for (i = 0; i < num_k8_northbridges; i++) {
 638                 dev = k8_northbridges[i];
 639                 new_aper_base = read_aperture(dev, &new_aper_size);
 640                 if (!new_aper_base)
 641                         goto nommu;
 642
 643                 if (!aper_base) {
 644                         aper_size = new_aper_size;
 645                         aper_base = new_aper_base;
 646                 }
 647                 if (aper_size != new_aper_size || aper_base != new_aper_base)
 648                         goto nommu;
 649         }
 650         if (!aper_base)
 651                 goto nommu;
 652         info->aper_base = aper_base;
 653         info->aper_size = aper_size >> 20;
 654
 655         gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
 656         gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size));
 657         if (!gatt)
 658                 panic("Cannot allocate GATT table");
 659         if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
 660                 panic("Could not set GART PTEs to uncacheable pages");
 661
 662         memset(gatt, 0, gatt_size);
 663         agp_gatt_table = gatt;
 664
 665         enable_gart_translations();
 666
 667         error = sysdev_class_register(&gart_sysdev_class);
 668         if (!error)
 669                 error = sysdev_register(&device_gart);
 670         if (error)
 671                 panic("Could not register gart_sysdev -- would corrupt data on next suspend");
 672
 673         flush_gart();
 674
 675         printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
 676                aper_base, aper_size>>10);
 677
 678         /* need to map that range */
 679         end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
 680         if (end_pfn > max_low_pfn_mapped) {
 681                 start_pfn = (aper_base>>PAGE_SHIFT);
 682                 init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
 683         }
 684         return 0;
 685
 686  nommu:
 687         /* Should not happen anymore */
 688         printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
 689                KERN_WARNING "falling back to iommu=soft.\n");
 690         return -1;
 691 }
 692
 693 extern int agp_amd64_init(void);
 694
 695 static struct dma_mapping_ops gart_dma_ops = {
 696         .map_single                     = gart_map_single,
 697         .map_simple                     = gart_map_simple,
 698         .unmap_single                   = gart_unmap_single,
 699         .sync_single_for_cpu            = NULL,
 700         .sync_single_for_device         = NULL,
 701         .sync_single_range_for_cpu      = NULL,
 702         .sync_single_range_for_device   = NULL,
 703         .sync_sg_for_cpu                = NULL,
 704         .sync_sg_for_device             = NULL,
 705         .map_sg                         = gart_map_sg,
 706         .unmap_sg                       = gart_unmap_sg,
 707 };
 708
 709 void gart_iommu_shutdown(void)
 710 {
 711         struct pci_dev *dev;
 712         int i;
 713
 714         if (no_agp && (dma_ops != &gart_dma_ops))
 715                 return;
 716
 717         for (i = 0; i < num_k8_northbridges; i++) {
 718                 u32 ctl;
 719
 720                 dev = k8_northbridges[i];
 721                 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
 722
 723                 ctl &= ~GARTEN;
 724
 725                 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
 726         }
 727 }
 728
 729 void __init gart_iommu_init(void)
 730 {
 731         struct agp_kern_info info;
 732         unsigned long iommu_start;
 733         unsigned long aper_size;
 734         unsigned long scratch;
 735         long i;
 736
 737         if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) {
 738                 printk(KERN_INFO "PCI-GART: No AMD northbridge found.\n");
 739                 return;
 740         }
 741
 742 #ifndef CONFIG_AGP_AMD64
 743         no_agp = 1;
 744 #else
 745         /* Makefile puts PCI initialization via subsys_initcall first. */
 746         /* Add other K8 AGP bridge drivers here */
 747         no_agp = no_agp ||
 748                 (agp_amd64_init() < 0) ||
 749                 (agp_copy_info(agp_bridge, &info) < 0);
 750 #endif
 751
 752         if (swiotlb)
 753                 return;
 754
 755         /* Did we detect a different HW IOMMU? */
 756         if (iommu_detected && !gart_iommu_aperture)
 757                 return;
 758
 759         if (no_iommu ||
 760             (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
 761             !gart_iommu_aperture ||
 762             (no_agp && init_k8_gatt(&info) < 0)) {
 763                 if (max_pfn > MAX_DMA32_PFN) {
 764                         printk(KERN_WARNING "More than 4GB of memory "
 765                                           "but GART IOMMU not available.\n"
 766                                KERN_WARNING "falling back to iommu=soft.\n");
 767                 }
 768                 return;
 769         }
 770
 771         printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
 772         aper_size = info.aper_size * 1024 * 1024;
 773         iommu_size = check_iommu_size(info.aper_base, aper_size);
 774         iommu_pages = iommu_size >> PAGE_SHIFT;
 775
 776         iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL,
 777                                                       get_order(iommu_pages/8));
 778         if (!iommu_gart_bitmap)
 779                 panic("Cannot allocate iommu bitmap\n");
 780         memset(iommu_gart_bitmap, 0, iommu_pages/8);
 781
 782 #ifdef CONFIG_IOMMU_LEAK
 783         if (leak_trace) {
 784                 iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL,
 785                                   get_order(iommu_pages*sizeof(void *)));
 786                 if (iommu_leak_tab)
 787                         memset(iommu_leak_tab, 0, iommu_pages * 8);
 788                 else
 789                         printk(KERN_DEBUG
 790                                "PCI-DMA: Cannot allocate leak trace area\n");
 791         }
 792 #endif
 793
 794         /*
 795          * Out of IOMMU space handling.
 796          * Reserve some invalid pages at the beginning of the GART.
 797          */
 798         set_bit_string(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
 799
 800         agp_memory_reserved = iommu_size;
 801         printk(KERN_INFO
 802                "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
 803                iommu_size >> 20);
 804
 805         iommu_start = aper_size - iommu_size;
 806         iommu_bus_base = info.aper_base + iommu_start;
 807         bad_dma_address = iommu_bus_base;
 808         iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
 809
 810         /*
 811          * Unmap the IOMMU part of the GART. The alias of the page is
 812          * always mapped with cache enabled and there is no full cache
 813          * coherency across the GART remapping. The unmapping avoids
 814          * automatic prefetches from the CPU allocating cache lines in
 815          * there. All CPU accesses are done via the direct mapping to
 816          * the backing memory. The GART address is only used by PCI
 817          * devices.
 818          */
 819         set_memory_np((unsigned long)__va(iommu_bus_base),
 820                                 iommu_size >> PAGE_SHIFT);
 821         /*
 822          * Tricky. The GART table remaps the physical memory range,
 823          * so the CPU wont notice potential aliases and if the memory
 824          * is remapped to UC later on, we might surprise the PCI devices
 825          * with a stray writeout of a cacheline. So play it sure and
 826          * do an explicit, full-scale wbinvd() _after_ having marked all
 827          * the pages as Not-Present:
 828          */
 829         wbinvd();
 830
 831         /*
 832          * Try to workaround a bug (thanks to BenH):
 833          * Set unmapped entries to a scratch page instead of 0.
 834          * Any prefetches that hit unmapped entries won't get an bus abort
 835          * then. (P2P bridge may be prefetching on DMA reads).
 836          */
 837         scratch = get_zeroed_page(GFP_KERNEL);
 838         if (!scratch)
 839                 panic("Cannot allocate iommu scratch page");
 840         gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
 841         for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
 842                 iommu_gatt_base[i] = gart_unmapped_entry;
 843
 844         flush_gart();
 845         dma_ops = &gart_dma_ops;
 846 }
 847
 848 void __init gart_parse_options(char *p)
 849 {
 850         int arg;
 851
 852 #ifdef CONFIG_IOMMU_LEAK
 853         if (!strncmp(p, "leak", 4)) {
 854                 leak_trace = 1;
 855                 p += 4;
 856                 if (*p == '=') ++p;
 857                 if (isdigit(*p) && get_option(&p, &arg))
 858                         iommu_leak_pages = arg;
 859         }
 860 #endif
 861         if (isdigit(*p) && get_option(&p, &arg))
 862                 iommu_size = arg;
 863         if (!strncmp(p, "fullflush", 8))
 864                 iommu_fullflush = 1;
 865         if (!strncmp(p, "nofullflush", 11))
 866                 iommu_fullflush = 0;
 867         if (!strncmp(p, "noagp", 5))
 868                 no_agp = 1;
 869         if (!strncmp(p, "noaperture", 10))
 870                 fix_aperture = 0;
 871         /* duplicated from pci-dma.c */
 872         if (!strncmp(p, "force", 5))
 873                 gart_iommu_aperture_allowed = 1;
 874         if (!strncmp(p, "allowed", 7))
 875                 gart_iommu_aperture_allowed = 1;
 876         if (!strncmp(p, "memaper", 7)) {
 877                 fallback_aper_force = 1;
 878                 p += 7;
 879                 if (*p == '=') {
 880                         ++p;
 881                         if (get_option(&p, &arg))
 882                                 fallback_aper_order = arg;
 883                 }
 884         }
 885 }