arch/x86/kernel/pci-gart_64.c

   1 /*
   2  * Dynamic DMA mapping support for AMD Hammer.
   3  *
   4  * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
   5  * This allows to use PCI devices that only support 32bit addresses on systems
   6  * with more than 4GB.
   7  *
   8  * See Documentation/DMA-mapping.txt for the interface specification.
   9  *
  10  * Copyright 2002 Andi Kleen, SuSE Labs.
  11  * Subject to the GNU General Public License v2 only.
  12  */
  13
  14 #include <linux/types.h>
  15 #include <linux/ctype.h>
  16 #include <linux/agp_backend.h>
  17 #include <linux/init.h>
  18 #include <linux/mm.h>
  19 #include <linux/string.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/pci.h>
  22 #include <linux/module.h>
  23 #include <linux/topology.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/bitops.h>
  26 #include <linux/kdebug.h>
  27 #include <linux/scatterlist.h>
  28 #include <asm/atomic.h>
  29 #include <asm/io.h>
  30 #include <asm/mtrr.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/proto.h>
  33 #include <asm/gart.h>
  34 #include <asm/cacheflush.h>
  35 #include <asm/swiotlb.h>
  36 #include <asm/dma.h>
  37 #include <asm/k8.h>
  38
  39 static unsigned long iommu_bus_base;    /* GART remapping area (physical) */
  40 static unsigned long iommu_size;        /* size of remapping area bytes */
  41 static unsigned long iommu_pages;       /* .. and in pages */
  42
  43 static u32 *iommu_gatt_base;            /* Remapping table */
  44
  45 /*
  46  * If this is disabled the IOMMU will use an optimized flushing strategy
  47  * of only flushing when an mapping is reused. With it true the GART is
  48  * flushed for every mapping. Problem is that doing the lazy flush seems
  49  * to trigger bugs with some popular PCI cards, in particular 3ware (but
  50  * has been also also seen with Qlogic at least).
  51  */
  52 int iommu_fullflush = 1;
  53
  54 /* Allocation bitmap for the remapping area: */
  55 static DEFINE_SPINLOCK(iommu_bitmap_lock);
  56 /* Guarded by iommu_bitmap_lock: */
  57 static unsigned long *iommu_gart_bitmap;
  58
  59 static u32 gart_unmapped_entry;
  60
  61 #define GPTE_VALID    1
  62 #define GPTE_COHERENT 2
  63 #define GPTE_ENCODE(x) \
  64         (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
  65 #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
  66
  67 #define to_pages(addr, size) \
  68         (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT)
  69
  70 #define EMERGENCY_PAGES 32 /* = 128KB */
  71
  72 #ifdef CONFIG_AGP
  73 #define AGPEXTERN extern
  74 #else
  75 #define AGPEXTERN
  76 #endif
  77
  78 /* backdoor interface to AGP driver */
  79 AGPEXTERN int agp_memory_reserved;
  80 AGPEXTERN __u32 *agp_gatt_table;
  81
  82 static unsigned long next_bit;  /* protected by iommu_bitmap_lock */
  83 static int need_flush;          /* global flush state. set for each gart wrap */
  84
  85 static unsigned long alloc_iommu(int size)
  86 {
  87         unsigned long offset, flags;
  88
  89         spin_lock_irqsave(&iommu_bitmap_lock, flags);
  90         offset = find_next_zero_string(iommu_gart_bitmap, next_bit,
  91                                         iommu_pages, size);
  92         if (offset == -1) {
  93                 need_flush = 1;
  94                 offset = find_next_zero_string(iommu_gart_bitmap, 0,
  95                                                 iommu_pages, size);
  96         }
  97         if (offset != -1) {
  98                 set_bit_string(iommu_gart_bitmap, offset, size);
  99                 next_bit = offset+size;
 100                 if (next_bit >= iommu_pages) {
 101                         next_bit = 0;
 102                         need_flush = 1;
 103                 }
 104         }
 105         if (iommu_fullflush)
 106                 need_flush = 1;
 107         spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
 108
 109         return offset;
 110 }
 111
 112 static void free_iommu(unsigned long offset, int size)
 113 {
 114         unsigned long flags;
 115
 116         spin_lock_irqsave(&iommu_bitmap_lock, flags);
 117         __clear_bit_string(iommu_gart_bitmap, offset, size);
 118         spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
 119 }
 120
 121 /*
 122  * Use global flush state to avoid races with multiple flushers.
 123  */
 124 static void flush_gart(void)
 125 {
 126         unsigned long flags;
 127
 128         spin_lock_irqsave(&iommu_bitmap_lock, flags);
 129         if (need_flush) {
 130                 k8_flush_garts();
 131                 need_flush = 0;
 132         }
 133         spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
 134 }
 135
 136 #ifdef CONFIG_IOMMU_LEAK
 137
 138 #define SET_LEAK(x)                                                     \
 139         do {                                                            \
 140                 if (iommu_leak_tab)                                     \
 141                         iommu_leak_tab[x] = __builtin_return_address(0);\
 142         } while (0)
 143
 144 #define CLEAR_LEAK(x)                                                   \
 145         do {                                                            \
 146                 if (iommu_leak_tab)                                     \
 147                         iommu_leak_tab[x] = NULL;                       \
 148         } while (0)
 149
 150 /* Debugging aid for drivers that don't free their IOMMU tables */
 151 static void **iommu_leak_tab;
 152 static int leak_trace;
 153 static int iommu_leak_pages = 20;
 154
 155 static void dump_leak(void)
 156 {
 157         int i;
 158         static int dump;
 159
 160         if (dump || !iommu_leak_tab)
 161                 return;
 162         dump = 1;
 163         show_stack(NULL, NULL);
 164
 165         /* Very crude. dump some from the end of the table too */
 166         printk(KERN_DEBUG "Dumping %d pages from end of IOMMU:\n",
 167                iommu_leak_pages);
 168         for (i = 0; i < iommu_leak_pages; i += 2) {
 169                 printk(KERN_DEBUG "%lu: ", iommu_pages-i);
 170                 printk_address((unsigned long) iommu_leak_tab[iommu_pages-i], 0);
 171                 printk(KERN_CONT "%c", (i+1)%2 == 0 ? '\n' : ' ');
 172         }
 173         printk(KERN_DEBUG "\n");
 174 }
 175 #else
 176 # define SET_LEAK(x)
 177 # define CLEAR_LEAK(x)
 178 #endif
 179
 180 static void iommu_full(struct device *dev, size_t size, int dir)
 181 {
 182         /*
 183          * Ran out of IOMMU space for this operation. This is very bad.
 184          * Unfortunately the drivers cannot handle this operation properly.
 185          * Return some non mapped prereserved space in the aperture and
 186          * let the Northbridge deal with it. This will result in garbage
 187          * in the IO operation. When the size exceeds the prereserved space
 188          * memory corruption will occur or random memory will be DMAed
 189          * out. Hopefully no network devices use single mappings that big.
 190          */
 191
 192         printk(KERN_ERR
 193                 "PCI-DMA: Out of IOMMU space for %lu bytes at device %s\n",
 194                 size, dev->bus_id);
 195
 196         if (size > PAGE_SIZE*EMERGENCY_PAGES) {
 197                 if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
 198                         panic("PCI-DMA: Memory would be corrupted\n");
 199                 if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
 200                         panic(KERN_ERR
 201                                 "PCI-DMA: Random memory would be DMAed\n");
 202         }
 203 #ifdef CONFIG_IOMMU_LEAK
 204         dump_leak();
 205 #endif
 206 }
 207
 208 static inline int
 209 need_iommu(struct device *dev, unsigned long addr, size_t size)
 210 {
 211         u64 mask = *dev->dma_mask;
 212         int high = addr + size > mask;
 213         int mmu = high;
 214
 215         if (force_iommu)
 216                 mmu = 1;
 217
 218         return mmu;
 219 }
 220
 221 static inline int
 222 nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
 223 {
 224         u64 mask = *dev->dma_mask;
 225         int high = addr + size > mask;
 226         int mmu = high;
 227
 228         return mmu;
 229 }
 230
 231 /* Map a single continuous physical area into the IOMMU.
 232  * Caller needs to check if the iommu is needed and flush.
 233  */
 234 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
 235                                 size_t size, int dir)
 236 {
 237         unsigned long npages = to_pages(phys_mem, size);
 238         unsigned long iommu_page = alloc_iommu(npages);
 239         int i;
 240
 241         if (iommu_page == -1) {
 242                 if (!nonforced_iommu(dev, phys_mem, size))
 243                         return phys_mem;
 244                 if (panic_on_overflow)
 245                         panic("dma_map_area overflow %lu bytes\n", size);
 246                 iommu_full(dev, size, dir);
 247                 return bad_dma_address;
 248         }
 249
 250         for (i = 0; i < npages; i++) {
 251                 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
 252                 SET_LEAK(iommu_page + i);
 253                 phys_mem += PAGE_SIZE;
 254         }
 255         return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
 256 }
 257
 258 static dma_addr_t
 259 gart_map_simple(struct device *dev, char *buf, size_t size, int dir)
 260 {
 261         dma_addr_t map = dma_map_area(dev, virt_to_bus(buf), size, dir);
 262
 263         flush_gart();
 264
 265         return map;
 266 }
 267
 268 /* Map a single area into the IOMMU */
 269 static dma_addr_t
 270 gart_map_single(struct device *dev, void *addr, size_t size, int dir)
 271 {
 272         unsigned long phys_mem, bus;
 273
 274         if (!dev)
 275                 dev = &fallback_dev;
 276
 277         phys_mem = virt_to_phys(addr);
 278         if (!need_iommu(dev, phys_mem, size))
 279                 return phys_mem;
 280
 281         bus = gart_map_simple(dev, addr, size, dir);
 282
 283         return bus;
 284 }
 285
 286 /*
 287  * Free a DMA mapping.
 288  */
 289 static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
 290                               size_t size, int direction)
 291 {
 292         unsigned long iommu_page;
 293         int npages;
 294         int i;
 295
 296         if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
 297             dma_addr >= iommu_bus_base + iommu_size)
 298                 return;
 299
 300         iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
 301         npages = to_pages(dma_addr, size);
 302         for (i = 0; i < npages; i++) {
 303                 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
 304                 CLEAR_LEAK(iommu_page + i);
 305         }
 306         free_iommu(iommu_page, npages);
 307 }
 308
 309 /*
 310  * Wrapper for pci_unmap_single working with scatterlists.
 311  */
 312 static void
 313 gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
 314 {
 315         struct scatterlist *s;
 316         int i;
 317
 318         for_each_sg(sg, s, nents, i) {
 319                 if (!s->dma_length || !s->length)
 320                         break;
 321                 gart_unmap_single(dev, s->dma_address, s->dma_length, dir);
 322         }
 323 }
 324
 325 /* Fallback for dma_map_sg in case of overflow */
 326 static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
 327                                int nents, int dir)
 328 {
 329         struct scatterlist *s;
 330         int i;
 331
 332 #ifdef CONFIG_IOMMU_DEBUG
 333         printk(KERN_DEBUG "dma_map_sg overflow\n");
 334 #endif
 335
 336         for_each_sg(sg, s, nents, i) {
 337                 unsigned long addr = sg_phys(s);
 338
 339                 if (nonforced_iommu(dev, addr, s->length)) {
 340                         addr = dma_map_area(dev, addr, s->length, dir);
 341                         if (addr == bad_dma_address) {
 342                                 if (i > 0)
 343                                         gart_unmap_sg(dev, sg, i, dir);
 344                                 nents = 0;
 345                                 sg[0].dma_length = 0;
 346                                 break;
 347                         }
 348                 }
 349                 s->dma_address = addr;
 350                 s->dma_length = s->length;
 351         }
 352         flush_gart();
 353
 354         return nents;
 355 }
 356
 357 /* Map multiple scatterlist entries continuous into the first. */
 358 static int __dma_map_cont(struct scatterlist *start, int nelems,
 359                           struct scatterlist *sout, unsigned long pages)
 360 {
 361         unsigned long iommu_start = alloc_iommu(pages);
 362         unsigned long iommu_page = iommu_start;
 363         struct scatterlist *s;
 364         int i;
 365
 366         if (iommu_start == -1)
 367                 return -1;
 368
 369         for_each_sg(start, s, nelems, i) {
 370                 unsigned long pages, addr;
 371                 unsigned long phys_addr = s->dma_address;
 372
 373                 BUG_ON(s != start && s->offset);
 374                 if (s == start) {
 375                         sout->dma_address = iommu_bus_base;
 376                         sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
 377                         sout->dma_length = s->length;
 378                 } else {
 379                         sout->dma_length += s->length;
 380                 }
 381
 382                 addr = phys_addr;
 383                 pages = to_pages(s->offset, s->length);
 384                 while (pages--) {
 385                         iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
 386                         SET_LEAK(iommu_page);
 387                         addr += PAGE_SIZE;
 388                         iommu_page++;
 389                 }
 390         }
 391         BUG_ON(iommu_page - iommu_start != pages);
 392
 393         return 0;
 394 }
 395
 396 static inline int
 397 dma_map_cont(struct scatterlist *start, int nelems, struct scatterlist *sout,
 398              unsigned long pages, int need)
 399 {
 400         if (!need) {
 401                 BUG_ON(nelems != 1);
 402                 sout->dma_address = start->dma_address;
 403                 sout->dma_length = start->length;
 404                 return 0;
 405         }
 406         return __dma_map_cont(start, nelems, sout, pages);
 407 }
 408
 409 /*
 410  * DMA map all entries in a scatterlist.
 411  * Merge chunks that have page aligned sizes into a continuous mapping.
 412  */
 413 static int
 414 gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
 415 {
 416         struct scatterlist *s, *ps, *start_sg, *sgmap;
 417         int need = 0, nextneed, i, out, start;
 418         unsigned long pages = 0;
 419
 420         if (nents == 0)
 421                 return 0;
 422
 423         if (!dev)
 424                 dev = &fallback_dev;
 425
 426         out = 0;
 427         start = 0;
 428         start_sg = sgmap = sg;
 429         ps = NULL; /* shut up gcc */
 430         for_each_sg(sg, s, nents, i) {
 431                 dma_addr_t addr = sg_phys(s);
 432
 433                 s->dma_address = addr;
 434                 BUG_ON(s->length == 0);
 435
 436                 nextneed = need_iommu(dev, addr, s->length);
 437
 438                 /* Handle the previous not yet processed entries */
 439                 if (i > start) {
 440                         /*
 441                          * Can only merge when the last chunk ends on a
 442                          * page boundary and the new one doesn't have an
 443                          * offset.
 444                          */
 445                         if (!iommu_merge || !nextneed || !need || s->offset ||
 446                             (ps->offset + ps->length) % PAGE_SIZE) {
 447                                 if (dma_map_cont(start_sg, i - start, sgmap,
 448                                                   pages, need) < 0)
 449                                         goto error;
 450                                 out++;
 451                                 sgmap = sg_next(sgmap);
 452                                 pages = 0;
 453                                 start = i;
 454                                 start_sg = s;
 455                         }
 456                 }
 457
 458                 need = nextneed;
 459                 pages += to_pages(s->offset, s->length);
 460                 ps = s;
 461         }
 462         if (dma_map_cont(start_sg, i - start, sgmap, pages, need) < 0)
 463                 goto error;
 464         out++;
 465         flush_gart();
 466         if (out < nents) {
 467                 sgmap = sg_next(sgmap);
 468                 sgmap->dma_length = 0;
 469         }
 470         return out;
 471
 472 error:
 473         flush_gart();
 474         gart_unmap_sg(dev, sg, out, dir);
 475
 476         /* When it was forced or merged try again in a dumb way */
 477         if (force_iommu || iommu_merge) {
 478                 out = dma_map_sg_nonforce(dev, sg, nents, dir);
 479                 if (out > 0)
 480                         return out;
 481         }
 482         if (panic_on_overflow)
 483                 panic("dma_map_sg: overflow on %lu pages\n", pages);
 484
 485         iommu_full(dev, pages << PAGE_SHIFT, dir);
 486         for_each_sg(sg, s, nents, i)
 487                 s->dma_address = bad_dma_address;
 488         return 0;
 489 }
 490
 491 static int no_agp;
 492
 493 static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
 494 {
 495         unsigned long a;
 496
 497         if (!iommu_size) {
 498                 iommu_size = aper_size;
 499                 if (!no_agp)
 500                         iommu_size /= 2;
 501         }
 502
 503         a = aper + iommu_size;
 504         iommu_size -= round_up(a, LARGE_PAGE_SIZE) - a;
 505
 506         if (iommu_size < 64*1024*1024) {
 507                 printk(KERN_WARNING
 508                         "PCI-DMA: Warning: Small IOMMU %luMB."
 509                         " Consider increasing the AGP aperture in BIOS\n",
 510                                 iommu_size >> 20);
 511         }
 512
 513         return iommu_size;
 514 }
 515
 516 static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
 517 {
 518         unsigned aper_size = 0, aper_base_32, aper_order;
 519         u64 aper_base;
 520
 521         pci_read_config_dword(dev, 0x94, &aper_base_32);
 522         pci_read_config_dword(dev, 0x90, &aper_order);
 523         aper_order = (aper_order >> 1) & 7;
 524
 525         aper_base = aper_base_32 & 0x7fff;
 526         aper_base <<= 25;
 527
 528         aper_size = (32 * 1024 * 1024) << aper_order;
 529         if (aper_base + aper_size > 0x100000000UL || !aper_size)
 530                 aper_base = 0;
 531
 532         *size = aper_size;
 533         return aper_base;
 534 }
 535
 536 /*
 537  * Private Northbridge GATT initialization in case we cannot use the
 538  * AGP driver for some reason.
 539  */
 540 static __init int init_k8_gatt(struct agp_kern_info *info)
 541 {
 542         unsigned aper_size, gatt_size, new_aper_size;
 543         unsigned aper_base, new_aper_base;
 544         struct pci_dev *dev;
 545         void *gatt;
 546         int i;
 547
 548         printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
 549         aper_size = aper_base = info->aper_size = 0;
 550         dev = NULL;
 551         for (i = 0; i < num_k8_northbridges; i++) {
 552                 dev = k8_northbridges[i];
 553                 new_aper_base = read_aperture(dev, &new_aper_size);
 554                 if (!new_aper_base)
 555                         goto nommu;
 556
 557                 if (!aper_base) {
 558                         aper_size = new_aper_size;
 559                         aper_base = new_aper_base;
 560                 }
 561                 if (aper_size != new_aper_size || aper_base != new_aper_base)
 562                         goto nommu;
 563         }
 564         if (!aper_base)
 565                 goto nommu;
 566         info->aper_base = aper_base;
 567         info->aper_size = aper_size >> 20;
 568
 569         gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
 570         gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size));
 571         if (!gatt)
 572                 panic("Cannot allocate GATT table");
 573         if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
 574                 panic("Could not set GART PTEs to uncacheable pages");
 575
 576         memset(gatt, 0, gatt_size);
 577         agp_gatt_table = gatt;
 578
 579         for (i = 0; i < num_k8_northbridges; i++) {
 580                 u32 gatt_reg;
 581                 u32 ctl;
 582
 583                 dev = k8_northbridges[i];
 584                 gatt_reg = __pa(gatt) >> 12;
 585                 gatt_reg <<= 4;
 586                 pci_write_config_dword(dev, 0x98, gatt_reg);
 587                 pci_read_config_dword(dev, 0x90, &ctl);
 588
 589                 ctl |= 1;
 590                 ctl &= ~((1<<4) | (1<<5));
 591
 592                 pci_write_config_dword(dev, 0x90, ctl);
 593         }
 594         flush_gart();
 595
 596         printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
 597                aper_base, aper_size>>10);
 598         return 0;
 599
 600  nommu:
 601         /* Should not happen anymore */
 602         printk(KERN_ERR "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
 603                KERN_ERR "PCI-DMA: 32bit PCI IO may malfunction.\n");
 604         return -1;
 605 }
 606
 607 extern int agp_amd64_init(void);
 608
 609 static const struct dma_mapping_ops gart_dma_ops = {
 610         .mapping_error                  = NULL,
 611         .map_single                     = gart_map_single,
 612         .map_simple                     = gart_map_simple,
 613         .unmap_single                   = gart_unmap_single,
 614         .sync_single_for_cpu            = NULL,
 615         .sync_single_for_device         = NULL,
 616         .sync_single_range_for_cpu      = NULL,
 617         .sync_single_range_for_device   = NULL,
 618         .sync_sg_for_cpu                = NULL,
 619         .sync_sg_for_device             = NULL,
 620         .map_sg                         = gart_map_sg,
 621         .unmap_sg                       = gart_unmap_sg,
 622 };
 623
 624 void gart_iommu_shutdown(void)
 625 {
 626         struct pci_dev *dev;
 627         int i;
 628
 629         if (no_agp && (dma_ops != &gart_dma_ops))
 630                 return;
 631
 632         for (i = 0; i < num_k8_northbridges; i++) {
 633                 u32 ctl;
 634
 635                 dev = k8_northbridges[i];
 636                 pci_read_config_dword(dev, 0x90, &ctl);
 637
 638                 ctl &= ~1;
 639
 640                 pci_write_config_dword(dev, 0x90, ctl);
 641         }
 642 }
 643
 644 void __init gart_iommu_init(void)
 645 {
 646         struct agp_kern_info info;
 647         unsigned long iommu_start;
 648         unsigned long aper_size;
 649         unsigned long scratch;
 650         long i;
 651
 652         if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) {
 653                 printk(KERN_INFO "PCI-GART: No AMD northbridge found.\n");
 654                 return;
 655         }
 656
 657 #ifndef CONFIG_AGP_AMD64
 658         no_agp = 1;
 659 #else
 660         /* Makefile puts PCI initialization via subsys_initcall first. */
 661         /* Add other K8 AGP bridge drivers here */
 662         no_agp = no_agp ||
 663                 (agp_amd64_init() < 0) ||
 664                 (agp_copy_info(agp_bridge, &info) < 0);
 665 #endif
 666
 667         if (swiotlb)
 668                 return;
 669
 670         /* Did we detect a different HW IOMMU? */
 671         if (iommu_detected && !gart_iommu_aperture)
 672                 return;
 673
 674         if (no_iommu ||
 675             (!force_iommu && end_pfn <= MAX_DMA32_PFN) ||
 676             !gart_iommu_aperture ||
 677             (no_agp && init_k8_gatt(&info) < 0)) {
 678                 if (end_pfn > MAX_DMA32_PFN) {
 679                         printk(KERN_ERR "WARNING more than 4GB of memory "
 680                                         "but GART IOMMU not available.\n"
 681                                KERN_ERR "WARNING 32bit PCI may malfunction.\n");
 682                 }
 683                 return;
 684         }
 685
 686         printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
 687         aper_size = info.aper_size * 1024 * 1024;
 688         iommu_size = check_iommu_size(info.aper_base, aper_size);
 689         iommu_pages = iommu_size >> PAGE_SHIFT;
 690
 691         iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL,
 692                                                       get_order(iommu_pages/8));
 693         if (!iommu_gart_bitmap)
 694                 panic("Cannot allocate iommu bitmap\n");
 695         memset(iommu_gart_bitmap, 0, iommu_pages/8);
 696
 697 #ifdef CONFIG_IOMMU_LEAK
 698         if (leak_trace) {
 699                 iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL,
 700                                   get_order(iommu_pages*sizeof(void *)));
 701                 if (iommu_leak_tab)
 702                         memset(iommu_leak_tab, 0, iommu_pages * 8);
 703                 else
 704                         printk(KERN_DEBUG
 705                                "PCI-DMA: Cannot allocate leak trace area\n");
 706         }
 707 #endif
 708
 709         /*
 710          * Out of IOMMU space handling.
 711          * Reserve some invalid pages at the beginning of the GART.
 712          */
 713         set_bit_string(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
 714
 715         agp_memory_reserved = iommu_size;
 716         printk(KERN_INFO
 717                "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
 718                iommu_size >> 20);
 719
 720         iommu_start = aper_size - iommu_size;
 721         iommu_bus_base = info.aper_base + iommu_start;
 722         bad_dma_address = iommu_bus_base;
 723         iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
 724
 725         /*
 726          * Unmap the IOMMU part of the GART. The alias of the page is
 727          * always mapped with cache enabled and there is no full cache
 728          * coherency across the GART remapping. The unmapping avoids
 729          * automatic prefetches from the CPU allocating cache lines in
 730          * there. All CPU accesses are done via the direct mapping to
 731          * the backing memory. The GART address is only used by PCI
 732          * devices.
 733          */
 734         clear_kernel_mapping((unsigned long)__va(iommu_bus_base), iommu_size);
 735
 736         /*
 737          * Try to workaround a bug (thanks to BenH)
 738          * Set unmapped entries to a scratch page instead of 0.
 739          * Any prefetches that hit unmapped entries won't get an bus abort
 740          * then.
 741          */
 742         scratch = get_zeroed_page(GFP_KERNEL);
 743         if (!scratch)
 744                 panic("Cannot allocate iommu scratch page");
 745         gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
 746         for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
 747                 iommu_gatt_base[i] = gart_unmapped_entry;
 748
 749         flush_gart();
 750         dma_ops = &gart_dma_ops;
 751 }
 752
 753 void __init gart_parse_options(char *p)
 754 {
 755         int arg;
 756
 757 #ifdef CONFIG_IOMMU_LEAK
 758         if (!strncmp(p, "leak", 4)) {
 759                 leak_trace = 1;
 760                 p += 4;
 761                 if (*p == '=') ++p;
 762                 if (isdigit(*p) && get_option(&p, &arg))
 763                         iommu_leak_pages = arg;
 764         }
 765 #endif
 766         if (isdigit(*p) && get_option(&p, &arg))
 767                 iommu_size = arg;
 768         if (!strncmp(p, "fullflush", 8))
 769                 iommu_fullflush = 1;
 770         if (!strncmp(p, "nofullflush", 11))
 771                 iommu_fullflush = 0;
 772         if (!strncmp(p, "noagp", 5))
 773                 no_agp = 1;
 774         if (!strncmp(p, "noaperture", 10))
 775                 fix_aperture = 0;
 776         /* duplicated from pci-dma.c */
 777         if (!strncmp(p, "force", 5))
 778                 gart_iommu_aperture_allowed = 1;
 779         if (!strncmp(p, "allowed", 7))
 780                 gart_iommu_aperture_allowed = 1;
 781         if (!strncmp(p, "memaper", 7)) {
 782                 fallback_aper_force = 1;
 783                 p += 7;
 784                 if (*p == '=') {
 785                         ++p;
 786                         if (get_option(&p, &arg))
 787                                 fallback_aper_order = arg;
 788                 }
 789         }
 790 }