arch/x86/kernel/process.c

   1 #include <linux/errno.h>
   2 #include <linux/kernel.h>
   3 #include <linux/mm.h>
   4 #include <linux/smp.h>
   5 #include <linux/prctl.h>
   6 #include <linux/slab.h>
   7 #include <linux/sched.h>
   8 #include <linux/module.h>
   9 #include <linux/pm.h>
  10 #include <linux/clockchips.h>
  11 #include <linux/random.h>
  12 #include <linux/user-return-notifier.h>
  13 #include <linux/dmi.h>
  14 #include <linux/utsname.h>
  15 #include <trace/events/power.h>
  16 #include <linux/hw_breakpoint.h>
  17 #include <asm/system.h>
  18 #include <asm/apic.h>
  19 #include <asm/syscalls.h>
  20 #include <asm/idle.h>
  21 #include <asm/uaccess.h>
  22 #include <asm/i387.h>
  23 #include <asm/ds.h>
  24 #include <asm/debugreg.h>
  25
  26 unsigned long idle_halt;
  27 EXPORT_SYMBOL(idle_halt);
  28 unsigned long idle_nomwait;
  29 EXPORT_SYMBOL(idle_nomwait);
  30
  31 struct kmem_cache *task_xstate_cachep;
  32
  33 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  34 {
  35         *dst = *src;
  36         if (src->thread.xstate) {
  37                 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
  38                                                       GFP_KERNEL);
  39                 if (!dst->thread.xstate)
  40                         return -ENOMEM;
  41                 WARN_ON((unsigned long)dst->thread.xstate & 15);
  42                 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
  43         }
  44         return 0;
  45 }
  46
  47 void free_thread_xstate(struct task_struct *tsk)
  48 {
  49         if (tsk->thread.xstate) {
  50                 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
  51                 tsk->thread.xstate = NULL;
  52         }
  53
  54         WARN(tsk->thread.ds_ctx, "leaking DS context\n");
  55 }
  56
  57 void free_thread_info(struct thread_info *ti)
  58 {
  59         free_thread_xstate(ti->task);
  60         free_pages((unsigned long)ti, get_order(THREAD_SIZE));
  61 }
  62
  63 void arch_task_cache_init(void)
  64 {
  65         task_xstate_cachep =
  66                 kmem_cache_create("task_xstate", xstate_size,
  67                                   __alignof__(union thread_xstate),
  68                                   SLAB_PANIC | SLAB_NOTRACK, NULL);
  69 }
  70
  71 /*
  72  * Free current thread data structures etc..
  73  */
  74 void exit_thread(void)
  75 {
  76         struct task_struct *me = current;
  77         struct thread_struct *t = &me->thread;
  78         unsigned long *bp = t->io_bitmap_ptr;
  79
  80         if (bp) {
  81                 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
  82
  83                 t->io_bitmap_ptr = NULL;
  84                 clear_thread_flag(TIF_IO_BITMAP);
  85                 /*
  86                  * Careful, clear this in the TSS too:
  87                  */
  88                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
  89                 t->io_bitmap_max = 0;
  90                 put_cpu();
  91                 kfree(bp);
  92         }
  93 }
  94
  95 void show_regs_common(void)
  96 {
  97         const char *board, *product;
  98
  99         board = dmi_get_system_info(DMI_BOARD_NAME);
 100         if (!board)
 101                 board = "";
 102         product = dmi_get_system_info(DMI_PRODUCT_NAME);
 103         if (!product)
 104                 product = "";
 105
 106         printk(KERN_CONT "\n");
 107         printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s/%s\n",
 108                 current->pid, current->comm, print_tainted(),
 109                 init_utsname()->release,
 110                 (int)strcspn(init_utsname()->version, " "),
 111                 init_utsname()->version, board, product);
 112 }
 113
 114 void flush_thread(void)
 115 {
 116         struct task_struct *tsk = current;
 117
 118 #ifdef CONFIG_X86_64
 119         if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
 120                 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
 121                 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
 122                         clear_tsk_thread_flag(tsk, TIF_IA32);
 123                 } else {
 124                         set_tsk_thread_flag(tsk, TIF_IA32);
 125                         current_thread_info()->status |= TS_COMPAT;
 126                 }
 127         }
 128 #endif
 129
 130         flush_ptrace_hw_breakpoint(tsk);
 131         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 132         /*
 133          * Forget coprocessor state..
 134          */
 135         tsk->fpu_counter = 0;
 136         clear_fpu(tsk);
 137         clear_used_math();
 138 }
 139
 140 static void hard_disable_TSC(void)
 141 {
 142         write_cr4(read_cr4() | X86_CR4_TSD);
 143 }
 144
 145 void disable_TSC(void)
 146 {
 147         preempt_disable();
 148         if (!test_and_set_thread_flag(TIF_NOTSC))
 149                 /*
 150                  * Must flip the CPU state synchronously with
 151                  * TIF_NOTSC in the current running context.
 152                  */
 153                 hard_disable_TSC();
 154         preempt_enable();
 155 }
 156
 157 static void hard_enable_TSC(void)
 158 {
 159         write_cr4(read_cr4() & ~X86_CR4_TSD);
 160 }
 161
 162 static void enable_TSC(void)
 163 {
 164         preempt_disable();
 165         if (test_and_clear_thread_flag(TIF_NOTSC))
 166                 /*
 167                  * Must flip the CPU state synchronously with
 168                  * TIF_NOTSC in the current running context.
 169                  */
 170                 hard_enable_TSC();
 171         preempt_enable();
 172 }
 173
 174 int get_tsc_mode(unsigned long adr)
 175 {
 176         unsigned int val;
 177
 178         if (test_thread_flag(TIF_NOTSC))
 179                 val = PR_TSC_SIGSEGV;
 180         else
 181                 val = PR_TSC_ENABLE;
 182
 183         return put_user(val, (unsigned int __user *)adr);
 184 }
 185
 186 int set_tsc_mode(unsigned int val)
 187 {
 188         if (val == PR_TSC_SIGSEGV)
 189                 disable_TSC();
 190         else if (val == PR_TSC_ENABLE)
 191                 enable_TSC();
 192         else
 193                 return -EINVAL;
 194
 195         return 0;
 196 }
 197
 198 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 199                       struct tss_struct *tss)
 200 {
 201         struct thread_struct *prev, *next;
 202
 203         prev = &prev_p->thread;
 204         next = &next_p->thread;
 205
 206         if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
 207             test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
 208                 ds_switch_to(prev_p, next_p);
 209         else if (next->debugctlmsr != prev->debugctlmsr)
 210                 update_debugctlmsr(next->debugctlmsr);
 211
 212         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
 213             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
 214                 /* prev and next are different */
 215                 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
 216                         hard_disable_TSC();
 217                 else
 218                         hard_enable_TSC();
 219         }
 220
 221         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
 222                 /*
 223                  * Copy the relevant range of the IO bitmap.
 224                  * Normally this is 128 bytes or less:
 225                  */
 226                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 227                        max(prev->io_bitmap_max, next->io_bitmap_max));
 228         } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
 229                 /*
 230                  * Clear any possible leftover bits:
 231                  */
 232                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 233         }
 234         propagate_user_return_notify(prev_p, next_p);
 235 }
 236
 237 int sys_fork(struct pt_regs *regs)
 238 {
 239         return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
 240 }
 241
 242 /*
 243  * This is trivial, and on the face of it looks like it
 244  * could equally well be done in user mode.
 245  *
 246  * Not so, for quite unobvious reasons - register pressure.
 247  * In user mode vfork() cannot have a stack frame, and if
 248  * done by calling the "clone()" system call directly, you
 249  * do not have enough call-clobbered registers to hold all
 250  * the information you need.
 251  */
 252 int sys_vfork(struct pt_regs *regs)
 253 {
 254         return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
 255                        NULL, NULL);
 256 }
 257
 258 long
 259 sys_clone(unsigned long clone_flags, unsigned long newsp,
 260           void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
 261 {
 262         if (!newsp)
 263                 newsp = regs->sp;
 264         return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
 265 }
 266
 267 /*
 268  * This gets run with %si containing the
 269  * function to call, and %di containing
 270  * the "args".
 271  */
 272 extern void kernel_thread_helper(void);
 273
 274 /*
 275  * Create a kernel thread
 276  */
 277 int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
 278 {
 279         struct pt_regs regs;
 280
 281         memset(&regs, 0, sizeof(regs));
 282
 283         regs.si = (unsigned long) fn;
 284         regs.di = (unsigned long) arg;
 285
 286 #ifdef CONFIG_X86_32
 287         regs.ds = __USER_DS;
 288         regs.es = __USER_DS;
 289         regs.fs = __KERNEL_PERCPU;
 290         regs.gs = __KERNEL_STACK_CANARY;
 291 #else
 292         regs.ss = __KERNEL_DS;
 293 #endif
 294
 295         regs.orig_ax = -1;
 296         regs.ip = (unsigned long) kernel_thread_helper;
 297         regs.cs = __KERNEL_CS | get_kernel_rpl();
 298         regs.flags = X86_EFLAGS_IF | 0x2;
 299
 300         /* Ok, create the new process.. */
 301         return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
 302 }
 303 EXPORT_SYMBOL(kernel_thread);
 304
 305 /*
 306  * sys_execve() executes a new program.
 307  */
 308 long sys_execve(char __user *name, char __user * __user *argv,
 309                 char __user * __user *envp, struct pt_regs *regs)
 310 {
 311         long error;
 312         char *filename;
 313
 314         filename = getname(name);
 315         error = PTR_ERR(filename);
 316         if (IS_ERR(filename))
 317                 return error;
 318         error = do_execve(filename, argv, envp, regs);
 319
 320 #ifdef CONFIG_X86_32
 321         if (error == 0) {
 322                 /* Make sure we don't return using sysenter.. */
 323                 set_thread_flag(TIF_IRET);
 324         }
 325 #endif
 326
 327         putname(filename);
 328         return error;
 329 }
 330
 331 /*
 332  * Idle related variables and functions
 333  */
 334 unsigned long boot_option_idle_override = 0;
 335 EXPORT_SYMBOL(boot_option_idle_override);
 336
 337 /*
 338  * Powermanagement idle function, if any..
 339  */
 340 void (*pm_idle)(void);
 341 EXPORT_SYMBOL(pm_idle);
 342
 343 #ifdef CONFIG_X86_32
 344 /*
 345  * This halt magic was a workaround for ancient floppy DMA
 346  * wreckage. It should be safe to remove.
 347  */
 348 static int hlt_counter;
 349 void disable_hlt(void)
 350 {
 351         hlt_counter++;
 352 }
 353 EXPORT_SYMBOL(disable_hlt);
 354
 355 void enable_hlt(void)
 356 {
 357         hlt_counter--;
 358 }
 359 EXPORT_SYMBOL(enable_hlt);
 360
 361 static inline int hlt_use_halt(void)
 362 {
 363         return (!hlt_counter && boot_cpu_data.hlt_works_ok);
 364 }
 365 #else
 366 static inline int hlt_use_halt(void)
 367 {
 368         return 1;
 369 }
 370 #endif
 371
 372 /*
 373  * We use this if we don't have any better
 374  * idle routine..
 375  */
 376 void default_idle(void)
 377 {
 378         if (hlt_use_halt()) {
 379                 trace_power_start(POWER_CSTATE, 1);
 380                 current_thread_info()->status &= ~TS_POLLING;
 381                 /*
 382                  * TS_POLLING-cleared state must be visible before we
 383                  * test NEED_RESCHED:
 384                  */
 385                 smp_mb();
 386
 387                 if (!need_resched())
 388                         safe_halt();    /* enables interrupts racelessly */
 389                 else
 390                         local_irq_enable();
 391                 current_thread_info()->status |= TS_POLLING;
 392         } else {
 393                 local_irq_enable();
 394                 /* loop is done by the caller */
 395                 cpu_relax();
 396         }
 397 }
 398 #ifdef CONFIG_APM_MODULE
 399 EXPORT_SYMBOL(default_idle);
 400 #endif
 401
 402 void stop_this_cpu(void *dummy)
 403 {
 404         local_irq_disable();
 405         /*
 406          * Remove this CPU:
 407          */
 408         set_cpu_online(smp_processor_id(), false);
 409         disable_local_APIC();
 410
 411         for (;;) {
 412                 if (hlt_works(smp_processor_id()))
 413                         halt();
 414         }
 415 }
 416
 417 static void do_nothing(void *unused)
 418 {
 419 }
 420
 421 /*
 422  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
 423  * pm_idle and update to new pm_idle value. Required while changing pm_idle
 424  * handler on SMP systems.
 425  *
 426  * Caller must have changed pm_idle to the new value before the call. Old
 427  * pm_idle value will not be used by any CPU after the return of this function.
 428  */
 429 void cpu_idle_wait(void)
 430 {
 431         smp_mb();
 432         /* kick all the CPUs so that they exit out of pm_idle */
 433         smp_call_function(do_nothing, NULL, 1);
 434 }
 435 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 436
 437 /*
 438  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 439  * which can obviate IPI to trigger checking of need_resched.
 440  * We execute MONITOR against need_resched and enter optimized wait state
 441  * through MWAIT. Whenever someone changes need_resched, we would be woken
 442  * up from MWAIT (without an IPI).
 443  *
 444  * New with Core Duo processors, MWAIT can take some hints based on CPU
 445  * capability.
 446  */
 447 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 448 {
 449         trace_power_start(POWER_CSTATE, (ax>>4)+1);
 450         if (!need_resched()) {
 451                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 452                         clflush((void *)&current_thread_info()->flags);
 453
 454                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 455                 smp_mb();
 456                 if (!need_resched())
 457                         __mwait(ax, cx);
 458         }
 459 }
 460
 461 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
 462 static void mwait_idle(void)
 463 {
 464         if (!need_resched()) {
 465                 trace_power_start(POWER_CSTATE, 1);
 466                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 467                         clflush((void *)&current_thread_info()->flags);
 468
 469                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 470                 smp_mb();
 471                 if (!need_resched())
 472                         __sti_mwait(0, 0);
 473                 else
 474                         local_irq_enable();
 475         } else
 476                 local_irq_enable();
 477 }
 478
 479 /*
 480  * On SMP it's slightly faster (but much more power-consuming!)
 481  * to poll the ->work.need_resched flag instead of waiting for the
 482  * cross-CPU IPI to arrive. Use this option with caution.
 483  */
 484 static void poll_idle(void)
 485 {
 486         trace_power_start(POWER_CSTATE, 0);
 487         local_irq_enable();
 488         while (!need_resched())
 489                 cpu_relax();
 490         trace_power_end(0);
 491 }
 492
 493 /*
 494  * mwait selection logic:
 495  *
 496  * It depends on the CPU. For AMD CPUs that support MWAIT this is
 497  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 498  * then depend on a clock divisor and current Pstate of the core. If
 499  * all cores of a processor are in halt state (C1) the processor can
 500  * enter the C1E (C1 enhanced) state. If mwait is used this will never
 501  * happen.
 502  *
 503  * idle=mwait overrides this decision and forces the usage of mwait.
 504  */
 505 static int __cpuinitdata force_mwait;
 506
 507 #define MWAIT_INFO                      0x05
 508 #define MWAIT_ECX_EXTENDED_INFO         0x01
 509 #define MWAIT_EDX_C1                    0xf0
 510
 511 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
 512 {
 513         u32 eax, ebx, ecx, edx;
 514
 515         if (force_mwait)
 516                 return 1;
 517
 518         if (c->cpuid_level < MWAIT_INFO)
 519                 return 0;
 520
 521         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
 522         /* Check, whether EDX has extended info about MWAIT */
 523         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
 524                 return 1;
 525
 526         /*
 527          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
 528          * C1  supports MWAIT
 529          */
 530         return (edx & MWAIT_EDX_C1);
 531 }
 532
 533 /*
 534  * Check for AMD CPUs, which have potentially C1E support
 535  */
 536 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
 537 {
 538         if (c->x86_vendor != X86_VENDOR_AMD)
 539                 return 0;
 540
 541         if (c->x86 < 0x0F)
 542                 return 0;
 543
 544         /* Family 0x0f models < rev F do not have C1E */
 545         if (c->x86 == 0x0f && c->x86_model < 0x40)
 546                 return 0;
 547
 548         return 1;
 549 }
 550
 551 static cpumask_var_t c1e_mask;
 552 static int c1e_detected;
 553
 554 void c1e_remove_cpu(int cpu)
 555 {
 556         if (c1e_mask != NULL)
 557                 cpumask_clear_cpu(cpu, c1e_mask);
 558 }
 559
 560 /*
 561  * C1E aware idle routine. We check for C1E active in the interrupt
 562  * pending message MSR. If we detect C1E, then we handle it the same
 563  * way as C3 power states (local apic timer and TSC stop)
 564  */
 565 static void c1e_idle(void)
 566 {
 567         if (need_resched())
 568                 return;
 569
 570         if (!c1e_detected) {
 571                 u32 lo, hi;
 572
 573                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 574                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
 575                         c1e_detected = 1;
 576                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 577                                 mark_tsc_unstable("TSC halt in AMD C1E");
 578                         printk(KERN_INFO "System has AMD C1E enabled\n");
 579                         set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
 580                 }
 581         }
 582
 583         if (c1e_detected) {
 584                 int cpu = smp_processor_id();
 585
 586                 if (!cpumask_test_cpu(cpu, c1e_mask)) {
 587                         cpumask_set_cpu(cpu, c1e_mask);
 588                         /*
 589                          * Force broadcast so ACPI can not interfere.
 590                          */
 591                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
 592                                            &cpu);
 593                         printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
 594                                cpu);
 595                 }
 596                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 597
 598                 default_idle();
 599
 600                 /*
 601                  * The switch back from broadcast mode needs to be
 602                  * called with interrupts disabled.
 603                  */
 604                  local_irq_disable();
 605                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 606                  local_irq_enable();
 607         } else
 608                 default_idle();
 609 }
 610
 611 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 612 {
 613 #ifdef CONFIG_SMP
 614         if (pm_idle == poll_idle && smp_num_siblings > 1) {
 615                 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
 616                         " performance may degrade.\n");
 617         }
 618 #endif
 619         if (pm_idle)
 620                 return;
 621
 622         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
 623                 /*
 624                  * One CPU supports mwait => All CPUs supports mwait
 625                  */
 626                 printk(KERN_INFO "using mwait in idle threads.\n");
 627                 pm_idle = mwait_idle;
 628         } else if (check_c1e_idle(c)) {
 629                 printk(KERN_INFO "using C1E aware idle routine\n");
 630                 pm_idle = c1e_idle;
 631         } else
 632                 pm_idle = default_idle;
 633 }
 634
 635 void __init init_c1e_mask(void)
 636 {
 637         /* If we're using c1e_idle, we need to allocate c1e_mask. */
 638         if (pm_idle == c1e_idle)
 639                 zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
 640 }
 641
 642 static int __init idle_setup(char *str)
 643 {
 644         if (!str)
 645                 return -EINVAL;
 646
 647         if (!strcmp(str, "poll")) {
 648                 printk("using polling idle threads.\n");
 649                 pm_idle = poll_idle;
 650         } else if (!strcmp(str, "mwait"))
 651                 force_mwait = 1;
 652         else if (!strcmp(str, "halt")) {
 653                 /*
 654                  * When the boot option of idle=halt is added, halt is
 655                  * forced to be used for CPU idle. In such case CPU C2/C3
 656                  * won't be used again.
 657                  * To continue to load the CPU idle driver, don't touch
 658                  * the boot_option_idle_override.
 659                  */
 660                 pm_idle = default_idle;
 661                 idle_halt = 1;
 662                 return 0;
 663         } else if (!strcmp(str, "nomwait")) {
 664                 /*
 665                  * If the boot option of "idle=nomwait" is added,
 666                  * it means that mwait will be disabled for CPU C2/C3
 667                  * states. In such case it won't touch the variable
 668                  * of boot_option_idle_override.
 669                  */
 670                 idle_nomwait = 1;
 671                 return 0;
 672         } else
 673                 return -1;
 674
 675         boot_option_idle_override = 1;
 676         return 0;
 677 }
 678 early_param("idle", idle_setup);
 679
 680 unsigned long arch_align_stack(unsigned long sp)
 681 {
 682         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 683                 sp -= get_random_int() % 8192;
 684         return sp & ~0xf;
 685 }
 686
 687 unsigned long arch_randomize_brk(struct mm_struct *mm)
 688 {
 689         unsigned long range_end = mm->brk + 0x02000000;
 690         return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
 691 }
 692