arch/x86/kernel/process.c

   1 #include <linux/errno.h>
   2 #include <linux/kernel.h>
   3 #include <linux/mm.h>
   4 #include <linux/smp.h>
   5 #include <linux/slab.h>
   6 #include <linux/sched.h>
   7 #include <linux/module.h>
   8 #include <linux/pm.h>
   9 #include <linux/clockchips.h>
  10 #include <asm/system.h>
  11
  12 unsigned long idle_halt;
  13 EXPORT_SYMBOL(idle_halt);
  14
  15 struct kmem_cache *task_xstate_cachep;
  16
  17 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  18 {
  19         *dst = *src;
  20         if (src->thread.xstate) {
  21                 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
  22                                                       GFP_KERNEL);
  23                 if (!dst->thread.xstate)
  24                         return -ENOMEM;
  25                 WARN_ON((unsigned long)dst->thread.xstate & 15);
  26                 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
  27         }
  28         return 0;
  29 }
  30
  31 void free_thread_xstate(struct task_struct *tsk)
  32 {
  33         if (tsk->thread.xstate) {
  34                 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
  35                 tsk->thread.xstate = NULL;
  36         }
  37 }
  38
  39 void free_thread_info(struct thread_info *ti)
  40 {
  41         free_thread_xstate(ti->task);
  42         free_pages((unsigned long)ti, get_order(THREAD_SIZE));
  43 }
  44
  45 void arch_task_cache_init(void)
  46 {
  47         task_xstate_cachep =
  48                 kmem_cache_create("task_xstate", xstate_size,
  49                                   __alignof__(union thread_xstate),
  50                                   SLAB_PANIC, NULL);
  51 }
  52
  53 /*
  54  * Idle related variables and functions
  55  */
  56 unsigned long boot_option_idle_override = 0;
  57 EXPORT_SYMBOL(boot_option_idle_override);
  58
  59 /*
  60  * Powermanagement idle function, if any..
  61  */
  62 void (*pm_idle)(void);
  63 EXPORT_SYMBOL(pm_idle);
  64
  65 #ifdef CONFIG_X86_32
  66 /*
  67  * This halt magic was a workaround for ancient floppy DMA
  68  * wreckage. It should be safe to remove.
  69  */
  70 static int hlt_counter;
  71 void disable_hlt(void)
  72 {
  73         hlt_counter++;
  74 }
  75 EXPORT_SYMBOL(disable_hlt);
  76
  77 void enable_hlt(void)
  78 {
  79         hlt_counter--;
  80 }
  81 EXPORT_SYMBOL(enable_hlt);
  82
  83 static inline int hlt_use_halt(void)
  84 {
  85         return (!hlt_counter && boot_cpu_data.hlt_works_ok);
  86 }
  87 #else
  88 static inline int hlt_use_halt(void)
  89 {
  90         return 1;
  91 }
  92 #endif
  93
  94 /*
  95  * We use this if we don't have any better
  96  * idle routine..
  97  */
  98 void default_idle(void)
  99 {
 100         if (hlt_use_halt()) {
 101                 current_thread_info()->status &= ~TS_POLLING;
 102                 /*
 103                  * TS_POLLING-cleared state must be visible before we
 104                  * test NEED_RESCHED:
 105                  */
 106                 smp_mb();
 107
 108                 if (!need_resched())
 109                         safe_halt();    /* enables interrupts racelessly */
 110                 else
 111                         local_irq_enable();
 112                 current_thread_info()->status |= TS_POLLING;
 113         } else {
 114                 local_irq_enable();
 115                 /* loop is done by the caller */
 116                 cpu_relax();
 117         }
 118 }
 119 #ifdef CONFIG_APM_MODULE
 120 EXPORT_SYMBOL(default_idle);
 121 #endif
 122
 123 static void do_nothing(void *unused)
 124 {
 125 }
 126
 127 /*
 128  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
 129  * pm_idle and update to new pm_idle value. Required while changing pm_idle
 130  * handler on SMP systems.
 131  *
 132  * Caller must have changed pm_idle to the new value before the call. Old
 133  * pm_idle value will not be used by any CPU after the return of this function.
 134  */
 135 void cpu_idle_wait(void)
 136 {
 137         smp_mb();
 138         /* kick all the CPUs so that they exit out of pm_idle */
 139         smp_call_function(do_nothing, NULL, 1);
 140 }
 141 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 142
 143 /*
 144  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 145  * which can obviate IPI to trigger checking of need_resched.
 146  * We execute MONITOR against need_resched and enter optimized wait state
 147  * through MWAIT. Whenever someone changes need_resched, we would be woken
 148  * up from MWAIT (without an IPI).
 149  *
 150  * New with Core Duo processors, MWAIT can take some hints based on CPU
 151  * capability.
 152  */
 153 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 154 {
 155         if (!need_resched()) {
 156                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 157                 smp_mb();
 158                 if (!need_resched())
 159                         __mwait(ax, cx);
 160         }
 161 }
 162
 163 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
 164 static void mwait_idle(void)
 165 {
 166         if (!need_resched()) {
 167                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 168                 smp_mb();
 169                 if (!need_resched())
 170                         __sti_mwait(0, 0);
 171                 else
 172                         local_irq_enable();
 173         } else
 174                 local_irq_enable();
 175 }
 176
 177 /*
 178  * On SMP it's slightly faster (but much more power-consuming!)
 179  * to poll the ->work.need_resched flag instead of waiting for the
 180  * cross-CPU IPI to arrive. Use this option with caution.
 181  */
 182 static void poll_idle(void)
 183 {
 184         local_irq_enable();
 185         cpu_relax();
 186 }
 187
 188 /*
 189  * mwait selection logic:
 190  *
 191  * It depends on the CPU. For AMD CPUs that support MWAIT this is
 192  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 193  * then depend on a clock divisor and current Pstate of the core. If
 194  * all cores of a processor are in halt state (C1) the processor can
 195  * enter the C1E (C1 enhanced) state. If mwait is used this will never
 196  * happen.
 197  *
 198  * idle=mwait overrides this decision and forces the usage of mwait.
 199  */
 200
 201 #define MWAIT_INFO                      0x05
 202 #define MWAIT_ECX_EXTENDED_INFO         0x01
 203 #define MWAIT_EDX_C1                    0xf0
 204
 205 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
 206 {
 207         u32 eax, ebx, ecx, edx;
 208
 209         if (force_mwait)
 210                 return 1;
 211
 212         if (c->cpuid_level < MWAIT_INFO)
 213                 return 0;
 214
 215         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
 216         /* Check, whether EDX has extended info about MWAIT */
 217         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
 218                 return 1;
 219
 220         /*
 221          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
 222          * C1  supports MWAIT
 223          */
 224         return (edx & MWAIT_EDX_C1);
 225 }
 226
 227 /*
 228  * Check for AMD CPUs, which have potentially C1E support
 229  */
 230 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
 231 {
 232         if (c->x86_vendor != X86_VENDOR_AMD)
 233                 return 0;
 234
 235         if (c->x86 < 0x0F)
 236                 return 0;
 237
 238         /* Family 0x0f models < rev F do not have C1E */
 239         if (c->x86 == 0x0f && c->x86_model < 0x40)
 240                 return 0;
 241
 242         return 1;
 243 }
 244
 245 /*
 246  * C1E aware idle routine. We check for C1E active in the interrupt
 247  * pending message MSR. If we detect C1E, then we handle it the same
 248  * way as C3 power states (local apic timer and TSC stop)
 249  */
 250 static void c1e_idle(void)
 251 {
 252         static cpumask_t c1e_mask = CPU_MASK_NONE;
 253         static int c1e_detected;
 254
 255         if (need_resched())
 256                 return;
 257
 258         if (!c1e_detected) {
 259                 u32 lo, hi;
 260
 261                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 262                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
 263                         c1e_detected = 1;
 264                         mark_tsc_unstable("TSC halt in C1E");
 265                         printk(KERN_INFO "System has C1E enabled\n");
 266                 }
 267         }
 268
 269         if (c1e_detected) {
 270                 int cpu = smp_processor_id();
 271
 272                 if (!cpu_isset(cpu, c1e_mask)) {
 273                         cpu_set(cpu, c1e_mask);
 274                         /*
 275                          * Force broadcast so ACPI can not interfere. Needs
 276                          * to run with interrupts enabled as it uses
 277                          * smp_function_call.
 278                          */
 279                         local_irq_enable();
 280                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
 281                                            &cpu);
 282                         printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
 283                                cpu);
 284                         local_irq_disable();
 285                 }
 286                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 287
 288                 default_idle();
 289
 290                 /*
 291                  * The switch back from broadcast mode needs to be
 292                  * called with interrupts disabled.
 293                  */
 294                  local_irq_disable();
 295                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 296                  local_irq_enable();
 297         } else
 298                 default_idle();
 299 }
 300
 301 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 302 {
 303 #ifdef CONFIG_X86_SMP
 304         if (pm_idle == poll_idle && smp_num_siblings > 1) {
 305                 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
 306                         " performance may degrade.\n");
 307         }
 308 #endif
 309         if (pm_idle)
 310                 return;
 311
 312         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
 313                 /*
 314                  * One CPU supports mwait => All CPUs supports mwait
 315                  */
 316                 printk(KERN_INFO "using mwait in idle threads.\n");
 317                 pm_idle = mwait_idle;
 318         } else if (check_c1e_idle(c)) {
 319                 printk(KERN_INFO "using C1E aware idle routine\n");
 320                 pm_idle = c1e_idle;
 321         } else
 322                 pm_idle = default_idle;
 323 }
 324
 325 static int __init idle_setup(char *str)
 326 {
 327         if (!strcmp(str, "poll")) {
 328                 printk("using polling idle threads.\n");
 329                 pm_idle = poll_idle;
 330         } else if (!strcmp(str, "mwait"))
 331                 force_mwait = 1;
 332         else if (!strcmp(str, "halt")) {
 333                 /*
 334                  * When the boot option of idle=halt is added, halt is
 335                  * forced to be used for CPU idle. In such case CPU C2/C3
 336                  * won't be used again.
 337                  * To continue to load the CPU idle driver, don't touch
 338                  * the boot_option_idle_override.
 339                  */
 340                 pm_idle = default_idle;
 341                 idle_halt = 1;
 342                 return 0;
 343         } else
 344                 return -1;
 345
 346         boot_option_idle_override = 1;
 347         return 0;
 348 }
 349 early_param("idle", idle_setup);
 350