arch/x86/kernel/process.c

   1 #include <linux/errno.h>
   2 #include <linux/kernel.h>
   3 #include <linux/mm.h>
   4 #include <asm/idle.h>
   5 #include <linux/smp.h>
   6 #include <linux/slab.h>
   7 #include <linux/sched.h>
   8 #include <linux/module.h>
   9 #include <linux/pm.h>
  10 #include <linux/clockchips.h>
  11 #include <linux/ftrace.h>
  12 #include <asm/system.h>
  13 #include <asm/apic.h>
  14
  15 unsigned long idle_halt;
  16 EXPORT_SYMBOL(idle_halt);
  17 unsigned long idle_nomwait;
  18 EXPORT_SYMBOL(idle_nomwait);
  19
  20 struct kmem_cache *task_xstate_cachep;
  21
  22 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  23 {
  24         *dst = *src;
  25         if (src->thread.xstate) {
  26                 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
  27                                                       GFP_KERNEL);
  28                 if (!dst->thread.xstate)
  29                         return -ENOMEM;
  30                 WARN_ON((unsigned long)dst->thread.xstate & 15);
  31                 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
  32         }
  33         return 0;
  34 }
  35
  36 void free_thread_xstate(struct task_struct *tsk)
  37 {
  38         if (tsk->thread.xstate) {
  39                 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
  40                 tsk->thread.xstate = NULL;
  41         }
  42 }
  43
  44 void free_thread_info(struct thread_info *ti)
  45 {
  46         free_thread_xstate(ti->task);
  47         free_pages((unsigned long)ti, get_order(THREAD_SIZE));
  48 }
  49
  50 void arch_task_cache_init(void)
  51 {
  52         task_xstate_cachep =
  53                 kmem_cache_create("task_xstate", xstate_size,
  54                                   __alignof__(union thread_xstate),
  55                                   SLAB_PANIC, NULL);
  56 }
  57
  58 /*
  59  * Idle related variables and functions
  60  */
  61 unsigned long boot_option_idle_override = 0;
  62 EXPORT_SYMBOL(boot_option_idle_override);
  63
  64 /*
  65  * Powermanagement idle function, if any..
  66  */
  67 void (*pm_idle)(void);
  68 EXPORT_SYMBOL(pm_idle);
  69
  70 #ifdef CONFIG_X86_32
  71 /*
  72  * This halt magic was a workaround for ancient floppy DMA
  73  * wreckage. It should be safe to remove.
  74  */
  75 static int hlt_counter;
  76 void disable_hlt(void)
  77 {
  78         hlt_counter++;
  79 }
  80 EXPORT_SYMBOL(disable_hlt);
  81
  82 void enable_hlt(void)
  83 {
  84         hlt_counter--;
  85 }
  86 EXPORT_SYMBOL(enable_hlt);
  87
  88 static inline int hlt_use_halt(void)
  89 {
  90         return (!hlt_counter && boot_cpu_data.hlt_works_ok);
  91 }
  92 #else
  93 static inline int hlt_use_halt(void)
  94 {
  95         return 1;
  96 }
  97 #endif
  98
  99 /*
 100  * We use this if we don't have any better
 101  * idle routine..
 102  */
 103 void default_idle(void)
 104 {
 105         if (hlt_use_halt()) {
 106                 struct power_trace it;
 107
 108                 trace_power_start(&it, POWER_CSTATE, 1);
 109                 current_thread_info()->status &= ~TS_POLLING;
 110                 /*
 111                  * TS_POLLING-cleared state must be visible before we
 112                  * test NEED_RESCHED:
 113                  */
 114                 smp_mb();
 115
 116                 if (!need_resched())
 117                         safe_halt();    /* enables interrupts racelessly */
 118                 else
 119                         local_irq_enable();
 120                 current_thread_info()->status |= TS_POLLING;
 121                 trace_power_end(&it);
 122         } else {
 123                 local_irq_enable();
 124                 /* loop is done by the caller */
 125                 cpu_relax();
 126         }
 127 }
 128 #ifdef CONFIG_APM_MODULE
 129 EXPORT_SYMBOL(default_idle);
 130 #endif
 131
 132 void stop_this_cpu(void *dummy)
 133 {
 134         local_irq_disable();
 135         /*
 136          * Remove this CPU:
 137          */
 138         cpu_clear(smp_processor_id(), cpu_online_map);
 139         disable_local_APIC();
 140
 141         for (;;) {
 142                 if (hlt_works(smp_processor_id()))
 143                         halt();
 144         }
 145 }
 146
 147 static void do_nothing(void *unused)
 148 {
 149 }
 150
 151 /*
 152  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
 153  * pm_idle and update to new pm_idle value. Required while changing pm_idle
 154  * handler on SMP systems.
 155  *
 156  * Caller must have changed pm_idle to the new value before the call. Old
 157  * pm_idle value will not be used by any CPU after the return of this function.
 158  */
 159 void cpu_idle_wait(void)
 160 {
 161         smp_mb();
 162         /* kick all the CPUs so that they exit out of pm_idle */
 163         smp_call_function(do_nothing, NULL, 1);
 164 }
 165 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 166
 167 /*
 168  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 169  * which can obviate IPI to trigger checking of need_resched.
 170  * We execute MONITOR against need_resched and enter optimized wait state
 171  * through MWAIT. Whenever someone changes need_resched, we would be woken
 172  * up from MWAIT (without an IPI).
 173  *
 174  * New with Core Duo processors, MWAIT can take some hints based on CPU
 175  * capability.
 176  */
 177 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 178 {
 179         struct power_trace it;
 180
 181         trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
 182         if (!need_resched()) {
 183                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 184                 smp_mb();
 185                 if (!need_resched())
 186                         __mwait(ax, cx);
 187         }
 188         trace_power_end(&it);
 189 }
 190
 191 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
 192 static void mwait_idle(void)
 193 {
 194         struct power_trace it;
 195         if (!need_resched()) {
 196                 trace_power_start(&it, POWER_CSTATE, 1);
 197                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 198                 smp_mb();
 199                 if (!need_resched())
 200                         __sti_mwait(0, 0);
 201                 else
 202                         local_irq_enable();
 203                 trace_power_end(&it);
 204         } else
 205                 local_irq_enable();
 206 }
 207
 208 /*
 209  * On SMP it's slightly faster (but much more power-consuming!)
 210  * to poll the ->work.need_resched flag instead of waiting for the
 211  * cross-CPU IPI to arrive. Use this option with caution.
 212  */
 213 static void poll_idle(void)
 214 {
 215         struct power_trace it;
 216
 217         trace_power_start(&it, POWER_CSTATE, 0);
 218         local_irq_enable();
 219         while (!need_resched())
 220                 cpu_relax();
 221         trace_power_end(&it);
 222 }
 223
 224 /*
 225  * mwait selection logic:
 226  *
 227  * It depends on the CPU. For AMD CPUs that support MWAIT this is
 228  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 229  * then depend on a clock divisor and current Pstate of the core. If
 230  * all cores of a processor are in halt state (C1) the processor can
 231  * enter the C1E (C1 enhanced) state. If mwait is used this will never
 232  * happen.
 233  *
 234  * idle=mwait overrides this decision and forces the usage of mwait.
 235  */
 236 static int __cpuinitdata force_mwait;
 237
 238 #define MWAIT_INFO                      0x05
 239 #define MWAIT_ECX_EXTENDED_INFO         0x01
 240 #define MWAIT_EDX_C1                    0xf0
 241
 242 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
 243 {
 244         u32 eax, ebx, ecx, edx;
 245
 246         if (force_mwait)
 247                 return 1;
 248
 249         if (c->cpuid_level < MWAIT_INFO)
 250                 return 0;
 251
 252         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
 253         /* Check, whether EDX has extended info about MWAIT */
 254         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
 255                 return 1;
 256
 257         /*
 258          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
 259          * C1  supports MWAIT
 260          */
 261         return (edx & MWAIT_EDX_C1);
 262 }
 263
 264 /*
 265  * Check for AMD CPUs, which have potentially C1E support
 266  */
 267 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
 268 {
 269         if (c->x86_vendor != X86_VENDOR_AMD)
 270                 return 0;
 271
 272         if (c->x86 < 0x0F)
 273                 return 0;
 274
 275         /* Family 0x0f models < rev F do not have C1E */
 276         if (c->x86 == 0x0f && c->x86_model < 0x40)
 277                 return 0;
 278
 279         return 1;
 280 }
 281
 282 static cpumask_t c1e_mask = CPU_MASK_NONE;
 283 static int c1e_detected;
 284
 285 void c1e_remove_cpu(int cpu)
 286 {
 287         cpu_clear(cpu, c1e_mask);
 288 }
 289
 290 /*
 291  * C1E aware idle routine. We check for C1E active in the interrupt
 292  * pending message MSR. If we detect C1E, then we handle it the same
 293  * way as C3 power states (local apic timer and TSC stop)
 294  */
 295 static void c1e_idle(void)
 296 {
 297         if (need_resched())
 298                 return;
 299
 300         if (!c1e_detected) {
 301                 u32 lo, hi;
 302
 303                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 304                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
 305                         c1e_detected = 1;
 306                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 307                                 mark_tsc_unstable("TSC halt in AMD C1E");
 308                         printk(KERN_INFO "System has AMD C1E enabled\n");
 309                         set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
 310                 }
 311         }
 312
 313         if (c1e_detected) {
 314                 int cpu = smp_processor_id();
 315
 316                 if (!cpu_isset(cpu, c1e_mask)) {
 317                         cpu_set(cpu, c1e_mask);
 318                         /*
 319                          * Force broadcast so ACPI can not interfere. Needs
 320                          * to run with interrupts enabled as it uses
 321                          * smp_function_call.
 322                          */
 323                         local_irq_enable();
 324                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
 325                                            &cpu);
 326                         printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
 327                                cpu);
 328                         local_irq_disable();
 329                 }
 330                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 331
 332                 default_idle();
 333
 334                 /*
 335                  * The switch back from broadcast mode needs to be
 336                  * called with interrupts disabled.
 337                  */
 338                  local_irq_disable();
 339                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 340                  local_irq_enable();
 341         } else
 342                 default_idle();
 343 }
 344
 345 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 346 {
 347 #ifdef CONFIG_X86_SMP
 348         if (pm_idle == poll_idle && smp_num_siblings > 1) {
 349                 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
 350                         " performance may degrade.\n");
 351         }
 352 #endif
 353         if (pm_idle)
 354                 return;
 355
 356         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
 357                 /*
 358                  * One CPU supports mwait => All CPUs supports mwait
 359                  */
 360                 printk(KERN_INFO "using mwait in idle threads.\n");
 361                 pm_idle = mwait_idle;
 362         } else if (check_c1e_idle(c)) {
 363                 printk(KERN_INFO "using C1E aware idle routine\n");
 364                 pm_idle = c1e_idle;
 365         } else
 366                 pm_idle = default_idle;
 367 }
 368
 369 static int __init idle_setup(char *str)
 370 {
 371         if (!str)
 372                 return -EINVAL;
 373
 374         if (!strcmp(str, "poll")) {
 375                 printk("using polling idle threads.\n");
 376                 pm_idle = poll_idle;
 377         } else if (!strcmp(str, "mwait"))
 378                 force_mwait = 1;
 379         else if (!strcmp(str, "halt")) {
 380                 /*
 381                  * When the boot option of idle=halt is added, halt is
 382                  * forced to be used for CPU idle. In such case CPU C2/C3
 383                  * won't be used again.
 384                  * To continue to load the CPU idle driver, don't touch
 385                  * the boot_option_idle_override.
 386                  */
 387                 pm_idle = default_idle;
 388                 idle_halt = 1;
 389                 return 0;
 390         } else if (!strcmp(str, "nomwait")) {
 391                 /*
 392                  * If the boot option of "idle=nomwait" is added,
 393                  * it means that mwait will be disabled for CPU C2/C3
 394                  * states. In such case it won't touch the variable
 395                  * of boot_option_idle_override.
 396                  */
 397                 idle_nomwait = 1;
 398                 return 0;
 399         } else
 400                 return -1;
 401
 402         boot_option_idle_override = 1;
 403         return 0;
 404 }
 405 early_param("idle", idle_setup);
 406