1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/errno.h>
4 #include <linux/kernel.h>
7 #include <linux/prctl.h>
8 #include <linux/slab.h>
9 #include <linux/sched.h>
10 #include <linux/module.h>
12 #include <linux/clockchips.h>
13 #include <linux/random.h>
14 #include <linux/user-return-notifier.h>
15 #include <linux/dmi.h>
16 #include <linux/utsname.h>
17 #include <linux/stackprotector.h>
18 #include <linux/tick.h>
19 #include <linux/cpuidle.h>
20 #include <trace/events/power.h>
21 #include <linux/hw_breakpoint.h>
24 #include <asm/syscalls.h>
26 #include <asm/uaccess.h>
28 #include <asm/fpu-internal.h>
29 #include <asm/debugreg.h>
31 #include <asm/tlbflush.h>
34 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
35 * no more per-task TSS's. The TSS size is kept cacheline-aligned
36 * so they are allowed to end up in the .data..cacheline_aligned
37 * section. Since TSS's are completely CPU-local, we want them
38 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
40 __visible
DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct
, init_tss
) = INIT_TSS
;
43 static DEFINE_PER_CPU(unsigned char, is_idle
);
44 static ATOMIC_NOTIFIER_HEAD(idle_notifier
);
46 void idle_notifier_register(struct notifier_block
*n
)
48 atomic_notifier_chain_register(&idle_notifier
, n
);
50 EXPORT_SYMBOL_GPL(idle_notifier_register
);
52 void idle_notifier_unregister(struct notifier_block
*n
)
54 atomic_notifier_chain_unregister(&idle_notifier
, n
);
56 EXPORT_SYMBOL_GPL(idle_notifier_unregister
);
59 struct kmem_cache
*task_xstate_cachep
;
60 EXPORT_SYMBOL_GPL(task_xstate_cachep
);
63 * this gets called so that we can store lazy state into memory and copy the
64 * current task into the new thread.
66 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
70 dst
->thread
.fpu_counter
= 0;
71 dst
->thread
.fpu
.has_fpu
= 0;
72 dst
->thread
.fpu
.last_cpu
= ~0;
73 dst
->thread
.fpu
.state
= NULL
;
74 if (tsk_used_math(src
)) {
75 int err
= fpu_alloc(&dst
->thread
.fpu
);
83 void free_thread_xstate(struct task_struct
*tsk
)
85 fpu_free(&tsk
->thread
.fpu
);
88 void arch_release_task_struct(struct task_struct
*tsk
)
90 free_thread_xstate(tsk
);
93 void arch_task_cache_init(void)
96 kmem_cache_create("task_xstate", xstate_size
,
97 __alignof__(union thread_xstate
),
98 SLAB_PANIC
| SLAB_NOTRACK
, NULL
);
103 * Free current thread data structures etc..
105 void exit_thread(void)
107 struct task_struct
*me
= current
;
108 struct thread_struct
*t
= &me
->thread
;
109 unsigned long *bp
= t
->io_bitmap_ptr
;
112 struct tss_struct
*tss
= &per_cpu(init_tss
, get_cpu());
114 t
->io_bitmap_ptr
= NULL
;
115 clear_thread_flag(TIF_IO_BITMAP
);
117 * Careful, clear this in the TSS too:
119 memset(tss
->io_bitmap
, 0xff, t
->io_bitmap_max
);
120 t
->io_bitmap_max
= 0;
128 void flush_thread(void)
130 struct task_struct
*tsk
= current
;
132 flush_ptrace_hw_breakpoint(tsk
);
133 memset(tsk
->thread
.tls_array
, 0, sizeof(tsk
->thread
.tls_array
));
136 * Free the FPU state for non xsave platforms. They get reallocated
137 * lazily at the first use.
139 if (!use_eager_fpu())
140 free_thread_xstate(tsk
);
143 static void hard_disable_TSC(void)
145 cr4_set_bits(X86_CR4_TSD
);
148 void disable_TSC(void)
151 if (!test_and_set_thread_flag(TIF_NOTSC
))
153 * Must flip the CPU state synchronously with
154 * TIF_NOTSC in the current running context.
160 static void hard_enable_TSC(void)
162 cr4_clear_bits(X86_CR4_TSD
);
165 static void enable_TSC(void)
168 if (test_and_clear_thread_flag(TIF_NOTSC
))
170 * Must flip the CPU state synchronously with
171 * TIF_NOTSC in the current running context.
177 int get_tsc_mode(unsigned long adr
)
181 if (test_thread_flag(TIF_NOTSC
))
182 val
= PR_TSC_SIGSEGV
;
186 return put_user(val
, (unsigned int __user
*)adr
);
189 int set_tsc_mode(unsigned int val
)
191 if (val
== PR_TSC_SIGSEGV
)
193 else if (val
== PR_TSC_ENABLE
)
201 void __switch_to_xtra(struct task_struct
*prev_p
, struct task_struct
*next_p
,
202 struct tss_struct
*tss
)
204 struct thread_struct
*prev
, *next
;
206 prev
= &prev_p
->thread
;
207 next
= &next_p
->thread
;
209 if (test_tsk_thread_flag(prev_p
, TIF_BLOCKSTEP
) ^
210 test_tsk_thread_flag(next_p
, TIF_BLOCKSTEP
)) {
211 unsigned long debugctl
= get_debugctlmsr();
213 debugctl
&= ~DEBUGCTLMSR_BTF
;
214 if (test_tsk_thread_flag(next_p
, TIF_BLOCKSTEP
))
215 debugctl
|= DEBUGCTLMSR_BTF
;
217 update_debugctlmsr(debugctl
);
220 if (test_tsk_thread_flag(prev_p
, TIF_NOTSC
) ^
221 test_tsk_thread_flag(next_p
, TIF_NOTSC
)) {
222 /* prev and next are different */
223 if (test_tsk_thread_flag(next_p
, TIF_NOTSC
))
229 if (test_tsk_thread_flag(next_p
, TIF_IO_BITMAP
)) {
231 * Copy the relevant range of the IO bitmap.
232 * Normally this is 128 bytes or less:
234 memcpy(tss
->io_bitmap
, next
->io_bitmap_ptr
,
235 max(prev
->io_bitmap_max
, next
->io_bitmap_max
));
236 } else if (test_tsk_thread_flag(prev_p
, TIF_IO_BITMAP
)) {
238 * Clear any possible leftover bits:
240 memset(tss
->io_bitmap
, 0xff, prev
->io_bitmap_max
);
242 propagate_user_return_notify(prev_p
, next_p
);
246 * Idle related variables and functions
248 unsigned long boot_option_idle_override
= IDLE_NO_OVERRIDE
;
249 EXPORT_SYMBOL(boot_option_idle_override
);
251 static void (*x86_idle
)(void);
254 static inline void play_dead(void)
261 void enter_idle(void)
263 this_cpu_write(is_idle
, 1);
264 atomic_notifier_call_chain(&idle_notifier
, IDLE_START
, NULL
);
267 static void __exit_idle(void)
269 if (x86_test_and_clear_bit_percpu(0, is_idle
) == 0)
271 atomic_notifier_call_chain(&idle_notifier
, IDLE_END
, NULL
);
274 /* Called from interrupts to signify idle end */
277 /* idle loop has pid 0 */
284 void arch_cpu_idle_enter(void)
290 void arch_cpu_idle_exit(void)
295 void arch_cpu_idle_dead(void)
301 * Called from the generic idle code.
303 void arch_cpu_idle(void)
309 * We use this if we don't have any better idle routine..
311 void default_idle(void)
313 trace_cpu_idle_rcuidle(1, smp_processor_id());
315 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT
, smp_processor_id());
317 #ifdef CONFIG_APM_MODULE
318 EXPORT_SYMBOL(default_idle
);
322 bool xen_set_default_idle(void)
324 bool ret
= !!x86_idle
;
326 x86_idle
= default_idle
;
331 void stop_this_cpu(void *dummy
)
337 set_cpu_online(smp_processor_id(), false);
338 disable_local_APIC();
344 bool amd_e400_c1e_detected
;
345 EXPORT_SYMBOL(amd_e400_c1e_detected
);
347 static cpumask_var_t amd_e400_c1e_mask
;
349 void amd_e400_remove_cpu(int cpu
)
351 if (amd_e400_c1e_mask
!= NULL
)
352 cpumask_clear_cpu(cpu
, amd_e400_c1e_mask
);
356 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
357 * pending message MSR. If we detect C1E, then we handle it the same
358 * way as C3 power states (local apic timer and TSC stop)
360 static void amd_e400_idle(void)
362 if (!amd_e400_c1e_detected
) {
365 rdmsr(MSR_K8_INT_PENDING_MSG
, lo
, hi
);
367 if (lo
& K8_INTP_C1E_ACTIVE_MASK
) {
368 amd_e400_c1e_detected
= true;
369 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC
))
370 mark_tsc_unstable("TSC halt in AMD C1E");
371 pr_info("System has AMD C1E enabled\n");
375 if (amd_e400_c1e_detected
) {
376 int cpu
= smp_processor_id();
378 if (!cpumask_test_cpu(cpu
, amd_e400_c1e_mask
)) {
379 cpumask_set_cpu(cpu
, amd_e400_c1e_mask
);
381 * Force broadcast so ACPI can not interfere.
383 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE
,
385 pr_info("Switch to broadcast mode on CPU%d\n", cpu
);
387 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER
, &cpu
);
392 * The switch back from broadcast mode needs to be
393 * called with interrupts disabled.
396 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT
, &cpu
);
402 void select_idle_routine(const struct cpuinfo_x86
*c
)
405 if (boot_option_idle_override
== IDLE_POLL
&& smp_num_siblings
> 1)
406 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
408 if (x86_idle
|| boot_option_idle_override
== IDLE_POLL
)
411 if (cpu_has_bug(c
, X86_BUG_AMD_APIC_C1E
)) {
412 /* E400: APIC timer interrupt does not wake up CPU from C1e */
413 pr_info("using AMD E400 aware idle routine\n");
414 x86_idle
= amd_e400_idle
;
416 x86_idle
= default_idle
;
419 void __init
init_amd_e400_c1e_mask(void)
421 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
422 if (x86_idle
== amd_e400_idle
)
423 zalloc_cpumask_var(&amd_e400_c1e_mask
, GFP_KERNEL
);
426 static int __init
idle_setup(char *str
)
431 if (!strcmp(str
, "poll")) {
432 pr_info("using polling idle threads\n");
433 boot_option_idle_override
= IDLE_POLL
;
434 cpu_idle_poll_ctrl(true);
435 } else if (!strcmp(str
, "halt")) {
437 * When the boot option of idle=halt is added, halt is
438 * forced to be used for CPU idle. In such case CPU C2/C3
439 * won't be used again.
440 * To continue to load the CPU idle driver, don't touch
441 * the boot_option_idle_override.
443 x86_idle
= default_idle
;
444 boot_option_idle_override
= IDLE_HALT
;
445 } else if (!strcmp(str
, "nomwait")) {
447 * If the boot option of "idle=nomwait" is added,
448 * it means that mwait will be disabled for CPU C2/C3
449 * states. In such case it won't touch the variable
450 * of boot_option_idle_override.
452 boot_option_idle_override
= IDLE_NOMWAIT
;
458 early_param("idle", idle_setup
);
460 unsigned long arch_align_stack(unsigned long sp
)
462 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
463 sp
-= get_random_int() % 8192;
467 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
469 unsigned long range_end
= mm
->brk
+ 0x02000000;
470 return randomize_range(mm
->brk
, range_end
, 0) ? : mm
->brk
;