1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/errno.h>
4 #include <linux/kernel.h>
7 #include <linux/prctl.h>
8 #include <linux/slab.h>
9 #include <linux/sched.h>
10 #include <linux/module.h>
12 #include <linux/clockchips.h>
13 #include <linux/random.h>
14 #include <linux/user-return-notifier.h>
15 #include <linux/dmi.h>
16 #include <linux/utsname.h>
17 #include <linux/stackprotector.h>
18 #include <linux/tick.h>
19 #include <linux/cpuidle.h>
20 #include <trace/events/power.h>
21 #include <linux/hw_breakpoint.h>
24 #include <asm/syscalls.h>
26 #include <asm/uaccess.h>
28 #include <asm/fpu-internal.h>
29 #include <asm/debugreg.h>
33 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
34 * no more per-task TSS's. The TSS size is kept cacheline-aligned
35 * so they are allowed to end up in the .data..cacheline_aligned
36 * section. Since TSS's are completely CPU-local, we want them
37 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
39 DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct
, init_tss
) = INIT_TSS
;
42 static DEFINE_PER_CPU(unsigned char, is_idle
);
43 static ATOMIC_NOTIFIER_HEAD(idle_notifier
);
45 void idle_notifier_register(struct notifier_block
*n
)
47 atomic_notifier_chain_register(&idle_notifier
, n
);
49 EXPORT_SYMBOL_GPL(idle_notifier_register
);
51 void idle_notifier_unregister(struct notifier_block
*n
)
53 atomic_notifier_chain_unregister(&idle_notifier
, n
);
55 EXPORT_SYMBOL_GPL(idle_notifier_unregister
);
58 struct kmem_cache
*task_xstate_cachep
;
59 EXPORT_SYMBOL_GPL(task_xstate_cachep
);
62 * this gets called so that we can store lazy state into memory and copy the
63 * current task into the new thread.
65 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
70 if (fpu_allocated(&src
->thread
.fpu
)) {
71 memset(&dst
->thread
.fpu
, 0, sizeof(dst
->thread
.fpu
));
72 ret
= fpu_alloc(&dst
->thread
.fpu
);
80 void free_thread_xstate(struct task_struct
*tsk
)
82 fpu_free(&tsk
->thread
.fpu
);
85 void arch_release_task_struct(struct task_struct
*tsk
)
87 free_thread_xstate(tsk
);
90 void arch_task_cache_init(void)
93 kmem_cache_create("task_xstate", xstate_size
,
94 __alignof__(union thread_xstate
),
95 SLAB_PANIC
| SLAB_NOTRACK
, NULL
);
99 * Free current thread data structures etc..
101 void exit_thread(void)
103 struct task_struct
*me
= current
;
104 struct thread_struct
*t
= &me
->thread
;
105 unsigned long *bp
= t
->io_bitmap_ptr
;
108 struct tss_struct
*tss
= &per_cpu(init_tss
, get_cpu());
110 t
->io_bitmap_ptr
= NULL
;
111 clear_thread_flag(TIF_IO_BITMAP
);
113 * Careful, clear this in the TSS too:
115 memset(tss
->io_bitmap
, 0xff, t
->io_bitmap_max
);
116 t
->io_bitmap_max
= 0;
124 void show_regs_common(void)
126 const char *vendor
, *product
, *board
;
128 vendor
= dmi_get_system_info(DMI_SYS_VENDOR
);
131 product
= dmi_get_system_info(DMI_PRODUCT_NAME
);
135 /* Board Name is optional */
136 board
= dmi_get_system_info(DMI_BOARD_NAME
);
138 printk(KERN_DEFAULT
"Pid: %d, comm: %.20s %s %s %.*s %s %s%s%s\n",
139 current
->pid
, current
->comm
, print_tainted(),
140 init_utsname()->release
,
141 (int)strcspn(init_utsname()->version
, " "),
142 init_utsname()->version
,
148 void flush_thread(void)
150 struct task_struct
*tsk
= current
;
152 flush_ptrace_hw_breakpoint(tsk
);
153 memset(tsk
->thread
.tls_array
, 0, sizeof(tsk
->thread
.tls_array
));
156 * Free the FPU state for non xsave platforms. They get reallocated
157 * lazily at the first use.
159 if (!use_eager_fpu())
160 free_thread_xstate(tsk
);
163 static void hard_disable_TSC(void)
165 write_cr4(read_cr4() | X86_CR4_TSD
);
168 void disable_TSC(void)
171 if (!test_and_set_thread_flag(TIF_NOTSC
))
173 * Must flip the CPU state synchronously with
174 * TIF_NOTSC in the current running context.
180 static void hard_enable_TSC(void)
182 write_cr4(read_cr4() & ~X86_CR4_TSD
);
185 static void enable_TSC(void)
188 if (test_and_clear_thread_flag(TIF_NOTSC
))
190 * Must flip the CPU state synchronously with
191 * TIF_NOTSC in the current running context.
197 int get_tsc_mode(unsigned long adr
)
201 if (test_thread_flag(TIF_NOTSC
))
202 val
= PR_TSC_SIGSEGV
;
206 return put_user(val
, (unsigned int __user
*)adr
);
209 int set_tsc_mode(unsigned int val
)
211 if (val
== PR_TSC_SIGSEGV
)
213 else if (val
== PR_TSC_ENABLE
)
221 void __switch_to_xtra(struct task_struct
*prev_p
, struct task_struct
*next_p
,
222 struct tss_struct
*tss
)
224 struct thread_struct
*prev
, *next
;
226 prev
= &prev_p
->thread
;
227 next
= &next_p
->thread
;
229 if (test_tsk_thread_flag(prev_p
, TIF_BLOCKSTEP
) ^
230 test_tsk_thread_flag(next_p
, TIF_BLOCKSTEP
)) {
231 unsigned long debugctl
= get_debugctlmsr();
233 debugctl
&= ~DEBUGCTLMSR_BTF
;
234 if (test_tsk_thread_flag(next_p
, TIF_BLOCKSTEP
))
235 debugctl
|= DEBUGCTLMSR_BTF
;
237 update_debugctlmsr(debugctl
);
240 if (test_tsk_thread_flag(prev_p
, TIF_NOTSC
) ^
241 test_tsk_thread_flag(next_p
, TIF_NOTSC
)) {
242 /* prev and next are different */
243 if (test_tsk_thread_flag(next_p
, TIF_NOTSC
))
249 if (test_tsk_thread_flag(next_p
, TIF_IO_BITMAP
)) {
251 * Copy the relevant range of the IO bitmap.
252 * Normally this is 128 bytes or less:
254 memcpy(tss
->io_bitmap
, next
->io_bitmap_ptr
,
255 max(prev
->io_bitmap_max
, next
->io_bitmap_max
));
256 } else if (test_tsk_thread_flag(prev_p
, TIF_IO_BITMAP
)) {
258 * Clear any possible leftover bits:
260 memset(tss
->io_bitmap
, 0xff, prev
->io_bitmap_max
);
262 propagate_user_return_notify(prev_p
, next_p
);
265 int sys_fork(struct pt_regs
*regs
)
267 return do_fork(SIGCHLD
, regs
->sp
, regs
, 0, NULL
, NULL
);
271 * This is trivial, and on the face of it looks like it
272 * could equally well be done in user mode.
274 * Not so, for quite unobvious reasons - register pressure.
275 * In user mode vfork() cannot have a stack frame, and if
276 * done by calling the "clone()" system call directly, you
277 * do not have enough call-clobbered registers to hold all
278 * the information you need.
280 int sys_vfork(struct pt_regs
*regs
)
282 return do_fork(CLONE_VFORK
| CLONE_VM
| SIGCHLD
, regs
->sp
, regs
, 0,
287 sys_clone(unsigned long clone_flags
, unsigned long newsp
,
288 void __user
*parent_tid
, void __user
*child_tid
, struct pt_regs
*regs
)
292 return do_fork(clone_flags
, newsp
, regs
, 0, parent_tid
, child_tid
);
296 * Idle related variables and functions
298 unsigned long boot_option_idle_override
= IDLE_NO_OVERRIDE
;
299 EXPORT_SYMBOL(boot_option_idle_override
);
302 * Powermanagement idle function, if any..
304 void (*pm_idle
)(void);
305 #ifdef CONFIG_APM_MODULE
306 EXPORT_SYMBOL(pm_idle
);
310 static inline void play_dead(void)
317 void enter_idle(void)
319 this_cpu_write(is_idle
, 1);
320 atomic_notifier_call_chain(&idle_notifier
, IDLE_START
, NULL
);
323 static void __exit_idle(void)
325 if (x86_test_and_clear_bit_percpu(0, is_idle
) == 0)
327 atomic_notifier_call_chain(&idle_notifier
, IDLE_END
, NULL
);
330 /* Called from interrupts to signify idle end */
333 /* idle loop has pid 0 */
341 * The idle thread. There's no useful work to be
342 * done, so just try to conserve power and have a
343 * low exit latency (ie sit in a loop waiting for
344 * somebody to say that they'd like to reschedule)
349 * If we're the non-boot CPU, nothing set the stack canary up
350 * for us. CPU0 already has it initialized but no harm in
351 * doing it again. This is a good place for updating it, as
352 * we wont ever return from this function (so the invalid
353 * canaries already on the stack wont ever trigger).
355 boot_init_stack_canary();
356 current_thread_info()->status
|= TS_POLLING
;
359 tick_nohz_idle_enter();
361 while (!need_resched()) {
364 if (cpu_is_offline(smp_processor_id()))
368 * Idle routines should keep interrupts disabled
369 * from here on, until they go to idle.
370 * Otherwise, idle callbacks can misfire.
377 /* Don't trace irqs off for idle */
378 stop_critical_timings();
380 /* enter_idle() needs rcu for notifiers */
383 if (cpuidle_idle_call())
387 start_critical_timings();
389 /* In many cases the interrupt that ended idle
390 has already called exit_idle. But some idle
391 loops can be woken up without interrupt. */
395 tick_nohz_idle_exit();
396 preempt_enable_no_resched();
403 * We use this if we don't have any better
406 void default_idle(void)
408 trace_power_start_rcuidle(POWER_CSTATE
, 1, smp_processor_id());
409 trace_cpu_idle_rcuidle(1, smp_processor_id());
410 current_thread_info()->status
&= ~TS_POLLING
;
412 * TS_POLLING-cleared state must be visible before we
418 safe_halt(); /* enables interrupts racelessly */
421 current_thread_info()->status
|= TS_POLLING
;
422 trace_power_end_rcuidle(smp_processor_id());
423 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT
, smp_processor_id());
425 #ifdef CONFIG_APM_MODULE
426 EXPORT_SYMBOL(default_idle
);
429 bool set_pm_idle_to_default(void)
431 bool ret
= !!pm_idle
;
433 pm_idle
= default_idle
;
437 void stop_this_cpu(void *dummy
)
443 set_cpu_online(smp_processor_id(), false);
444 disable_local_APIC();
447 if (hlt_works(smp_processor_id()))
452 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
453 static void mwait_idle(void)
455 if (!need_resched()) {
456 trace_power_start_rcuidle(POWER_CSTATE
, 1, smp_processor_id());
457 trace_cpu_idle_rcuidle(1, smp_processor_id());
458 if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR
))
459 clflush((void *)¤t_thread_info()->flags
);
461 __monitor((void *)¤t_thread_info()->flags
, 0, 0);
467 trace_power_end_rcuidle(smp_processor_id());
468 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT
, smp_processor_id());
474 * On SMP it's slightly faster (but much more power-consuming!)
475 * to poll the ->work.need_resched flag instead of waiting for the
476 * cross-CPU IPI to arrive. Use this option with caution.
478 static void poll_idle(void)
480 trace_power_start_rcuidle(POWER_CSTATE
, 0, smp_processor_id());
481 trace_cpu_idle_rcuidle(0, smp_processor_id());
483 while (!need_resched())
485 trace_power_end_rcuidle(smp_processor_id());
486 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT
, smp_processor_id());
490 * mwait selection logic:
492 * It depends on the CPU. For AMD CPUs that support MWAIT this is
493 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
494 * then depend on a clock divisor and current Pstate of the core. If
495 * all cores of a processor are in halt state (C1) the processor can
496 * enter the C1E (C1 enhanced) state. If mwait is used this will never
499 * idle=mwait overrides this decision and forces the usage of mwait.
502 #define MWAIT_INFO 0x05
503 #define MWAIT_ECX_EXTENDED_INFO 0x01
504 #define MWAIT_EDX_C1 0xf0
506 int mwait_usable(const struct cpuinfo_x86
*c
)
508 u32 eax
, ebx
, ecx
, edx
;
510 /* Use mwait if idle=mwait boot option is given */
511 if (boot_option_idle_override
== IDLE_FORCE_MWAIT
)
515 * Any idle= boot option other than idle=mwait means that we must not
516 * use mwait. Eg: idle=halt or idle=poll or idle=nomwait
518 if (boot_option_idle_override
!= IDLE_NO_OVERRIDE
)
521 if (c
->cpuid_level
< MWAIT_INFO
)
524 cpuid(MWAIT_INFO
, &eax
, &ebx
, &ecx
, &edx
);
525 /* Check, whether EDX has extended info about MWAIT */
526 if (!(ecx
& MWAIT_ECX_EXTENDED_INFO
))
530 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
533 return (edx
& MWAIT_EDX_C1
);
536 bool amd_e400_c1e_detected
;
537 EXPORT_SYMBOL(amd_e400_c1e_detected
);
539 static cpumask_var_t amd_e400_c1e_mask
;
541 void amd_e400_remove_cpu(int cpu
)
543 if (amd_e400_c1e_mask
!= NULL
)
544 cpumask_clear_cpu(cpu
, amd_e400_c1e_mask
);
548 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
549 * pending message MSR. If we detect C1E, then we handle it the same
550 * way as C3 power states (local apic timer and TSC stop)
552 static void amd_e400_idle(void)
557 if (!amd_e400_c1e_detected
) {
560 rdmsr(MSR_K8_INT_PENDING_MSG
, lo
, hi
);
562 if (lo
& K8_INTP_C1E_ACTIVE_MASK
) {
563 amd_e400_c1e_detected
= true;
564 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC
))
565 mark_tsc_unstable("TSC halt in AMD C1E");
566 pr_info("System has AMD C1E enabled\n");
570 if (amd_e400_c1e_detected
) {
571 int cpu
= smp_processor_id();
573 if (!cpumask_test_cpu(cpu
, amd_e400_c1e_mask
)) {
574 cpumask_set_cpu(cpu
, amd_e400_c1e_mask
);
576 * Force broadcast so ACPI can not interfere.
578 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE
,
580 pr_info("Switch to broadcast mode on CPU%d\n", cpu
);
582 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER
, &cpu
);
587 * The switch back from broadcast mode needs to be
588 * called with interrupts disabled.
591 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT
, &cpu
);
597 void __cpuinit
select_idle_routine(const struct cpuinfo_x86
*c
)
600 if (pm_idle
== poll_idle
&& smp_num_siblings
> 1) {
601 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
607 if (cpu_has(c
, X86_FEATURE_MWAIT
) && mwait_usable(c
)) {
609 * One CPU supports mwait => All CPUs supports mwait
611 pr_info("using mwait in idle threads\n");
612 pm_idle
= mwait_idle
;
613 } else if (cpu_has_amd_erratum(amd_erratum_400
)) {
614 /* E400: APIC timer interrupt does not wake up CPU from C1e */
615 pr_info("using AMD E400 aware idle routine\n");
616 pm_idle
= amd_e400_idle
;
618 pm_idle
= default_idle
;
621 void __init
init_amd_e400_c1e_mask(void)
623 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
624 if (pm_idle
== amd_e400_idle
)
625 zalloc_cpumask_var(&amd_e400_c1e_mask
, GFP_KERNEL
);
628 static int __init
idle_setup(char *str
)
633 if (!strcmp(str
, "poll")) {
634 pr_info("using polling idle threads\n");
636 boot_option_idle_override
= IDLE_POLL
;
637 } else if (!strcmp(str
, "mwait")) {
638 boot_option_idle_override
= IDLE_FORCE_MWAIT
;
639 WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n");
640 } else if (!strcmp(str
, "halt")) {
642 * When the boot option of idle=halt is added, halt is
643 * forced to be used for CPU idle. In such case CPU C2/C3
644 * won't be used again.
645 * To continue to load the CPU idle driver, don't touch
646 * the boot_option_idle_override.
648 pm_idle
= default_idle
;
649 boot_option_idle_override
= IDLE_HALT
;
650 } else if (!strcmp(str
, "nomwait")) {
652 * If the boot option of "idle=nomwait" is added,
653 * it means that mwait will be disabled for CPU C2/C3
654 * states. In such case it won't touch the variable
655 * of boot_option_idle_override.
657 boot_option_idle_override
= IDLE_NOMWAIT
;
663 early_param("idle", idle_setup
);
665 unsigned long arch_align_stack(unsigned long sp
)
667 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
668 sp
-= get_random_int() % 8192;
672 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
674 unsigned long range_end
= mm
->brk
+ 0x02000000;
675 return randomize_range(mm
->brk
, range_end
, 0) ? : mm
->brk
;