1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/errno.h>
4 #include <linux/kernel.h>
7 #include <linux/prctl.h>
8 #include <linux/slab.h>
9 #include <linux/sched.h>
10 #include <linux/module.h>
12 #include <linux/clockchips.h>
13 #include <linux/random.h>
14 #include <linux/user-return-notifier.h>
15 #include <linux/dmi.h>
16 #include <linux/utsname.h>
17 #include <linux/stackprotector.h>
18 #include <linux/tick.h>
19 #include <linux/cpuidle.h>
20 #include <trace/events/power.h>
21 #include <linux/hw_breakpoint.h>
24 #include <asm/syscalls.h>
26 #include <asm/uaccess.h>
28 #include <asm/fpu-internal.h>
29 #include <asm/debugreg.h>
33 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
34 * no more per-task TSS's. The TSS size is kept cacheline-aligned
35 * so they are allowed to end up in the .data..cacheline_aligned
36 * section. Since TSS's are completely CPU-local, we want them
37 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
39 __visible
DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct
, init_tss
) = INIT_TSS
;
42 static DEFINE_PER_CPU(unsigned char, is_idle
);
43 static ATOMIC_NOTIFIER_HEAD(idle_notifier
);
45 void idle_notifier_register(struct notifier_block
*n
)
47 atomic_notifier_chain_register(&idle_notifier
, n
);
49 EXPORT_SYMBOL_GPL(idle_notifier_register
);
51 void idle_notifier_unregister(struct notifier_block
*n
)
53 atomic_notifier_chain_unregister(&idle_notifier
, n
);
55 EXPORT_SYMBOL_GPL(idle_notifier_unregister
);
58 struct kmem_cache
*task_xstate_cachep
;
59 EXPORT_SYMBOL_GPL(task_xstate_cachep
);
62 * this gets called so that we can store lazy state into memory and copy the
63 * current task into the new thread.
65 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
69 dst
->thread
.fpu_counter
= 0;
70 dst
->thread
.fpu
.has_fpu
= 0;
71 dst
->thread
.fpu
.last_cpu
= ~0;
72 dst
->thread
.fpu
.state
= NULL
;
73 if (tsk_used_math(src
)) {
74 int err
= fpu_alloc(&dst
->thread
.fpu
);
82 void free_thread_xstate(struct task_struct
*tsk
)
84 fpu_free(&tsk
->thread
.fpu
);
87 void arch_release_task_struct(struct task_struct
*tsk
)
89 free_thread_xstate(tsk
);
92 void arch_task_cache_init(void)
95 kmem_cache_create("task_xstate", xstate_size
,
96 __alignof__(union thread_xstate
),
97 SLAB_PANIC
| SLAB_NOTRACK
, NULL
);
102 * Free current thread data structures etc..
104 void exit_thread(void)
106 struct task_struct
*me
= current
;
107 struct thread_struct
*t
= &me
->thread
;
108 unsigned long *bp
= t
->io_bitmap_ptr
;
111 struct tss_struct
*tss
= &per_cpu(init_tss
, get_cpu());
113 t
->io_bitmap_ptr
= NULL
;
114 clear_thread_flag(TIF_IO_BITMAP
);
116 * Careful, clear this in the TSS too:
118 memset(tss
->io_bitmap
, 0xff, t
->io_bitmap_max
);
119 t
->io_bitmap_max
= 0;
127 void flush_thread(void)
129 struct task_struct
*tsk
= current
;
131 flush_ptrace_hw_breakpoint(tsk
);
132 memset(tsk
->thread
.tls_array
, 0, sizeof(tsk
->thread
.tls_array
));
135 * Free the FPU state for non xsave platforms. They get reallocated
136 * lazily at the first use.
138 if (!use_eager_fpu())
139 free_thread_xstate(tsk
);
142 static void hard_disable_TSC(void)
144 write_cr4(read_cr4() | X86_CR4_TSD
);
147 void disable_TSC(void)
150 if (!test_and_set_thread_flag(TIF_NOTSC
))
152 * Must flip the CPU state synchronously with
153 * TIF_NOTSC in the current running context.
159 static void hard_enable_TSC(void)
161 write_cr4(read_cr4() & ~X86_CR4_TSD
);
164 static void enable_TSC(void)
167 if (test_and_clear_thread_flag(TIF_NOTSC
))
169 * Must flip the CPU state synchronously with
170 * TIF_NOTSC in the current running context.
176 int get_tsc_mode(unsigned long adr
)
180 if (test_thread_flag(TIF_NOTSC
))
181 val
= PR_TSC_SIGSEGV
;
185 return put_user(val
, (unsigned int __user
*)adr
);
188 int set_tsc_mode(unsigned int val
)
190 if (val
== PR_TSC_SIGSEGV
)
192 else if (val
== PR_TSC_ENABLE
)
200 void __switch_to_xtra(struct task_struct
*prev_p
, struct task_struct
*next_p
,
201 struct tss_struct
*tss
)
203 struct thread_struct
*prev
, *next
;
205 prev
= &prev_p
->thread
;
206 next
= &next_p
->thread
;
208 if (test_tsk_thread_flag(prev_p
, TIF_BLOCKSTEP
) ^
209 test_tsk_thread_flag(next_p
, TIF_BLOCKSTEP
)) {
210 unsigned long debugctl
= get_debugctlmsr();
212 debugctl
&= ~DEBUGCTLMSR_BTF
;
213 if (test_tsk_thread_flag(next_p
, TIF_BLOCKSTEP
))
214 debugctl
|= DEBUGCTLMSR_BTF
;
216 update_debugctlmsr(debugctl
);
219 if (test_tsk_thread_flag(prev_p
, TIF_NOTSC
) ^
220 test_tsk_thread_flag(next_p
, TIF_NOTSC
)) {
221 /* prev and next are different */
222 if (test_tsk_thread_flag(next_p
, TIF_NOTSC
))
228 if (test_tsk_thread_flag(next_p
, TIF_IO_BITMAP
)) {
230 * Copy the relevant range of the IO bitmap.
231 * Normally this is 128 bytes or less:
233 memcpy(tss
->io_bitmap
, next
->io_bitmap_ptr
,
234 max(prev
->io_bitmap_max
, next
->io_bitmap_max
));
235 } else if (test_tsk_thread_flag(prev_p
, TIF_IO_BITMAP
)) {
237 * Clear any possible leftover bits:
239 memset(tss
->io_bitmap
, 0xff, prev
->io_bitmap_max
);
241 propagate_user_return_notify(prev_p
, next_p
);
245 * Idle related variables and functions
247 unsigned long boot_option_idle_override
= IDLE_NO_OVERRIDE
;
248 EXPORT_SYMBOL(boot_option_idle_override
);
250 static void (*x86_idle
)(void);
253 static inline void play_dead(void)
260 void enter_idle(void)
262 this_cpu_write(is_idle
, 1);
263 atomic_notifier_call_chain(&idle_notifier
, IDLE_START
, NULL
);
266 static void __exit_idle(void)
268 if (x86_test_and_clear_bit_percpu(0, is_idle
) == 0)
270 atomic_notifier_call_chain(&idle_notifier
, IDLE_END
, NULL
);
273 /* Called from interrupts to signify idle end */
276 /* idle loop has pid 0 */
283 void arch_cpu_idle_enter(void)
289 void arch_cpu_idle_exit(void)
294 void arch_cpu_idle_dead(void)
300 * Called from the generic idle code.
302 void arch_cpu_idle(void)
308 * We use this if we don't have any better idle routine..
310 void default_idle(void)
312 trace_cpu_idle_rcuidle(1, smp_processor_id());
314 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT
, smp_processor_id());
316 #ifdef CONFIG_APM_MODULE
317 EXPORT_SYMBOL(default_idle
);
321 bool xen_set_default_idle(void)
323 bool ret
= !!x86_idle
;
325 x86_idle
= default_idle
;
330 void stop_this_cpu(void *dummy
)
336 set_cpu_online(smp_processor_id(), false);
337 disable_local_APIC();
343 bool amd_e400_c1e_detected
;
344 EXPORT_SYMBOL(amd_e400_c1e_detected
);
346 static cpumask_var_t amd_e400_c1e_mask
;
348 void amd_e400_remove_cpu(int cpu
)
350 if (amd_e400_c1e_mask
!= NULL
)
351 cpumask_clear_cpu(cpu
, amd_e400_c1e_mask
);
355 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
356 * pending message MSR. If we detect C1E, then we handle it the same
357 * way as C3 power states (local apic timer and TSC stop)
359 static void amd_e400_idle(void)
361 if (!amd_e400_c1e_detected
) {
364 rdmsr(MSR_K8_INT_PENDING_MSG
, lo
, hi
);
366 if (lo
& K8_INTP_C1E_ACTIVE_MASK
) {
367 amd_e400_c1e_detected
= true;
368 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC
))
369 mark_tsc_unstable("TSC halt in AMD C1E");
370 pr_info("System has AMD C1E enabled\n");
374 if (amd_e400_c1e_detected
) {
375 int cpu
= smp_processor_id();
377 if (!cpumask_test_cpu(cpu
, amd_e400_c1e_mask
)) {
378 cpumask_set_cpu(cpu
, amd_e400_c1e_mask
);
380 * Force broadcast so ACPI can not interfere.
382 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE
,
384 pr_info("Switch to broadcast mode on CPU%d\n", cpu
);
386 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER
, &cpu
);
391 * The switch back from broadcast mode needs to be
392 * called with interrupts disabled.
395 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT
, &cpu
);
401 void select_idle_routine(const struct cpuinfo_x86
*c
)
404 if (boot_option_idle_override
== IDLE_POLL
&& smp_num_siblings
> 1)
405 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
407 if (x86_idle
|| boot_option_idle_override
== IDLE_POLL
)
410 if (cpu_has_bug(c
, X86_BUG_AMD_APIC_C1E
)) {
411 /* E400: APIC timer interrupt does not wake up CPU from C1e */
412 pr_info("using AMD E400 aware idle routine\n");
413 x86_idle
= amd_e400_idle
;
415 x86_idle
= default_idle
;
418 void __init
init_amd_e400_c1e_mask(void)
420 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
421 if (x86_idle
== amd_e400_idle
)
422 zalloc_cpumask_var(&amd_e400_c1e_mask
, GFP_KERNEL
);
425 static int __init
idle_setup(char *str
)
430 if (!strcmp(str
, "poll")) {
431 pr_info("using polling idle threads\n");
432 boot_option_idle_override
= IDLE_POLL
;
433 cpu_idle_poll_ctrl(true);
434 } else if (!strcmp(str
, "halt")) {
436 * When the boot option of idle=halt is added, halt is
437 * forced to be used for CPU idle. In such case CPU C2/C3
438 * won't be used again.
439 * To continue to load the CPU idle driver, don't touch
440 * the boot_option_idle_override.
442 x86_idle
= default_idle
;
443 boot_option_idle_override
= IDLE_HALT
;
444 } else if (!strcmp(str
, "nomwait")) {
446 * If the boot option of "idle=nomwait" is added,
447 * it means that mwait will be disabled for CPU C2/C3
448 * states. In such case it won't touch the variable
449 * of boot_option_idle_override.
451 boot_option_idle_override
= IDLE_NOMWAIT
;
457 early_param("idle", idle_setup
);
459 unsigned long arch_align_stack(unsigned long sp
)
461 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
462 sp
-= get_random_int() % 8192;
466 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
468 unsigned long range_end
= mm
->brk
+ 0x02000000;
469 return randomize_range(mm
->brk
, range_end
, 0) ? : mm
->brk
;