arch/x86/kernel/quirks.c

   1 /*
   2  * This file contains work-arounds for x86 and x86_64 platform bugs.
   3  */
   4 #include <linux/pci.h>
   5 #include <linux/irq.h>
   6
   7 #include <asm/hpet.h>
   8
   9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
  10
  11 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
  12 {
  13         u8 config, rev;
  14         u32 word;
  15
  16         /* BIOS may enable hardware IRQ balancing for
  17          * E7520/E7320/E7525(revision ID 0x9 and below)
  18          * based platforms.
  19          * Disable SW irqbalance/affinity on those platforms.
  20          */
  21         pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
  22         if (rev > 0x9)
  23                 return;
  24
  25         /* enable access to config space*/
  26         pci_read_config_byte(dev, 0xf4, &config);
  27         pci_write_config_byte(dev, 0xf4, config|0x2);
  28
  29         /* read xTPR register */
  30         raw_pci_ops->read(0, 0, 0x40, 0x4c, 2, &word);
  31
  32         if (!(word & (1 << 13))) {
  33                 printk(KERN_INFO "Intel E7520/7320/7525 detected. "
  34                         "Disabling irq balancing and affinity\n");
  35 #ifdef CONFIG_IRQBALANCE
  36                 irqbalance_disable("");
  37 #endif
  38                 noirqdebug_setup("");
  39 #ifdef CONFIG_PROC_FS
  40                 no_irq_affinity = 1;
  41 #endif
  42         }
  43
  44         /* put back the original value for config space*/
  45         if (!(config & 0x2))
  46                 pci_write_config_byte(dev, 0xf4, config);
  47 }
  48 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
  49                         quirk_intel_irqbalance);
  50 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
  51                         quirk_intel_irqbalance);
  52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
  53                         quirk_intel_irqbalance);
  54 #endif
  55
  56 #if defined(CONFIG_HPET_TIMER)
  57 unsigned long force_hpet_address;
  58
  59 static enum {
  60         NONE_FORCE_HPET_RESUME,
  61         OLD_ICH_FORCE_HPET_RESUME,
  62         ICH_FORCE_HPET_RESUME,
  63         VT8237_FORCE_HPET_RESUME
  64 } force_hpet_resume_type;
  65
  66 static void __iomem *rcba_base;
  67
  68 static void ich_force_hpet_resume(void)
  69 {
  70         u32 val;
  71
  72         if (!force_hpet_address)
  73                 return;
  74
  75         if (rcba_base == NULL)
  76                 BUG();
  77
  78         /* read the Function Disable register, dword mode only */
  79         val = readl(rcba_base + 0x3404);
  80         if (!(val & 0x80)) {
  81                 /* HPET disabled in HPTC. Trying to enable */
  82                 writel(val | 0x80, rcba_base + 0x3404);
  83         }
  84
  85         val = readl(rcba_base + 0x3404);
  86         if (!(val & 0x80))
  87                 BUG();
  88         else
  89                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
  90
  91         return;
  92 }
  93
  94 static void ich_force_enable_hpet(struct pci_dev *dev)
  95 {
  96         u32 val;
  97         u32 uninitialized_var(rcba);
  98         int err = 0;
  99
 100         if (hpet_address || force_hpet_address)
 101                 return;
 102
 103         pci_read_config_dword(dev, 0xF0, &rcba);
 104         rcba &= 0xFFFFC000;
 105         if (rcba == 0) {
 106                 printk(KERN_DEBUG "RCBA disabled. Cannot force enable HPET\n");
 107                 return;
 108         }
 109
 110         /* use bits 31:14, 16 kB aligned */
 111         rcba_base = ioremap_nocache(rcba, 0x4000);
 112         if (rcba_base == NULL) {
 113                 printk(KERN_DEBUG "ioremap failed. Cannot force enable HPET\n");
 114                 return;
 115         }
 116
 117         /* read the Function Disable register, dword mode only */
 118         val = readl(rcba_base + 0x3404);
 119
 120         if (val & 0x80) {
 121                 /* HPET is enabled in HPTC. Just not reported by BIOS */
 122                 val = val & 0x3;
 123                 force_hpet_address = 0xFED00000 | (val << 12);
 124                 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
 125                                force_hpet_address);
 126                 iounmap(rcba_base);
 127                 return;
 128         }
 129
 130         /* HPET disabled in HPTC. Trying to enable */
 131         writel(val | 0x80, rcba_base + 0x3404);
 132
 133         val = readl(rcba_base + 0x3404);
 134         if (!(val & 0x80)) {
 135                 err = 1;
 136         } else {
 137                 val = val & 0x3;
 138                 force_hpet_address = 0xFED00000 | (val << 12);
 139         }
 140
 141         if (err) {
 142                 force_hpet_address = 0;
 143                 iounmap(rcba_base);
 144                 printk(KERN_DEBUG "Failed to force enable HPET\n");
 145         } else {
 146                 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
 147                 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
 148                                force_hpet_address);
 149         }
 150 }
 151
 152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
 153                          ich_force_enable_hpet);
 154 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
 155                          ich_force_enable_hpet);
 156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
 157                          ich_force_enable_hpet);
 158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
 159                          ich_force_enable_hpet);
 160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
 161                          ich_force_enable_hpet);
 162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
 163                          ich_force_enable_hpet);
 164
 165
 166 static struct pci_dev *cached_dev;
 167
 168 static void old_ich_force_hpet_resume(void)
 169 {
 170         u32 val;
 171         u32 uninitialized_var(gen_cntl);
 172
 173         if (!force_hpet_address || !cached_dev)
 174                 return;
 175
 176         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
 177         gen_cntl &= (~(0x7 << 15));
 178         gen_cntl |= (0x4 << 15);
 179
 180         pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
 181         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
 182         val = gen_cntl >> 15;
 183         val &= 0x7;
 184         if (val == 0x4)
 185                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
 186         else
 187                 BUG();
 188 }
 189
 190 static void old_ich_force_enable_hpet(struct pci_dev *dev)
 191 {
 192         u32 val;
 193         u32 uninitialized_var(gen_cntl);
 194
 195         if (hpet_address || force_hpet_address)
 196                 return;
 197
 198         pci_read_config_dword(dev, 0xD0, &gen_cntl);
 199         /*
 200          * Bit 17 is HPET enable bit.
 201          * Bit 16:15 control the HPET base address.
 202          */
 203         val = gen_cntl >> 15;
 204         val &= 0x7;
 205         if (val & 0x4) {
 206                 val &= 0x3;
 207                 force_hpet_address = 0xFED00000 | (val << 12);
 208                 printk(KERN_DEBUG "HPET at base address 0x%lx\n",
 209                                force_hpet_address);
 210                 return;
 211         }
 212
 213         /*
 214          * HPET is disabled. Trying enabling at FED00000 and check
 215          * whether it sticks
 216          */
 217         gen_cntl &= (~(0x7 << 15));
 218         gen_cntl |= (0x4 << 15);
 219         pci_write_config_dword(dev, 0xD0, gen_cntl);
 220
 221         pci_read_config_dword(dev, 0xD0, &gen_cntl);
 222
 223         val = gen_cntl >> 15;
 224         val &= 0x7;
 225         if (val & 0x4) {
 226                 /* HPET is enabled in HPTC. Just not reported by BIOS */
 227                 val &= 0x3;
 228                 force_hpet_address = 0xFED00000 | (val << 12);
 229                 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
 230                                force_hpet_address);
 231                 cached_dev = dev;
 232                 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
 233                 return;
 234         }
 235
 236         printk(KERN_DEBUG "Failed to force enable HPET\n");
 237 }
 238
 239 /*
 240  * Undocumented chipset features. Make sure that the user enforced
 241  * this.
 242  */
 243 static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
 244 {
 245         if (hpet_force_user)
 246                 old_ich_force_enable_hpet(dev);
 247 }
 248
 249 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
 250                          old_ich_force_enable_hpet_user);
 251 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
 252                          old_ich_force_enable_hpet_user);
 253 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
 254                          old_ich_force_enable_hpet_user);
 255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
 256                          old_ich_force_enable_hpet_user);
 257 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
 258                          old_ich_force_enable_hpet);
 259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
 260                          old_ich_force_enable_hpet);
 261
 262
 263 static void vt8237_force_hpet_resume(void)
 264 {
 265         u32 val;
 266
 267         if (!force_hpet_address || !cached_dev)
 268                 return;
 269
 270         val = 0xfed00000 | 0x80;
 271         pci_write_config_dword(cached_dev, 0x68, val);
 272
 273         pci_read_config_dword(cached_dev, 0x68, &val);
 274         if (val & 0x80)
 275                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
 276         else
 277                 BUG();
 278 }
 279
 280 static void vt8237_force_enable_hpet(struct pci_dev *dev)
 281 {
 282         u32 uninitialized_var(val);
 283
 284         if (!hpet_force_user || hpet_address || force_hpet_address)
 285                 return;
 286
 287         pci_read_config_dword(dev, 0x68, &val);
 288         /*
 289          * Bit 7 is HPET enable bit.
 290          * Bit 31:10 is HPET base address (contrary to what datasheet claims)
 291          */
 292         if (val & 0x80) {
 293                 force_hpet_address = (val & ~0x3ff);
 294                 printk(KERN_DEBUG "HPET at base address 0x%lx\n",
 295                                force_hpet_address);
 296                 return;
 297         }
 298
 299         /*
 300          * HPET is disabled. Trying enabling at FED00000 and check
 301          * whether it sticks
 302          */
 303         val = 0xfed00000 | 0x80;
 304         pci_write_config_dword(dev, 0x68, val);
 305
 306         pci_read_config_dword(dev, 0x68, &val);
 307         if (val & 0x80) {
 308                 force_hpet_address = (val & ~0x3ff);
 309                 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
 310                                force_hpet_address);
 311                 cached_dev = dev;
 312                 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
 313                 return;
 314         }
 315
 316         printk(KERN_DEBUG "Failed to force enable HPET\n");
 317 }
 318
 319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
 320                          vt8237_force_enable_hpet);
 321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
 322                          vt8237_force_enable_hpet);
 323
 324
 325 void force_hpet_resume(void)
 326 {
 327         switch (force_hpet_resume_type) {
 328             case ICH_FORCE_HPET_RESUME:
 329                 return ich_force_hpet_resume();
 330
 331             case OLD_ICH_FORCE_HPET_RESUME:
 332                 return old_ich_force_hpet_resume();
 333
 334             case VT8237_FORCE_HPET_RESUME:
 335                 return vt8237_force_hpet_resume();
 336
 337             default:
 338                 break;
 339         }
 340 }
 341
 342 #endif