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341230db74e1d20256ea79256c3cb0c54393a943
[deliverable/linux.git] / arch / x86 / kernel / setup_64.c
1 /*
2 * Copyright (C) 1995 Linus Torvalds
3 */
4
5 /*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
12 #include <linux/mm.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/screen_info.h>
19 #include <linux/ioport.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/initrd.h>
23 #include <linux/highmem.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
26 #include <asm/processor.h>
27 #include <linux/console.h>
28 #include <linux/seq_file.h>
29 #include <linux/crash_dump.h>
30 #include <linux/root_dev.h>
31 #include <linux/pci.h>
32 #include <asm/pci-direct.h>
33 #include <linux/efi.h>
34 #include <linux/acpi.h>
35 #include <linux/kallsyms.h>
36 #include <linux/edd.h>
37 #include <linux/iscsi_ibft.h>
38 #include <linux/mmzone.h>
39 #include <linux/kexec.h>
40 #include <linux/cpufreq.h>
41 #include <linux/dmi.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/ctype.h>
44 #include <linux/sort.h>
45 #include <linux/uaccess.h>
46 #include <linux/init_ohci1394_dma.h>
47 #include <linux/kvm_para.h>
48
49 #include <asm/mtrr.h>
50 #include <asm/uaccess.h>
51 #include <asm/system.h>
52 #include <asm/vsyscall.h>
53 #include <asm/io.h>
54 #include <asm/smp.h>
55 #include <asm/msr.h>
56 #include <asm/desc.h>
57 #include <video/edid.h>
58 #include <asm/e820.h>
59 #include <asm/dma.h>
60 #include <asm/gart.h>
61 #include <asm/mpspec.h>
62 #include <asm/mmu_context.h>
63 #include <asm/proto.h>
64 #include <asm/setup.h>
65 #include <asm/numa.h>
66 #include <asm/sections.h>
67 #include <asm/dmi.h>
68 #include <asm/cacheflush.h>
69 #include <asm/mce.h>
70 #include <asm/ds.h>
71 #include <asm/topology.h>
72 #include <asm/trampoline.h>
73 #include <asm/pat.h>
74 #include <asm/mmconfig.h>
75
76 #include <mach_apic.h>
77 #ifdef CONFIG_PARAVIRT
78 #include <asm/paravirt.h>
79 #else
80 #define ARCH_SETUP
81 #endif
82
83 /*
84 * Machine setup..
85 */
86
87 struct cpuinfo_x86 boot_cpu_data __read_mostly;
88 EXPORT_SYMBOL(boot_cpu_data);
89
90 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
91
92 unsigned long mmu_cr4_features;
93
94 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
95 int bootloader_type;
96
97 unsigned long saved_video_mode;
98
99 int force_mwait __cpuinitdata;
100
101 /*
102 * Early DMI memory
103 */
104 int dmi_alloc_index;
105 char dmi_alloc_data[DMI_MAX_DATA];
106
107 /*
108 * Setup options
109 */
110 struct screen_info screen_info;
111 EXPORT_SYMBOL(screen_info);
112 struct sys_desc_table_struct {
113 unsigned short length;
114 unsigned char table[0];
115 };
116
117 struct edid_info edid_info;
118 EXPORT_SYMBOL_GPL(edid_info);
119
120 extern int root_mountflags;
121
122 char __initdata command_line[COMMAND_LINE_SIZE];
123
124 static struct resource standard_io_resources[] = {
125 { .name = "dma1", .start = 0x00, .end = 0x1f,
126 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
127 { .name = "pic1", .start = 0x20, .end = 0x21,
128 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
129 { .name = "timer0", .start = 0x40, .end = 0x43,
130 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
131 { .name = "timer1", .start = 0x50, .end = 0x53,
132 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
133 { .name = "keyboard", .start = 0x60, .end = 0x60,
134 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
135 { .name = "keyboard", .start = 0x64, .end = 0x64,
136 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
137 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
138 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
139 { .name = "pic2", .start = 0xa0, .end = 0xa1,
140 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
141 { .name = "dma2", .start = 0xc0, .end = 0xdf,
142 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
143 { .name = "fpu", .start = 0xf0, .end = 0xff,
144 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
145 };
146
147 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
148
149 static struct resource data_resource = {
150 .name = "Kernel data",
151 .start = 0,
152 .end = 0,
153 .flags = IORESOURCE_RAM,
154 };
155 static struct resource code_resource = {
156 .name = "Kernel code",
157 .start = 0,
158 .end = 0,
159 .flags = IORESOURCE_RAM,
160 };
161 static struct resource bss_resource = {
162 .name = "Kernel bss",
163 .start = 0,
164 .end = 0,
165 .flags = IORESOURCE_RAM,
166 };
167
168 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
169
170 #ifdef CONFIG_PROC_VMCORE
171 /* elfcorehdr= specifies the location of elf core header
172 * stored by the crashed kernel. This option will be passed
173 * by kexec loader to the capture kernel.
174 */
175 static int __init setup_elfcorehdr(char *arg)
176 {
177 char *end;
178 if (!arg)
179 return -EINVAL;
180 elfcorehdr_addr = memparse(arg, &end);
181 return end > arg ? 0 : -EINVAL;
182 }
183 early_param("elfcorehdr", setup_elfcorehdr);
184 #endif
185
186 #ifndef CONFIG_NUMA
187 static void __init
188 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
189 {
190 unsigned long bootmap_size, bootmap;
191
192 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
193 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
194 PAGE_SIZE);
195 if (bootmap == -1L)
196 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
197 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
198 e820_register_active_regions(0, start_pfn, end_pfn);
199 free_bootmem_with_active_regions(0, end_pfn);
200 early_res_to_bootmem(0, end_pfn<<PAGE_SHIFT);
201 reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
202 }
203 #endif
204
205 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
206 struct edd edd;
207 #ifdef CONFIG_EDD_MODULE
208 EXPORT_SYMBOL(edd);
209 #endif
210 /**
211 * copy_edd() - Copy the BIOS EDD information
212 * from boot_params into a safe place.
213 *
214 */
215 static inline void copy_edd(void)
216 {
217 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
218 sizeof(edd.mbr_signature));
219 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
220 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
221 edd.edd_info_nr = boot_params.eddbuf_entries;
222 }
223 #else
224 static inline void copy_edd(void)
225 {
226 }
227 #endif
228
229 #ifdef CONFIG_KEXEC
230 static void __init reserve_crashkernel(void)
231 {
232 unsigned long long total_mem;
233 unsigned long long crash_size, crash_base;
234 int ret;
235
236 total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
237
238 ret = parse_crashkernel(boot_command_line, total_mem,
239 &crash_size, &crash_base);
240 if (ret == 0 && crash_size) {
241 if (crash_base <= 0) {
242 printk(KERN_INFO "crashkernel reservation failed - "
243 "you have to specify a base address\n");
244 return;
245 }
246
247 if (reserve_bootmem(crash_base, crash_size,
248 BOOTMEM_EXCLUSIVE) < 0) {
249 printk(KERN_INFO "crashkernel reservation failed - "
250 "memory is in use\n");
251 return;
252 }
253
254 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
255 "for crashkernel (System RAM: %ldMB)\n",
256 (unsigned long)(crash_size >> 20),
257 (unsigned long)(crash_base >> 20),
258 (unsigned long)(total_mem >> 20));
259 crashk_res.start = crash_base;
260 crashk_res.end = crash_base + crash_size - 1;
261 insert_resource(&iomem_resource, &crashk_res);
262 }
263 }
264 #else
265 static inline void __init reserve_crashkernel(void)
266 {}
267 #endif
268
269 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
270 void __attribute__((weak)) __init memory_setup(void)
271 {
272 machine_specific_memory_setup();
273 }
274
275 static void __init parse_setup_data(void)
276 {
277 struct setup_data *data;
278 unsigned long pa_data;
279
280 if (boot_params.hdr.version < 0x0209)
281 return;
282 pa_data = boot_params.hdr.setup_data;
283 while (pa_data) {
284 data = early_ioremap(pa_data, PAGE_SIZE);
285 switch (data->type) {
286 default:
287 break;
288 }
289 #ifndef CONFIG_DEBUG_BOOT_PARAMS
290 free_early(pa_data, pa_data+sizeof(*data)+data->len);
291 #endif
292 pa_data = data->next;
293 early_iounmap(data, PAGE_SIZE);
294 }
295 }
296
297 /*
298 * setup_arch - architecture-specific boot-time initializations
299 *
300 * Note: On x86_64, fixmaps are ready for use even before this is called.
301 */
302 void __init setup_arch(char **cmdline_p)
303 {
304 unsigned i;
305
306 printk(KERN_INFO "Command line: %s\n", boot_command_line);
307
308 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
309 screen_info = boot_params.screen_info;
310 edid_info = boot_params.edid_info;
311 saved_video_mode = boot_params.hdr.vid_mode;
312 bootloader_type = boot_params.hdr.type_of_loader;
313
314 #ifdef CONFIG_BLK_DEV_RAM
315 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
316 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
317 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
318 #endif
319 #ifdef CONFIG_EFI
320 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
321 "EL64", 4))
322 efi_enabled = 1;
323 #endif
324
325 ARCH_SETUP
326
327 memory_setup();
328 copy_edd();
329
330 if (!boot_params.hdr.root_flags)
331 root_mountflags &= ~MS_RDONLY;
332 init_mm.start_code = (unsigned long) &_text;
333 init_mm.end_code = (unsigned long) &_etext;
334 init_mm.end_data = (unsigned long) &_edata;
335 init_mm.brk = (unsigned long) &_end;
336
337 code_resource.start = virt_to_phys(&_text);
338 code_resource.end = virt_to_phys(&_etext)-1;
339 data_resource.start = virt_to_phys(&_etext);
340 data_resource.end = virt_to_phys(&_edata)-1;
341 bss_resource.start = virt_to_phys(&__bss_start);
342 bss_resource.end = virt_to_phys(&__bss_stop)-1;
343
344 early_identify_cpu(&boot_cpu_data);
345
346 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
347 *cmdline_p = command_line;
348
349 parse_setup_data();
350
351 parse_early_param();
352
353 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
354 if (init_ohci1394_dma_early)
355 init_ohci1394_dma_on_all_controllers();
356 #endif
357
358 finish_e820_parsing();
359
360 /* after parse_early_param, so could debug it */
361 insert_resource(&iomem_resource, &code_resource);
362 insert_resource(&iomem_resource, &data_resource);
363 insert_resource(&iomem_resource, &bss_resource);
364
365 early_gart_iommu_check();
366
367 e820_register_active_regions(0, 0, -1UL);
368 /*
369 * partially used pages are not usable - thus
370 * we are rounding upwards:
371 */
372 end_pfn = e820_end_of_ram();
373 /* update e820 for memory not covered by WB MTRRs */
374 mtrr_bp_init();
375 if (mtrr_trim_uncached_memory(end_pfn)) {
376 e820_register_active_regions(0, 0, -1UL);
377 end_pfn = e820_end_of_ram();
378 }
379
380 num_physpages = end_pfn;
381
382 check_efer();
383
384 max_pfn_mapped = init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
385 if (efi_enabled)
386 efi_init();
387
388 vsmp_init();
389
390 dmi_scan_machine();
391
392 io_delay_init();
393
394 #ifdef CONFIG_KVM_CLOCK
395 kvmclock_init();
396 #endif
397
398 #ifdef CONFIG_SMP
399 /* setup to use the early static init tables during kernel startup */
400 x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
401 x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
402 #ifdef CONFIG_NUMA
403 x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
404 #endif
405 #endif
406
407 #ifdef CONFIG_ACPI
408 /*
409 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
410 * Call this early for SRAT node setup.
411 */
412 acpi_boot_table_init();
413 #endif
414
415 /* How many end-of-memory variables you have, grandma! */
416 max_low_pfn = end_pfn;
417 max_pfn = end_pfn;
418 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
419
420 /* Remove active ranges so rediscovery with NUMA-awareness happens */
421 remove_all_active_ranges();
422
423 #ifdef CONFIG_ACPI_NUMA
424 /*
425 * Parse SRAT to discover nodes.
426 */
427 acpi_numa_init();
428 #endif
429
430 #ifdef CONFIG_NUMA
431 numa_initmem_init(0, end_pfn);
432 #else
433 contig_initmem_init(0, end_pfn);
434 #endif
435
436 dma32_reserve_bootmem();
437
438 #ifdef CONFIG_ACPI_SLEEP
439 /*
440 * Reserve low memory region for sleep support.
441 */
442 acpi_reserve_bootmem();
443 #endif
444
445 if (efi_enabled)
446 efi_reserve_bootmem();
447
448 /*
449 * Find and reserve possible boot-time SMP configuration:
450 */
451 find_smp_config();
452 #ifdef CONFIG_BLK_DEV_INITRD
453 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
454 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
455 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
456 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
457 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
458
459 if (ramdisk_end <= end_of_mem) {
460 /*
461 * don't need to reserve again, already reserved early
462 * in x86_64_start_kernel, and early_res_to_bootmem
463 * convert that to reserved in bootmem
464 */
465 initrd_start = ramdisk_image + PAGE_OFFSET;
466 initrd_end = initrd_start+ramdisk_size;
467 } else {
468 free_bootmem(ramdisk_image, ramdisk_size);
469 printk(KERN_ERR "initrd extends beyond end of memory "
470 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
471 ramdisk_end, end_of_mem);
472 initrd_start = 0;
473 }
474 }
475 #endif
476 reserve_crashkernel();
477
478 reserve_ibft_region();
479
480 paging_init();
481 map_vsyscall();
482
483 early_quirks();
484
485 #ifdef CONFIG_ACPI
486 /*
487 * Read APIC and some other early information from ACPI tables.
488 */
489 acpi_boot_init();
490 #endif
491
492 init_cpu_to_node();
493
494 /*
495 * get boot-time SMP configuration:
496 */
497 if (smp_found_config)
498 get_smp_config();
499 init_apic_mappings();
500 ioapic_init_mappings();
501
502 kvm_guest_init();
503
504 /*
505 * We trust e820 completely. No explicit ROM probing in memory.
506 */
507 e820_reserve_resources();
508 e820_mark_nosave_regions();
509
510 /* request I/O space for devices used on all i[345]86 PCs */
511 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
512 request_resource(&ioport_resource, &standard_io_resources[i]);
513
514 e820_setup_gap();
515
516 #ifdef CONFIG_VT
517 #if defined(CONFIG_VGA_CONSOLE)
518 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
519 conswitchp = &vga_con;
520 #elif defined(CONFIG_DUMMY_CONSOLE)
521 conswitchp = &dummy_con;
522 #endif
523 #endif
524
525 /* do this before identify_cpu for boot cpu */
526 check_enable_amd_mmconf_dmi();
527 }
528
529 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
530 {
531 unsigned int *v;
532
533 if (c->extended_cpuid_level < 0x80000004)
534 return 0;
535
536 v = (unsigned int *) c->x86_model_id;
537 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
538 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
539 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
540 c->x86_model_id[48] = 0;
541 return 1;
542 }
543
544
545 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
546 {
547 unsigned int n, dummy, eax, ebx, ecx, edx;
548
549 n = c->extended_cpuid_level;
550
551 if (n >= 0x80000005) {
552 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
553 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
554 "D cache %dK (%d bytes/line)\n",
555 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
556 c->x86_cache_size = (ecx>>24) + (edx>>24);
557 /* On K8 L1 TLB is inclusive, so don't count it */
558 c->x86_tlbsize = 0;
559 }
560
561 if (n >= 0x80000006) {
562 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
563 ecx = cpuid_ecx(0x80000006);
564 c->x86_cache_size = ecx >> 16;
565 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
566
567 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
568 c->x86_cache_size, ecx & 0xFF);
569 }
570 if (n >= 0x80000008) {
571 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
572 c->x86_virt_bits = (eax >> 8) & 0xff;
573 c->x86_phys_bits = eax & 0xff;
574 }
575 }
576
577 #ifdef CONFIG_NUMA
578 static int __cpuinit nearby_node(int apicid)
579 {
580 int i, node;
581
582 for (i = apicid - 1; i >= 0; i--) {
583 node = apicid_to_node[i];
584 if (node != NUMA_NO_NODE && node_online(node))
585 return node;
586 }
587 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
588 node = apicid_to_node[i];
589 if (node != NUMA_NO_NODE && node_online(node))
590 return node;
591 }
592 return first_node(node_online_map); /* Shouldn't happen */
593 }
594 #endif
595
596 /*
597 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
598 * Assumes number of cores is a power of two.
599 */
600 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
601 {
602 #ifdef CONFIG_SMP
603 unsigned bits;
604 #ifdef CONFIG_NUMA
605 int cpu = smp_processor_id();
606 int node = 0;
607 unsigned apicid = hard_smp_processor_id();
608 #endif
609 bits = c->x86_coreid_bits;
610
611 /* Low order bits define the core id (index of core in socket) */
612 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
613 /* Convert the initial APIC ID into the socket ID */
614 c->phys_proc_id = c->initial_apicid >> bits;
615
616 #ifdef CONFIG_NUMA
617 node = c->phys_proc_id;
618 if (apicid_to_node[apicid] != NUMA_NO_NODE)
619 node = apicid_to_node[apicid];
620 if (!node_online(node)) {
621 /* Two possibilities here:
622 - The CPU is missing memory and no node was created.
623 In that case try picking one from a nearby CPU
624 - The APIC IDs differ from the HyperTransport node IDs
625 which the K8 northbridge parsing fills in.
626 Assume they are all increased by a constant offset,
627 but in the same order as the HT nodeids.
628 If that doesn't result in a usable node fall back to the
629 path for the previous case. */
630
631 int ht_nodeid = c->initial_apicid;
632
633 if (ht_nodeid >= 0 &&
634 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
635 node = apicid_to_node[ht_nodeid];
636 /* Pick a nearby node */
637 if (!node_online(node))
638 node = nearby_node(apicid);
639 }
640 numa_set_node(cpu, node);
641
642 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
643 #endif
644 #endif
645 }
646
647 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
648 {
649 #ifdef CONFIG_SMP
650 unsigned bits, ecx;
651
652 /* Multi core CPU? */
653 if (c->extended_cpuid_level < 0x80000008)
654 return;
655
656 ecx = cpuid_ecx(0x80000008);
657
658 c->x86_max_cores = (ecx & 0xff) + 1;
659
660 /* CPU telling us the core id bits shift? */
661 bits = (ecx >> 12) & 0xF;
662
663 /* Otherwise recompute */
664 if (bits == 0) {
665 while ((1 << bits) < c->x86_max_cores)
666 bits++;
667 }
668
669 c->x86_coreid_bits = bits;
670
671 #endif
672 }
673
674 #define ENABLE_C1E_MASK 0x18000000
675 #define CPUID_PROCESSOR_SIGNATURE 1
676 #define CPUID_XFAM 0x0ff00000
677 #define CPUID_XFAM_K8 0x00000000
678 #define CPUID_XFAM_10H 0x00100000
679 #define CPUID_XFAM_11H 0x00200000
680 #define CPUID_XMOD 0x000f0000
681 #define CPUID_XMOD_REV_F 0x00040000
682
683 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
684 static __cpuinit int amd_apic_timer_broken(void)
685 {
686 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
687
688 switch (eax & CPUID_XFAM) {
689 case CPUID_XFAM_K8:
690 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
691 break;
692 case CPUID_XFAM_10H:
693 case CPUID_XFAM_11H:
694 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
695 if (lo & ENABLE_C1E_MASK)
696 return 1;
697 break;
698 default:
699 /* err on the side of caution */
700 return 1;
701 }
702 return 0;
703 }
704
705 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
706 {
707 early_init_amd_mc(c);
708
709 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
710 if (c->x86_power & (1<<8))
711 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
712 }
713
714 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
715 {
716 unsigned level;
717
718 #ifdef CONFIG_SMP
719 unsigned long value;
720
721 /*
722 * Disable TLB flush filter by setting HWCR.FFDIS on K8
723 * bit 6 of msr C001_0015
724 *
725 * Errata 63 for SH-B3 steppings
726 * Errata 122 for all steppings (F+ have it disabled by default)
727 */
728 if (c->x86 == 15) {
729 rdmsrl(MSR_K8_HWCR, value);
730 value |= 1 << 6;
731 wrmsrl(MSR_K8_HWCR, value);
732 }
733 #endif
734
735 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
736 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
737 clear_cpu_cap(c, 0*32+31);
738
739 /* On C+ stepping K8 rep microcode works well for copy/memset */
740 level = cpuid_eax(1);
741 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
742 level >= 0x0f58))
743 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
744 if (c->x86 == 0x10 || c->x86 == 0x11)
745 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
746
747 /* Enable workaround for FXSAVE leak */
748 if (c->x86 >= 6)
749 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
750
751 level = get_model_name(c);
752 if (!level) {
753 switch (c->x86) {
754 case 15:
755 /* Should distinguish Models here, but this is only
756 a fallback anyways. */
757 strcpy(c->x86_model_id, "Hammer");
758 break;
759 }
760 }
761 display_cacheinfo(c);
762
763 /* Multi core CPU? */
764 if (c->extended_cpuid_level >= 0x80000008)
765 amd_detect_cmp(c);
766
767 if (c->extended_cpuid_level >= 0x80000006 &&
768 (cpuid_edx(0x80000006) & 0xf000))
769 num_cache_leaves = 4;
770 else
771 num_cache_leaves = 3;
772
773 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
774 set_cpu_cap(c, X86_FEATURE_K8);
775
776 /* MFENCE stops RDTSC speculation */
777 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
778
779 if (c->x86 == 0x10)
780 fam10h_check_enable_mmcfg();
781
782 if (amd_apic_timer_broken())
783 disable_apic_timer = 1;
784
785 if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
786 unsigned long long tseg;
787
788 /*
789 * Split up direct mapping around the TSEG SMM area.
790 * Don't do it for gbpages because there seems very little
791 * benefit in doing so.
792 */
793 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
794 (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
795 set_memory_4k((unsigned long)__va(tseg), 1);
796 }
797 }
798
799 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
800 {
801 #ifdef CONFIG_SMP
802 u32 eax, ebx, ecx, edx;
803 int index_msb, core_bits;
804
805 cpuid(1, &eax, &ebx, &ecx, &edx);
806
807
808 if (!cpu_has(c, X86_FEATURE_HT))
809 return;
810 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
811 goto out;
812
813 smp_num_siblings = (ebx & 0xff0000) >> 16;
814
815 if (smp_num_siblings == 1) {
816 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
817 } else if (smp_num_siblings > 1) {
818
819 if (smp_num_siblings > NR_CPUS) {
820 printk(KERN_WARNING "CPU: Unsupported number of "
821 "siblings %d", smp_num_siblings);
822 smp_num_siblings = 1;
823 return;
824 }
825
826 index_msb = get_count_order(smp_num_siblings);
827 c->phys_proc_id = phys_pkg_id(index_msb);
828
829 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
830
831 index_msb = get_count_order(smp_num_siblings);
832
833 core_bits = get_count_order(c->x86_max_cores);
834
835 c->cpu_core_id = phys_pkg_id(index_msb) &
836 ((1 << core_bits) - 1);
837 }
838 out:
839 if ((c->x86_max_cores * smp_num_siblings) > 1) {
840 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
841 c->phys_proc_id);
842 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
843 c->cpu_core_id);
844 }
845
846 #endif
847 }
848
849 /*
850 * find out the number of processor cores on the die
851 */
852 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
853 {
854 unsigned int eax, t;
855
856 if (c->cpuid_level < 4)
857 return 1;
858
859 cpuid_count(4, 0, &eax, &t, &t, &t);
860
861 if (eax & 0x1f)
862 return ((eax >> 26) + 1);
863 else
864 return 1;
865 }
866
867 static void __cpuinit srat_detect_node(void)
868 {
869 #ifdef CONFIG_NUMA
870 unsigned node;
871 int cpu = smp_processor_id();
872 int apicid = hard_smp_processor_id();
873
874 /* Don't do the funky fallback heuristics the AMD version employs
875 for now. */
876 node = apicid_to_node[apicid];
877 if (node == NUMA_NO_NODE || !node_online(node))
878 node = first_node(node_online_map);
879 numa_set_node(cpu, node);
880
881 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
882 #endif
883 }
884
885 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
886 {
887 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
888 (c->x86 == 0x6 && c->x86_model >= 0x0e))
889 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
890 }
891
892 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
893 {
894 /* Cache sizes */
895 unsigned n;
896
897 init_intel_cacheinfo(c);
898 if (c->cpuid_level > 9) {
899 unsigned eax = cpuid_eax(10);
900 /* Check for version and the number of counters */
901 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
902 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
903 }
904
905 if (cpu_has_ds) {
906 unsigned int l1, l2;
907 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
908 if (!(l1 & (1<<11)))
909 set_cpu_cap(c, X86_FEATURE_BTS);
910 if (!(l1 & (1<<12)))
911 set_cpu_cap(c, X86_FEATURE_PEBS);
912 }
913
914
915 if (cpu_has_bts)
916 ds_init_intel(c);
917
918 n = c->extended_cpuid_level;
919 if (n >= 0x80000008) {
920 unsigned eax = cpuid_eax(0x80000008);
921 c->x86_virt_bits = (eax >> 8) & 0xff;
922 c->x86_phys_bits = eax & 0xff;
923 /* CPUID workaround for Intel 0F34 CPU */
924 if (c->x86_vendor == X86_VENDOR_INTEL &&
925 c->x86 == 0xF && c->x86_model == 0x3 &&
926 c->x86_mask == 0x4)
927 c->x86_phys_bits = 36;
928 }
929
930 if (c->x86 == 15)
931 c->x86_cache_alignment = c->x86_clflush_size * 2;
932 if (c->x86 == 6)
933 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
934 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
935 c->x86_max_cores = intel_num_cpu_cores(c);
936
937 srat_detect_node();
938 }
939
940 static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
941 {
942 if (c->x86 == 0x6 && c->x86_model >= 0xf)
943 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
944 }
945
946 static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
947 {
948 /* Cache sizes */
949 unsigned n;
950
951 n = c->extended_cpuid_level;
952 if (n >= 0x80000008) {
953 unsigned eax = cpuid_eax(0x80000008);
954 c->x86_virt_bits = (eax >> 8) & 0xff;
955 c->x86_phys_bits = eax & 0xff;
956 }
957
958 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
959 c->x86_cache_alignment = c->x86_clflush_size * 2;
960 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
961 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
962 }
963 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
964 }
965
966 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
967 {
968 char *v = c->x86_vendor_id;
969
970 if (!strcmp(v, "AuthenticAMD"))
971 c->x86_vendor = X86_VENDOR_AMD;
972 else if (!strcmp(v, "GenuineIntel"))
973 c->x86_vendor = X86_VENDOR_INTEL;
974 else if (!strcmp(v, "CentaurHauls"))
975 c->x86_vendor = X86_VENDOR_CENTAUR;
976 else
977 c->x86_vendor = X86_VENDOR_UNKNOWN;
978 }
979
980 /* Do some early cpuid on the boot CPU to get some parameter that are
981 needed before check_bugs. Everything advanced is in identify_cpu
982 below. */
983 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
984 {
985 u32 tfms, xlvl;
986
987 c->loops_per_jiffy = loops_per_jiffy;
988 c->x86_cache_size = -1;
989 c->x86_vendor = X86_VENDOR_UNKNOWN;
990 c->x86_model = c->x86_mask = 0; /* So far unknown... */
991 c->x86_vendor_id[0] = '\0'; /* Unset */
992 c->x86_model_id[0] = '\0'; /* Unset */
993 c->x86_clflush_size = 64;
994 c->x86_cache_alignment = c->x86_clflush_size;
995 c->x86_max_cores = 1;
996 c->x86_coreid_bits = 0;
997 c->extended_cpuid_level = 0;
998 memset(&c->x86_capability, 0, sizeof c->x86_capability);
999
1000 /* Get vendor name */
1001 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
1002 (unsigned int *)&c->x86_vendor_id[0],
1003 (unsigned int *)&c->x86_vendor_id[8],
1004 (unsigned int *)&c->x86_vendor_id[4]);
1005
1006 get_cpu_vendor(c);
1007
1008 /* Initialize the standard set of capabilities */
1009 /* Note that the vendor-specific code below might override */
1010
1011 /* Intel-defined flags: level 0x00000001 */
1012 if (c->cpuid_level >= 0x00000001) {
1013 __u32 misc;
1014 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
1015 &c->x86_capability[0]);
1016 c->x86 = (tfms >> 8) & 0xf;
1017 c->x86_model = (tfms >> 4) & 0xf;
1018 c->x86_mask = tfms & 0xf;
1019 if (c->x86 == 0xf)
1020 c->x86 += (tfms >> 20) & 0xff;
1021 if (c->x86 >= 0x6)
1022 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1023 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
1024 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1025 } else {
1026 /* Have CPUID level 0 only - unheard of */
1027 c->x86 = 4;
1028 }
1029
1030 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
1031 #ifdef CONFIG_SMP
1032 c->phys_proc_id = c->initial_apicid;
1033 #endif
1034 /* AMD-defined flags: level 0x80000001 */
1035 xlvl = cpuid_eax(0x80000000);
1036 c->extended_cpuid_level = xlvl;
1037 if ((xlvl & 0xffff0000) == 0x80000000) {
1038 if (xlvl >= 0x80000001) {
1039 c->x86_capability[1] = cpuid_edx(0x80000001);
1040 c->x86_capability[6] = cpuid_ecx(0x80000001);
1041 }
1042 if (xlvl >= 0x80000004)
1043 get_model_name(c); /* Default name */
1044 }
1045
1046 /* Transmeta-defined flags: level 0x80860001 */
1047 xlvl = cpuid_eax(0x80860000);
1048 if ((xlvl & 0xffff0000) == 0x80860000) {
1049 /* Don't set x86_cpuid_level here for now to not confuse. */
1050 if (xlvl >= 0x80860001)
1051 c->x86_capability[2] = cpuid_edx(0x80860001);
1052 }
1053
1054 c->extended_cpuid_level = cpuid_eax(0x80000000);
1055 if (c->extended_cpuid_level >= 0x80000007)
1056 c->x86_power = cpuid_edx(0x80000007);
1057
1058 switch (c->x86_vendor) {
1059 case X86_VENDOR_AMD:
1060 early_init_amd(c);
1061 break;
1062 case X86_VENDOR_INTEL:
1063 early_init_intel(c);
1064 break;
1065 case X86_VENDOR_CENTAUR:
1066 early_init_centaur(c);
1067 break;
1068 }
1069
1070 validate_pat_support(c);
1071 }
1072
1073 /*
1074 * This does the hard work of actually picking apart the CPU stuff...
1075 */
1076 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1077 {
1078 int i;
1079
1080 early_identify_cpu(c);
1081
1082 init_scattered_cpuid_features(c);
1083
1084 c->apicid = phys_pkg_id(0);
1085
1086 /*
1087 * Vendor-specific initialization. In this section we
1088 * canonicalize the feature flags, meaning if there are
1089 * features a certain CPU supports which CPUID doesn't
1090 * tell us, CPUID claiming incorrect flags, or other bugs,
1091 * we handle them here.
1092 *
1093 * At the end of this section, c->x86_capability better
1094 * indicate the features this CPU genuinely supports!
1095 */
1096 switch (c->x86_vendor) {
1097 case X86_VENDOR_AMD:
1098 init_amd(c);
1099 break;
1100
1101 case X86_VENDOR_INTEL:
1102 init_intel(c);
1103 break;
1104
1105 case X86_VENDOR_CENTAUR:
1106 init_centaur(c);
1107 break;
1108
1109 case X86_VENDOR_UNKNOWN:
1110 default:
1111 display_cacheinfo(c);
1112 break;
1113 }
1114
1115 detect_ht(c);
1116
1117 /*
1118 * On SMP, boot_cpu_data holds the common feature set between
1119 * all CPUs; so make sure that we indicate which features are
1120 * common between the CPUs. The first time this routine gets
1121 * executed, c == &boot_cpu_data.
1122 */
1123 if (c != &boot_cpu_data) {
1124 /* AND the already accumulated flags with these */
1125 for (i = 0; i < NCAPINTS; i++)
1126 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1127 }
1128
1129 /* Clear all flags overriden by options */
1130 for (i = 0; i < NCAPINTS; i++)
1131 c->x86_capability[i] &= ~cleared_cpu_caps[i];
1132
1133 #ifdef CONFIG_X86_MCE
1134 mcheck_init(c);
1135 #endif
1136 select_idle_routine(c);
1137
1138 #ifdef CONFIG_NUMA
1139 numa_add_cpu(smp_processor_id());
1140 #endif
1141
1142 }
1143
1144 void __cpuinit identify_boot_cpu(void)
1145 {
1146 identify_cpu(&boot_cpu_data);
1147 }
1148
1149 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1150 {
1151 BUG_ON(c == &boot_cpu_data);
1152 identify_cpu(c);
1153 mtrr_ap_init();
1154 }
1155
1156 static __init int setup_noclflush(char *arg)
1157 {
1158 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1159 return 1;
1160 }
1161 __setup("noclflush", setup_noclflush);
1162
1163 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1164 {
1165 if (c->x86_model_id[0])
1166 printk(KERN_CONT "%s", c->x86_model_id);
1167
1168 if (c->x86_mask || c->cpuid_level >= 0)
1169 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1170 else
1171 printk(KERN_CONT "\n");
1172 }
1173
1174 static __init int setup_disablecpuid(char *arg)
1175 {
1176 int bit;
1177 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1178 setup_clear_cpu_cap(bit);
1179 else
1180 return 0;
1181 return 1;
1182 }
1183 __setup("clearcpuid=", setup_disablecpuid);
Linux kernel - Deliverables
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