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x86, boot: export linked list of struct setup_data via debugfs
[deliverable/linux.git] / arch / x86 / kernel / setup_64.c
1 /*
2 * Copyright (C) 1995 Linus Torvalds
3 */
4
5 /*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
12 #include <linux/mm.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/screen_info.h>
19 #include <linux/ioport.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/initrd.h>
23 #include <linux/highmem.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
26 #include <asm/processor.h>
27 #include <linux/console.h>
28 #include <linux/seq_file.h>
29 #include <linux/crash_dump.h>
30 #include <linux/root_dev.h>
31 #include <linux/pci.h>
32 #include <linux/efi.h>
33 #include <linux/acpi.h>
34 #include <linux/kallsyms.h>
35 #include <linux/edd.h>
36 #include <linux/iscsi_ibft.h>
37 #include <linux/mmzone.h>
38 #include <linux/kexec.h>
39 #include <linux/cpufreq.h>
40 #include <linux/dmi.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/ctype.h>
43 #include <linux/uaccess.h>
44 #include <linux/init_ohci1394_dma.h>
45
46 #include <asm/mtrr.h>
47 #include <asm/uaccess.h>
48 #include <asm/system.h>
49 #include <asm/vsyscall.h>
50 #include <asm/io.h>
51 #include <asm/smp.h>
52 #include <asm/msr.h>
53 #include <asm/desc.h>
54 #include <video/edid.h>
55 #include <asm/e820.h>
56 #include <asm/dma.h>
57 #include <asm/gart.h>
58 #include <asm/mpspec.h>
59 #include <asm/mmu_context.h>
60 #include <asm/proto.h>
61 #include <asm/setup.h>
62 #include <asm/numa.h>
63 #include <asm/sections.h>
64 #include <asm/dmi.h>
65 #include <asm/cacheflush.h>
66 #include <asm/mce.h>
67 #include <asm/ds.h>
68 #include <asm/topology.h>
69 #include <asm/trampoline.h>
70
71 #include <mach_apic.h>
72 #ifdef CONFIG_PARAVIRT
73 #include <asm/paravirt.h>
74 #else
75 #define ARCH_SETUP
76 #endif
77
78 /*
79 * Machine setup..
80 */
81
82 struct cpuinfo_x86 boot_cpu_data __read_mostly;
83 EXPORT_SYMBOL(boot_cpu_data);
84
85 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
86
87 unsigned long mmu_cr4_features;
88
89 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
90 int bootloader_type;
91
92 unsigned long saved_video_mode;
93
94 int force_mwait __cpuinitdata;
95
96 /*
97 * Early DMI memory
98 */
99 int dmi_alloc_index;
100 char dmi_alloc_data[DMI_MAX_DATA];
101
102 /*
103 * Setup options
104 */
105 struct screen_info screen_info;
106 EXPORT_SYMBOL(screen_info);
107 struct sys_desc_table_struct {
108 unsigned short length;
109 unsigned char table[0];
110 };
111
112 struct edid_info edid_info;
113 EXPORT_SYMBOL_GPL(edid_info);
114
115 extern int root_mountflags;
116
117 char __initdata command_line[COMMAND_LINE_SIZE];
118
119 static struct resource standard_io_resources[] = {
120 { .name = "dma1", .start = 0x00, .end = 0x1f,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "pic1", .start = 0x20, .end = 0x21,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
124 { .name = "timer0", .start = 0x40, .end = 0x43,
125 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
126 { .name = "timer1", .start = 0x50, .end = 0x53,
127 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
128 { .name = "keyboard", .start = 0x60, .end = 0x6f,
129 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
130 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
131 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
132 { .name = "pic2", .start = 0xa0, .end = 0xa1,
133 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
134 { .name = "dma2", .start = 0xc0, .end = 0xdf,
135 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
136 { .name = "fpu", .start = 0xf0, .end = 0xff,
137 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
138 };
139
140 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
141
142 static struct resource data_resource = {
143 .name = "Kernel data",
144 .start = 0,
145 .end = 0,
146 .flags = IORESOURCE_RAM,
147 };
148 static struct resource code_resource = {
149 .name = "Kernel code",
150 .start = 0,
151 .end = 0,
152 .flags = IORESOURCE_RAM,
153 };
154 static struct resource bss_resource = {
155 .name = "Kernel bss",
156 .start = 0,
157 .end = 0,
158 .flags = IORESOURCE_RAM,
159 };
160
161 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
162
163 #ifdef CONFIG_PROC_VMCORE
164 /* elfcorehdr= specifies the location of elf core header
165 * stored by the crashed kernel. This option will be passed
166 * by kexec loader to the capture kernel.
167 */
168 static int __init setup_elfcorehdr(char *arg)
169 {
170 char *end;
171 if (!arg)
172 return -EINVAL;
173 elfcorehdr_addr = memparse(arg, &end);
174 return end > arg ? 0 : -EINVAL;
175 }
176 early_param("elfcorehdr", setup_elfcorehdr);
177 #endif
178
179 #ifndef CONFIG_NUMA
180 static void __init
181 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
182 {
183 unsigned long bootmap_size, bootmap;
184
185 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
186 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
187 PAGE_SIZE);
188 if (bootmap == -1L)
189 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
190 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
191 e820_register_active_regions(0, start_pfn, end_pfn);
192 free_bootmem_with_active_regions(0, end_pfn);
193 reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
194 }
195 #endif
196
197 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
198 struct edd edd;
199 #ifdef CONFIG_EDD_MODULE
200 EXPORT_SYMBOL(edd);
201 #endif
202 /**
203 * copy_edd() - Copy the BIOS EDD information
204 * from boot_params into a safe place.
205 *
206 */
207 static inline void copy_edd(void)
208 {
209 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
210 sizeof(edd.mbr_signature));
211 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
212 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
213 edd.edd_info_nr = boot_params.eddbuf_entries;
214 }
215 #else
216 static inline void copy_edd(void)
217 {
218 }
219 #endif
220
221 #ifdef CONFIG_KEXEC
222 static void __init reserve_crashkernel(void)
223 {
224 unsigned long long total_mem;
225 unsigned long long crash_size, crash_base;
226 int ret;
227
228 total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
229
230 ret = parse_crashkernel(boot_command_line, total_mem,
231 &crash_size, &crash_base);
232 if (ret == 0 && crash_size) {
233 if (crash_base <= 0) {
234 printk(KERN_INFO "crashkernel reservation failed - "
235 "you have to specify a base address\n");
236 return;
237 }
238
239 if (reserve_bootmem(crash_base, crash_size,
240 BOOTMEM_EXCLUSIVE) < 0) {
241 printk(KERN_INFO "crashkernel reservation failed - "
242 "memory is in use\n");
243 return;
244 }
245
246 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
247 "for crashkernel (System RAM: %ldMB)\n",
248 (unsigned long)(crash_size >> 20),
249 (unsigned long)(crash_base >> 20),
250 (unsigned long)(total_mem >> 20));
251 crashk_res.start = crash_base;
252 crashk_res.end = crash_base + crash_size - 1;
253 insert_resource(&iomem_resource, &crashk_res);
254 }
255 }
256 #else
257 static inline void __init reserve_crashkernel(void)
258 {}
259 #endif
260
261 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
262 void __attribute__((weak)) __init memory_setup(void)
263 {
264 machine_specific_memory_setup();
265 }
266
267 static void __init parse_setup_data(void)
268 {
269 struct setup_data *data;
270 unsigned long pa_data;
271
272 if (boot_params.hdr.version < 0x0209)
273 return;
274 pa_data = boot_params.hdr.setup_data;
275 while (pa_data) {
276 data = early_ioremap(pa_data, PAGE_SIZE);
277 switch (data->type) {
278 default:
279 break;
280 }
281 #ifndef CONFIG_DEBUG_BOOT_PARAMS
282 free_early(pa_data, pa_data+sizeof(*data)+data->len);
283 #endif
284 pa_data = data->next;
285 early_iounmap(data, PAGE_SIZE);
286 }
287 }
288
289 /*
290 * setup_arch - architecture-specific boot-time initializations
291 *
292 * Note: On x86_64, fixmaps are ready for use even before this is called.
293 */
294 void __init setup_arch(char **cmdline_p)
295 {
296 unsigned i;
297
298 printk(KERN_INFO "Command line: %s\n", boot_command_line);
299
300 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
301 screen_info = boot_params.screen_info;
302 edid_info = boot_params.edid_info;
303 saved_video_mode = boot_params.hdr.vid_mode;
304 bootloader_type = boot_params.hdr.type_of_loader;
305
306 #ifdef CONFIG_BLK_DEV_RAM
307 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
308 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
309 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
310 #endif
311 #ifdef CONFIG_EFI
312 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
313 "EL64", 4))
314 efi_enabled = 1;
315 #endif
316
317 ARCH_SETUP
318
319 memory_setup();
320 copy_edd();
321
322 if (!boot_params.hdr.root_flags)
323 root_mountflags &= ~MS_RDONLY;
324 init_mm.start_code = (unsigned long) &_text;
325 init_mm.end_code = (unsigned long) &_etext;
326 init_mm.end_data = (unsigned long) &_edata;
327 init_mm.brk = (unsigned long) &_end;
328
329 code_resource.start = virt_to_phys(&_text);
330 code_resource.end = virt_to_phys(&_etext)-1;
331 data_resource.start = virt_to_phys(&_etext);
332 data_resource.end = virt_to_phys(&_edata)-1;
333 bss_resource.start = virt_to_phys(&__bss_start);
334 bss_resource.end = virt_to_phys(&__bss_stop)-1;
335
336 early_identify_cpu(&boot_cpu_data);
337
338 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
339 *cmdline_p = command_line;
340
341 parse_setup_data();
342
343 parse_early_param();
344
345 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
346 if (init_ohci1394_dma_early)
347 init_ohci1394_dma_on_all_controllers();
348 #endif
349
350 finish_e820_parsing();
351
352 /* after parse_early_param, so could debug it */
353 insert_resource(&iomem_resource, &code_resource);
354 insert_resource(&iomem_resource, &data_resource);
355 insert_resource(&iomem_resource, &bss_resource);
356
357 early_gart_iommu_check();
358
359 e820_register_active_regions(0, 0, -1UL);
360 /*
361 * partially used pages are not usable - thus
362 * we are rounding upwards:
363 */
364 end_pfn = e820_end_of_ram();
365 /* update e820 for memory not covered by WB MTRRs */
366 mtrr_bp_init();
367 if (mtrr_trim_uncached_memory(end_pfn)) {
368 e820_register_active_regions(0, 0, -1UL);
369 end_pfn = e820_end_of_ram();
370 }
371
372 num_physpages = end_pfn;
373
374 check_efer();
375
376 max_pfn_mapped = init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
377 if (efi_enabled)
378 efi_init();
379
380 vsmp_init();
381
382 dmi_scan_machine();
383
384 io_delay_init();
385
386 #ifdef CONFIG_SMP
387 /* setup to use the early static init tables during kernel startup */
388 x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
389 x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
390 #ifdef CONFIG_NUMA
391 x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
392 #endif
393 #endif
394
395 #ifdef CONFIG_ACPI
396 /*
397 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
398 * Call this early for SRAT node setup.
399 */
400 acpi_boot_table_init();
401 #endif
402
403 /* How many end-of-memory variables you have, grandma! */
404 max_low_pfn = end_pfn;
405 max_pfn = end_pfn;
406 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
407
408 /* Remove active ranges so rediscovery with NUMA-awareness happens */
409 remove_all_active_ranges();
410
411 #ifdef CONFIG_ACPI_NUMA
412 /*
413 * Parse SRAT to discover nodes.
414 */
415 acpi_numa_init();
416 #endif
417
418 #ifdef CONFIG_NUMA
419 numa_initmem_init(0, end_pfn);
420 #else
421 contig_initmem_init(0, end_pfn);
422 #endif
423
424 early_res_to_bootmem();
425
426 dma32_reserve_bootmem();
427
428 #ifdef CONFIG_ACPI_SLEEP
429 /*
430 * Reserve low memory region for sleep support.
431 */
432 acpi_reserve_bootmem();
433 #endif
434
435 if (efi_enabled)
436 efi_reserve_bootmem();
437
438 /*
439 * Find and reserve possible boot-time SMP configuration:
440 */
441 find_smp_config();
442 #ifdef CONFIG_BLK_DEV_INITRD
443 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
444 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
445 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
446 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
447 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
448
449 if (ramdisk_end <= end_of_mem) {
450 /*
451 * don't need to reserve again, already reserved early
452 * in x86_64_start_kernel, and early_res_to_bootmem
453 * convert that to reserved in bootmem
454 */
455 initrd_start = ramdisk_image + PAGE_OFFSET;
456 initrd_end = initrd_start+ramdisk_size;
457 } else {
458 free_bootmem(ramdisk_image, ramdisk_size);
459 printk(KERN_ERR "initrd extends beyond end of memory "
460 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
461 ramdisk_end, end_of_mem);
462 initrd_start = 0;
463 }
464 }
465 #endif
466 reserve_crashkernel();
467
468 reserve_ibft_region();
469
470 paging_init();
471 map_vsyscall();
472
473 early_quirks();
474
475 #ifdef CONFIG_ACPI
476 /*
477 * Read APIC and some other early information from ACPI tables.
478 */
479 acpi_boot_init();
480 #endif
481
482 init_cpu_to_node();
483
484 /*
485 * get boot-time SMP configuration:
486 */
487 if (smp_found_config)
488 get_smp_config();
489 init_apic_mappings();
490 ioapic_init_mappings();
491
492 /*
493 * We trust e820 completely. No explicit ROM probing in memory.
494 */
495 e820_reserve_resources();
496 e820_mark_nosave_regions();
497
498 /* request I/O space for devices used on all i[345]86 PCs */
499 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
500 request_resource(&ioport_resource, &standard_io_resources[i]);
501
502 e820_setup_gap();
503
504 #ifdef CONFIG_VT
505 #if defined(CONFIG_VGA_CONSOLE)
506 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
507 conswitchp = &vga_con;
508 #elif defined(CONFIG_DUMMY_CONSOLE)
509 conswitchp = &dummy_con;
510 #endif
511 #endif
512 }
513
514 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
515 {
516 unsigned int *v;
517
518 if (c->extended_cpuid_level < 0x80000004)
519 return 0;
520
521 v = (unsigned int *) c->x86_model_id;
522 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
523 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
524 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
525 c->x86_model_id[48] = 0;
526 return 1;
527 }
528
529
530 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
531 {
532 unsigned int n, dummy, eax, ebx, ecx, edx;
533
534 n = c->extended_cpuid_level;
535
536 if (n >= 0x80000005) {
537 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
538 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
539 "D cache %dK (%d bytes/line)\n",
540 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
541 c->x86_cache_size = (ecx>>24) + (edx>>24);
542 /* On K8 L1 TLB is inclusive, so don't count it */
543 c->x86_tlbsize = 0;
544 }
545
546 if (n >= 0x80000006) {
547 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
548 ecx = cpuid_ecx(0x80000006);
549 c->x86_cache_size = ecx >> 16;
550 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
551
552 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
553 c->x86_cache_size, ecx & 0xFF);
554 }
555 if (n >= 0x80000008) {
556 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
557 c->x86_virt_bits = (eax >> 8) & 0xff;
558 c->x86_phys_bits = eax & 0xff;
559 }
560 }
561
562 #ifdef CONFIG_NUMA
563 static int __cpuinit nearby_node(int apicid)
564 {
565 int i, node;
566
567 for (i = apicid - 1; i >= 0; i--) {
568 node = apicid_to_node[i];
569 if (node != NUMA_NO_NODE && node_online(node))
570 return node;
571 }
572 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
573 node = apicid_to_node[i];
574 if (node != NUMA_NO_NODE && node_online(node))
575 return node;
576 }
577 return first_node(node_online_map); /* Shouldn't happen */
578 }
579 #endif
580
581 /*
582 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
583 * Assumes number of cores is a power of two.
584 */
585 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
586 {
587 #ifdef CONFIG_SMP
588 unsigned bits;
589 #ifdef CONFIG_NUMA
590 int cpu = smp_processor_id();
591 int node = 0;
592 unsigned apicid = hard_smp_processor_id();
593 #endif
594 bits = c->x86_coreid_bits;
595
596 /* Low order bits define the core id (index of core in socket) */
597 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
598 /* Convert the initial APIC ID into the socket ID */
599 c->phys_proc_id = c->initial_apicid >> bits;
600
601 #ifdef CONFIG_NUMA
602 node = c->phys_proc_id;
603 if (apicid_to_node[apicid] != NUMA_NO_NODE)
604 node = apicid_to_node[apicid];
605 if (!node_online(node)) {
606 /* Two possibilities here:
607 - The CPU is missing memory and no node was created.
608 In that case try picking one from a nearby CPU
609 - The APIC IDs differ from the HyperTransport node IDs
610 which the K8 northbridge parsing fills in.
611 Assume they are all increased by a constant offset,
612 but in the same order as the HT nodeids.
613 If that doesn't result in a usable node fall back to the
614 path for the previous case. */
615
616 int ht_nodeid = c->initial_apicid;
617
618 if (ht_nodeid >= 0 &&
619 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
620 node = apicid_to_node[ht_nodeid];
621 /* Pick a nearby node */
622 if (!node_online(node))
623 node = nearby_node(apicid);
624 }
625 numa_set_node(cpu, node);
626
627 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
628 #endif
629 #endif
630 }
631
632 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
633 {
634 #ifdef CONFIG_SMP
635 unsigned bits, ecx;
636
637 /* Multi core CPU? */
638 if (c->extended_cpuid_level < 0x80000008)
639 return;
640
641 ecx = cpuid_ecx(0x80000008);
642
643 c->x86_max_cores = (ecx & 0xff) + 1;
644
645 /* CPU telling us the core id bits shift? */
646 bits = (ecx >> 12) & 0xF;
647
648 /* Otherwise recompute */
649 if (bits == 0) {
650 while ((1 << bits) < c->x86_max_cores)
651 bits++;
652 }
653
654 c->x86_coreid_bits = bits;
655
656 #endif
657 }
658
659 #define ENABLE_C1E_MASK 0x18000000
660 #define CPUID_PROCESSOR_SIGNATURE 1
661 #define CPUID_XFAM 0x0ff00000
662 #define CPUID_XFAM_K8 0x00000000
663 #define CPUID_XFAM_10H 0x00100000
664 #define CPUID_XFAM_11H 0x00200000
665 #define CPUID_XMOD 0x000f0000
666 #define CPUID_XMOD_REV_F 0x00040000
667
668 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
669 static __cpuinit int amd_apic_timer_broken(void)
670 {
671 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
672
673 switch (eax & CPUID_XFAM) {
674 case CPUID_XFAM_K8:
675 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
676 break;
677 case CPUID_XFAM_10H:
678 case CPUID_XFAM_11H:
679 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
680 if (lo & ENABLE_C1E_MASK)
681 return 1;
682 break;
683 default:
684 /* err on the side of caution */
685 return 1;
686 }
687 return 0;
688 }
689
690 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
691 {
692 early_init_amd_mc(c);
693
694 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
695 if (c->x86_power & (1<<8))
696 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
697 }
698
699 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
700 {
701 unsigned level;
702
703 #ifdef CONFIG_SMP
704 unsigned long value;
705
706 /*
707 * Disable TLB flush filter by setting HWCR.FFDIS on K8
708 * bit 6 of msr C001_0015
709 *
710 * Errata 63 for SH-B3 steppings
711 * Errata 122 for all steppings (F+ have it disabled by default)
712 */
713 if (c->x86 == 15) {
714 rdmsrl(MSR_K8_HWCR, value);
715 value |= 1 << 6;
716 wrmsrl(MSR_K8_HWCR, value);
717 }
718 #endif
719
720 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
721 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
722 clear_cpu_cap(c, 0*32+31);
723
724 /* On C+ stepping K8 rep microcode works well for copy/memset */
725 level = cpuid_eax(1);
726 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
727 level >= 0x0f58))
728 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
729 if (c->x86 == 0x10 || c->x86 == 0x11)
730 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
731
732 /* Enable workaround for FXSAVE leak */
733 if (c->x86 >= 6)
734 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
735
736 level = get_model_name(c);
737 if (!level) {
738 switch (c->x86) {
739 case 15:
740 /* Should distinguish Models here, but this is only
741 a fallback anyways. */
742 strcpy(c->x86_model_id, "Hammer");
743 break;
744 }
745 }
746 display_cacheinfo(c);
747
748 /* Multi core CPU? */
749 if (c->extended_cpuid_level >= 0x80000008)
750 amd_detect_cmp(c);
751
752 if (c->extended_cpuid_level >= 0x80000006 &&
753 (cpuid_edx(0x80000006) & 0xf000))
754 num_cache_leaves = 4;
755 else
756 num_cache_leaves = 3;
757
758 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
759 set_cpu_cap(c, X86_FEATURE_K8);
760
761 /* MFENCE stops RDTSC speculation */
762 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
763
764 if (amd_apic_timer_broken())
765 disable_apic_timer = 1;
766
767 if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
768 unsigned long long tseg;
769
770 /*
771 * Split up direct mapping around the TSEG SMM area.
772 * Don't do it for gbpages because there seems very little
773 * benefit in doing so.
774 */
775 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
776 (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
777 set_memory_4k((unsigned long)__va(tseg), 1);
778 }
779 }
780
781 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
782 {
783 #ifdef CONFIG_SMP
784 u32 eax, ebx, ecx, edx;
785 int index_msb, core_bits;
786
787 cpuid(1, &eax, &ebx, &ecx, &edx);
788
789
790 if (!cpu_has(c, X86_FEATURE_HT))
791 return;
792 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
793 goto out;
794
795 smp_num_siblings = (ebx & 0xff0000) >> 16;
796
797 if (smp_num_siblings == 1) {
798 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
799 } else if (smp_num_siblings > 1) {
800
801 if (smp_num_siblings > NR_CPUS) {
802 printk(KERN_WARNING "CPU: Unsupported number of "
803 "siblings %d", smp_num_siblings);
804 smp_num_siblings = 1;
805 return;
806 }
807
808 index_msb = get_count_order(smp_num_siblings);
809 c->phys_proc_id = phys_pkg_id(index_msb);
810
811 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
812
813 index_msb = get_count_order(smp_num_siblings);
814
815 core_bits = get_count_order(c->x86_max_cores);
816
817 c->cpu_core_id = phys_pkg_id(index_msb) &
818 ((1 << core_bits) - 1);
819 }
820 out:
821 if ((c->x86_max_cores * smp_num_siblings) > 1) {
822 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
823 c->phys_proc_id);
824 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
825 c->cpu_core_id);
826 }
827
828 #endif
829 }
830
831 /*
832 * find out the number of processor cores on the die
833 */
834 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
835 {
836 unsigned int eax, t;
837
838 if (c->cpuid_level < 4)
839 return 1;
840
841 cpuid_count(4, 0, &eax, &t, &t, &t);
842
843 if (eax & 0x1f)
844 return ((eax >> 26) + 1);
845 else
846 return 1;
847 }
848
849 static void __cpuinit srat_detect_node(void)
850 {
851 #ifdef CONFIG_NUMA
852 unsigned node;
853 int cpu = smp_processor_id();
854 int apicid = hard_smp_processor_id();
855
856 /* Don't do the funky fallback heuristics the AMD version employs
857 for now. */
858 node = apicid_to_node[apicid];
859 if (node == NUMA_NO_NODE || !node_online(node))
860 node = first_node(node_online_map);
861 numa_set_node(cpu, node);
862
863 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
864 #endif
865 }
866
867 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
868 {
869 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
870 (c->x86 == 0x6 && c->x86_model >= 0x0e))
871 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
872 }
873
874 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
875 {
876 /* Cache sizes */
877 unsigned n;
878
879 init_intel_cacheinfo(c);
880 if (c->cpuid_level > 9) {
881 unsigned eax = cpuid_eax(10);
882 /* Check for version and the number of counters */
883 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
884 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
885 }
886
887 if (cpu_has_ds) {
888 unsigned int l1, l2;
889 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
890 if (!(l1 & (1<<11)))
891 set_cpu_cap(c, X86_FEATURE_BTS);
892 if (!(l1 & (1<<12)))
893 set_cpu_cap(c, X86_FEATURE_PEBS);
894 }
895
896
897 if (cpu_has_bts)
898 ds_init_intel(c);
899
900 n = c->extended_cpuid_level;
901 if (n >= 0x80000008) {
902 unsigned eax = cpuid_eax(0x80000008);
903 c->x86_virt_bits = (eax >> 8) & 0xff;
904 c->x86_phys_bits = eax & 0xff;
905 /* CPUID workaround for Intel 0F34 CPU */
906 if (c->x86_vendor == X86_VENDOR_INTEL &&
907 c->x86 == 0xF && c->x86_model == 0x3 &&
908 c->x86_mask == 0x4)
909 c->x86_phys_bits = 36;
910 }
911
912 if (c->x86 == 15)
913 c->x86_cache_alignment = c->x86_clflush_size * 2;
914 if (c->x86 == 6)
915 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
916 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
917 c->x86_max_cores = intel_num_cpu_cores(c);
918
919 srat_detect_node();
920 }
921
922 static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
923 {
924 if (c->x86 == 0x6 && c->x86_model >= 0xf)
925 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
926 }
927
928 static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
929 {
930 /* Cache sizes */
931 unsigned n;
932
933 n = c->extended_cpuid_level;
934 if (n >= 0x80000008) {
935 unsigned eax = cpuid_eax(0x80000008);
936 c->x86_virt_bits = (eax >> 8) & 0xff;
937 c->x86_phys_bits = eax & 0xff;
938 }
939
940 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
941 c->x86_cache_alignment = c->x86_clflush_size * 2;
942 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
943 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
944 }
945 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
946 }
947
948 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
949 {
950 char *v = c->x86_vendor_id;
951
952 if (!strcmp(v, "AuthenticAMD"))
953 c->x86_vendor = X86_VENDOR_AMD;
954 else if (!strcmp(v, "GenuineIntel"))
955 c->x86_vendor = X86_VENDOR_INTEL;
956 else if (!strcmp(v, "CentaurHauls"))
957 c->x86_vendor = X86_VENDOR_CENTAUR;
958 else
959 c->x86_vendor = X86_VENDOR_UNKNOWN;
960 }
961
962 /* Do some early cpuid on the boot CPU to get some parameter that are
963 needed before check_bugs. Everything advanced is in identify_cpu
964 below. */
965 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
966 {
967 u32 tfms, xlvl;
968
969 c->loops_per_jiffy = loops_per_jiffy;
970 c->x86_cache_size = -1;
971 c->x86_vendor = X86_VENDOR_UNKNOWN;
972 c->x86_model = c->x86_mask = 0; /* So far unknown... */
973 c->x86_vendor_id[0] = '\0'; /* Unset */
974 c->x86_model_id[0] = '\0'; /* Unset */
975 c->x86_clflush_size = 64;
976 c->x86_cache_alignment = c->x86_clflush_size;
977 c->x86_max_cores = 1;
978 c->x86_coreid_bits = 0;
979 c->extended_cpuid_level = 0;
980 memset(&c->x86_capability, 0, sizeof c->x86_capability);
981
982 /* Get vendor name */
983 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
984 (unsigned int *)&c->x86_vendor_id[0],
985 (unsigned int *)&c->x86_vendor_id[8],
986 (unsigned int *)&c->x86_vendor_id[4]);
987
988 get_cpu_vendor(c);
989
990 /* Initialize the standard set of capabilities */
991 /* Note that the vendor-specific code below might override */
992
993 /* Intel-defined flags: level 0x00000001 */
994 if (c->cpuid_level >= 0x00000001) {
995 __u32 misc;
996 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
997 &c->x86_capability[0]);
998 c->x86 = (tfms >> 8) & 0xf;
999 c->x86_model = (tfms >> 4) & 0xf;
1000 c->x86_mask = tfms & 0xf;
1001 if (c->x86 == 0xf)
1002 c->x86 += (tfms >> 20) & 0xff;
1003 if (c->x86 >= 0x6)
1004 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1005 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
1006 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1007 } else {
1008 /* Have CPUID level 0 only - unheard of */
1009 c->x86 = 4;
1010 }
1011
1012 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
1013 #ifdef CONFIG_SMP
1014 c->phys_proc_id = c->initial_apicid;
1015 #endif
1016 /* AMD-defined flags: level 0x80000001 */
1017 xlvl = cpuid_eax(0x80000000);
1018 c->extended_cpuid_level = xlvl;
1019 if ((xlvl & 0xffff0000) == 0x80000000) {
1020 if (xlvl >= 0x80000001) {
1021 c->x86_capability[1] = cpuid_edx(0x80000001);
1022 c->x86_capability[6] = cpuid_ecx(0x80000001);
1023 }
1024 if (xlvl >= 0x80000004)
1025 get_model_name(c); /* Default name */
1026 }
1027
1028 /* Transmeta-defined flags: level 0x80860001 */
1029 xlvl = cpuid_eax(0x80860000);
1030 if ((xlvl & 0xffff0000) == 0x80860000) {
1031 /* Don't set x86_cpuid_level here for now to not confuse. */
1032 if (xlvl >= 0x80860001)
1033 c->x86_capability[2] = cpuid_edx(0x80860001);
1034 }
1035
1036 c->extended_cpuid_level = cpuid_eax(0x80000000);
1037 if (c->extended_cpuid_level >= 0x80000007)
1038 c->x86_power = cpuid_edx(0x80000007);
1039
1040
1041 clear_cpu_cap(c, X86_FEATURE_PAT);
1042
1043 switch (c->x86_vendor) {
1044 case X86_VENDOR_AMD:
1045 early_init_amd(c);
1046 if (c->x86 >= 0xf && c->x86 <= 0x11)
1047 set_cpu_cap(c, X86_FEATURE_PAT);
1048 break;
1049 case X86_VENDOR_INTEL:
1050 early_init_intel(c);
1051 if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
1052 set_cpu_cap(c, X86_FEATURE_PAT);
1053 break;
1054 case X86_VENDOR_CENTAUR:
1055 early_init_centaur(c);
1056 break;
1057 }
1058
1059 }
1060
1061 /*
1062 * This does the hard work of actually picking apart the CPU stuff...
1063 */
1064 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1065 {
1066 int i;
1067
1068 early_identify_cpu(c);
1069
1070 init_scattered_cpuid_features(c);
1071
1072 c->apicid = phys_pkg_id(0);
1073
1074 /*
1075 * Vendor-specific initialization. In this section we
1076 * canonicalize the feature flags, meaning if there are
1077 * features a certain CPU supports which CPUID doesn't
1078 * tell us, CPUID claiming incorrect flags, or other bugs,
1079 * we handle them here.
1080 *
1081 * At the end of this section, c->x86_capability better
1082 * indicate the features this CPU genuinely supports!
1083 */
1084 switch (c->x86_vendor) {
1085 case X86_VENDOR_AMD:
1086 init_amd(c);
1087 break;
1088
1089 case X86_VENDOR_INTEL:
1090 init_intel(c);
1091 break;
1092
1093 case X86_VENDOR_CENTAUR:
1094 init_centaur(c);
1095 break;
1096
1097 case X86_VENDOR_UNKNOWN:
1098 default:
1099 display_cacheinfo(c);
1100 break;
1101 }
1102
1103 detect_ht(c);
1104
1105 /*
1106 * On SMP, boot_cpu_data holds the common feature set between
1107 * all CPUs; so make sure that we indicate which features are
1108 * common between the CPUs. The first time this routine gets
1109 * executed, c == &boot_cpu_data.
1110 */
1111 if (c != &boot_cpu_data) {
1112 /* AND the already accumulated flags with these */
1113 for (i = 0; i < NCAPINTS; i++)
1114 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1115 }
1116
1117 /* Clear all flags overriden by options */
1118 for (i = 0; i < NCAPINTS; i++)
1119 c->x86_capability[i] &= ~cleared_cpu_caps[i];
1120
1121 #ifdef CONFIG_X86_MCE
1122 mcheck_init(c);
1123 #endif
1124 select_idle_routine(c);
1125
1126 #ifdef CONFIG_NUMA
1127 numa_add_cpu(smp_processor_id());
1128 #endif
1129
1130 }
1131
1132 void __cpuinit identify_boot_cpu(void)
1133 {
1134 identify_cpu(&boot_cpu_data);
1135 }
1136
1137 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1138 {
1139 BUG_ON(c == &boot_cpu_data);
1140 identify_cpu(c);
1141 mtrr_ap_init();
1142 }
1143
1144 static __init int setup_noclflush(char *arg)
1145 {
1146 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1147 return 1;
1148 }
1149 __setup("noclflush", setup_noclflush);
1150
1151 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1152 {
1153 if (c->x86_model_id[0])
1154 printk(KERN_CONT "%s", c->x86_model_id);
1155
1156 if (c->x86_mask || c->cpuid_level >= 0)
1157 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1158 else
1159 printk(KERN_CONT "\n");
1160 }
1161
1162 static __init int setup_disablecpuid(char *arg)
1163 {
1164 int bit;
1165 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1166 setup_clear_cpu_cap(bit);
1167 else
1168 return 0;
1169 return 1;
1170 }
1171 __setup("clearcpuid=", setup_disablecpuid);
Linux kernel - Deliverables
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