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x86: remove struct cpu_model_info
[deliverable/linux.git] / arch / x86 / kernel / setup_64.c
1 /*
2 * Copyright (C) 1995 Linus Torvalds
3 */
4
5 /*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
12 #include <linux/mm.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/a.out.h>
19 #include <linux/screen_info.h>
20 #include <linux/ioport.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/initrd.h>
24 #include <linux/highmem.h>
25 #include <linux/bootmem.h>
26 #include <linux/module.h>
27 #include <asm/processor.h>
28 #include <linux/console.h>
29 #include <linux/seq_file.h>
30 #include <linux/crash_dump.h>
31 #include <linux/root_dev.h>
32 #include <linux/pci.h>
33 #include <linux/efi.h>
34 #include <linux/acpi.h>
35 #include <linux/kallsyms.h>
36 #include <linux/edd.h>
37 #include <linux/mmzone.h>
38 #include <linux/kexec.h>
39 #include <linux/cpufreq.h>
40 #include <linux/dmi.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/ctype.h>
43 #include <linux/uaccess.h>
44
45 #include <asm/mtrr.h>
46 #include <asm/uaccess.h>
47 #include <asm/system.h>
48 #include <asm/vsyscall.h>
49 #include <asm/io.h>
50 #include <asm/smp.h>
51 #include <asm/msr.h>
52 #include <asm/desc.h>
53 #include <video/edid.h>
54 #include <asm/e820.h>
55 #include <asm/dma.h>
56 #include <asm/gart.h>
57 #include <asm/mpspec.h>
58 #include <asm/mmu_context.h>
59 #include <asm/proto.h>
60 #include <asm/setup.h>
61 #include <asm/mach_apic.h>
62 #include <asm/numa.h>
63 #include <asm/sections.h>
64 #include <asm/dmi.h>
65 #include <asm/cacheflush.h>
66 #include <asm/mce.h>
67 #include <asm/ds.h>
68 #include <asm/topology.h>
69
70 #ifdef CONFIG_PARAVIRT
71 #include <asm/paravirt.h>
72 #else
73 #define ARCH_SETUP
74 #endif
75
76 /*
77 * Machine setup..
78 */
79
80 struct cpuinfo_x86 boot_cpu_data __read_mostly;
81 EXPORT_SYMBOL(boot_cpu_data);
82
83 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
84
85 unsigned long mmu_cr4_features;
86
87 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
88 int bootloader_type;
89
90 unsigned long saved_video_mode;
91
92 int force_mwait __cpuinitdata;
93
94 /*
95 * Early DMI memory
96 */
97 int dmi_alloc_index;
98 char dmi_alloc_data[DMI_MAX_DATA];
99
100 /*
101 * Setup options
102 */
103 struct screen_info screen_info;
104 EXPORT_SYMBOL(screen_info);
105 struct sys_desc_table_struct {
106 unsigned short length;
107 unsigned char table[0];
108 };
109
110 struct edid_info edid_info;
111 EXPORT_SYMBOL_GPL(edid_info);
112
113 extern int root_mountflags;
114
115 char __initdata command_line[COMMAND_LINE_SIZE];
116
117 struct resource standard_io_resources[] = {
118 { .name = "dma1", .start = 0x00, .end = 0x1f,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "pic1", .start = 0x20, .end = 0x21,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "timer0", .start = 0x40, .end = 0x43,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
124 { .name = "timer1", .start = 0x50, .end = 0x53,
125 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
126 { .name = "keyboard", .start = 0x60, .end = 0x6f,
127 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
128 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
129 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
130 { .name = "pic2", .start = 0xa0, .end = 0xa1,
131 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
132 { .name = "dma2", .start = 0xc0, .end = 0xdf,
133 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
134 { .name = "fpu", .start = 0xf0, .end = 0xff,
135 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
136 };
137
138 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
139
140 static struct resource data_resource = {
141 .name = "Kernel data",
142 .start = 0,
143 .end = 0,
144 .flags = IORESOURCE_RAM,
145 };
146 static struct resource code_resource = {
147 .name = "Kernel code",
148 .start = 0,
149 .end = 0,
150 .flags = IORESOURCE_RAM,
151 };
152 static struct resource bss_resource = {
153 .name = "Kernel bss",
154 .start = 0,
155 .end = 0,
156 .flags = IORESOURCE_RAM,
157 };
158
159 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
160
161 #ifdef CONFIG_PROC_VMCORE
162 /* elfcorehdr= specifies the location of elf core header
163 * stored by the crashed kernel. This option will be passed
164 * by kexec loader to the capture kernel.
165 */
166 static int __init setup_elfcorehdr(char *arg)
167 {
168 char *end;
169 if (!arg)
170 return -EINVAL;
171 elfcorehdr_addr = memparse(arg, &end);
172 return end > arg ? 0 : -EINVAL;
173 }
174 early_param("elfcorehdr", setup_elfcorehdr);
175 #endif
176
177 #ifndef CONFIG_NUMA
178 static void __init
179 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
180 {
181 unsigned long bootmap_size, bootmap;
182
183 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
184 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
185 if (bootmap == -1L)
186 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
187 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
188 e820_register_active_regions(0, start_pfn, end_pfn);
189 free_bootmem_with_active_regions(0, end_pfn);
190 reserve_bootmem(bootmap, bootmap_size);
191 }
192 #endif
193
194 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
195 struct edd edd;
196 #ifdef CONFIG_EDD_MODULE
197 EXPORT_SYMBOL(edd);
198 #endif
199 /**
200 * copy_edd() - Copy the BIOS EDD information
201 * from boot_params into a safe place.
202 *
203 */
204 static inline void copy_edd(void)
205 {
206 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
207 sizeof(edd.mbr_signature));
208 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
209 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
210 edd.edd_info_nr = boot_params.eddbuf_entries;
211 }
212 #else
213 static inline void copy_edd(void)
214 {
215 }
216 #endif
217
218 #ifdef CONFIG_KEXEC
219 static void __init reserve_crashkernel(void)
220 {
221 unsigned long long free_mem;
222 unsigned long long crash_size, crash_base;
223 int ret;
224
225 free_mem =
226 ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
227
228 ret = parse_crashkernel(boot_command_line, free_mem,
229 &crash_size, &crash_base);
230 if (ret == 0 && crash_size) {
231 if (crash_base > 0) {
232 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
233 "for crashkernel (System RAM: %ldMB)\n",
234 (unsigned long)(crash_size >> 20),
235 (unsigned long)(crash_base >> 20),
236 (unsigned long)(free_mem >> 20));
237 crashk_res.start = crash_base;
238 crashk_res.end = crash_base + crash_size - 1;
239 reserve_bootmem(crash_base, crash_size);
240 } else
241 printk(KERN_INFO "crashkernel reservation failed - "
242 "you have to specify a base address\n");
243 }
244 }
245 #else
246 static inline void __init reserve_crashkernel(void)
247 {}
248 #endif
249
250 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
251 void __attribute__((weak)) __init memory_setup(void)
252 {
253 machine_specific_memory_setup();
254 }
255
256 void __init setup_arch(char **cmdline_p)
257 {
258 unsigned i;
259
260 printk(KERN_INFO "Command line: %s\n", boot_command_line);
261
262 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
263 screen_info = boot_params.screen_info;
264 edid_info = boot_params.edid_info;
265 saved_video_mode = boot_params.hdr.vid_mode;
266 bootloader_type = boot_params.hdr.type_of_loader;
267
268 #ifdef CONFIG_BLK_DEV_RAM
269 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
270 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
271 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
272 #endif
273 #ifdef CONFIG_EFI
274 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
275 "EL64", 4))
276 efi_enabled = 1;
277 #endif
278
279 ARCH_SETUP
280
281 memory_setup();
282 copy_edd();
283
284 if (!boot_params.hdr.root_flags)
285 root_mountflags &= ~MS_RDONLY;
286 init_mm.start_code = (unsigned long) &_text;
287 init_mm.end_code = (unsigned long) &_etext;
288 init_mm.end_data = (unsigned long) &_edata;
289 init_mm.brk = (unsigned long) &_end;
290
291 code_resource.start = virt_to_phys(&_text);
292 code_resource.end = virt_to_phys(&_etext)-1;
293 data_resource.start = virt_to_phys(&_etext);
294 data_resource.end = virt_to_phys(&_edata)-1;
295 bss_resource.start = virt_to_phys(&__bss_start);
296 bss_resource.end = virt_to_phys(&__bss_stop)-1;
297
298 early_identify_cpu(&boot_cpu_data);
299
300 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
301 *cmdline_p = command_line;
302
303 parse_early_param();
304
305 finish_e820_parsing();
306
307 early_gart_iommu_check();
308
309 e820_register_active_regions(0, 0, -1UL);
310 /*
311 * partially used pages are not usable - thus
312 * we are rounding upwards:
313 */
314 end_pfn = e820_end_of_ram();
315 /* update e820 for memory not covered by WB MTRRs */
316 mtrr_bp_init();
317 if (mtrr_trim_uncached_memory(end_pfn)) {
318 e820_register_active_regions(0, 0, -1UL);
319 end_pfn = e820_end_of_ram();
320 }
321
322 num_physpages = end_pfn;
323
324 check_efer();
325
326 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
327 if (efi_enabled)
328 efi_init();
329
330 dmi_scan_machine();
331
332 io_delay_init();
333
334 #ifdef CONFIG_SMP
335 /* setup to use the early static init tables during kernel startup */
336 x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
337 x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
338 #ifdef CONFIG_NUMA
339 x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
340 #endif
341 #endif
342
343 #ifdef CONFIG_ACPI
344 /*
345 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
346 * Call this early for SRAT node setup.
347 */
348 acpi_boot_table_init();
349 #endif
350
351 /* How many end-of-memory variables you have, grandma! */
352 max_low_pfn = end_pfn;
353 max_pfn = end_pfn;
354 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
355
356 /* Remove active ranges so rediscovery with NUMA-awareness happens */
357 remove_all_active_ranges();
358
359 #ifdef CONFIG_ACPI_NUMA
360 /*
361 * Parse SRAT to discover nodes.
362 */
363 acpi_numa_init();
364 #endif
365
366 #ifdef CONFIG_NUMA
367 numa_initmem_init(0, end_pfn);
368 #else
369 contig_initmem_init(0, end_pfn);
370 #endif
371
372 early_res_to_bootmem();
373
374 #ifdef CONFIG_ACPI_SLEEP
375 /*
376 * Reserve low memory region for sleep support.
377 */
378 acpi_reserve_bootmem();
379 #endif
380
381 if (efi_enabled) {
382 efi_map_memmap();
383 efi_reserve_bootmem();
384 }
385
386 /*
387 * Find and reserve possible boot-time SMP configuration:
388 */
389 find_smp_config();
390 #ifdef CONFIG_BLK_DEV_INITRD
391 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
392 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
393 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
394 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
395 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
396
397 if (ramdisk_end <= end_of_mem) {
398 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
399 initrd_start = ramdisk_image + PAGE_OFFSET;
400 initrd_end = initrd_start+ramdisk_size;
401 } else {
402 /* Assumes everything on node 0 */
403 free_bootmem(ramdisk_image, ramdisk_size);
404 printk(KERN_ERR "initrd extends beyond end of memory "
405 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
406 ramdisk_end, end_of_mem);
407 initrd_start = 0;
408 }
409 }
410 #endif
411 reserve_crashkernel();
412 paging_init();
413 map_vsyscall();
414
415 early_quirks();
416
417 /*
418 * set this early, so we dont allocate cpu0
419 * if MADT list doesnt list BSP first
420 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
421 */
422 cpu_set(0, cpu_present_map);
423 #ifdef CONFIG_ACPI
424 /*
425 * Read APIC and some other early information from ACPI tables.
426 */
427 acpi_boot_init();
428 #endif
429
430 init_cpu_to_node();
431
432 /*
433 * get boot-time SMP configuration:
434 */
435 if (smp_found_config)
436 get_smp_config();
437 init_apic_mappings();
438 ioapic_init_mappings();
439
440 /*
441 * We trust e820 completely. No explicit ROM probing in memory.
442 */
443 e820_reserve_resources(&code_resource, &data_resource, &bss_resource);
444 e820_mark_nosave_regions();
445
446 /* request I/O space for devices used on all i[345]86 PCs */
447 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
448 request_resource(&ioport_resource, &standard_io_resources[i]);
449
450 e820_setup_gap();
451
452 #ifdef CONFIG_VT
453 #if defined(CONFIG_VGA_CONSOLE)
454 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
455 conswitchp = &vga_con;
456 #elif defined(CONFIG_DUMMY_CONSOLE)
457 conswitchp = &dummy_con;
458 #endif
459 #endif
460 }
461
462 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
463 {
464 unsigned int *v;
465
466 if (c->extended_cpuid_level < 0x80000004)
467 return 0;
468
469 v = (unsigned int *) c->x86_model_id;
470 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
471 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
472 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
473 c->x86_model_id[48] = 0;
474 return 1;
475 }
476
477
478 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
479 {
480 unsigned int n, dummy, eax, ebx, ecx, edx;
481
482 n = c->extended_cpuid_level;
483
484 if (n >= 0x80000005) {
485 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
486 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
487 "D cache %dK (%d bytes/line)\n",
488 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
489 c->x86_cache_size = (ecx>>24) + (edx>>24);
490 /* On K8 L1 TLB is inclusive, so don't count it */
491 c->x86_tlbsize = 0;
492 }
493
494 if (n >= 0x80000006) {
495 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
496 ecx = cpuid_ecx(0x80000006);
497 c->x86_cache_size = ecx >> 16;
498 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
499
500 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
501 c->x86_cache_size, ecx & 0xFF);
502 }
503 if (n >= 0x80000008) {
504 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
505 c->x86_virt_bits = (eax >> 8) & 0xff;
506 c->x86_phys_bits = eax & 0xff;
507 }
508 }
509
510 #ifdef CONFIG_NUMA
511 static int nearby_node(int apicid)
512 {
513 int i, node;
514
515 for (i = apicid - 1; i >= 0; i--) {
516 node = apicid_to_node[i];
517 if (node != NUMA_NO_NODE && node_online(node))
518 return node;
519 }
520 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
521 node = apicid_to_node[i];
522 if (node != NUMA_NO_NODE && node_online(node))
523 return node;
524 }
525 return first_node(node_online_map); /* Shouldn't happen */
526 }
527 #endif
528
529 /*
530 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
531 * Assumes number of cores is a power of two.
532 */
533 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
534 {
535 #ifdef CONFIG_SMP
536 unsigned bits;
537 #ifdef CONFIG_NUMA
538 int cpu = smp_processor_id();
539 int node = 0;
540 unsigned apicid = hard_smp_processor_id();
541 #endif
542 bits = c->x86_coreid_bits;
543
544 /* Low order bits define the core id (index of core in socket) */
545 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
546 /* Convert the APIC ID into the socket ID */
547 c->phys_proc_id = phys_pkg_id(bits);
548
549 #ifdef CONFIG_NUMA
550 node = c->phys_proc_id;
551 if (apicid_to_node[apicid] != NUMA_NO_NODE)
552 node = apicid_to_node[apicid];
553 if (!node_online(node)) {
554 /* Two possibilities here:
555 - The CPU is missing memory and no node was created.
556 In that case try picking one from a nearby CPU
557 - The APIC IDs differ from the HyperTransport node IDs
558 which the K8 northbridge parsing fills in.
559 Assume they are all increased by a constant offset,
560 but in the same order as the HT nodeids.
561 If that doesn't result in a usable node fall back to the
562 path for the previous case. */
563
564 int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
565
566 if (ht_nodeid >= 0 &&
567 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
568 node = apicid_to_node[ht_nodeid];
569 /* Pick a nearby node */
570 if (!node_online(node))
571 node = nearby_node(apicid);
572 }
573 numa_set_node(cpu, node);
574
575 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
576 #endif
577 #endif
578 }
579
580 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
581 {
582 #ifdef CONFIG_SMP
583 unsigned bits, ecx;
584
585 /* Multi core CPU? */
586 if (c->extended_cpuid_level < 0x80000008)
587 return;
588
589 ecx = cpuid_ecx(0x80000008);
590
591 c->x86_max_cores = (ecx & 0xff) + 1;
592
593 /* CPU telling us the core id bits shift? */
594 bits = (ecx >> 12) & 0xF;
595
596 /* Otherwise recompute */
597 if (bits == 0) {
598 while ((1 << bits) < c->x86_max_cores)
599 bits++;
600 }
601
602 c->x86_coreid_bits = bits;
603
604 #endif
605 }
606
607 #define ENABLE_C1E_MASK 0x18000000
608 #define CPUID_PROCESSOR_SIGNATURE 1
609 #define CPUID_XFAM 0x0ff00000
610 #define CPUID_XFAM_K8 0x00000000
611 #define CPUID_XFAM_10H 0x00100000
612 #define CPUID_XFAM_11H 0x00200000
613 #define CPUID_XMOD 0x000f0000
614 #define CPUID_XMOD_REV_F 0x00040000
615
616 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
617 static __cpuinit int amd_apic_timer_broken(void)
618 {
619 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
620
621 switch (eax & CPUID_XFAM) {
622 case CPUID_XFAM_K8:
623 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
624 break;
625 case CPUID_XFAM_10H:
626 case CPUID_XFAM_11H:
627 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
628 if (lo & ENABLE_C1E_MASK)
629 return 1;
630 break;
631 default:
632 /* err on the side of caution */
633 return 1;
634 }
635 return 0;
636 }
637
638 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
639 {
640 early_init_amd_mc(c);
641
642 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
643 if (c->x86_power & (1<<8))
644 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
645 }
646
647 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
648 {
649 unsigned level;
650
651 #ifdef CONFIG_SMP
652 unsigned long value;
653
654 /*
655 * Disable TLB flush filter by setting HWCR.FFDIS on K8
656 * bit 6 of msr C001_0015
657 *
658 * Errata 63 for SH-B3 steppings
659 * Errata 122 for all steppings (F+ have it disabled by default)
660 */
661 if (c->x86 == 15) {
662 rdmsrl(MSR_K8_HWCR, value);
663 value |= 1 << 6;
664 wrmsrl(MSR_K8_HWCR, value);
665 }
666 #endif
667
668 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
669 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
670 clear_bit(0*32+31, (unsigned long *)&c->x86_capability);
671
672 /* On C+ stepping K8 rep microcode works well for copy/memset */
673 level = cpuid_eax(1);
674 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
675 level >= 0x0f58))
676 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
677 if (c->x86 == 0x10 || c->x86 == 0x11)
678 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
679
680 /* Enable workaround for FXSAVE leak */
681 if (c->x86 >= 6)
682 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
683
684 level = get_model_name(c);
685 if (!level) {
686 switch (c->x86) {
687 case 15:
688 /* Should distinguish Models here, but this is only
689 a fallback anyways. */
690 strcpy(c->x86_model_id, "Hammer");
691 break;
692 }
693 }
694 display_cacheinfo(c);
695
696 /* Multi core CPU? */
697 if (c->extended_cpuid_level >= 0x80000008)
698 amd_detect_cmp(c);
699
700 if (c->extended_cpuid_level >= 0x80000006 &&
701 (cpuid_edx(0x80000006) & 0xf000))
702 num_cache_leaves = 4;
703 else
704 num_cache_leaves = 3;
705
706 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
707 set_cpu_cap(c, X86_FEATURE_K8);
708
709 /* MFENCE stops RDTSC speculation */
710 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
711
712 if (amd_apic_timer_broken())
713 disable_apic_timer = 1;
714 }
715
716 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
717 {
718 #ifdef CONFIG_SMP
719 u32 eax, ebx, ecx, edx;
720 int index_msb, core_bits;
721
722 cpuid(1, &eax, &ebx, &ecx, &edx);
723
724
725 if (!cpu_has(c, X86_FEATURE_HT))
726 return;
727 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
728 goto out;
729
730 smp_num_siblings = (ebx & 0xff0000) >> 16;
731
732 if (smp_num_siblings == 1) {
733 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
734 } else if (smp_num_siblings > 1) {
735
736 if (smp_num_siblings > NR_CPUS) {
737 printk(KERN_WARNING "CPU: Unsupported number of "
738 "siblings %d", smp_num_siblings);
739 smp_num_siblings = 1;
740 return;
741 }
742
743 index_msb = get_count_order(smp_num_siblings);
744 c->phys_proc_id = phys_pkg_id(index_msb);
745
746 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
747
748 index_msb = get_count_order(smp_num_siblings);
749
750 core_bits = get_count_order(c->x86_max_cores);
751
752 c->cpu_core_id = phys_pkg_id(index_msb) &
753 ((1 << core_bits) - 1);
754 }
755 out:
756 if ((c->x86_max_cores * smp_num_siblings) > 1) {
757 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
758 c->phys_proc_id);
759 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
760 c->cpu_core_id);
761 }
762
763 #endif
764 }
765
766 /*
767 * find out the number of processor cores on the die
768 */
769 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
770 {
771 unsigned int eax, t;
772
773 if (c->cpuid_level < 4)
774 return 1;
775
776 cpuid_count(4, 0, &eax, &t, &t, &t);
777
778 if (eax & 0x1f)
779 return ((eax >> 26) + 1);
780 else
781 return 1;
782 }
783
784 static void srat_detect_node(void)
785 {
786 #ifdef CONFIG_NUMA
787 unsigned node;
788 int cpu = smp_processor_id();
789 int apicid = hard_smp_processor_id();
790
791 /* Don't do the funky fallback heuristics the AMD version employs
792 for now. */
793 node = apicid_to_node[apicid];
794 if (node == NUMA_NO_NODE)
795 node = first_node(node_online_map);
796 numa_set_node(cpu, node);
797
798 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
799 #endif
800 }
801
802 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
803 {
804 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
805 (c->x86 == 0x6 && c->x86_model >= 0x0e))
806 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
807 }
808
809 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
810 {
811 /* Cache sizes */
812 unsigned n;
813
814 init_intel_cacheinfo(c);
815 if (c->cpuid_level > 9) {
816 unsigned eax = cpuid_eax(10);
817 /* Check for version and the number of counters */
818 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
819 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
820 }
821
822 if (cpu_has_ds) {
823 unsigned int l1, l2;
824 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
825 if (!(l1 & (1<<11)))
826 set_cpu_cap(c, X86_FEATURE_BTS);
827 if (!(l1 & (1<<12)))
828 set_cpu_cap(c, X86_FEATURE_PEBS);
829 }
830
831
832 if (cpu_has_bts)
833 ds_init_intel(c);
834
835 n = c->extended_cpuid_level;
836 if (n >= 0x80000008) {
837 unsigned eax = cpuid_eax(0x80000008);
838 c->x86_virt_bits = (eax >> 8) & 0xff;
839 c->x86_phys_bits = eax & 0xff;
840 /* CPUID workaround for Intel 0F34 CPU */
841 if (c->x86_vendor == X86_VENDOR_INTEL &&
842 c->x86 == 0xF && c->x86_model == 0x3 &&
843 c->x86_mask == 0x4)
844 c->x86_phys_bits = 36;
845 }
846
847 if (c->x86 == 15)
848 c->x86_cache_alignment = c->x86_clflush_size * 2;
849 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
850 (c->x86 == 0x6 && c->x86_model >= 0x0e))
851 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
852 if (c->x86 == 6)
853 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
854 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
855 c->x86_max_cores = intel_num_cpu_cores(c);
856
857 srat_detect_node();
858 }
859
860 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
861 {
862 char *v = c->x86_vendor_id;
863
864 if (!strcmp(v, "AuthenticAMD"))
865 c->x86_vendor = X86_VENDOR_AMD;
866 else if (!strcmp(v, "GenuineIntel"))
867 c->x86_vendor = X86_VENDOR_INTEL;
868 else
869 c->x86_vendor = X86_VENDOR_UNKNOWN;
870 }
871
872 /* Do some early cpuid on the boot CPU to get some parameter that are
873 needed before check_bugs. Everything advanced is in identify_cpu
874 below. */
875 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
876 {
877 u32 tfms, xlvl;
878
879 c->loops_per_jiffy = loops_per_jiffy;
880 c->x86_cache_size = -1;
881 c->x86_vendor = X86_VENDOR_UNKNOWN;
882 c->x86_model = c->x86_mask = 0; /* So far unknown... */
883 c->x86_vendor_id[0] = '\0'; /* Unset */
884 c->x86_model_id[0] = '\0'; /* Unset */
885 c->x86_clflush_size = 64;
886 c->x86_cache_alignment = c->x86_clflush_size;
887 c->x86_max_cores = 1;
888 c->x86_coreid_bits = 0;
889 c->extended_cpuid_level = 0;
890 memset(&c->x86_capability, 0, sizeof c->x86_capability);
891
892 /* Get vendor name */
893 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
894 (unsigned int *)&c->x86_vendor_id[0],
895 (unsigned int *)&c->x86_vendor_id[8],
896 (unsigned int *)&c->x86_vendor_id[4]);
897
898 get_cpu_vendor(c);
899
900 /* Initialize the standard set of capabilities */
901 /* Note that the vendor-specific code below might override */
902
903 /* Intel-defined flags: level 0x00000001 */
904 if (c->cpuid_level >= 0x00000001) {
905 __u32 misc;
906 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
907 &c->x86_capability[0]);
908 c->x86 = (tfms >> 8) & 0xf;
909 c->x86_model = (tfms >> 4) & 0xf;
910 c->x86_mask = tfms & 0xf;
911 if (c->x86 == 0xf)
912 c->x86 += (tfms >> 20) & 0xff;
913 if (c->x86 >= 0x6)
914 c->x86_model += ((tfms >> 16) & 0xF) << 4;
915 if (c->x86_capability[0] & (1<<19))
916 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
917 } else {
918 /* Have CPUID level 0 only - unheard of */
919 c->x86 = 4;
920 }
921
922 #ifdef CONFIG_SMP
923 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
924 #endif
925 /* AMD-defined flags: level 0x80000001 */
926 xlvl = cpuid_eax(0x80000000);
927 c->extended_cpuid_level = xlvl;
928 if ((xlvl & 0xffff0000) == 0x80000000) {
929 if (xlvl >= 0x80000001) {
930 c->x86_capability[1] = cpuid_edx(0x80000001);
931 c->x86_capability[6] = cpuid_ecx(0x80000001);
932 }
933 if (xlvl >= 0x80000004)
934 get_model_name(c); /* Default name */
935 }
936
937 /* Transmeta-defined flags: level 0x80860001 */
938 xlvl = cpuid_eax(0x80860000);
939 if ((xlvl & 0xffff0000) == 0x80860000) {
940 /* Don't set x86_cpuid_level here for now to not confuse. */
941 if (xlvl >= 0x80860001)
942 c->x86_capability[2] = cpuid_edx(0x80860001);
943 }
944
945 c->extended_cpuid_level = cpuid_eax(0x80000000);
946 if (c->extended_cpuid_level >= 0x80000007)
947 c->x86_power = cpuid_edx(0x80000007);
948
949 switch (c->x86_vendor) {
950 case X86_VENDOR_AMD:
951 early_init_amd(c);
952 break;
953 case X86_VENDOR_INTEL:
954 early_init_intel(c);
955 break;
956 }
957
958 }
959
960 /*
961 * This does the hard work of actually picking apart the CPU stuff...
962 */
963 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
964 {
965 int i;
966
967 early_identify_cpu(c);
968
969 init_scattered_cpuid_features(c);
970
971 c->apicid = phys_pkg_id(0);
972
973 /*
974 * Vendor-specific initialization. In this section we
975 * canonicalize the feature flags, meaning if there are
976 * features a certain CPU supports which CPUID doesn't
977 * tell us, CPUID claiming incorrect flags, or other bugs,
978 * we handle them here.
979 *
980 * At the end of this section, c->x86_capability better
981 * indicate the features this CPU genuinely supports!
982 */
983 switch (c->x86_vendor) {
984 case X86_VENDOR_AMD:
985 init_amd(c);
986 break;
987
988 case X86_VENDOR_INTEL:
989 init_intel(c);
990 break;
991
992 case X86_VENDOR_UNKNOWN:
993 default:
994 display_cacheinfo(c);
995 break;
996 }
997
998 detect_ht(c);
999
1000 /*
1001 * On SMP, boot_cpu_data holds the common feature set between
1002 * all CPUs; so make sure that we indicate which features are
1003 * common between the CPUs. The first time this routine gets
1004 * executed, c == &boot_cpu_data.
1005 */
1006 if (c != &boot_cpu_data) {
1007 /* AND the already accumulated flags with these */
1008 for (i = 0; i < NCAPINTS; i++)
1009 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1010 }
1011
1012 /* Clear all flags overriden by options */
1013 for (i = 0; i < NCAPINTS; i++)
1014 c->x86_capability[i] ^= cleared_cpu_caps[i];
1015
1016 #ifdef CONFIG_X86_MCE
1017 mcheck_init(c);
1018 #endif
1019 select_idle_routine(c);
1020
1021 if (c != &boot_cpu_data)
1022 mtrr_ap_init();
1023 #ifdef CONFIG_NUMA
1024 numa_add_cpu(smp_processor_id());
1025 #endif
1026
1027 }
1028
1029 static __init int setup_noclflush(char *arg)
1030 {
1031 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1032 return 1;
1033 }
1034 __setup("noclflush", setup_noclflush);
1035
1036 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1037 {
1038 if (c->x86_model_id[0])
1039 printk(KERN_INFO "%s", c->x86_model_id);
1040
1041 if (c->x86_mask || c->cpuid_level >= 0)
1042 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1043 else
1044 printk(KERN_CONT "\n");
1045 }
1046
1047 static __init int setup_disablecpuid(char *arg)
1048 {
1049 int bit;
1050 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1051 setup_clear_cpu_cap(bit);
1052 else
1053 return 0;
1054 return 1;
1055 }
1056 __setup("clearcpuid=", setup_disablecpuid);
1057
1058 /*
1059 * Get CPU information for use by the procfs.
1060 */
1061
1062 static int show_cpuinfo(struct seq_file *m, void *v)
1063 {
1064 struct cpuinfo_x86 *c = v;
1065 int cpu = 0, i;
1066
1067 /*
1068 * These flag bits must match the definitions in <asm/cpufeature.h>.
1069 * NULL means this bit is undefined or reserved; either way it doesn't
1070 * have meaning as far as Linux is concerned. Note that it's important
1071 * to realize there is a difference between this table and CPUID -- if
1072 * applications want to get the raw CPUID data, they should access
1073 * /dev/cpu/<cpu_nr>/cpuid instead.
1074 */
1075 static const char *const x86_cap_flags[] = {
1076 /* Intel-defined */
1077 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1078 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1079 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1080 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
1081
1082 /* AMD-defined */
1083 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1084 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1085 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
1086 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
1087 "3dnowext", "3dnow",
1088
1089 /* Transmeta-defined */
1090 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1091 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1092 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1093 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1094
1095 /* Other (Linux-defined) */
1096 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
1097 NULL, NULL, NULL, NULL,
1098 "constant_tsc", "up", NULL, "arch_perfmon",
1099 "pebs", "bts", NULL, "sync_rdtsc",
1100 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1101 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1102
1103 /* Intel-defined (#2) */
1104 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
1105 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
1106 NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt",
1107 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1108
1109 /* VIA/Cyrix/Centaur-defined */
1110 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1111 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
1112 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1113 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1114
1115 /* AMD-defined (#2) */
1116 "lahf_lm", "cmp_legacy", "svm", "extapic",
1117 "cr8_legacy", "abm", "sse4a", "misalignsse",
1118 "3dnowprefetch", "osvw", "ibs", "sse5",
1119 "skinit", "wdt", NULL, NULL,
1120 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1122
1123 /* Auxiliary (Linux-defined) */
1124 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1125 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1126 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1127 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1128 };
1129 static const char *const x86_power_flags[] = {
1130 "ts", /* temperature sensor */
1131 "fid", /* frequency id control */
1132 "vid", /* voltage id control */
1133 "ttp", /* thermal trip */
1134 "tm",
1135 "stc",
1136 "100mhzsteps",
1137 "hwpstate",
1138 "", /* tsc invariant mapped to constant_tsc */
1139 /* nothing */
1140 };
1141
1142
1143 #ifdef CONFIG_SMP
1144 cpu = c->cpu_index;
1145 #endif
1146
1147 seq_printf(m, "processor\t: %u\n"
1148 "vendor_id\t: %s\n"
1149 "cpu family\t: %d\n"
1150 "model\t\t: %d\n"
1151 "model name\t: %s\n",
1152 (unsigned)cpu,
1153 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1154 c->x86,
1155 (int)c->x86_model,
1156 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1157
1158 if (c->x86_mask || c->cpuid_level >= 0)
1159 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1160 else
1161 seq_printf(m, "stepping\t: unknown\n");
1162
1163 if (cpu_has(c, X86_FEATURE_TSC)) {
1164 unsigned int freq = cpufreq_quick_get((unsigned)cpu);
1165
1166 if (!freq)
1167 freq = cpu_khz;
1168 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1169 freq / 1000, (freq % 1000));
1170 }
1171
1172 /* Cache size */
1173 if (c->x86_cache_size >= 0)
1174 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1175
1176 #ifdef CONFIG_SMP
1177 if (smp_num_siblings * c->x86_max_cores > 1) {
1178 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1179 seq_printf(m, "siblings\t: %d\n",
1180 cpus_weight(per_cpu(cpu_core_map, cpu)));
1181 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1182 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1183 }
1184 #endif
1185
1186 seq_printf(m,
1187 "fpu\t\t: yes\n"
1188 "fpu_exception\t: yes\n"
1189 "cpuid level\t: %d\n"
1190 "wp\t\t: yes\n"
1191 "flags\t\t:",
1192 c->cpuid_level);
1193
1194 for (i = 0; i < 32*NCAPINTS; i++)
1195 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1196 seq_printf(m, " %s", x86_cap_flags[i]);
1197
1198 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1199 c->loops_per_jiffy/(500000/HZ),
1200 (c->loops_per_jiffy/(5000/HZ)) % 100);
1201
1202 if (c->x86_tlbsize > 0)
1203 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1204 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1205 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1206
1207 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1208 c->x86_phys_bits, c->x86_virt_bits);
1209
1210 seq_printf(m, "power management:");
1211 for (i = 0; i < 32; i++) {
1212 if (c->x86_power & (1 << i)) {
1213 if (i < ARRAY_SIZE(x86_power_flags) &&
1214 x86_power_flags[i])
1215 seq_printf(m, "%s%s",
1216 x86_power_flags[i][0]?" ":"",
1217 x86_power_flags[i]);
1218 else
1219 seq_printf(m, " [%d]", i);
1220 }
1221 }
1222
1223 seq_printf(m, "\n\n");
1224
1225 return 0;
1226 }
1227
1228 static void *c_start(struct seq_file *m, loff_t *pos)
1229 {
1230 if (*pos == 0) /* just in case, cpu 0 is not the first */
1231 *pos = first_cpu(cpu_online_map);
1232 if ((*pos) < NR_CPUS && cpu_online(*pos))
1233 return &cpu_data(*pos);
1234 return NULL;
1235 }
1236
1237 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1238 {
1239 *pos = next_cpu(*pos, cpu_online_map);
1240 return c_start(m, pos);
1241 }
1242
1243 static void c_stop(struct seq_file *m, void *v)
1244 {
1245 }
1246
1247 const struct seq_operations cpuinfo_op = {
1248 .start = c_start,
1249 .next = c_next,
1250 .stop = c_stop,
1251 .show = show_cpuinfo,
1252 };
Linux kernel - Deliverables
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