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Merge git://git.kernel.org/pub/scm/linux/kernel/git/tglx/linux-2.6-hrt
[deliverable/linux.git] / arch / x86 / kernel / setup_64.c
1 /*
2 * Copyright (C) 1995 Linus Torvalds
3 */
4
5 /*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
12 #include <linux/mm.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/screen_info.h>
19 #include <linux/ioport.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/initrd.h>
23 #include <linux/highmem.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
26 #include <asm/processor.h>
27 #include <linux/console.h>
28 #include <linux/seq_file.h>
29 #include <linux/crash_dump.h>
30 #include <linux/root_dev.h>
31 #include <linux/pci.h>
32 #include <linux/efi.h>
33 #include <linux/acpi.h>
34 #include <linux/kallsyms.h>
35 #include <linux/edd.h>
36 #include <linux/iscsi_ibft.h>
37 #include <linux/mmzone.h>
38 #include <linux/kexec.h>
39 #include <linux/cpufreq.h>
40 #include <linux/dmi.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/ctype.h>
43 #include <linux/uaccess.h>
44 #include <linux/init_ohci1394_dma.h>
45 #include <linux/kvm_para.h>
46
47 #include <asm/mtrr.h>
48 #include <asm/uaccess.h>
49 #include <asm/system.h>
50 #include <asm/vsyscall.h>
51 #include <asm/io.h>
52 #include <asm/smp.h>
53 #include <asm/msr.h>
54 #include <asm/desc.h>
55 #include <video/edid.h>
56 #include <asm/e820.h>
57 #include <asm/dma.h>
58 #include <asm/gart.h>
59 #include <asm/mpspec.h>
60 #include <asm/mmu_context.h>
61 #include <asm/proto.h>
62 #include <asm/setup.h>
63 #include <asm/numa.h>
64 #include <asm/sections.h>
65 #include <asm/dmi.h>
66 #include <asm/cacheflush.h>
67 #include <asm/mce.h>
68 #include <asm/ds.h>
69 #include <asm/topology.h>
70 #include <asm/trampoline.h>
71
72 #include <mach_apic.h>
73 #ifdef CONFIG_PARAVIRT
74 #include <asm/paravirt.h>
75 #else
76 #define ARCH_SETUP
77 #endif
78
79 /*
80 * Machine setup..
81 */
82
83 struct cpuinfo_x86 boot_cpu_data __read_mostly;
84 EXPORT_SYMBOL(boot_cpu_data);
85
86 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
87
88 unsigned long mmu_cr4_features;
89
90 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
91 int bootloader_type;
92
93 unsigned long saved_video_mode;
94
95 int force_mwait __cpuinitdata;
96
97 /*
98 * Early DMI memory
99 */
100 int dmi_alloc_index;
101 char dmi_alloc_data[DMI_MAX_DATA];
102
103 /*
104 * Setup options
105 */
106 struct screen_info screen_info;
107 EXPORT_SYMBOL(screen_info);
108 struct sys_desc_table_struct {
109 unsigned short length;
110 unsigned char table[0];
111 };
112
113 struct edid_info edid_info;
114 EXPORT_SYMBOL_GPL(edid_info);
115
116 extern int root_mountflags;
117
118 char __initdata command_line[COMMAND_LINE_SIZE];
119
120 static struct resource standard_io_resources[] = {
121 { .name = "dma1", .start = 0x00, .end = 0x1f,
122 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
123 { .name = "pic1", .start = 0x20, .end = 0x21,
124 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
125 { .name = "timer0", .start = 0x40, .end = 0x43,
126 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
127 { .name = "timer1", .start = 0x50, .end = 0x53,
128 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
129 { .name = "keyboard", .start = 0x60, .end = 0x6f,
130 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
131 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
132 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
133 { .name = "pic2", .start = 0xa0, .end = 0xa1,
134 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
135 { .name = "dma2", .start = 0xc0, .end = 0xdf,
136 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
137 { .name = "fpu", .start = 0xf0, .end = 0xff,
138 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
139 };
140
141 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
142
143 static struct resource data_resource = {
144 .name = "Kernel data",
145 .start = 0,
146 .end = 0,
147 .flags = IORESOURCE_RAM,
148 };
149 static struct resource code_resource = {
150 .name = "Kernel code",
151 .start = 0,
152 .end = 0,
153 .flags = IORESOURCE_RAM,
154 };
155 static struct resource bss_resource = {
156 .name = "Kernel bss",
157 .start = 0,
158 .end = 0,
159 .flags = IORESOURCE_RAM,
160 };
161
162 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
163
164 #ifdef CONFIG_PROC_VMCORE
165 /* elfcorehdr= specifies the location of elf core header
166 * stored by the crashed kernel. This option will be passed
167 * by kexec loader to the capture kernel.
168 */
169 static int __init setup_elfcorehdr(char *arg)
170 {
171 char *end;
172 if (!arg)
173 return -EINVAL;
174 elfcorehdr_addr = memparse(arg, &end);
175 return end > arg ? 0 : -EINVAL;
176 }
177 early_param("elfcorehdr", setup_elfcorehdr);
178 #endif
179
180 #ifndef CONFIG_NUMA
181 static void __init
182 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
183 {
184 unsigned long bootmap_size, bootmap;
185
186 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
187 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
188 PAGE_SIZE);
189 if (bootmap == -1L)
190 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
191 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
192 e820_register_active_regions(0, start_pfn, end_pfn);
193 free_bootmem_with_active_regions(0, end_pfn);
194 early_res_to_bootmem(0, end_pfn<<PAGE_SHIFT);
195 reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
196 }
197 #endif
198
199 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
200 struct edd edd;
201 #ifdef CONFIG_EDD_MODULE
202 EXPORT_SYMBOL(edd);
203 #endif
204 /**
205 * copy_edd() - Copy the BIOS EDD information
206 * from boot_params into a safe place.
207 *
208 */
209 static inline void copy_edd(void)
210 {
211 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
212 sizeof(edd.mbr_signature));
213 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
214 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
215 edd.edd_info_nr = boot_params.eddbuf_entries;
216 }
217 #else
218 static inline void copy_edd(void)
219 {
220 }
221 #endif
222
223 #ifdef CONFIG_KEXEC
224 static void __init reserve_crashkernel(void)
225 {
226 unsigned long long total_mem;
227 unsigned long long crash_size, crash_base;
228 int ret;
229
230 total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
231
232 ret = parse_crashkernel(boot_command_line, total_mem,
233 &crash_size, &crash_base);
234 if (ret == 0 && crash_size) {
235 if (crash_base <= 0) {
236 printk(KERN_INFO "crashkernel reservation failed - "
237 "you have to specify a base address\n");
238 return;
239 }
240
241 if (reserve_bootmem(crash_base, crash_size,
242 BOOTMEM_EXCLUSIVE) < 0) {
243 printk(KERN_INFO "crashkernel reservation failed - "
244 "memory is in use\n");
245 return;
246 }
247
248 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
249 "for crashkernel (System RAM: %ldMB)\n",
250 (unsigned long)(crash_size >> 20),
251 (unsigned long)(crash_base >> 20),
252 (unsigned long)(total_mem >> 20));
253 crashk_res.start = crash_base;
254 crashk_res.end = crash_base + crash_size - 1;
255 insert_resource(&iomem_resource, &crashk_res);
256 }
257 }
258 #else
259 static inline void __init reserve_crashkernel(void)
260 {}
261 #endif
262
263 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
264 void __attribute__((weak)) __init memory_setup(void)
265 {
266 machine_specific_memory_setup();
267 }
268
269 static void __init parse_setup_data(void)
270 {
271 struct setup_data *data;
272 unsigned long pa_data;
273
274 if (boot_params.hdr.version < 0x0209)
275 return;
276 pa_data = boot_params.hdr.setup_data;
277 while (pa_data) {
278 data = early_ioremap(pa_data, PAGE_SIZE);
279 switch (data->type) {
280 default:
281 break;
282 }
283 #ifndef CONFIG_DEBUG_BOOT_PARAMS
284 free_early(pa_data, pa_data+sizeof(*data)+data->len);
285 #endif
286 pa_data = data->next;
287 early_iounmap(data, PAGE_SIZE);
288 }
289 }
290
291 /*
292 * setup_arch - architecture-specific boot-time initializations
293 *
294 * Note: On x86_64, fixmaps are ready for use even before this is called.
295 */
296 void __init setup_arch(char **cmdline_p)
297 {
298 unsigned i;
299
300 printk(KERN_INFO "Command line: %s\n", boot_command_line);
301
302 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
303 screen_info = boot_params.screen_info;
304 edid_info = boot_params.edid_info;
305 saved_video_mode = boot_params.hdr.vid_mode;
306 bootloader_type = boot_params.hdr.type_of_loader;
307
308 #ifdef CONFIG_BLK_DEV_RAM
309 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
310 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
311 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
312 #endif
313 #ifdef CONFIG_EFI
314 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
315 "EL64", 4))
316 efi_enabled = 1;
317 #endif
318
319 ARCH_SETUP
320
321 memory_setup();
322 copy_edd();
323
324 if (!boot_params.hdr.root_flags)
325 root_mountflags &= ~MS_RDONLY;
326 init_mm.start_code = (unsigned long) &_text;
327 init_mm.end_code = (unsigned long) &_etext;
328 init_mm.end_data = (unsigned long) &_edata;
329 init_mm.brk = (unsigned long) &_end;
330
331 code_resource.start = virt_to_phys(&_text);
332 code_resource.end = virt_to_phys(&_etext)-1;
333 data_resource.start = virt_to_phys(&_etext);
334 data_resource.end = virt_to_phys(&_edata)-1;
335 bss_resource.start = virt_to_phys(&__bss_start);
336 bss_resource.end = virt_to_phys(&__bss_stop)-1;
337
338 early_identify_cpu(&boot_cpu_data);
339
340 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
341 *cmdline_p = command_line;
342
343 parse_setup_data();
344
345 parse_early_param();
346
347 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
348 if (init_ohci1394_dma_early)
349 init_ohci1394_dma_on_all_controllers();
350 #endif
351
352 finish_e820_parsing();
353
354 /* after parse_early_param, so could debug it */
355 insert_resource(&iomem_resource, &code_resource);
356 insert_resource(&iomem_resource, &data_resource);
357 insert_resource(&iomem_resource, &bss_resource);
358
359 early_gart_iommu_check();
360
361 e820_register_active_regions(0, 0, -1UL);
362 /*
363 * partially used pages are not usable - thus
364 * we are rounding upwards:
365 */
366 end_pfn = e820_end_of_ram();
367 /* update e820 for memory not covered by WB MTRRs */
368 mtrr_bp_init();
369 if (mtrr_trim_uncached_memory(end_pfn)) {
370 e820_register_active_regions(0, 0, -1UL);
371 end_pfn = e820_end_of_ram();
372 }
373
374 num_physpages = end_pfn;
375
376 check_efer();
377
378 max_pfn_mapped = init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
379 if (efi_enabled)
380 efi_init();
381
382 vsmp_init();
383
384 dmi_scan_machine();
385
386 io_delay_init();
387
388 #ifdef CONFIG_KVM_CLOCK
389 kvmclock_init();
390 #endif
391
392 #ifdef CONFIG_SMP
393 /* setup to use the early static init tables during kernel startup */
394 x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
395 x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
396 #ifdef CONFIG_NUMA
397 x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
398 #endif
399 #endif
400
401 #ifdef CONFIG_ACPI
402 /*
403 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
404 * Call this early for SRAT node setup.
405 */
406 acpi_boot_table_init();
407 #endif
408
409 /* How many end-of-memory variables you have, grandma! */
410 max_low_pfn = end_pfn;
411 max_pfn = end_pfn;
412 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
413
414 /* Remove active ranges so rediscovery with NUMA-awareness happens */
415 remove_all_active_ranges();
416
417 #ifdef CONFIG_ACPI_NUMA
418 /*
419 * Parse SRAT to discover nodes.
420 */
421 acpi_numa_init();
422 #endif
423
424 #ifdef CONFIG_NUMA
425 numa_initmem_init(0, end_pfn);
426 #else
427 contig_initmem_init(0, end_pfn);
428 #endif
429
430 dma32_reserve_bootmem();
431
432 #ifdef CONFIG_ACPI_SLEEP
433 /*
434 * Reserve low memory region for sleep support.
435 */
436 acpi_reserve_bootmem();
437 #endif
438
439 if (efi_enabled)
440 efi_reserve_bootmem();
441
442 /*
443 * Find and reserve possible boot-time SMP configuration:
444 */
445 find_smp_config();
446 #ifdef CONFIG_BLK_DEV_INITRD
447 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
448 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
449 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
450 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
451 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
452
453 if (ramdisk_end <= end_of_mem) {
454 /*
455 * don't need to reserve again, already reserved early
456 * in x86_64_start_kernel, and early_res_to_bootmem
457 * convert that to reserved in bootmem
458 */
459 initrd_start = ramdisk_image + PAGE_OFFSET;
460 initrd_end = initrd_start+ramdisk_size;
461 } else {
462 free_bootmem(ramdisk_image, ramdisk_size);
463 printk(KERN_ERR "initrd extends beyond end of memory "
464 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
465 ramdisk_end, end_of_mem);
466 initrd_start = 0;
467 }
468 }
469 #endif
470 reserve_crashkernel();
471
472 reserve_ibft_region();
473
474 paging_init();
475 map_vsyscall();
476
477 early_quirks();
478
479 #ifdef CONFIG_ACPI
480 /*
481 * Read APIC and some other early information from ACPI tables.
482 */
483 acpi_boot_init();
484 #endif
485
486 init_cpu_to_node();
487
488 /*
489 * get boot-time SMP configuration:
490 */
491 if (smp_found_config)
492 get_smp_config();
493 init_apic_mappings();
494 ioapic_init_mappings();
495
496 kvm_guest_init();
497
498 /*
499 * We trust e820 completely. No explicit ROM probing in memory.
500 */
501 e820_reserve_resources();
502 e820_mark_nosave_regions();
503
504 /* request I/O space for devices used on all i[345]86 PCs */
505 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
506 request_resource(&ioport_resource, &standard_io_resources[i]);
507
508 e820_setup_gap();
509
510 #ifdef CONFIG_VT
511 #if defined(CONFIG_VGA_CONSOLE)
512 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
513 conswitchp = &vga_con;
514 #elif defined(CONFIG_DUMMY_CONSOLE)
515 conswitchp = &dummy_con;
516 #endif
517 #endif
518 }
519
520 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
521 {
522 unsigned int *v;
523
524 if (c->extended_cpuid_level < 0x80000004)
525 return 0;
526
527 v = (unsigned int *) c->x86_model_id;
528 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
529 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
530 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
531 c->x86_model_id[48] = 0;
532 return 1;
533 }
534
535
536 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
537 {
538 unsigned int n, dummy, eax, ebx, ecx, edx;
539
540 n = c->extended_cpuid_level;
541
542 if (n >= 0x80000005) {
543 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
544 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
545 "D cache %dK (%d bytes/line)\n",
546 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
547 c->x86_cache_size = (ecx>>24) + (edx>>24);
548 /* On K8 L1 TLB is inclusive, so don't count it */
549 c->x86_tlbsize = 0;
550 }
551
552 if (n >= 0x80000006) {
553 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
554 ecx = cpuid_ecx(0x80000006);
555 c->x86_cache_size = ecx >> 16;
556 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
557
558 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
559 c->x86_cache_size, ecx & 0xFF);
560 }
561 if (n >= 0x80000008) {
562 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
563 c->x86_virt_bits = (eax >> 8) & 0xff;
564 c->x86_phys_bits = eax & 0xff;
565 }
566 }
567
568 #ifdef CONFIG_NUMA
569 static int __cpuinit nearby_node(int apicid)
570 {
571 int i, node;
572
573 for (i = apicid - 1; i >= 0; i--) {
574 node = apicid_to_node[i];
575 if (node != NUMA_NO_NODE && node_online(node))
576 return node;
577 }
578 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
579 node = apicid_to_node[i];
580 if (node != NUMA_NO_NODE && node_online(node))
581 return node;
582 }
583 return first_node(node_online_map); /* Shouldn't happen */
584 }
585 #endif
586
587 /*
588 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
589 * Assumes number of cores is a power of two.
590 */
591 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
592 {
593 #ifdef CONFIG_SMP
594 unsigned bits;
595 #ifdef CONFIG_NUMA
596 int cpu = smp_processor_id();
597 int node = 0;
598 unsigned apicid = hard_smp_processor_id();
599 #endif
600 bits = c->x86_coreid_bits;
601
602 /* Low order bits define the core id (index of core in socket) */
603 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
604 /* Convert the initial APIC ID into the socket ID */
605 c->phys_proc_id = c->initial_apicid >> bits;
606
607 #ifdef CONFIG_NUMA
608 node = c->phys_proc_id;
609 if (apicid_to_node[apicid] != NUMA_NO_NODE)
610 node = apicid_to_node[apicid];
611 if (!node_online(node)) {
612 /* Two possibilities here:
613 - The CPU is missing memory and no node was created.
614 In that case try picking one from a nearby CPU
615 - The APIC IDs differ from the HyperTransport node IDs
616 which the K8 northbridge parsing fills in.
617 Assume they are all increased by a constant offset,
618 but in the same order as the HT nodeids.
619 If that doesn't result in a usable node fall back to the
620 path for the previous case. */
621
622 int ht_nodeid = c->initial_apicid;
623
624 if (ht_nodeid >= 0 &&
625 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
626 node = apicid_to_node[ht_nodeid];
627 /* Pick a nearby node */
628 if (!node_online(node))
629 node = nearby_node(apicid);
630 }
631 numa_set_node(cpu, node);
632
633 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
634 #endif
635 #endif
636 }
637
638 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
639 {
640 #ifdef CONFIG_SMP
641 unsigned bits, ecx;
642
643 /* Multi core CPU? */
644 if (c->extended_cpuid_level < 0x80000008)
645 return;
646
647 ecx = cpuid_ecx(0x80000008);
648
649 c->x86_max_cores = (ecx & 0xff) + 1;
650
651 /* CPU telling us the core id bits shift? */
652 bits = (ecx >> 12) & 0xF;
653
654 /* Otherwise recompute */
655 if (bits == 0) {
656 while ((1 << bits) < c->x86_max_cores)
657 bits++;
658 }
659
660 c->x86_coreid_bits = bits;
661
662 #endif
663 }
664
665 #define ENABLE_C1E_MASK 0x18000000
666 #define CPUID_PROCESSOR_SIGNATURE 1
667 #define CPUID_XFAM 0x0ff00000
668 #define CPUID_XFAM_K8 0x00000000
669 #define CPUID_XFAM_10H 0x00100000
670 #define CPUID_XFAM_11H 0x00200000
671 #define CPUID_XMOD 0x000f0000
672 #define CPUID_XMOD_REV_F 0x00040000
673
674 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
675 static __cpuinit int amd_apic_timer_broken(void)
676 {
677 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
678
679 switch (eax & CPUID_XFAM) {
680 case CPUID_XFAM_K8:
681 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
682 break;
683 case CPUID_XFAM_10H:
684 case CPUID_XFAM_11H:
685 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
686 if (lo & ENABLE_C1E_MASK)
687 return 1;
688 break;
689 default:
690 /* err on the side of caution */
691 return 1;
692 }
693 return 0;
694 }
695
696 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
697 {
698 early_init_amd_mc(c);
699
700 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
701 if (c->x86_power & (1<<8))
702 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
703 }
704
705 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
706 {
707 unsigned level;
708
709 #ifdef CONFIG_SMP
710 unsigned long value;
711
712 /*
713 * Disable TLB flush filter by setting HWCR.FFDIS on K8
714 * bit 6 of msr C001_0015
715 *
716 * Errata 63 for SH-B3 steppings
717 * Errata 122 for all steppings (F+ have it disabled by default)
718 */
719 if (c->x86 == 15) {
720 rdmsrl(MSR_K8_HWCR, value);
721 value |= 1 << 6;
722 wrmsrl(MSR_K8_HWCR, value);
723 }
724 #endif
725
726 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
727 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
728 clear_cpu_cap(c, 0*32+31);
729
730 /* On C+ stepping K8 rep microcode works well for copy/memset */
731 level = cpuid_eax(1);
732 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
733 level >= 0x0f58))
734 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
735 if (c->x86 == 0x10 || c->x86 == 0x11)
736 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
737
738 /* Enable workaround for FXSAVE leak */
739 if (c->x86 >= 6)
740 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
741
742 level = get_model_name(c);
743 if (!level) {
744 switch (c->x86) {
745 case 15:
746 /* Should distinguish Models here, but this is only
747 a fallback anyways. */
748 strcpy(c->x86_model_id, "Hammer");
749 break;
750 }
751 }
752 display_cacheinfo(c);
753
754 /* Multi core CPU? */
755 if (c->extended_cpuid_level >= 0x80000008)
756 amd_detect_cmp(c);
757
758 if (c->extended_cpuid_level >= 0x80000006 &&
759 (cpuid_edx(0x80000006) & 0xf000))
760 num_cache_leaves = 4;
761 else
762 num_cache_leaves = 3;
763
764 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
765 set_cpu_cap(c, X86_FEATURE_K8);
766
767 /* MFENCE stops RDTSC speculation */
768 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
769
770 if (amd_apic_timer_broken())
771 disable_apic_timer = 1;
772
773 if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
774 unsigned long long tseg;
775
776 /*
777 * Split up direct mapping around the TSEG SMM area.
778 * Don't do it for gbpages because there seems very little
779 * benefit in doing so.
780 */
781 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
782 (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
783 set_memory_4k((unsigned long)__va(tseg), 1);
784 }
785 }
786
787 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
788 {
789 #ifdef CONFIG_SMP
790 u32 eax, ebx, ecx, edx;
791 int index_msb, core_bits;
792
793 cpuid(1, &eax, &ebx, &ecx, &edx);
794
795
796 if (!cpu_has(c, X86_FEATURE_HT))
797 return;
798 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
799 goto out;
800
801 smp_num_siblings = (ebx & 0xff0000) >> 16;
802
803 if (smp_num_siblings == 1) {
804 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
805 } else if (smp_num_siblings > 1) {
806
807 if (smp_num_siblings > NR_CPUS) {
808 printk(KERN_WARNING "CPU: Unsupported number of "
809 "siblings %d", smp_num_siblings);
810 smp_num_siblings = 1;
811 return;
812 }
813
814 index_msb = get_count_order(smp_num_siblings);
815 c->phys_proc_id = phys_pkg_id(index_msb);
816
817 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
818
819 index_msb = get_count_order(smp_num_siblings);
820
821 core_bits = get_count_order(c->x86_max_cores);
822
823 c->cpu_core_id = phys_pkg_id(index_msb) &
824 ((1 << core_bits) - 1);
825 }
826 out:
827 if ((c->x86_max_cores * smp_num_siblings) > 1) {
828 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
829 c->phys_proc_id);
830 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
831 c->cpu_core_id);
832 }
833
834 #endif
835 }
836
837 /*
838 * find out the number of processor cores on the die
839 */
840 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
841 {
842 unsigned int eax, t;
843
844 if (c->cpuid_level < 4)
845 return 1;
846
847 cpuid_count(4, 0, &eax, &t, &t, &t);
848
849 if (eax & 0x1f)
850 return ((eax >> 26) + 1);
851 else
852 return 1;
853 }
854
855 static void __cpuinit srat_detect_node(void)
856 {
857 #ifdef CONFIG_NUMA
858 unsigned node;
859 int cpu = smp_processor_id();
860 int apicid = hard_smp_processor_id();
861
862 /* Don't do the funky fallback heuristics the AMD version employs
863 for now. */
864 node = apicid_to_node[apicid];
865 if (node == NUMA_NO_NODE || !node_online(node))
866 node = first_node(node_online_map);
867 numa_set_node(cpu, node);
868
869 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
870 #endif
871 }
872
873 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
874 {
875 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
876 (c->x86 == 0x6 && c->x86_model >= 0x0e))
877 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
878 }
879
880 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
881 {
882 /* Cache sizes */
883 unsigned n;
884
885 init_intel_cacheinfo(c);
886 if (c->cpuid_level > 9) {
887 unsigned eax = cpuid_eax(10);
888 /* Check for version and the number of counters */
889 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
890 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
891 }
892
893 if (cpu_has_ds) {
894 unsigned int l1, l2;
895 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
896 if (!(l1 & (1<<11)))
897 set_cpu_cap(c, X86_FEATURE_BTS);
898 if (!(l1 & (1<<12)))
899 set_cpu_cap(c, X86_FEATURE_PEBS);
900 }
901
902
903 if (cpu_has_bts)
904 ds_init_intel(c);
905
906 n = c->extended_cpuid_level;
907 if (n >= 0x80000008) {
908 unsigned eax = cpuid_eax(0x80000008);
909 c->x86_virt_bits = (eax >> 8) & 0xff;
910 c->x86_phys_bits = eax & 0xff;
911 /* CPUID workaround for Intel 0F34 CPU */
912 if (c->x86_vendor == X86_VENDOR_INTEL &&
913 c->x86 == 0xF && c->x86_model == 0x3 &&
914 c->x86_mask == 0x4)
915 c->x86_phys_bits = 36;
916 }
917
918 if (c->x86 == 15)
919 c->x86_cache_alignment = c->x86_clflush_size * 2;
920 if (c->x86 == 6)
921 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
922 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
923 c->x86_max_cores = intel_num_cpu_cores(c);
924
925 srat_detect_node();
926 }
927
928 static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
929 {
930 if (c->x86 == 0x6 && c->x86_model >= 0xf)
931 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
932 }
933
934 static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
935 {
936 /* Cache sizes */
937 unsigned n;
938
939 n = c->extended_cpuid_level;
940 if (n >= 0x80000008) {
941 unsigned eax = cpuid_eax(0x80000008);
942 c->x86_virt_bits = (eax >> 8) & 0xff;
943 c->x86_phys_bits = eax & 0xff;
944 }
945
946 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
947 c->x86_cache_alignment = c->x86_clflush_size * 2;
948 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
949 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
950 }
951 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
952 }
953
954 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
955 {
956 char *v = c->x86_vendor_id;
957
958 if (!strcmp(v, "AuthenticAMD"))
959 c->x86_vendor = X86_VENDOR_AMD;
960 else if (!strcmp(v, "GenuineIntel"))
961 c->x86_vendor = X86_VENDOR_INTEL;
962 else if (!strcmp(v, "CentaurHauls"))
963 c->x86_vendor = X86_VENDOR_CENTAUR;
964 else
965 c->x86_vendor = X86_VENDOR_UNKNOWN;
966 }
967
968 /* Do some early cpuid on the boot CPU to get some parameter that are
969 needed before check_bugs. Everything advanced is in identify_cpu
970 below. */
971 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
972 {
973 u32 tfms, xlvl;
974
975 c->loops_per_jiffy = loops_per_jiffy;
976 c->x86_cache_size = -1;
977 c->x86_vendor = X86_VENDOR_UNKNOWN;
978 c->x86_model = c->x86_mask = 0; /* So far unknown... */
979 c->x86_vendor_id[0] = '\0'; /* Unset */
980 c->x86_model_id[0] = '\0'; /* Unset */
981 c->x86_clflush_size = 64;
982 c->x86_cache_alignment = c->x86_clflush_size;
983 c->x86_max_cores = 1;
984 c->x86_coreid_bits = 0;
985 c->extended_cpuid_level = 0;
986 memset(&c->x86_capability, 0, sizeof c->x86_capability);
987
988 /* Get vendor name */
989 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
990 (unsigned int *)&c->x86_vendor_id[0],
991 (unsigned int *)&c->x86_vendor_id[8],
992 (unsigned int *)&c->x86_vendor_id[4]);
993
994 get_cpu_vendor(c);
995
996 /* Initialize the standard set of capabilities */
997 /* Note that the vendor-specific code below might override */
998
999 /* Intel-defined flags: level 0x00000001 */
1000 if (c->cpuid_level >= 0x00000001) {
1001 __u32 misc;
1002 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
1003 &c->x86_capability[0]);
1004 c->x86 = (tfms >> 8) & 0xf;
1005 c->x86_model = (tfms >> 4) & 0xf;
1006 c->x86_mask = tfms & 0xf;
1007 if (c->x86 == 0xf)
1008 c->x86 += (tfms >> 20) & 0xff;
1009 if (c->x86 >= 0x6)
1010 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1011 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
1012 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1013 } else {
1014 /* Have CPUID level 0 only - unheard of */
1015 c->x86 = 4;
1016 }
1017
1018 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
1019 #ifdef CONFIG_SMP
1020 c->phys_proc_id = c->initial_apicid;
1021 #endif
1022 /* AMD-defined flags: level 0x80000001 */
1023 xlvl = cpuid_eax(0x80000000);
1024 c->extended_cpuid_level = xlvl;
1025 if ((xlvl & 0xffff0000) == 0x80000000) {
1026 if (xlvl >= 0x80000001) {
1027 c->x86_capability[1] = cpuid_edx(0x80000001);
1028 c->x86_capability[6] = cpuid_ecx(0x80000001);
1029 }
1030 if (xlvl >= 0x80000004)
1031 get_model_name(c); /* Default name */
1032 }
1033
1034 /* Transmeta-defined flags: level 0x80860001 */
1035 xlvl = cpuid_eax(0x80860000);
1036 if ((xlvl & 0xffff0000) == 0x80860000) {
1037 /* Don't set x86_cpuid_level here for now to not confuse. */
1038 if (xlvl >= 0x80860001)
1039 c->x86_capability[2] = cpuid_edx(0x80860001);
1040 }
1041
1042 c->extended_cpuid_level = cpuid_eax(0x80000000);
1043 if (c->extended_cpuid_level >= 0x80000007)
1044 c->x86_power = cpuid_edx(0x80000007);
1045
1046
1047 clear_cpu_cap(c, X86_FEATURE_PAT);
1048
1049 switch (c->x86_vendor) {
1050 case X86_VENDOR_AMD:
1051 early_init_amd(c);
1052 if (c->x86 >= 0xf && c->x86 <= 0x11)
1053 set_cpu_cap(c, X86_FEATURE_PAT);
1054 break;
1055 case X86_VENDOR_INTEL:
1056 early_init_intel(c);
1057 if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
1058 set_cpu_cap(c, X86_FEATURE_PAT);
1059 break;
1060 case X86_VENDOR_CENTAUR:
1061 early_init_centaur(c);
1062 break;
1063 }
1064
1065 }
1066
1067 /*
1068 * This does the hard work of actually picking apart the CPU stuff...
1069 */
1070 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1071 {
1072 int i;
1073
1074 early_identify_cpu(c);
1075
1076 init_scattered_cpuid_features(c);
1077
1078 c->apicid = phys_pkg_id(0);
1079
1080 /*
1081 * Vendor-specific initialization. In this section we
1082 * canonicalize the feature flags, meaning if there are
1083 * features a certain CPU supports which CPUID doesn't
1084 * tell us, CPUID claiming incorrect flags, or other bugs,
1085 * we handle them here.
1086 *
1087 * At the end of this section, c->x86_capability better
1088 * indicate the features this CPU genuinely supports!
1089 */
1090 switch (c->x86_vendor) {
1091 case X86_VENDOR_AMD:
1092 init_amd(c);
1093 break;
1094
1095 case X86_VENDOR_INTEL:
1096 init_intel(c);
1097 break;
1098
1099 case X86_VENDOR_CENTAUR:
1100 init_centaur(c);
1101 break;
1102
1103 case X86_VENDOR_UNKNOWN:
1104 default:
1105 display_cacheinfo(c);
1106 break;
1107 }
1108
1109 detect_ht(c);
1110
1111 /*
1112 * On SMP, boot_cpu_data holds the common feature set between
1113 * all CPUs; so make sure that we indicate which features are
1114 * common between the CPUs. The first time this routine gets
1115 * executed, c == &boot_cpu_data.
1116 */
1117 if (c != &boot_cpu_data) {
1118 /* AND the already accumulated flags with these */
1119 for (i = 0; i < NCAPINTS; i++)
1120 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1121 }
1122
1123 /* Clear all flags overriden by options */
1124 for (i = 0; i < NCAPINTS; i++)
1125 c->x86_capability[i] &= ~cleared_cpu_caps[i];
1126
1127 #ifdef CONFIG_X86_MCE
1128 mcheck_init(c);
1129 #endif
1130 select_idle_routine(c);
1131
1132 #ifdef CONFIG_NUMA
1133 numa_add_cpu(smp_processor_id());
1134 #endif
1135
1136 }
1137
1138 void __cpuinit identify_boot_cpu(void)
1139 {
1140 identify_cpu(&boot_cpu_data);
1141 }
1142
1143 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1144 {
1145 BUG_ON(c == &boot_cpu_data);
1146 identify_cpu(c);
1147 mtrr_ap_init();
1148 }
1149
1150 static __init int setup_noclflush(char *arg)
1151 {
1152 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1153 return 1;
1154 }
1155 __setup("noclflush", setup_noclflush);
1156
1157 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1158 {
1159 if (c->x86_model_id[0])
1160 printk(KERN_CONT "%s", c->x86_model_id);
1161
1162 if (c->x86_mask || c->cpuid_level >= 0)
1163 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1164 else
1165 printk(KERN_CONT "\n");
1166 }
1167
1168 static __init int setup_disablecpuid(char *arg)
1169 {
1170 int bit;
1171 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1172 setup_clear_cpu_cap(bit);
1173 else
1174 return 0;
1175 return 1;
1176 }
1177 __setup("clearcpuid=", setup_disablecpuid);
Linux kernel - Deliverables
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