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Merge branch 'for-linus' of git://www.linux-m32r.org/git/takata/linux-2.6_dev
[deliverable/linux.git] / arch / x86 / kernel / setup_64.c
1 /*
2 * Copyright (C) 1995 Linus Torvalds
3 */
4
5 /*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
12 #include <linux/mm.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/screen_info.h>
19 #include <linux/ioport.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/initrd.h>
23 #include <linux/highmem.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
26 #include <asm/processor.h>
27 #include <linux/console.h>
28 #include <linux/seq_file.h>
29 #include <linux/crash_dump.h>
30 #include <linux/root_dev.h>
31 #include <linux/pci.h>
32 #include <asm/pci-direct.h>
33 #include <linux/efi.h>
34 #include <linux/acpi.h>
35 #include <linux/kallsyms.h>
36 #include <linux/edd.h>
37 #include <linux/iscsi_ibft.h>
38 #include <linux/mmzone.h>
39 #include <linux/kexec.h>
40 #include <linux/cpufreq.h>
41 #include <linux/dmi.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/ctype.h>
44 #include <linux/sort.h>
45 #include <linux/uaccess.h>
46 #include <linux/init_ohci1394_dma.h>
47 #include <linux/kvm_para.h>
48
49 #include <asm/mtrr.h>
50 #include <asm/uaccess.h>
51 #include <asm/system.h>
52 #include <asm/vsyscall.h>
53 #include <asm/io.h>
54 #include <asm/smp.h>
55 #include <asm/msr.h>
56 #include <asm/desc.h>
57 #include <video/edid.h>
58 #include <asm/e820.h>
59 #include <asm/dma.h>
60 #include <asm/gart.h>
61 #include <asm/mpspec.h>
62 #include <asm/mmu_context.h>
63 #include <asm/proto.h>
64 #include <asm/setup.h>
65 #include <asm/numa.h>
66 #include <asm/sections.h>
67 #include <asm/dmi.h>
68 #include <asm/cacheflush.h>
69 #include <asm/mce.h>
70 #include <asm/ds.h>
71 #include <asm/topology.h>
72 #include <asm/trampoline.h>
73
74 #include <mach_apic.h>
75 #ifdef CONFIG_PARAVIRT
76 #include <asm/paravirt.h>
77 #else
78 #define ARCH_SETUP
79 #endif
80
81 /*
82 * Machine setup..
83 */
84
85 struct cpuinfo_x86 boot_cpu_data __read_mostly;
86 EXPORT_SYMBOL(boot_cpu_data);
87
88 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
89
90 unsigned long mmu_cr4_features;
91
92 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
93 int bootloader_type;
94
95 unsigned long saved_video_mode;
96
97 int force_mwait __cpuinitdata;
98
99 /*
100 * Early DMI memory
101 */
102 int dmi_alloc_index;
103 char dmi_alloc_data[DMI_MAX_DATA];
104
105 /*
106 * Setup options
107 */
108 struct screen_info screen_info;
109 EXPORT_SYMBOL(screen_info);
110 struct sys_desc_table_struct {
111 unsigned short length;
112 unsigned char table[0];
113 };
114
115 struct edid_info edid_info;
116 EXPORT_SYMBOL_GPL(edid_info);
117
118 extern int root_mountflags;
119
120 char __initdata command_line[COMMAND_LINE_SIZE];
121
122 static struct resource standard_io_resources[] = {
123 { .name = "dma1", .start = 0x00, .end = 0x1f,
124 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
125 { .name = "pic1", .start = 0x20, .end = 0x21,
126 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
127 { .name = "timer0", .start = 0x40, .end = 0x43,
128 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
129 { .name = "timer1", .start = 0x50, .end = 0x53,
130 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
131 { .name = "keyboard", .start = 0x60, .end = 0x6f,
132 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
133 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
134 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
135 { .name = "pic2", .start = 0xa0, .end = 0xa1,
136 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
137 { .name = "dma2", .start = 0xc0, .end = 0xdf,
138 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
139 { .name = "fpu", .start = 0xf0, .end = 0xff,
140 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
141 };
142
143 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
144
145 static struct resource data_resource = {
146 .name = "Kernel data",
147 .start = 0,
148 .end = 0,
149 .flags = IORESOURCE_RAM,
150 };
151 static struct resource code_resource = {
152 .name = "Kernel code",
153 .start = 0,
154 .end = 0,
155 .flags = IORESOURCE_RAM,
156 };
157 static struct resource bss_resource = {
158 .name = "Kernel bss",
159 .start = 0,
160 .end = 0,
161 .flags = IORESOURCE_RAM,
162 };
163
164 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
165
166 #ifdef CONFIG_PROC_VMCORE
167 /* elfcorehdr= specifies the location of elf core header
168 * stored by the crashed kernel. This option will be passed
169 * by kexec loader to the capture kernel.
170 */
171 static int __init setup_elfcorehdr(char *arg)
172 {
173 char *end;
174 if (!arg)
175 return -EINVAL;
176 elfcorehdr_addr = memparse(arg, &end);
177 return end > arg ? 0 : -EINVAL;
178 }
179 early_param("elfcorehdr", setup_elfcorehdr);
180 #endif
181
182 #ifndef CONFIG_NUMA
183 static void __init
184 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
185 {
186 unsigned long bootmap_size, bootmap;
187
188 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
189 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
190 PAGE_SIZE);
191 if (bootmap == -1L)
192 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
193 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
194 e820_register_active_regions(0, start_pfn, end_pfn);
195 free_bootmem_with_active_regions(0, end_pfn);
196 early_res_to_bootmem(0, end_pfn<<PAGE_SHIFT);
197 reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
198 }
199 #endif
200
201 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
202 struct edd edd;
203 #ifdef CONFIG_EDD_MODULE
204 EXPORT_SYMBOL(edd);
205 #endif
206 /**
207 * copy_edd() - Copy the BIOS EDD information
208 * from boot_params into a safe place.
209 *
210 */
211 static inline void copy_edd(void)
212 {
213 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
214 sizeof(edd.mbr_signature));
215 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
216 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
217 edd.edd_info_nr = boot_params.eddbuf_entries;
218 }
219 #else
220 static inline void copy_edd(void)
221 {
222 }
223 #endif
224
225 #ifdef CONFIG_KEXEC
226 static void __init reserve_crashkernel(void)
227 {
228 unsigned long long total_mem;
229 unsigned long long crash_size, crash_base;
230 int ret;
231
232 total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
233
234 ret = parse_crashkernel(boot_command_line, total_mem,
235 &crash_size, &crash_base);
236 if (ret == 0 && crash_size) {
237 if (crash_base <= 0) {
238 printk(KERN_INFO "crashkernel reservation failed - "
239 "you have to specify a base address\n");
240 return;
241 }
242
243 if (reserve_bootmem(crash_base, crash_size,
244 BOOTMEM_EXCLUSIVE) < 0) {
245 printk(KERN_INFO "crashkernel reservation failed - "
246 "memory is in use\n");
247 return;
248 }
249
250 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
251 "for crashkernel (System RAM: %ldMB)\n",
252 (unsigned long)(crash_size >> 20),
253 (unsigned long)(crash_base >> 20),
254 (unsigned long)(total_mem >> 20));
255 crashk_res.start = crash_base;
256 crashk_res.end = crash_base + crash_size - 1;
257 insert_resource(&iomem_resource, &crashk_res);
258 }
259 }
260 #else
261 static inline void __init reserve_crashkernel(void)
262 {}
263 #endif
264
265 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
266 void __attribute__((weak)) __init memory_setup(void)
267 {
268 machine_specific_memory_setup();
269 }
270
271 static void __init parse_setup_data(void)
272 {
273 struct setup_data *data;
274 unsigned long pa_data;
275
276 if (boot_params.hdr.version < 0x0209)
277 return;
278 pa_data = boot_params.hdr.setup_data;
279 while (pa_data) {
280 data = early_ioremap(pa_data, PAGE_SIZE);
281 switch (data->type) {
282 default:
283 break;
284 }
285 #ifndef CONFIG_DEBUG_BOOT_PARAMS
286 free_early(pa_data, pa_data+sizeof(*data)+data->len);
287 #endif
288 pa_data = data->next;
289 early_iounmap(data, PAGE_SIZE);
290 }
291 }
292
293 #ifdef CONFIG_PCI_MMCONFIG
294 extern void __cpuinit fam10h_check_enable_mmcfg(void);
295 extern void __init check_enable_amd_mmconf_dmi(void);
296 #else
297 void __cpuinit fam10h_check_enable_mmcfg(void)
298 {
299 }
300 void __init check_enable_amd_mmconf_dmi(void)
301 {
302 }
303 #endif
304
305 /*
306 * setup_arch - architecture-specific boot-time initializations
307 *
308 * Note: On x86_64, fixmaps are ready for use even before this is called.
309 */
310 void __init setup_arch(char **cmdline_p)
311 {
312 unsigned i;
313
314 printk(KERN_INFO "Command line: %s\n", boot_command_line);
315
316 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
317 screen_info = boot_params.screen_info;
318 edid_info = boot_params.edid_info;
319 saved_video_mode = boot_params.hdr.vid_mode;
320 bootloader_type = boot_params.hdr.type_of_loader;
321
322 #ifdef CONFIG_BLK_DEV_RAM
323 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
324 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
325 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
326 #endif
327 #ifdef CONFIG_EFI
328 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
329 "EL64", 4))
330 efi_enabled = 1;
331 #endif
332
333 ARCH_SETUP
334
335 memory_setup();
336 copy_edd();
337
338 if (!boot_params.hdr.root_flags)
339 root_mountflags &= ~MS_RDONLY;
340 init_mm.start_code = (unsigned long) &_text;
341 init_mm.end_code = (unsigned long) &_etext;
342 init_mm.end_data = (unsigned long) &_edata;
343 init_mm.brk = (unsigned long) &_end;
344
345 code_resource.start = virt_to_phys(&_text);
346 code_resource.end = virt_to_phys(&_etext)-1;
347 data_resource.start = virt_to_phys(&_etext);
348 data_resource.end = virt_to_phys(&_edata)-1;
349 bss_resource.start = virt_to_phys(&__bss_start);
350 bss_resource.end = virt_to_phys(&__bss_stop)-1;
351
352 early_identify_cpu(&boot_cpu_data);
353
354 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
355 *cmdline_p = command_line;
356
357 parse_setup_data();
358
359 parse_early_param();
360
361 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
362 if (init_ohci1394_dma_early)
363 init_ohci1394_dma_on_all_controllers();
364 #endif
365
366 finish_e820_parsing();
367
368 /* after parse_early_param, so could debug it */
369 insert_resource(&iomem_resource, &code_resource);
370 insert_resource(&iomem_resource, &data_resource);
371 insert_resource(&iomem_resource, &bss_resource);
372
373 early_gart_iommu_check();
374
375 e820_register_active_regions(0, 0, -1UL);
376 /*
377 * partially used pages are not usable - thus
378 * we are rounding upwards:
379 */
380 end_pfn = e820_end_of_ram();
381 /* update e820 for memory not covered by WB MTRRs */
382 mtrr_bp_init();
383 if (mtrr_trim_uncached_memory(end_pfn)) {
384 e820_register_active_regions(0, 0, -1UL);
385 end_pfn = e820_end_of_ram();
386 }
387
388 num_physpages = end_pfn;
389
390 check_efer();
391
392 max_pfn_mapped = init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
393 if (efi_enabled)
394 efi_init();
395
396 vsmp_init();
397
398 dmi_scan_machine();
399
400 io_delay_init();
401
402 #ifdef CONFIG_KVM_CLOCK
403 kvmclock_init();
404 #endif
405
406 #ifdef CONFIG_SMP
407 /* setup to use the early static init tables during kernel startup */
408 x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
409 x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
410 #ifdef CONFIG_NUMA
411 x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
412 #endif
413 #endif
414
415 #ifdef CONFIG_ACPI
416 /*
417 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
418 * Call this early for SRAT node setup.
419 */
420 acpi_boot_table_init();
421 #endif
422
423 /* How many end-of-memory variables you have, grandma! */
424 max_low_pfn = end_pfn;
425 max_pfn = end_pfn;
426 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
427
428 /* Remove active ranges so rediscovery with NUMA-awareness happens */
429 remove_all_active_ranges();
430
431 #ifdef CONFIG_ACPI_NUMA
432 /*
433 * Parse SRAT to discover nodes.
434 */
435 acpi_numa_init();
436 #endif
437
438 #ifdef CONFIG_NUMA
439 numa_initmem_init(0, end_pfn);
440 #else
441 contig_initmem_init(0, end_pfn);
442 #endif
443
444 dma32_reserve_bootmem();
445
446 #ifdef CONFIG_ACPI_SLEEP
447 /*
448 * Reserve low memory region for sleep support.
449 */
450 acpi_reserve_bootmem();
451 #endif
452
453 if (efi_enabled)
454 efi_reserve_bootmem();
455
456 /*
457 * Find and reserve possible boot-time SMP configuration:
458 */
459 find_smp_config();
460 #ifdef CONFIG_BLK_DEV_INITRD
461 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
462 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
463 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
464 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
465 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
466
467 if (ramdisk_end <= end_of_mem) {
468 /*
469 * don't need to reserve again, already reserved early
470 * in x86_64_start_kernel, and early_res_to_bootmem
471 * convert that to reserved in bootmem
472 */
473 initrd_start = ramdisk_image + PAGE_OFFSET;
474 initrd_end = initrd_start+ramdisk_size;
475 } else {
476 free_bootmem(ramdisk_image, ramdisk_size);
477 printk(KERN_ERR "initrd extends beyond end of memory "
478 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
479 ramdisk_end, end_of_mem);
480 initrd_start = 0;
481 }
482 }
483 #endif
484 reserve_crashkernel();
485
486 reserve_ibft_region();
487
488 paging_init();
489 map_vsyscall();
490
491 early_quirks();
492
493 #ifdef CONFIG_ACPI
494 /*
495 * Read APIC and some other early information from ACPI tables.
496 */
497 acpi_boot_init();
498 #endif
499
500 init_cpu_to_node();
501
502 /*
503 * get boot-time SMP configuration:
504 */
505 if (smp_found_config)
506 get_smp_config();
507 init_apic_mappings();
508 ioapic_init_mappings();
509
510 kvm_guest_init();
511
512 /*
513 * We trust e820 completely. No explicit ROM probing in memory.
514 */
515 e820_reserve_resources();
516 e820_mark_nosave_regions();
517
518 /* request I/O space for devices used on all i[345]86 PCs */
519 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
520 request_resource(&ioport_resource, &standard_io_resources[i]);
521
522 e820_setup_gap();
523
524 #ifdef CONFIG_VT
525 #if defined(CONFIG_VGA_CONSOLE)
526 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
527 conswitchp = &vga_con;
528 #elif defined(CONFIG_DUMMY_CONSOLE)
529 conswitchp = &dummy_con;
530 #endif
531 #endif
532
533 /* do this before identify_cpu for boot cpu */
534 check_enable_amd_mmconf_dmi();
535 }
536
537 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
538 {
539 unsigned int *v;
540
541 if (c->extended_cpuid_level < 0x80000004)
542 return 0;
543
544 v = (unsigned int *) c->x86_model_id;
545 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
546 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
547 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
548 c->x86_model_id[48] = 0;
549 return 1;
550 }
551
552
553 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
554 {
555 unsigned int n, dummy, eax, ebx, ecx, edx;
556
557 n = c->extended_cpuid_level;
558
559 if (n >= 0x80000005) {
560 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
561 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
562 "D cache %dK (%d bytes/line)\n",
563 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
564 c->x86_cache_size = (ecx>>24) + (edx>>24);
565 /* On K8 L1 TLB is inclusive, so don't count it */
566 c->x86_tlbsize = 0;
567 }
568
569 if (n >= 0x80000006) {
570 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
571 ecx = cpuid_ecx(0x80000006);
572 c->x86_cache_size = ecx >> 16;
573 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
574
575 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
576 c->x86_cache_size, ecx & 0xFF);
577 }
578 if (n >= 0x80000008) {
579 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
580 c->x86_virt_bits = (eax >> 8) & 0xff;
581 c->x86_phys_bits = eax & 0xff;
582 }
583 }
584
585 #ifdef CONFIG_NUMA
586 static int __cpuinit nearby_node(int apicid)
587 {
588 int i, node;
589
590 for (i = apicid - 1; i >= 0; i--) {
591 node = apicid_to_node[i];
592 if (node != NUMA_NO_NODE && node_online(node))
593 return node;
594 }
595 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
596 node = apicid_to_node[i];
597 if (node != NUMA_NO_NODE && node_online(node))
598 return node;
599 }
600 return first_node(node_online_map); /* Shouldn't happen */
601 }
602 #endif
603
604 /*
605 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
606 * Assumes number of cores is a power of two.
607 */
608 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
609 {
610 #ifdef CONFIG_SMP
611 unsigned bits;
612 #ifdef CONFIG_NUMA
613 int cpu = smp_processor_id();
614 int node = 0;
615 unsigned apicid = hard_smp_processor_id();
616 #endif
617 bits = c->x86_coreid_bits;
618
619 /* Low order bits define the core id (index of core in socket) */
620 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
621 /* Convert the initial APIC ID into the socket ID */
622 c->phys_proc_id = c->initial_apicid >> bits;
623
624 #ifdef CONFIG_NUMA
625 node = c->phys_proc_id;
626 if (apicid_to_node[apicid] != NUMA_NO_NODE)
627 node = apicid_to_node[apicid];
628 if (!node_online(node)) {
629 /* Two possibilities here:
630 - The CPU is missing memory and no node was created.
631 In that case try picking one from a nearby CPU
632 - The APIC IDs differ from the HyperTransport node IDs
633 which the K8 northbridge parsing fills in.
634 Assume they are all increased by a constant offset,
635 but in the same order as the HT nodeids.
636 If that doesn't result in a usable node fall back to the
637 path for the previous case. */
638
639 int ht_nodeid = c->initial_apicid;
640
641 if (ht_nodeid >= 0 &&
642 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
643 node = apicid_to_node[ht_nodeid];
644 /* Pick a nearby node */
645 if (!node_online(node))
646 node = nearby_node(apicid);
647 }
648 numa_set_node(cpu, node);
649
650 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
651 #endif
652 #endif
653 }
654
655 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
656 {
657 #ifdef CONFIG_SMP
658 unsigned bits, ecx;
659
660 /* Multi core CPU? */
661 if (c->extended_cpuid_level < 0x80000008)
662 return;
663
664 ecx = cpuid_ecx(0x80000008);
665
666 c->x86_max_cores = (ecx & 0xff) + 1;
667
668 /* CPU telling us the core id bits shift? */
669 bits = (ecx >> 12) & 0xF;
670
671 /* Otherwise recompute */
672 if (bits == 0) {
673 while ((1 << bits) < c->x86_max_cores)
674 bits++;
675 }
676
677 c->x86_coreid_bits = bits;
678
679 #endif
680 }
681
682 #define ENABLE_C1E_MASK 0x18000000
683 #define CPUID_PROCESSOR_SIGNATURE 1
684 #define CPUID_XFAM 0x0ff00000
685 #define CPUID_XFAM_K8 0x00000000
686 #define CPUID_XFAM_10H 0x00100000
687 #define CPUID_XFAM_11H 0x00200000
688 #define CPUID_XMOD 0x000f0000
689 #define CPUID_XMOD_REV_F 0x00040000
690
691 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
692 static __cpuinit int amd_apic_timer_broken(void)
693 {
694 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
695
696 switch (eax & CPUID_XFAM) {
697 case CPUID_XFAM_K8:
698 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
699 break;
700 case CPUID_XFAM_10H:
701 case CPUID_XFAM_11H:
702 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
703 if (lo & ENABLE_C1E_MASK)
704 return 1;
705 break;
706 default:
707 /* err on the side of caution */
708 return 1;
709 }
710 return 0;
711 }
712
713 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
714 {
715 early_init_amd_mc(c);
716
717 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
718 if (c->x86_power & (1<<8))
719 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
720 }
721
722 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
723 {
724 unsigned level;
725
726 #ifdef CONFIG_SMP
727 unsigned long value;
728
729 /*
730 * Disable TLB flush filter by setting HWCR.FFDIS on K8
731 * bit 6 of msr C001_0015
732 *
733 * Errata 63 for SH-B3 steppings
734 * Errata 122 for all steppings (F+ have it disabled by default)
735 */
736 if (c->x86 == 15) {
737 rdmsrl(MSR_K8_HWCR, value);
738 value |= 1 << 6;
739 wrmsrl(MSR_K8_HWCR, value);
740 }
741 #endif
742
743 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
744 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
745 clear_cpu_cap(c, 0*32+31);
746
747 /* On C+ stepping K8 rep microcode works well for copy/memset */
748 level = cpuid_eax(1);
749 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
750 level >= 0x0f58))
751 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
752 if (c->x86 == 0x10 || c->x86 == 0x11)
753 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
754
755 /* Enable workaround for FXSAVE leak */
756 if (c->x86 >= 6)
757 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
758
759 level = get_model_name(c);
760 if (!level) {
761 switch (c->x86) {
762 case 15:
763 /* Should distinguish Models here, but this is only
764 a fallback anyways. */
765 strcpy(c->x86_model_id, "Hammer");
766 break;
767 }
768 }
769 display_cacheinfo(c);
770
771 /* Multi core CPU? */
772 if (c->extended_cpuid_level >= 0x80000008)
773 amd_detect_cmp(c);
774
775 if (c->extended_cpuid_level >= 0x80000006 &&
776 (cpuid_edx(0x80000006) & 0xf000))
777 num_cache_leaves = 4;
778 else
779 num_cache_leaves = 3;
780
781 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
782 set_cpu_cap(c, X86_FEATURE_K8);
783
784 /* MFENCE stops RDTSC speculation */
785 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
786
787 if (c->x86 == 0x10)
788 fam10h_check_enable_mmcfg();
789
790 if (amd_apic_timer_broken())
791 disable_apic_timer = 1;
792
793 if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
794 unsigned long long tseg;
795
796 /*
797 * Split up direct mapping around the TSEG SMM area.
798 * Don't do it for gbpages because there seems very little
799 * benefit in doing so.
800 */
801 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
802 (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
803 set_memory_4k((unsigned long)__va(tseg), 1);
804 }
805 }
806
807 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
808 {
809 #ifdef CONFIG_SMP
810 u32 eax, ebx, ecx, edx;
811 int index_msb, core_bits;
812
813 cpuid(1, &eax, &ebx, &ecx, &edx);
814
815
816 if (!cpu_has(c, X86_FEATURE_HT))
817 return;
818 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
819 goto out;
820
821 smp_num_siblings = (ebx & 0xff0000) >> 16;
822
823 if (smp_num_siblings == 1) {
824 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
825 } else if (smp_num_siblings > 1) {
826
827 if (smp_num_siblings > NR_CPUS) {
828 printk(KERN_WARNING "CPU: Unsupported number of "
829 "siblings %d", smp_num_siblings);
830 smp_num_siblings = 1;
831 return;
832 }
833
834 index_msb = get_count_order(smp_num_siblings);
835 c->phys_proc_id = phys_pkg_id(index_msb);
836
837 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
838
839 index_msb = get_count_order(smp_num_siblings);
840
841 core_bits = get_count_order(c->x86_max_cores);
842
843 c->cpu_core_id = phys_pkg_id(index_msb) &
844 ((1 << core_bits) - 1);
845 }
846 out:
847 if ((c->x86_max_cores * smp_num_siblings) > 1) {
848 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
849 c->phys_proc_id);
850 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
851 c->cpu_core_id);
852 }
853
854 #endif
855 }
856
857 /*
858 * find out the number of processor cores on the die
859 */
860 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
861 {
862 unsigned int eax, t;
863
864 if (c->cpuid_level < 4)
865 return 1;
866
867 cpuid_count(4, 0, &eax, &t, &t, &t);
868
869 if (eax & 0x1f)
870 return ((eax >> 26) + 1);
871 else
872 return 1;
873 }
874
875 static void __cpuinit srat_detect_node(void)
876 {
877 #ifdef CONFIG_NUMA
878 unsigned node;
879 int cpu = smp_processor_id();
880 int apicid = hard_smp_processor_id();
881
882 /* Don't do the funky fallback heuristics the AMD version employs
883 for now. */
884 node = apicid_to_node[apicid];
885 if (node == NUMA_NO_NODE || !node_online(node))
886 node = first_node(node_online_map);
887 numa_set_node(cpu, node);
888
889 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
890 #endif
891 }
892
893 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
894 {
895 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
896 (c->x86 == 0x6 && c->x86_model >= 0x0e))
897 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
898 }
899
900 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
901 {
902 /* Cache sizes */
903 unsigned n;
904
905 init_intel_cacheinfo(c);
906 if (c->cpuid_level > 9) {
907 unsigned eax = cpuid_eax(10);
908 /* Check for version and the number of counters */
909 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
910 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
911 }
912
913 if (cpu_has_ds) {
914 unsigned int l1, l2;
915 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
916 if (!(l1 & (1<<11)))
917 set_cpu_cap(c, X86_FEATURE_BTS);
918 if (!(l1 & (1<<12)))
919 set_cpu_cap(c, X86_FEATURE_PEBS);
920 }
921
922
923 if (cpu_has_bts)
924 ds_init_intel(c);
925
926 n = c->extended_cpuid_level;
927 if (n >= 0x80000008) {
928 unsigned eax = cpuid_eax(0x80000008);
929 c->x86_virt_bits = (eax >> 8) & 0xff;
930 c->x86_phys_bits = eax & 0xff;
931 /* CPUID workaround for Intel 0F34 CPU */
932 if (c->x86_vendor == X86_VENDOR_INTEL &&
933 c->x86 == 0xF && c->x86_model == 0x3 &&
934 c->x86_mask == 0x4)
935 c->x86_phys_bits = 36;
936 }
937
938 if (c->x86 == 15)
939 c->x86_cache_alignment = c->x86_clflush_size * 2;
940 if (c->x86 == 6)
941 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
942 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
943 c->x86_max_cores = intel_num_cpu_cores(c);
944
945 srat_detect_node();
946 }
947
948 static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
949 {
950 if (c->x86 == 0x6 && c->x86_model >= 0xf)
951 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
952 }
953
954 static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
955 {
956 /* Cache sizes */
957 unsigned n;
958
959 n = c->extended_cpuid_level;
960 if (n >= 0x80000008) {
961 unsigned eax = cpuid_eax(0x80000008);
962 c->x86_virt_bits = (eax >> 8) & 0xff;
963 c->x86_phys_bits = eax & 0xff;
964 }
965
966 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
967 c->x86_cache_alignment = c->x86_clflush_size * 2;
968 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
969 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
970 }
971 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
972 }
973
974 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
975 {
976 char *v = c->x86_vendor_id;
977
978 if (!strcmp(v, "AuthenticAMD"))
979 c->x86_vendor = X86_VENDOR_AMD;
980 else if (!strcmp(v, "GenuineIntel"))
981 c->x86_vendor = X86_VENDOR_INTEL;
982 else if (!strcmp(v, "CentaurHauls"))
983 c->x86_vendor = X86_VENDOR_CENTAUR;
984 else
985 c->x86_vendor = X86_VENDOR_UNKNOWN;
986 }
987
988 /* Do some early cpuid on the boot CPU to get some parameter that are
989 needed before check_bugs. Everything advanced is in identify_cpu
990 below. */
991 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
992 {
993 u32 tfms, xlvl;
994
995 c->loops_per_jiffy = loops_per_jiffy;
996 c->x86_cache_size = -1;
997 c->x86_vendor = X86_VENDOR_UNKNOWN;
998 c->x86_model = c->x86_mask = 0; /* So far unknown... */
999 c->x86_vendor_id[0] = '\0'; /* Unset */
1000 c->x86_model_id[0] = '\0'; /* Unset */
1001 c->x86_clflush_size = 64;
1002 c->x86_cache_alignment = c->x86_clflush_size;
1003 c->x86_max_cores = 1;
1004 c->x86_coreid_bits = 0;
1005 c->extended_cpuid_level = 0;
1006 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1007
1008 /* Get vendor name */
1009 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
1010 (unsigned int *)&c->x86_vendor_id[0],
1011 (unsigned int *)&c->x86_vendor_id[8],
1012 (unsigned int *)&c->x86_vendor_id[4]);
1013
1014 get_cpu_vendor(c);
1015
1016 /* Initialize the standard set of capabilities */
1017 /* Note that the vendor-specific code below might override */
1018
1019 /* Intel-defined flags: level 0x00000001 */
1020 if (c->cpuid_level >= 0x00000001) {
1021 __u32 misc;
1022 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
1023 &c->x86_capability[0]);
1024 c->x86 = (tfms >> 8) & 0xf;
1025 c->x86_model = (tfms >> 4) & 0xf;
1026 c->x86_mask = tfms & 0xf;
1027 if (c->x86 == 0xf)
1028 c->x86 += (tfms >> 20) & 0xff;
1029 if (c->x86 >= 0x6)
1030 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1031 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
1032 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1033 } else {
1034 /* Have CPUID level 0 only - unheard of */
1035 c->x86 = 4;
1036 }
1037
1038 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
1039 #ifdef CONFIG_SMP
1040 c->phys_proc_id = c->initial_apicid;
1041 #endif
1042 /* AMD-defined flags: level 0x80000001 */
1043 xlvl = cpuid_eax(0x80000000);
1044 c->extended_cpuid_level = xlvl;
1045 if ((xlvl & 0xffff0000) == 0x80000000) {
1046 if (xlvl >= 0x80000001) {
1047 c->x86_capability[1] = cpuid_edx(0x80000001);
1048 c->x86_capability[6] = cpuid_ecx(0x80000001);
1049 }
1050 if (xlvl >= 0x80000004)
1051 get_model_name(c); /* Default name */
1052 }
1053
1054 /* Transmeta-defined flags: level 0x80860001 */
1055 xlvl = cpuid_eax(0x80860000);
1056 if ((xlvl & 0xffff0000) == 0x80860000) {
1057 /* Don't set x86_cpuid_level here for now to not confuse. */
1058 if (xlvl >= 0x80860001)
1059 c->x86_capability[2] = cpuid_edx(0x80860001);
1060 }
1061
1062 c->extended_cpuid_level = cpuid_eax(0x80000000);
1063 if (c->extended_cpuid_level >= 0x80000007)
1064 c->x86_power = cpuid_edx(0x80000007);
1065
1066
1067 clear_cpu_cap(c, X86_FEATURE_PAT);
1068
1069 switch (c->x86_vendor) {
1070 case X86_VENDOR_AMD:
1071 early_init_amd(c);
1072 if (c->x86 >= 0xf && c->x86 <= 0x11)
1073 set_cpu_cap(c, X86_FEATURE_PAT);
1074 break;
1075 case X86_VENDOR_INTEL:
1076 early_init_intel(c);
1077 if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
1078 set_cpu_cap(c, X86_FEATURE_PAT);
1079 break;
1080 case X86_VENDOR_CENTAUR:
1081 early_init_centaur(c);
1082 break;
1083 }
1084
1085 }
1086
1087 /*
1088 * This does the hard work of actually picking apart the CPU stuff...
1089 */
1090 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1091 {
1092 int i;
1093
1094 early_identify_cpu(c);
1095
1096 init_scattered_cpuid_features(c);
1097
1098 c->apicid = phys_pkg_id(0);
1099
1100 /*
1101 * Vendor-specific initialization. In this section we
1102 * canonicalize the feature flags, meaning if there are
1103 * features a certain CPU supports which CPUID doesn't
1104 * tell us, CPUID claiming incorrect flags, or other bugs,
1105 * we handle them here.
1106 *
1107 * At the end of this section, c->x86_capability better
1108 * indicate the features this CPU genuinely supports!
1109 */
1110 switch (c->x86_vendor) {
1111 case X86_VENDOR_AMD:
1112 init_amd(c);
1113 break;
1114
1115 case X86_VENDOR_INTEL:
1116 init_intel(c);
1117 break;
1118
1119 case X86_VENDOR_CENTAUR:
1120 init_centaur(c);
1121 break;
1122
1123 case X86_VENDOR_UNKNOWN:
1124 default:
1125 display_cacheinfo(c);
1126 break;
1127 }
1128
1129 detect_ht(c);
1130
1131 /*
1132 * On SMP, boot_cpu_data holds the common feature set between
1133 * all CPUs; so make sure that we indicate which features are
1134 * common between the CPUs. The first time this routine gets
1135 * executed, c == &boot_cpu_data.
1136 */
1137 if (c != &boot_cpu_data) {
1138 /* AND the already accumulated flags with these */
1139 for (i = 0; i < NCAPINTS; i++)
1140 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1141 }
1142
1143 /* Clear all flags overriden by options */
1144 for (i = 0; i < NCAPINTS; i++)
1145 c->x86_capability[i] &= ~cleared_cpu_caps[i];
1146
1147 #ifdef CONFIG_X86_MCE
1148 mcheck_init(c);
1149 #endif
1150 select_idle_routine(c);
1151
1152 #ifdef CONFIG_NUMA
1153 numa_add_cpu(smp_processor_id());
1154 #endif
1155
1156 }
1157
1158 void __cpuinit identify_boot_cpu(void)
1159 {
1160 identify_cpu(&boot_cpu_data);
1161 }
1162
1163 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1164 {
1165 BUG_ON(c == &boot_cpu_data);
1166 identify_cpu(c);
1167 mtrr_ap_init();
1168 }
1169
1170 static __init int setup_noclflush(char *arg)
1171 {
1172 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1173 return 1;
1174 }
1175 __setup("noclflush", setup_noclflush);
1176
1177 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1178 {
1179 if (c->x86_model_id[0])
1180 printk(KERN_CONT "%s", c->x86_model_id);
1181
1182 if (c->x86_mask || c->cpuid_level >= 0)
1183 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1184 else
1185 printk(KERN_CONT "\n");
1186 }
1187
1188 static __init int setup_disablecpuid(char *arg)
1189 {
1190 int bit;
1191 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1192 setup_clear_cpu_cap(bit);
1193 else
1194 return 0;
1195 return 1;
1196 }
1197 __setup("clearcpuid=", setup_disablecpuid);
Linux kernel - Deliverables
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