2 * Copyright (C) 1995 Linus Torvalds
6 * This file handles the architecture-dependent parts of initialization
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/screen_info.h>
19 #include <linux/ioport.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/initrd.h>
23 #include <linux/highmem.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
26 #include <asm/processor.h>
27 #include <linux/console.h>
28 #include <linux/seq_file.h>
29 #include <linux/crash_dump.h>
30 #include <linux/root_dev.h>
31 #include <linux/pci.h>
32 #include <linux/efi.h>
33 #include <linux/acpi.h>
34 #include <linux/kallsyms.h>
35 #include <linux/edd.h>
36 #include <linux/iscsi_ibft.h>
37 #include <linux/mmzone.h>
38 #include <linux/kexec.h>
39 #include <linux/cpufreq.h>
40 #include <linux/dmi.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/ctype.h>
43 #include <linux/uaccess.h>
44 #include <linux/init_ohci1394_dma.h>
47 #include <asm/uaccess.h>
48 #include <asm/system.h>
49 #include <asm/vsyscall.h>
54 #include <video/edid.h>
58 #include <asm/mpspec.h>
59 #include <asm/mmu_context.h>
60 #include <asm/proto.h>
61 #include <asm/setup.h>
63 #include <asm/sections.h>
65 #include <asm/cacheflush.h>
68 #include <asm/topology.h>
69 #include <asm/trampoline.h>
71 #include <mach_apic.h>
72 #ifdef CONFIG_PARAVIRT
73 #include <asm/paravirt.h>
82 struct cpuinfo_x86 boot_cpu_data __read_mostly
;
83 EXPORT_SYMBOL(boot_cpu_data
);
85 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
87 unsigned long mmu_cr4_features
;
89 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
92 unsigned long saved_video_mode
;
94 int force_mwait __cpuinitdata
;
100 char dmi_alloc_data
[DMI_MAX_DATA
];
105 struct screen_info screen_info
;
106 EXPORT_SYMBOL(screen_info
);
107 struct sys_desc_table_struct
{
108 unsigned short length
;
109 unsigned char table
[0];
112 struct edid_info edid_info
;
113 EXPORT_SYMBOL_GPL(edid_info
);
115 extern int root_mountflags
;
117 char __initdata command_line
[COMMAND_LINE_SIZE
];
119 static struct resource standard_io_resources
[] = {
120 { .name
= "dma1", .start
= 0x00, .end
= 0x1f,
121 .flags
= IORESOURCE_BUSY
| IORESOURCE_IO
},
122 { .name
= "pic1", .start
= 0x20, .end
= 0x21,
123 .flags
= IORESOURCE_BUSY
| IORESOURCE_IO
},
124 { .name
= "timer0", .start
= 0x40, .end
= 0x43,
125 .flags
= IORESOURCE_BUSY
| IORESOURCE_IO
},
126 { .name
= "timer1", .start
= 0x50, .end
= 0x53,
127 .flags
= IORESOURCE_BUSY
| IORESOURCE_IO
},
128 { .name
= "keyboard", .start
= 0x60, .end
= 0x6f,
129 .flags
= IORESOURCE_BUSY
| IORESOURCE_IO
},
130 { .name
= "dma page reg", .start
= 0x80, .end
= 0x8f,
131 .flags
= IORESOURCE_BUSY
| IORESOURCE_IO
},
132 { .name
= "pic2", .start
= 0xa0, .end
= 0xa1,
133 .flags
= IORESOURCE_BUSY
| IORESOURCE_IO
},
134 { .name
= "dma2", .start
= 0xc0, .end
= 0xdf,
135 .flags
= IORESOURCE_BUSY
| IORESOURCE_IO
},
136 { .name
= "fpu", .start
= 0xf0, .end
= 0xff,
137 .flags
= IORESOURCE_BUSY
| IORESOURCE_IO
}
140 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
142 static struct resource data_resource
= {
143 .name
= "Kernel data",
146 .flags
= IORESOURCE_RAM
,
148 static struct resource code_resource
= {
149 .name
= "Kernel code",
152 .flags
= IORESOURCE_RAM
,
154 static struct resource bss_resource
= {
155 .name
= "Kernel bss",
158 .flags
= IORESOURCE_RAM
,
161 static void __cpuinit
early_identify_cpu(struct cpuinfo_x86
*c
);
163 #ifdef CONFIG_PROC_VMCORE
164 /* elfcorehdr= specifies the location of elf core header
165 * stored by the crashed kernel. This option will be passed
166 * by kexec loader to the capture kernel.
168 static int __init
setup_elfcorehdr(char *arg
)
173 elfcorehdr_addr
= memparse(arg
, &end
);
174 return end
> arg
? 0 : -EINVAL
;
176 early_param("elfcorehdr", setup_elfcorehdr
);
181 contig_initmem_init(unsigned long start_pfn
, unsigned long end_pfn
)
183 unsigned long bootmap_size
, bootmap
;
185 bootmap_size
= bootmem_bootmap_pages(end_pfn
)<<PAGE_SHIFT
;
186 bootmap
= find_e820_area(0, end_pfn
<<PAGE_SHIFT
, bootmap_size
,
189 panic("Cannot find bootmem map of size %ld\n", bootmap_size
);
190 bootmap_size
= init_bootmem(bootmap
>> PAGE_SHIFT
, end_pfn
);
191 e820_register_active_regions(0, start_pfn
, end_pfn
);
192 free_bootmem_with_active_regions(0, end_pfn
);
193 reserve_bootmem(bootmap
, bootmap_size
, BOOTMEM_DEFAULT
);
197 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
199 #ifdef CONFIG_EDD_MODULE
203 * copy_edd() - Copy the BIOS EDD information
204 * from boot_params into a safe place.
207 static inline void copy_edd(void)
209 memcpy(edd
.mbr_signature
, boot_params
.edd_mbr_sig_buffer
,
210 sizeof(edd
.mbr_signature
));
211 memcpy(edd
.edd_info
, boot_params
.eddbuf
, sizeof(edd
.edd_info
));
212 edd
.mbr_signature_nr
= boot_params
.edd_mbr_sig_buf_entries
;
213 edd
.edd_info_nr
= boot_params
.eddbuf_entries
;
216 static inline void copy_edd(void)
222 static void __init
reserve_crashkernel(void)
224 unsigned long long total_mem
;
225 unsigned long long crash_size
, crash_base
;
228 total_mem
= ((unsigned long long)max_low_pfn
- min_low_pfn
) << PAGE_SHIFT
;
230 ret
= parse_crashkernel(boot_command_line
, total_mem
,
231 &crash_size
, &crash_base
);
232 if (ret
== 0 && crash_size
) {
233 if (crash_base
<= 0) {
234 printk(KERN_INFO
"crashkernel reservation failed - "
235 "you have to specify a base address\n");
239 if (reserve_bootmem(crash_base
, crash_size
,
240 BOOTMEM_EXCLUSIVE
) < 0) {
241 printk(KERN_INFO
"crashkernel reservation failed - "
242 "memory is in use\n");
246 printk(KERN_INFO
"Reserving %ldMB of memory at %ldMB "
247 "for crashkernel (System RAM: %ldMB)\n",
248 (unsigned long)(crash_size
>> 20),
249 (unsigned long)(crash_base
>> 20),
250 (unsigned long)(total_mem
>> 20));
251 crashk_res
.start
= crash_base
;
252 crashk_res
.end
= crash_base
+ crash_size
- 1;
253 insert_resource(&iomem_resource
, &crashk_res
);
257 static inline void __init
reserve_crashkernel(void)
261 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
262 void __attribute__((weak
)) __init
memory_setup(void)
264 machine_specific_memory_setup();
267 static void __init
parse_setup_data(void)
269 struct setup_data
*data
;
270 unsigned long pa_data
;
272 if (boot_params
.hdr
.version
< 0x0209)
274 pa_data
= boot_params
.hdr
.setup_data
;
276 data
= early_ioremap(pa_data
, PAGE_SIZE
);
277 switch (data
->type
) {
281 #ifndef CONFIG_DEBUG_BOOT_PARAMS
282 free_early(pa_data
, pa_data
+sizeof(*data
)+data
->len
);
284 pa_data
= data
->next
;
285 early_iounmap(data
, PAGE_SIZE
);
290 * setup_arch - architecture-specific boot-time initializations
292 * Note: On x86_64, fixmaps are ready for use even before this is called.
294 void __init
setup_arch(char **cmdline_p
)
298 printk(KERN_INFO
"Command line: %s\n", boot_command_line
);
300 ROOT_DEV
= old_decode_dev(boot_params
.hdr
.root_dev
);
301 screen_info
= boot_params
.screen_info
;
302 edid_info
= boot_params
.edid_info
;
303 saved_video_mode
= boot_params
.hdr
.vid_mode
;
304 bootloader_type
= boot_params
.hdr
.type_of_loader
;
306 #ifdef CONFIG_BLK_DEV_RAM
307 rd_image_start
= boot_params
.hdr
.ram_size
& RAMDISK_IMAGE_START_MASK
;
308 rd_prompt
= ((boot_params
.hdr
.ram_size
& RAMDISK_PROMPT_FLAG
) != 0);
309 rd_doload
= ((boot_params
.hdr
.ram_size
& RAMDISK_LOAD_FLAG
) != 0);
312 if (!strncmp((char *)&boot_params
.efi_info
.efi_loader_signature
,
322 if (!boot_params
.hdr
.root_flags
)
323 root_mountflags
&= ~MS_RDONLY
;
324 init_mm
.start_code
= (unsigned long) &_text
;
325 init_mm
.end_code
= (unsigned long) &_etext
;
326 init_mm
.end_data
= (unsigned long) &_edata
;
327 init_mm
.brk
= (unsigned long) &_end
;
329 code_resource
.start
= virt_to_phys(&_text
);
330 code_resource
.end
= virt_to_phys(&_etext
)-1;
331 data_resource
.start
= virt_to_phys(&_etext
);
332 data_resource
.end
= virt_to_phys(&_edata
)-1;
333 bss_resource
.start
= virt_to_phys(&__bss_start
);
334 bss_resource
.end
= virt_to_phys(&__bss_stop
)-1;
336 early_identify_cpu(&boot_cpu_data
);
338 strlcpy(command_line
, boot_command_line
, COMMAND_LINE_SIZE
);
339 *cmdline_p
= command_line
;
345 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
346 if (init_ohci1394_dma_early
)
347 init_ohci1394_dma_on_all_controllers();
350 finish_e820_parsing();
352 /* after parse_early_param, so could debug it */
353 insert_resource(&iomem_resource
, &code_resource
);
354 insert_resource(&iomem_resource
, &data_resource
);
355 insert_resource(&iomem_resource
, &bss_resource
);
357 early_gart_iommu_check();
359 e820_register_active_regions(0, 0, -1UL);
361 * partially used pages are not usable - thus
362 * we are rounding upwards:
364 end_pfn
= e820_end_of_ram();
365 /* update e820 for memory not covered by WB MTRRs */
367 if (mtrr_trim_uncached_memory(end_pfn
)) {
368 e820_register_active_regions(0, 0, -1UL);
369 end_pfn
= e820_end_of_ram();
372 num_physpages
= end_pfn
;
376 max_pfn_mapped
= init_memory_mapping(0, (max_pfn_mapped
<< PAGE_SHIFT
));
387 /* setup to use the early static init tables during kernel startup */
388 x86_cpu_to_apicid_early_ptr
= (void *)x86_cpu_to_apicid_init
;
389 x86_bios_cpu_apicid_early_ptr
= (void *)x86_bios_cpu_apicid_init
;
391 x86_cpu_to_node_map_early_ptr
= (void *)x86_cpu_to_node_map_init
;
397 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
398 * Call this early for SRAT node setup.
400 acpi_boot_table_init();
403 /* How many end-of-memory variables you have, grandma! */
404 max_low_pfn
= end_pfn
;
406 high_memory
= (void *)__va(end_pfn
* PAGE_SIZE
- 1) + 1;
408 /* Remove active ranges so rediscovery with NUMA-awareness happens */
409 remove_all_active_ranges();
411 #ifdef CONFIG_ACPI_NUMA
413 * Parse SRAT to discover nodes.
419 numa_initmem_init(0, end_pfn
);
421 contig_initmem_init(0, end_pfn
);
424 early_res_to_bootmem();
426 dma32_reserve_bootmem();
428 #ifdef CONFIG_ACPI_SLEEP
430 * Reserve low memory region for sleep support.
432 acpi_reserve_bootmem();
436 efi_reserve_bootmem();
439 * Find and reserve possible boot-time SMP configuration:
442 #ifdef CONFIG_BLK_DEV_INITRD
443 if (boot_params
.hdr
.type_of_loader
&& boot_params
.hdr
.ramdisk_image
) {
444 unsigned long ramdisk_image
= boot_params
.hdr
.ramdisk_image
;
445 unsigned long ramdisk_size
= boot_params
.hdr
.ramdisk_size
;
446 unsigned long ramdisk_end
= ramdisk_image
+ ramdisk_size
;
447 unsigned long end_of_mem
= end_pfn
<< PAGE_SHIFT
;
449 if (ramdisk_end
<= end_of_mem
) {
451 * don't need to reserve again, already reserved early
452 * in x86_64_start_kernel, and early_res_to_bootmem
453 * convert that to reserved in bootmem
455 initrd_start
= ramdisk_image
+ PAGE_OFFSET
;
456 initrd_end
= initrd_start
+ramdisk_size
;
458 free_bootmem(ramdisk_image
, ramdisk_size
);
459 printk(KERN_ERR
"initrd extends beyond end of memory "
460 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
461 ramdisk_end
, end_of_mem
);
466 reserve_crashkernel();
468 reserve_ibft_region();
477 * Read APIC and some other early information from ACPI tables.
485 * get boot-time SMP configuration:
487 if (smp_found_config
)
489 init_apic_mappings();
490 ioapic_init_mappings();
493 * We trust e820 completely. No explicit ROM probing in memory.
495 e820_reserve_resources();
496 e820_mark_nosave_regions();
498 /* request I/O space for devices used on all i[345]86 PCs */
499 for (i
= 0; i
< ARRAY_SIZE(standard_io_resources
); i
++)
500 request_resource(&ioport_resource
, &standard_io_resources
[i
]);
505 #if defined(CONFIG_VGA_CONSOLE)
506 if (!efi_enabled
|| (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY
))
507 conswitchp
= &vga_con
;
508 #elif defined(CONFIG_DUMMY_CONSOLE)
509 conswitchp
= &dummy_con
;
514 static int __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
518 if (c
->extended_cpuid_level
< 0x80000004)
521 v
= (unsigned int *) c
->x86_model_id
;
522 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
523 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
524 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
525 c
->x86_model_id
[48] = 0;
530 static void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
532 unsigned int n
, dummy
, eax
, ebx
, ecx
, edx
;
534 n
= c
->extended_cpuid_level
;
536 if (n
>= 0x80000005) {
537 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
538 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), "
539 "D cache %dK (%d bytes/line)\n",
540 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
541 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
542 /* On K8 L1 TLB is inclusive, so don't count it */
546 if (n
>= 0x80000006) {
547 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
548 ecx
= cpuid_ecx(0x80000006);
549 c
->x86_cache_size
= ecx
>> 16;
550 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
552 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
553 c
->x86_cache_size
, ecx
& 0xFF);
555 if (n
>= 0x80000008) {
556 cpuid(0x80000008, &eax
, &dummy
, &dummy
, &dummy
);
557 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
558 c
->x86_phys_bits
= eax
& 0xff;
563 static int __cpuinit
nearby_node(int apicid
)
567 for (i
= apicid
- 1; i
>= 0; i
--) {
568 node
= apicid_to_node
[i
];
569 if (node
!= NUMA_NO_NODE
&& node_online(node
))
572 for (i
= apicid
+ 1; i
< MAX_LOCAL_APIC
; i
++) {
573 node
= apicid_to_node
[i
];
574 if (node
!= NUMA_NO_NODE
&& node_online(node
))
577 return first_node(node_online_map
); /* Shouldn't happen */
582 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
583 * Assumes number of cores is a power of two.
585 static void __cpuinit
amd_detect_cmp(struct cpuinfo_x86
*c
)
590 int cpu
= smp_processor_id();
592 unsigned apicid
= hard_smp_processor_id();
594 bits
= c
->x86_coreid_bits
;
596 /* Low order bits define the core id (index of core in socket) */
597 c
->cpu_core_id
= c
->initial_apicid
& ((1 << bits
)-1);
598 /* Convert the initial APIC ID into the socket ID */
599 c
->phys_proc_id
= c
->initial_apicid
>> bits
;
602 node
= c
->phys_proc_id
;
603 if (apicid_to_node
[apicid
] != NUMA_NO_NODE
)
604 node
= apicid_to_node
[apicid
];
605 if (!node_online(node
)) {
606 /* Two possibilities here:
607 - The CPU is missing memory and no node was created.
608 In that case try picking one from a nearby CPU
609 - The APIC IDs differ from the HyperTransport node IDs
610 which the K8 northbridge parsing fills in.
611 Assume they are all increased by a constant offset,
612 but in the same order as the HT nodeids.
613 If that doesn't result in a usable node fall back to the
614 path for the previous case. */
616 int ht_nodeid
= c
->initial_apicid
;
618 if (ht_nodeid
>= 0 &&
619 apicid_to_node
[ht_nodeid
] != NUMA_NO_NODE
)
620 node
= apicid_to_node
[ht_nodeid
];
621 /* Pick a nearby node */
622 if (!node_online(node
))
623 node
= nearby_node(apicid
);
625 numa_set_node(cpu
, node
);
627 printk(KERN_INFO
"CPU %d/%x -> Node %d\n", cpu
, apicid
, node
);
632 static void __cpuinit
early_init_amd_mc(struct cpuinfo_x86
*c
)
637 /* Multi core CPU? */
638 if (c
->extended_cpuid_level
< 0x80000008)
641 ecx
= cpuid_ecx(0x80000008);
643 c
->x86_max_cores
= (ecx
& 0xff) + 1;
645 /* CPU telling us the core id bits shift? */
646 bits
= (ecx
>> 12) & 0xF;
648 /* Otherwise recompute */
650 while ((1 << bits
) < c
->x86_max_cores
)
654 c
->x86_coreid_bits
= bits
;
659 #define ENABLE_C1E_MASK 0x18000000
660 #define CPUID_PROCESSOR_SIGNATURE 1
661 #define CPUID_XFAM 0x0ff00000
662 #define CPUID_XFAM_K8 0x00000000
663 #define CPUID_XFAM_10H 0x00100000
664 #define CPUID_XFAM_11H 0x00200000
665 #define CPUID_XMOD 0x000f0000
666 #define CPUID_XMOD_REV_F 0x00040000
668 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
669 static __cpuinit
int amd_apic_timer_broken(void)
671 u32 lo
, hi
, eax
= cpuid_eax(CPUID_PROCESSOR_SIGNATURE
);
673 switch (eax
& CPUID_XFAM
) {
675 if ((eax
& CPUID_XMOD
) < CPUID_XMOD_REV_F
)
679 rdmsr(MSR_K8_ENABLE_C1E
, lo
, hi
);
680 if (lo
& ENABLE_C1E_MASK
)
684 /* err on the side of caution */
690 static void __cpuinit
early_init_amd(struct cpuinfo_x86
*c
)
692 early_init_amd_mc(c
);
694 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
695 if (c
->x86_power
& (1<<8))
696 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
699 static void __cpuinit
init_amd(struct cpuinfo_x86
*c
)
707 * Disable TLB flush filter by setting HWCR.FFDIS on K8
708 * bit 6 of msr C001_0015
710 * Errata 63 for SH-B3 steppings
711 * Errata 122 for all steppings (F+ have it disabled by default)
714 rdmsrl(MSR_K8_HWCR
, value
);
716 wrmsrl(MSR_K8_HWCR
, value
);
720 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
721 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
722 clear_cpu_cap(c
, 0*32+31);
724 /* On C+ stepping K8 rep microcode works well for copy/memset */
725 level
= cpuid_eax(1);
726 if (c
->x86
== 15 && ((level
>= 0x0f48 && level
< 0x0f50) ||
728 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
729 if (c
->x86
== 0x10 || c
->x86
== 0x11)
730 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
732 /* Enable workaround for FXSAVE leak */
734 set_cpu_cap(c
, X86_FEATURE_FXSAVE_LEAK
);
736 level
= get_model_name(c
);
740 /* Should distinguish Models here, but this is only
741 a fallback anyways. */
742 strcpy(c
->x86_model_id
, "Hammer");
746 display_cacheinfo(c
);
748 /* Multi core CPU? */
749 if (c
->extended_cpuid_level
>= 0x80000008)
752 if (c
->extended_cpuid_level
>= 0x80000006 &&
753 (cpuid_edx(0x80000006) & 0xf000))
754 num_cache_leaves
= 4;
756 num_cache_leaves
= 3;
758 if (c
->x86
== 0xf || c
->x86
== 0x10 || c
->x86
== 0x11)
759 set_cpu_cap(c
, X86_FEATURE_K8
);
761 /* MFENCE stops RDTSC speculation */
762 set_cpu_cap(c
, X86_FEATURE_MFENCE_RDTSC
);
764 if (amd_apic_timer_broken())
765 disable_apic_timer
= 1;
767 if (c
== &boot_cpu_data
&& c
->x86
>= 0xf && c
->x86
<= 0x11) {
768 unsigned long long tseg
;
771 * Split up direct mapping around the TSEG SMM area.
772 * Don't do it for gbpages because there seems very little
773 * benefit in doing so.
775 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR
, &tseg
) &&
776 (tseg
>> PMD_SHIFT
) < (max_pfn_mapped
>> (PMD_SHIFT
-PAGE_SHIFT
)))
777 set_memory_4k((unsigned long)__va(tseg
), 1);
781 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
784 u32 eax
, ebx
, ecx
, edx
;
785 int index_msb
, core_bits
;
787 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
790 if (!cpu_has(c
, X86_FEATURE_HT
))
792 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
795 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
797 if (smp_num_siblings
== 1) {
798 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
799 } else if (smp_num_siblings
> 1) {
801 if (smp_num_siblings
> NR_CPUS
) {
802 printk(KERN_WARNING
"CPU: Unsupported number of "
803 "siblings %d", smp_num_siblings
);
804 smp_num_siblings
= 1;
808 index_msb
= get_count_order(smp_num_siblings
);
809 c
->phys_proc_id
= phys_pkg_id(index_msb
);
811 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
813 index_msb
= get_count_order(smp_num_siblings
);
815 core_bits
= get_count_order(c
->x86_max_cores
);
817 c
->cpu_core_id
= phys_pkg_id(index_msb
) &
818 ((1 << core_bits
) - 1);
821 if ((c
->x86_max_cores
* smp_num_siblings
) > 1) {
822 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
824 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
832 * find out the number of processor cores on the die
834 static int __cpuinit
intel_num_cpu_cores(struct cpuinfo_x86
*c
)
838 if (c
->cpuid_level
< 4)
841 cpuid_count(4, 0, &eax
, &t
, &t
, &t
);
844 return ((eax
>> 26) + 1);
849 static void __cpuinit
srat_detect_node(void)
853 int cpu
= smp_processor_id();
854 int apicid
= hard_smp_processor_id();
856 /* Don't do the funky fallback heuristics the AMD version employs
858 node
= apicid_to_node
[apicid
];
859 if (node
== NUMA_NO_NODE
|| !node_online(node
))
860 node
= first_node(node_online_map
);
861 numa_set_node(cpu
, node
);
863 printk(KERN_INFO
"CPU %d/%x -> Node %d\n", cpu
, apicid
, node
);
867 static void __cpuinit
early_init_intel(struct cpuinfo_x86
*c
)
869 if ((c
->x86
== 0xf && c
->x86_model
>= 0x03) ||
870 (c
->x86
== 0x6 && c
->x86_model
>= 0x0e))
871 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
874 static void __cpuinit
init_intel(struct cpuinfo_x86
*c
)
879 init_intel_cacheinfo(c
);
880 if (c
->cpuid_level
> 9) {
881 unsigned eax
= cpuid_eax(10);
882 /* Check for version and the number of counters */
883 if ((eax
& 0xff) && (((eax
>>8) & 0xff) > 1))
884 set_cpu_cap(c
, X86_FEATURE_ARCH_PERFMON
);
889 rdmsr(MSR_IA32_MISC_ENABLE
, l1
, l2
);
891 set_cpu_cap(c
, X86_FEATURE_BTS
);
893 set_cpu_cap(c
, X86_FEATURE_PEBS
);
900 n
= c
->extended_cpuid_level
;
901 if (n
>= 0x80000008) {
902 unsigned eax
= cpuid_eax(0x80000008);
903 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
904 c
->x86_phys_bits
= eax
& 0xff;
905 /* CPUID workaround for Intel 0F34 CPU */
906 if (c
->x86_vendor
== X86_VENDOR_INTEL
&&
907 c
->x86
== 0xF && c
->x86_model
== 0x3 &&
909 c
->x86_phys_bits
= 36;
913 c
->x86_cache_alignment
= c
->x86_clflush_size
* 2;
915 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
916 set_cpu_cap(c
, X86_FEATURE_LFENCE_RDTSC
);
917 c
->x86_max_cores
= intel_num_cpu_cores(c
);
922 static void __cpuinit
early_init_centaur(struct cpuinfo_x86
*c
)
924 if (c
->x86
== 0x6 && c
->x86_model
>= 0xf)
925 set_bit(X86_FEATURE_CONSTANT_TSC
, &c
->x86_capability
);
928 static void __cpuinit
init_centaur(struct cpuinfo_x86
*c
)
933 n
= c
->extended_cpuid_level
;
934 if (n
>= 0x80000008) {
935 unsigned eax
= cpuid_eax(0x80000008);
936 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
937 c
->x86_phys_bits
= eax
& 0xff;
940 if (c
->x86
== 0x6 && c
->x86_model
>= 0xf) {
941 c
->x86_cache_alignment
= c
->x86_clflush_size
* 2;
942 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
943 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
945 set_cpu_cap(c
, X86_FEATURE_LFENCE_RDTSC
);
948 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
)
950 char *v
= c
->x86_vendor_id
;
952 if (!strcmp(v
, "AuthenticAMD"))
953 c
->x86_vendor
= X86_VENDOR_AMD
;
954 else if (!strcmp(v
, "GenuineIntel"))
955 c
->x86_vendor
= X86_VENDOR_INTEL
;
956 else if (!strcmp(v
, "CentaurHauls"))
957 c
->x86_vendor
= X86_VENDOR_CENTAUR
;
959 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
962 /* Do some early cpuid on the boot CPU to get some parameter that are
963 needed before check_bugs. Everything advanced is in identify_cpu
965 static void __cpuinit
early_identify_cpu(struct cpuinfo_x86
*c
)
969 c
->loops_per_jiffy
= loops_per_jiffy
;
970 c
->x86_cache_size
= -1;
971 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
972 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
973 c
->x86_vendor_id
[0] = '\0'; /* Unset */
974 c
->x86_model_id
[0] = '\0'; /* Unset */
975 c
->x86_clflush_size
= 64;
976 c
->x86_cache_alignment
= c
->x86_clflush_size
;
977 c
->x86_max_cores
= 1;
978 c
->x86_coreid_bits
= 0;
979 c
->extended_cpuid_level
= 0;
980 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
982 /* Get vendor name */
983 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
984 (unsigned int *)&c
->x86_vendor_id
[0],
985 (unsigned int *)&c
->x86_vendor_id
[8],
986 (unsigned int *)&c
->x86_vendor_id
[4]);
990 /* Initialize the standard set of capabilities */
991 /* Note that the vendor-specific code below might override */
993 /* Intel-defined flags: level 0x00000001 */
994 if (c
->cpuid_level
>= 0x00000001) {
996 cpuid(0x00000001, &tfms
, &misc
, &c
->x86_capability
[4],
997 &c
->x86_capability
[0]);
998 c
->x86
= (tfms
>> 8) & 0xf;
999 c
->x86_model
= (tfms
>> 4) & 0xf;
1000 c
->x86_mask
= tfms
& 0xf;
1002 c
->x86
+= (tfms
>> 20) & 0xff;
1004 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
1005 if (test_cpu_cap(c
, X86_FEATURE_CLFLSH
))
1006 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
1008 /* Have CPUID level 0 only - unheard of */
1012 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xff;
1014 c
->phys_proc_id
= c
->initial_apicid
;
1016 /* AMD-defined flags: level 0x80000001 */
1017 xlvl
= cpuid_eax(0x80000000);
1018 c
->extended_cpuid_level
= xlvl
;
1019 if ((xlvl
& 0xffff0000) == 0x80000000) {
1020 if (xlvl
>= 0x80000001) {
1021 c
->x86_capability
[1] = cpuid_edx(0x80000001);
1022 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
1024 if (xlvl
>= 0x80000004)
1025 get_model_name(c
); /* Default name */
1028 /* Transmeta-defined flags: level 0x80860001 */
1029 xlvl
= cpuid_eax(0x80860000);
1030 if ((xlvl
& 0xffff0000) == 0x80860000) {
1031 /* Don't set x86_cpuid_level here for now to not confuse. */
1032 if (xlvl
>= 0x80860001)
1033 c
->x86_capability
[2] = cpuid_edx(0x80860001);
1036 c
->extended_cpuid_level
= cpuid_eax(0x80000000);
1037 if (c
->extended_cpuid_level
>= 0x80000007)
1038 c
->x86_power
= cpuid_edx(0x80000007);
1041 clear_cpu_cap(c
, X86_FEATURE_PAT
);
1043 switch (c
->x86_vendor
) {
1044 case X86_VENDOR_AMD
:
1046 if (c
->x86
>= 0xf && c
->x86
<= 0x11)
1047 set_cpu_cap(c
, X86_FEATURE_PAT
);
1049 case X86_VENDOR_INTEL
:
1050 early_init_intel(c
);
1051 if (c
->x86
== 0xF || (c
->x86
== 6 && c
->x86_model
>= 15))
1052 set_cpu_cap(c
, X86_FEATURE_PAT
);
1054 case X86_VENDOR_CENTAUR
:
1055 early_init_centaur(c
);
1062 * This does the hard work of actually picking apart the CPU stuff...
1064 void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
1068 early_identify_cpu(c
);
1070 init_scattered_cpuid_features(c
);
1072 c
->apicid
= phys_pkg_id(0);
1075 * Vendor-specific initialization. In this section we
1076 * canonicalize the feature flags, meaning if there are
1077 * features a certain CPU supports which CPUID doesn't
1078 * tell us, CPUID claiming incorrect flags, or other bugs,
1079 * we handle them here.
1081 * At the end of this section, c->x86_capability better
1082 * indicate the features this CPU genuinely supports!
1084 switch (c
->x86_vendor
) {
1085 case X86_VENDOR_AMD
:
1089 case X86_VENDOR_INTEL
:
1093 case X86_VENDOR_CENTAUR
:
1097 case X86_VENDOR_UNKNOWN
:
1099 display_cacheinfo(c
);
1106 * On SMP, boot_cpu_data holds the common feature set between
1107 * all CPUs; so make sure that we indicate which features are
1108 * common between the CPUs. The first time this routine gets
1109 * executed, c == &boot_cpu_data.
1111 if (c
!= &boot_cpu_data
) {
1112 /* AND the already accumulated flags with these */
1113 for (i
= 0; i
< NCAPINTS
; i
++)
1114 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
1117 /* Clear all flags overriden by options */
1118 for (i
= 0; i
< NCAPINTS
; i
++)
1119 c
->x86_capability
[i
] &= ~cleared_cpu_caps
[i
];
1121 #ifdef CONFIG_X86_MCE
1124 select_idle_routine(c
);
1127 numa_add_cpu(smp_processor_id());
1132 void __cpuinit
identify_boot_cpu(void)
1134 identify_cpu(&boot_cpu_data
);
1137 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
1139 BUG_ON(c
== &boot_cpu_data
);
1144 static __init
int setup_noclflush(char *arg
)
1146 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
1149 __setup("noclflush", setup_noclflush
);
1151 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
1153 if (c
->x86_model_id
[0])
1154 printk(KERN_CONT
"%s", c
->x86_model_id
);
1156 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
1157 printk(KERN_CONT
" stepping %02x\n", c
->x86_mask
);
1159 printk(KERN_CONT
"\n");
1162 static __init
int setup_disablecpuid(char *arg
)
1165 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
1166 setup_clear_cpu_cap(bit
);
1171 __setup("clearcpuid=", setup_disablecpuid
);