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x86: disable the GART early, 64-bit
[deliverable/linux.git] / arch / x86 / kernel / setup_64.c
1 /*
2 * Copyright (C) 1995 Linus Torvalds
3 */
4
5 /*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
12 #include <linux/mm.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/a.out.h>
19 #include <linux/screen_info.h>
20 #include <linux/ioport.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/initrd.h>
24 #include <linux/highmem.h>
25 #include <linux/bootmem.h>
26 #include <linux/module.h>
27 #include <asm/processor.h>
28 #include <linux/console.h>
29 #include <linux/seq_file.h>
30 #include <linux/crash_dump.h>
31 #include <linux/root_dev.h>
32 #include <linux/pci.h>
33 #include <linux/efi.h>
34 #include <linux/acpi.h>
35 #include <linux/kallsyms.h>
36 #include <linux/edd.h>
37 #include <linux/mmzone.h>
38 #include <linux/kexec.h>
39 #include <linux/cpufreq.h>
40 #include <linux/dmi.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/ctype.h>
43 #include <linux/uaccess.h>
44
45 #include <asm/mtrr.h>
46 #include <asm/uaccess.h>
47 #include <asm/system.h>
48 #include <asm/vsyscall.h>
49 #include <asm/io.h>
50 #include <asm/smp.h>
51 #include <asm/msr.h>
52 #include <asm/desc.h>
53 #include <video/edid.h>
54 #include <asm/e820.h>
55 #include <asm/dma.h>
56 #include <asm/gart.h>
57 #include <asm/mpspec.h>
58 #include <asm/mmu_context.h>
59 #include <asm/proto.h>
60 #include <asm/setup.h>
61 #include <asm/mach_apic.h>
62 #include <asm/numa.h>
63 #include <asm/sections.h>
64 #include <asm/dmi.h>
65 #include <asm/cacheflush.h>
66 #include <asm/mce.h>
67 #include <asm/ds.h>
68
69 #ifdef CONFIG_PARAVIRT
70 #include <asm/paravirt.h>
71 #else
72 #define ARCH_SETUP
73 #endif
74
75 /*
76 * Machine setup..
77 */
78
79 struct cpuinfo_x86 boot_cpu_data __read_mostly;
80 EXPORT_SYMBOL(boot_cpu_data);
81
82 unsigned long mmu_cr4_features;
83
84 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
85 int bootloader_type;
86
87 unsigned long saved_video_mode;
88
89 int force_mwait __cpuinitdata;
90
91 /*
92 * Early DMI memory
93 */
94 int dmi_alloc_index;
95 char dmi_alloc_data[DMI_MAX_DATA];
96
97 /*
98 * Setup options
99 */
100 struct screen_info screen_info;
101 EXPORT_SYMBOL(screen_info);
102 struct sys_desc_table_struct {
103 unsigned short length;
104 unsigned char table[0];
105 };
106
107 struct edid_info edid_info;
108 EXPORT_SYMBOL_GPL(edid_info);
109
110 extern int root_mountflags;
111
112 char __initdata command_line[COMMAND_LINE_SIZE];
113
114 struct resource standard_io_resources[] = {
115 { .name = "dma1", .start = 0x00, .end = 0x1f,
116 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
117 { .name = "pic1", .start = 0x20, .end = 0x21,
118 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
119 { .name = "timer0", .start = 0x40, .end = 0x43,
120 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
121 { .name = "timer1", .start = 0x50, .end = 0x53,
122 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
123 { .name = "keyboard", .start = 0x60, .end = 0x6f,
124 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
125 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
126 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
127 { .name = "pic2", .start = 0xa0, .end = 0xa1,
128 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
129 { .name = "dma2", .start = 0xc0, .end = 0xdf,
130 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
131 { .name = "fpu", .start = 0xf0, .end = 0xff,
132 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
133 };
134
135 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
136
137 static struct resource data_resource = {
138 .name = "Kernel data",
139 .start = 0,
140 .end = 0,
141 .flags = IORESOURCE_RAM,
142 };
143 static struct resource code_resource = {
144 .name = "Kernel code",
145 .start = 0,
146 .end = 0,
147 .flags = IORESOURCE_RAM,
148 };
149 static struct resource bss_resource = {
150 .name = "Kernel bss",
151 .start = 0,
152 .end = 0,
153 .flags = IORESOURCE_RAM,
154 };
155
156 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
157
158 #ifdef CONFIG_PROC_VMCORE
159 /* elfcorehdr= specifies the location of elf core header
160 * stored by the crashed kernel. This option will be passed
161 * by kexec loader to the capture kernel.
162 */
163 static int __init setup_elfcorehdr(char *arg)
164 {
165 char *end;
166 if (!arg)
167 return -EINVAL;
168 elfcorehdr_addr = memparse(arg, &end);
169 return end > arg ? 0 : -EINVAL;
170 }
171 early_param("elfcorehdr", setup_elfcorehdr);
172 #endif
173
174 #ifndef CONFIG_NUMA
175 static void __init
176 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
177 {
178 unsigned long bootmap_size, bootmap;
179
180 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
181 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
182 if (bootmap == -1L)
183 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
184 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
185 e820_register_active_regions(0, start_pfn, end_pfn);
186 free_bootmem_with_active_regions(0, end_pfn);
187 reserve_bootmem(bootmap, bootmap_size);
188 }
189 #endif
190
191 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
192 struct edd edd;
193 #ifdef CONFIG_EDD_MODULE
194 EXPORT_SYMBOL(edd);
195 #endif
196 /**
197 * copy_edd() - Copy the BIOS EDD information
198 * from boot_params into a safe place.
199 *
200 */
201 static inline void copy_edd(void)
202 {
203 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
204 sizeof(edd.mbr_signature));
205 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
206 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
207 edd.edd_info_nr = boot_params.eddbuf_entries;
208 }
209 #else
210 static inline void copy_edd(void)
211 {
212 }
213 #endif
214
215 #ifdef CONFIG_KEXEC
216 static void __init reserve_crashkernel(void)
217 {
218 unsigned long long free_mem;
219 unsigned long long crash_size, crash_base;
220 int ret;
221
222 free_mem =
223 ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
224
225 ret = parse_crashkernel(boot_command_line, free_mem,
226 &crash_size, &crash_base);
227 if (ret == 0 && crash_size) {
228 if (crash_base > 0) {
229 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
230 "for crashkernel (System RAM: %ldMB)\n",
231 (unsigned long)(crash_size >> 20),
232 (unsigned long)(crash_base >> 20),
233 (unsigned long)(free_mem >> 20));
234 crashk_res.start = crash_base;
235 crashk_res.end = crash_base + crash_size - 1;
236 reserve_bootmem(crash_base, crash_size);
237 } else
238 printk(KERN_INFO "crashkernel reservation failed - "
239 "you have to specify a base address\n");
240 }
241 }
242 #else
243 static inline void __init reserve_crashkernel(void)
244 {}
245 #endif
246
247 #define EBDA_ADDR_POINTER 0x40E
248
249 unsigned __initdata ebda_addr;
250 unsigned __initdata ebda_size;
251
252 static void __init discover_ebda(void)
253 {
254 /*
255 * there is a real-mode segmented pointer pointing to the
256 * 4K EBDA area at 0x40E
257 */
258 ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
259 /*
260 * There can be some situations, like paravirtualized guests,
261 * in which there is no available ebda information. In such
262 * case, just skip it
263 */
264 if (!ebda_addr) {
265 ebda_size = 0;
266 return;
267 }
268
269 ebda_addr <<= 4;
270
271 ebda_size = *(unsigned short *)__va(ebda_addr);
272
273 /* Round EBDA up to pages */
274 if (ebda_size == 0)
275 ebda_size = 1;
276 ebda_size <<= 10;
277 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
278 if (ebda_size > 64*1024)
279 ebda_size = 64*1024;
280 }
281
282 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
283 void __attribute__((weak)) __init memory_setup(void)
284 {
285 machine_specific_memory_setup();
286 }
287
288 void __init setup_arch(char **cmdline_p)
289 {
290 unsigned i;
291
292 printk(KERN_INFO "Command line: %s\n", boot_command_line);
293
294 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
295 screen_info = boot_params.screen_info;
296 edid_info = boot_params.edid_info;
297 saved_video_mode = boot_params.hdr.vid_mode;
298 bootloader_type = boot_params.hdr.type_of_loader;
299
300 #ifdef CONFIG_BLK_DEV_RAM
301 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
302 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
303 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
304 #endif
305 #ifdef CONFIG_EFI
306 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
307 "EL64", 4))
308 efi_enabled = 1;
309 #endif
310
311 ARCH_SETUP
312
313 memory_setup();
314 copy_edd();
315
316 if (!boot_params.hdr.root_flags)
317 root_mountflags &= ~MS_RDONLY;
318 init_mm.start_code = (unsigned long) &_text;
319 init_mm.end_code = (unsigned long) &_etext;
320 init_mm.end_data = (unsigned long) &_edata;
321 init_mm.brk = (unsigned long) &_end;
322
323 code_resource.start = virt_to_phys(&_text);
324 code_resource.end = virt_to_phys(&_etext)-1;
325 data_resource.start = virt_to_phys(&_etext);
326 data_resource.end = virt_to_phys(&_edata)-1;
327 bss_resource.start = virt_to_phys(&__bss_start);
328 bss_resource.end = virt_to_phys(&__bss_stop)-1;
329
330 early_identify_cpu(&boot_cpu_data);
331
332 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
333 *cmdline_p = command_line;
334
335 parse_early_param();
336
337 finish_e820_parsing();
338
339 early_gart_iommu_check();
340
341 e820_register_active_regions(0, 0, -1UL);
342 /*
343 * partially used pages are not usable - thus
344 * we are rounding upwards:
345 */
346 end_pfn = e820_end_of_ram();
347 num_physpages = end_pfn;
348
349 check_efer();
350
351 discover_ebda();
352
353 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
354 if (efi_enabled)
355 efi_init();
356
357 dmi_scan_machine();
358
359 io_delay_init();
360
361 #ifdef CONFIG_SMP
362 /* setup to use the static apicid table during kernel startup */
363 x86_cpu_to_apicid_ptr = (void *)&x86_cpu_to_apicid_init;
364 #endif
365
366 #ifdef CONFIG_ACPI
367 /*
368 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
369 * Call this early for SRAT node setup.
370 */
371 acpi_boot_table_init();
372 #endif
373
374 /* How many end-of-memory variables you have, grandma! */
375 max_low_pfn = end_pfn;
376 max_pfn = end_pfn;
377 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
378
379 /* Remove active ranges so rediscovery with NUMA-awareness happens */
380 remove_all_active_ranges();
381
382 #ifdef CONFIG_ACPI_NUMA
383 /*
384 * Parse SRAT to discover nodes.
385 */
386 acpi_numa_init();
387 #endif
388
389 #ifdef CONFIG_NUMA
390 numa_initmem_init(0, end_pfn);
391 #else
392 contig_initmem_init(0, end_pfn);
393 #endif
394
395 /* Reserve direct mapping */
396 reserve_bootmem_generic(table_start << PAGE_SHIFT,
397 (table_end - table_start) << PAGE_SHIFT);
398
399 /* reserve kernel */
400 reserve_bootmem_generic(__pa_symbol(&_text),
401 __pa_symbol(&_end) - __pa_symbol(&_text));
402
403 /*
404 * reserve physical page 0 - it's a special BIOS page on many boxes,
405 * enabling clean reboots, SMP operation, laptop functions.
406 */
407 reserve_bootmem_generic(0, PAGE_SIZE);
408
409 /* reserve ebda region */
410 if (ebda_addr)
411 reserve_bootmem_generic(ebda_addr, ebda_size);
412 #ifdef CONFIG_NUMA
413 /* reserve nodemap region */
414 if (nodemap_addr)
415 reserve_bootmem_generic(nodemap_addr, nodemap_size);
416 #endif
417
418 #ifdef CONFIG_SMP
419 /* Reserve SMP trampoline */
420 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
421 #endif
422
423 #ifdef CONFIG_ACPI_SLEEP
424 /*
425 * Reserve low memory region for sleep support.
426 */
427 acpi_reserve_bootmem();
428 #endif
429
430 if (efi_enabled) {
431 efi_map_memmap();
432 efi_reserve_bootmem();
433 }
434
435 /*
436 * Find and reserve possible boot-time SMP configuration:
437 */
438 find_smp_config();
439 #ifdef CONFIG_BLK_DEV_INITRD
440 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
441 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
442 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
443 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
444 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
445
446 if (ramdisk_end <= end_of_mem) {
447 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
448 initrd_start = ramdisk_image + PAGE_OFFSET;
449 initrd_end = initrd_start+ramdisk_size;
450 } else {
451 printk(KERN_ERR "initrd extends beyond end of memory "
452 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
453 ramdisk_end, end_of_mem);
454 initrd_start = 0;
455 }
456 }
457 #endif
458 reserve_crashkernel();
459 paging_init();
460 map_vsyscall();
461
462 early_quirks();
463
464 /*
465 * set this early, so we dont allocate cpu0
466 * if MADT list doesnt list BSP first
467 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
468 */
469 cpu_set(0, cpu_present_map);
470 #ifdef CONFIG_ACPI
471 /*
472 * Read APIC and some other early information from ACPI tables.
473 */
474 acpi_boot_init();
475 #endif
476
477 init_cpu_to_node();
478
479 /*
480 * get boot-time SMP configuration:
481 */
482 if (smp_found_config)
483 get_smp_config();
484 init_apic_mappings();
485 ioapic_init_mappings();
486
487 /*
488 * We trust e820 completely. No explicit ROM probing in memory.
489 */
490 e820_reserve_resources(&code_resource, &data_resource, &bss_resource);
491 e820_mark_nosave_regions();
492
493 /* request I/O space for devices used on all i[345]86 PCs */
494 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
495 request_resource(&ioport_resource, &standard_io_resources[i]);
496
497 e820_setup_gap();
498
499 #ifdef CONFIG_VT
500 #if defined(CONFIG_VGA_CONSOLE)
501 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
502 conswitchp = &vga_con;
503 #elif defined(CONFIG_DUMMY_CONSOLE)
504 conswitchp = &dummy_con;
505 #endif
506 #endif
507 }
508
509 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
510 {
511 unsigned int *v;
512
513 if (c->extended_cpuid_level < 0x80000004)
514 return 0;
515
516 v = (unsigned int *) c->x86_model_id;
517 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
518 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
519 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
520 c->x86_model_id[48] = 0;
521 return 1;
522 }
523
524
525 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
526 {
527 unsigned int n, dummy, eax, ebx, ecx, edx;
528
529 n = c->extended_cpuid_level;
530
531 if (n >= 0x80000005) {
532 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
533 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
534 "D cache %dK (%d bytes/line)\n",
535 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
536 c->x86_cache_size = (ecx>>24) + (edx>>24);
537 /* On K8 L1 TLB is inclusive, so don't count it */
538 c->x86_tlbsize = 0;
539 }
540
541 if (n >= 0x80000006) {
542 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
543 ecx = cpuid_ecx(0x80000006);
544 c->x86_cache_size = ecx >> 16;
545 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
546
547 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
548 c->x86_cache_size, ecx & 0xFF);
549 }
550 if (n >= 0x80000008) {
551 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
552 c->x86_virt_bits = (eax >> 8) & 0xff;
553 c->x86_phys_bits = eax & 0xff;
554 }
555 }
556
557 #ifdef CONFIG_NUMA
558 static int nearby_node(int apicid)
559 {
560 int i, node;
561
562 for (i = apicid - 1; i >= 0; i--) {
563 node = apicid_to_node[i];
564 if (node != NUMA_NO_NODE && node_online(node))
565 return node;
566 }
567 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
568 node = apicid_to_node[i];
569 if (node != NUMA_NO_NODE && node_online(node))
570 return node;
571 }
572 return first_node(node_online_map); /* Shouldn't happen */
573 }
574 #endif
575
576 /*
577 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
578 * Assumes number of cores is a power of two.
579 */
580 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
581 {
582 #ifdef CONFIG_SMP
583 unsigned bits;
584 #ifdef CONFIG_NUMA
585 int cpu = smp_processor_id();
586 int node = 0;
587 unsigned apicid = hard_smp_processor_id();
588 #endif
589 bits = c->x86_coreid_bits;
590
591 /* Low order bits define the core id (index of core in socket) */
592 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
593 /* Convert the APIC ID into the socket ID */
594 c->phys_proc_id = phys_pkg_id(bits);
595
596 #ifdef CONFIG_NUMA
597 node = c->phys_proc_id;
598 if (apicid_to_node[apicid] != NUMA_NO_NODE)
599 node = apicid_to_node[apicid];
600 if (!node_online(node)) {
601 /* Two possibilities here:
602 - The CPU is missing memory and no node was created.
603 In that case try picking one from a nearby CPU
604 - The APIC IDs differ from the HyperTransport node IDs
605 which the K8 northbridge parsing fills in.
606 Assume they are all increased by a constant offset,
607 but in the same order as the HT nodeids.
608 If that doesn't result in a usable node fall back to the
609 path for the previous case. */
610
611 int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
612
613 if (ht_nodeid >= 0 &&
614 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
615 node = apicid_to_node[ht_nodeid];
616 /* Pick a nearby node */
617 if (!node_online(node))
618 node = nearby_node(apicid);
619 }
620 numa_set_node(cpu, node);
621
622 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
623 #endif
624 #endif
625 }
626
627 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
628 {
629 #ifdef CONFIG_SMP
630 unsigned bits, ecx;
631
632 /* Multi core CPU? */
633 if (c->extended_cpuid_level < 0x80000008)
634 return;
635
636 ecx = cpuid_ecx(0x80000008);
637
638 c->x86_max_cores = (ecx & 0xff) + 1;
639
640 /* CPU telling us the core id bits shift? */
641 bits = (ecx >> 12) & 0xF;
642
643 /* Otherwise recompute */
644 if (bits == 0) {
645 while ((1 << bits) < c->x86_max_cores)
646 bits++;
647 }
648
649 c->x86_coreid_bits = bits;
650
651 #endif
652 }
653
654 #define ENABLE_C1E_MASK 0x18000000
655 #define CPUID_PROCESSOR_SIGNATURE 1
656 #define CPUID_XFAM 0x0ff00000
657 #define CPUID_XFAM_K8 0x00000000
658 #define CPUID_XFAM_10H 0x00100000
659 #define CPUID_XFAM_11H 0x00200000
660 #define CPUID_XMOD 0x000f0000
661 #define CPUID_XMOD_REV_F 0x00040000
662
663 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
664 static __cpuinit int amd_apic_timer_broken(void)
665 {
666 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
667
668 switch (eax & CPUID_XFAM) {
669 case CPUID_XFAM_K8:
670 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
671 break;
672 case CPUID_XFAM_10H:
673 case CPUID_XFAM_11H:
674 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
675 if (lo & ENABLE_C1E_MASK)
676 return 1;
677 break;
678 default:
679 /* err on the side of caution */
680 return 1;
681 }
682 return 0;
683 }
684
685 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
686 {
687 early_init_amd_mc(c);
688
689 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
690 if (c->x86_power & (1<<8))
691 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
692 }
693
694 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
695 {
696 unsigned level;
697
698 #ifdef CONFIG_SMP
699 unsigned long value;
700
701 /*
702 * Disable TLB flush filter by setting HWCR.FFDIS on K8
703 * bit 6 of msr C001_0015
704 *
705 * Errata 63 for SH-B3 steppings
706 * Errata 122 for all steppings (F+ have it disabled by default)
707 */
708 if (c->x86 == 15) {
709 rdmsrl(MSR_K8_HWCR, value);
710 value |= 1 << 6;
711 wrmsrl(MSR_K8_HWCR, value);
712 }
713 #endif
714
715 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
716 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
717 clear_bit(0*32+31, (unsigned long *)&c->x86_capability);
718
719 /* On C+ stepping K8 rep microcode works well for copy/memset */
720 level = cpuid_eax(1);
721 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
722 level >= 0x0f58))
723 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
724 if (c->x86 == 0x10 || c->x86 == 0x11)
725 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
726
727 /* Enable workaround for FXSAVE leak */
728 if (c->x86 >= 6)
729 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
730
731 level = get_model_name(c);
732 if (!level) {
733 switch (c->x86) {
734 case 15:
735 /* Should distinguish Models here, but this is only
736 a fallback anyways. */
737 strcpy(c->x86_model_id, "Hammer");
738 break;
739 }
740 }
741 display_cacheinfo(c);
742
743 /* Multi core CPU? */
744 if (c->extended_cpuid_level >= 0x80000008)
745 amd_detect_cmp(c);
746
747 if (c->extended_cpuid_level >= 0x80000006 &&
748 (cpuid_edx(0x80000006) & 0xf000))
749 num_cache_leaves = 4;
750 else
751 num_cache_leaves = 3;
752
753 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
754 set_cpu_cap(c, X86_FEATURE_K8);
755
756 /* MFENCE stops RDTSC speculation */
757 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
758
759 /* Family 10 doesn't support C states in MWAIT so don't use it */
760 if (c->x86 == 0x10 && !force_mwait)
761 clear_cpu_cap(c, X86_FEATURE_MWAIT);
762
763 if (amd_apic_timer_broken())
764 disable_apic_timer = 1;
765 }
766
767 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
768 {
769 #ifdef CONFIG_SMP
770 u32 eax, ebx, ecx, edx;
771 int index_msb, core_bits;
772
773 cpuid(1, &eax, &ebx, &ecx, &edx);
774
775
776 if (!cpu_has(c, X86_FEATURE_HT))
777 return;
778 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
779 goto out;
780
781 smp_num_siblings = (ebx & 0xff0000) >> 16;
782
783 if (smp_num_siblings == 1) {
784 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
785 } else if (smp_num_siblings > 1) {
786
787 if (smp_num_siblings > NR_CPUS) {
788 printk(KERN_WARNING "CPU: Unsupported number of "
789 "siblings %d", smp_num_siblings);
790 smp_num_siblings = 1;
791 return;
792 }
793
794 index_msb = get_count_order(smp_num_siblings);
795 c->phys_proc_id = phys_pkg_id(index_msb);
796
797 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
798
799 index_msb = get_count_order(smp_num_siblings);
800
801 core_bits = get_count_order(c->x86_max_cores);
802
803 c->cpu_core_id = phys_pkg_id(index_msb) &
804 ((1 << core_bits) - 1);
805 }
806 out:
807 if ((c->x86_max_cores * smp_num_siblings) > 1) {
808 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
809 c->phys_proc_id);
810 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
811 c->cpu_core_id);
812 }
813
814 #endif
815 }
816
817 /*
818 * find out the number of processor cores on the die
819 */
820 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
821 {
822 unsigned int eax, t;
823
824 if (c->cpuid_level < 4)
825 return 1;
826
827 cpuid_count(4, 0, &eax, &t, &t, &t);
828
829 if (eax & 0x1f)
830 return ((eax >> 26) + 1);
831 else
832 return 1;
833 }
834
835 static void srat_detect_node(void)
836 {
837 #ifdef CONFIG_NUMA
838 unsigned node;
839 int cpu = smp_processor_id();
840 int apicid = hard_smp_processor_id();
841
842 /* Don't do the funky fallback heuristics the AMD version employs
843 for now. */
844 node = apicid_to_node[apicid];
845 if (node == NUMA_NO_NODE)
846 node = first_node(node_online_map);
847 numa_set_node(cpu, node);
848
849 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
850 #endif
851 }
852
853 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
854 {
855 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
856 (c->x86 == 0x6 && c->x86_model >= 0x0e))
857 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
858 }
859
860 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
861 {
862 /* Cache sizes */
863 unsigned n;
864
865 init_intel_cacheinfo(c);
866 if (c->cpuid_level > 9) {
867 unsigned eax = cpuid_eax(10);
868 /* Check for version and the number of counters */
869 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
870 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
871 }
872
873 if (cpu_has_ds) {
874 unsigned int l1, l2;
875 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
876 if (!(l1 & (1<<11)))
877 set_cpu_cap(c, X86_FEATURE_BTS);
878 if (!(l1 & (1<<12)))
879 set_cpu_cap(c, X86_FEATURE_PEBS);
880 }
881
882
883 if (cpu_has_bts)
884 ds_init_intel(c);
885
886 n = c->extended_cpuid_level;
887 if (n >= 0x80000008) {
888 unsigned eax = cpuid_eax(0x80000008);
889 c->x86_virt_bits = (eax >> 8) & 0xff;
890 c->x86_phys_bits = eax & 0xff;
891 /* CPUID workaround for Intel 0F34 CPU */
892 if (c->x86_vendor == X86_VENDOR_INTEL &&
893 c->x86 == 0xF && c->x86_model == 0x3 &&
894 c->x86_mask == 0x4)
895 c->x86_phys_bits = 36;
896 }
897
898 if (c->x86 == 15)
899 c->x86_cache_alignment = c->x86_clflush_size * 2;
900 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
901 (c->x86 == 0x6 && c->x86_model >= 0x0e))
902 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
903 if (c->x86 == 6)
904 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
905 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
906 c->x86_max_cores = intel_num_cpu_cores(c);
907
908 srat_detect_node();
909 }
910
911 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
912 {
913 char *v = c->x86_vendor_id;
914
915 if (!strcmp(v, "AuthenticAMD"))
916 c->x86_vendor = X86_VENDOR_AMD;
917 else if (!strcmp(v, "GenuineIntel"))
918 c->x86_vendor = X86_VENDOR_INTEL;
919 else
920 c->x86_vendor = X86_VENDOR_UNKNOWN;
921 }
922
923 struct cpu_model_info {
924 int vendor;
925 int family;
926 char *model_names[16];
927 };
928
929 /* Do some early cpuid on the boot CPU to get some parameter that are
930 needed before check_bugs. Everything advanced is in identify_cpu
931 below. */
932 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
933 {
934 u32 tfms, xlvl;
935
936 c->loops_per_jiffy = loops_per_jiffy;
937 c->x86_cache_size = -1;
938 c->x86_vendor = X86_VENDOR_UNKNOWN;
939 c->x86_model = c->x86_mask = 0; /* So far unknown... */
940 c->x86_vendor_id[0] = '\0'; /* Unset */
941 c->x86_model_id[0] = '\0'; /* Unset */
942 c->x86_clflush_size = 64;
943 c->x86_cache_alignment = c->x86_clflush_size;
944 c->x86_max_cores = 1;
945 c->x86_coreid_bits = 0;
946 c->extended_cpuid_level = 0;
947 memset(&c->x86_capability, 0, sizeof c->x86_capability);
948
949 /* Get vendor name */
950 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
951 (unsigned int *)&c->x86_vendor_id[0],
952 (unsigned int *)&c->x86_vendor_id[8],
953 (unsigned int *)&c->x86_vendor_id[4]);
954
955 get_cpu_vendor(c);
956
957 /* Initialize the standard set of capabilities */
958 /* Note that the vendor-specific code below might override */
959
960 /* Intel-defined flags: level 0x00000001 */
961 if (c->cpuid_level >= 0x00000001) {
962 __u32 misc;
963 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
964 &c->x86_capability[0]);
965 c->x86 = (tfms >> 8) & 0xf;
966 c->x86_model = (tfms >> 4) & 0xf;
967 c->x86_mask = tfms & 0xf;
968 if (c->x86 == 0xf)
969 c->x86 += (tfms >> 20) & 0xff;
970 if (c->x86 >= 0x6)
971 c->x86_model += ((tfms >> 16) & 0xF) << 4;
972 if (c->x86_capability[0] & (1<<19))
973 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
974 } else {
975 /* Have CPUID level 0 only - unheard of */
976 c->x86 = 4;
977 }
978
979 #ifdef CONFIG_SMP
980 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
981 #endif
982 /* AMD-defined flags: level 0x80000001 */
983 xlvl = cpuid_eax(0x80000000);
984 c->extended_cpuid_level = xlvl;
985 if ((xlvl & 0xffff0000) == 0x80000000) {
986 if (xlvl >= 0x80000001) {
987 c->x86_capability[1] = cpuid_edx(0x80000001);
988 c->x86_capability[6] = cpuid_ecx(0x80000001);
989 }
990 if (xlvl >= 0x80000004)
991 get_model_name(c); /* Default name */
992 }
993
994 /* Transmeta-defined flags: level 0x80860001 */
995 xlvl = cpuid_eax(0x80860000);
996 if ((xlvl & 0xffff0000) == 0x80860000) {
997 /* Don't set x86_cpuid_level here for now to not confuse. */
998 if (xlvl >= 0x80860001)
999 c->x86_capability[2] = cpuid_edx(0x80860001);
1000 }
1001
1002 c->extended_cpuid_level = cpuid_eax(0x80000000);
1003 if (c->extended_cpuid_level >= 0x80000007)
1004 c->x86_power = cpuid_edx(0x80000007);
1005
1006 switch (c->x86_vendor) {
1007 case X86_VENDOR_AMD:
1008 early_init_amd(c);
1009 break;
1010 }
1011
1012 }
1013
1014 /*
1015 * This does the hard work of actually picking apart the CPU stuff...
1016 */
1017 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1018 {
1019 int i;
1020
1021 early_identify_cpu(c);
1022
1023 init_scattered_cpuid_features(c);
1024
1025 c->apicid = phys_pkg_id(0);
1026
1027 /*
1028 * Vendor-specific initialization. In this section we
1029 * canonicalize the feature flags, meaning if there are
1030 * features a certain CPU supports which CPUID doesn't
1031 * tell us, CPUID claiming incorrect flags, or other bugs,
1032 * we handle them here.
1033 *
1034 * At the end of this section, c->x86_capability better
1035 * indicate the features this CPU genuinely supports!
1036 */
1037 switch (c->x86_vendor) {
1038 case X86_VENDOR_AMD:
1039 init_amd(c);
1040 break;
1041
1042 case X86_VENDOR_INTEL:
1043 init_intel(c);
1044 break;
1045
1046 case X86_VENDOR_UNKNOWN:
1047 default:
1048 display_cacheinfo(c);
1049 break;
1050 }
1051
1052 select_idle_routine(c);
1053 detect_ht(c);
1054
1055 /*
1056 * On SMP, boot_cpu_data holds the common feature set between
1057 * all CPUs; so make sure that we indicate which features are
1058 * common between the CPUs. The first time this routine gets
1059 * executed, c == &boot_cpu_data.
1060 */
1061 if (c != &boot_cpu_data) {
1062 /* AND the already accumulated flags with these */
1063 for (i = 0; i < NCAPINTS; i++)
1064 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1065 }
1066
1067 #ifdef CONFIG_X86_MCE
1068 mcheck_init(c);
1069 #endif
1070 if (c != &boot_cpu_data)
1071 mtrr_ap_init();
1072 #ifdef CONFIG_NUMA
1073 numa_add_cpu(smp_processor_id());
1074 #endif
1075
1076 switch (c->x86_vendor) {
1077 case X86_VENDOR_AMD:
1078 early_init_amd(c);
1079 break;
1080 case X86_VENDOR_INTEL:
1081 early_init_intel(c);
1082 break;
1083 }
1084 }
1085
1086 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1087 {
1088 if (c->x86_model_id[0])
1089 printk(KERN_INFO "%s", c->x86_model_id);
1090
1091 if (c->x86_mask || c->cpuid_level >= 0)
1092 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1093 else
1094 printk(KERN_CONT "\n");
1095 }
1096
1097 /*
1098 * Get CPU information for use by the procfs.
1099 */
1100
1101 static int show_cpuinfo(struct seq_file *m, void *v)
1102 {
1103 struct cpuinfo_x86 *c = v;
1104 int cpu = 0, i;
1105
1106 /*
1107 * These flag bits must match the definitions in <asm/cpufeature.h>.
1108 * NULL means this bit is undefined or reserved; either way it doesn't
1109 * have meaning as far as Linux is concerned. Note that it's important
1110 * to realize there is a difference between this table and CPUID -- if
1111 * applications want to get the raw CPUID data, they should access
1112 * /dev/cpu/<cpu_nr>/cpuid instead.
1113 */
1114 static const char *const x86_cap_flags[] = {
1115 /* Intel-defined */
1116 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1117 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1118 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1119 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
1120
1121 /* AMD-defined */
1122 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1123 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1124 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
1125 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
1126 "3dnowext", "3dnow",
1127
1128 /* Transmeta-defined */
1129 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1130 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1131 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1133
1134 /* Other (Linux-defined) */
1135 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
1136 NULL, NULL, NULL, NULL,
1137 "constant_tsc", "up", NULL, "arch_perfmon",
1138 "pebs", "bts", NULL, "sync_rdtsc",
1139 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1140 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1141
1142 /* Intel-defined (#2) */
1143 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
1144 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
1145 NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt",
1146 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1147
1148 /* VIA/Cyrix/Centaur-defined */
1149 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1150 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
1151 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1153
1154 /* AMD-defined (#2) */
1155 "lahf_lm", "cmp_legacy", "svm", "extapic",
1156 "cr8_legacy", "abm", "sse4a", "misalignsse",
1157 "3dnowprefetch", "osvw", "ibs", "sse5",
1158 "skinit", "wdt", NULL, NULL,
1159 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1160 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1161
1162 /* Auxiliary (Linux-defined) */
1163 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1164 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1165 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1166 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1167 };
1168 static const char *const x86_power_flags[] = {
1169 "ts", /* temperature sensor */
1170 "fid", /* frequency id control */
1171 "vid", /* voltage id control */
1172 "ttp", /* thermal trip */
1173 "tm",
1174 "stc",
1175 "100mhzsteps",
1176 "hwpstate",
1177 "", /* tsc invariant mapped to constant_tsc */
1178 /* nothing */
1179 };
1180
1181
1182 #ifdef CONFIG_SMP
1183 cpu = c->cpu_index;
1184 #endif
1185
1186 seq_printf(m, "processor\t: %u\n"
1187 "vendor_id\t: %s\n"
1188 "cpu family\t: %d\n"
1189 "model\t\t: %d\n"
1190 "model name\t: %s\n",
1191 (unsigned)cpu,
1192 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1193 c->x86,
1194 (int)c->x86_model,
1195 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1196
1197 if (c->x86_mask || c->cpuid_level >= 0)
1198 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1199 else
1200 seq_printf(m, "stepping\t: unknown\n");
1201
1202 if (cpu_has(c, X86_FEATURE_TSC)) {
1203 unsigned int freq = cpufreq_quick_get((unsigned)cpu);
1204
1205 if (!freq)
1206 freq = cpu_khz;
1207 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1208 freq / 1000, (freq % 1000));
1209 }
1210
1211 /* Cache size */
1212 if (c->x86_cache_size >= 0)
1213 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1214
1215 #ifdef CONFIG_SMP
1216 if (smp_num_siblings * c->x86_max_cores > 1) {
1217 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1218 seq_printf(m, "siblings\t: %d\n",
1219 cpus_weight(per_cpu(cpu_core_map, cpu)));
1220 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1221 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1222 }
1223 #endif
1224
1225 seq_printf(m,
1226 "fpu\t\t: yes\n"
1227 "fpu_exception\t: yes\n"
1228 "cpuid level\t: %d\n"
1229 "wp\t\t: yes\n"
1230 "flags\t\t:",
1231 c->cpuid_level);
1232
1233 for (i = 0; i < 32*NCAPINTS; i++)
1234 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1235 seq_printf(m, " %s", x86_cap_flags[i]);
1236
1237 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1238 c->loops_per_jiffy/(500000/HZ),
1239 (c->loops_per_jiffy/(5000/HZ)) % 100);
1240
1241 if (c->x86_tlbsize > 0)
1242 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1243 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1244 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1245
1246 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1247 c->x86_phys_bits, c->x86_virt_bits);
1248
1249 seq_printf(m, "power management:");
1250 for (i = 0; i < 32; i++) {
1251 if (c->x86_power & (1 << i)) {
1252 if (i < ARRAY_SIZE(x86_power_flags) &&
1253 x86_power_flags[i])
1254 seq_printf(m, "%s%s",
1255 x86_power_flags[i][0]?" ":"",
1256 x86_power_flags[i]);
1257 else
1258 seq_printf(m, " [%d]", i);
1259 }
1260 }
1261
1262 seq_printf(m, "\n\n");
1263
1264 return 0;
1265 }
1266
1267 static void *c_start(struct seq_file *m, loff_t *pos)
1268 {
1269 if (*pos == 0) /* just in case, cpu 0 is not the first */
1270 *pos = first_cpu(cpu_online_map);
1271 if ((*pos) < NR_CPUS && cpu_online(*pos))
1272 return &cpu_data(*pos);
1273 return NULL;
1274 }
1275
1276 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1277 {
1278 *pos = next_cpu(*pos, cpu_online_map);
1279 return c_start(m, pos);
1280 }
1281
1282 static void c_stop(struct seq_file *m, void *v)
1283 {
1284 }
1285
1286 struct seq_operations cpuinfo_op = {
1287 .start = c_start,
1288 .next = c_next,
1289 .stop = c_stop,
1290 .show = show_cpuinfo,
1291 };
Linux kernel - Deliverables
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