arch/x86/kernel/smp.c

   1 /*
   2  *      Intel SMP support routines.
   3  *
   4  *      (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
   5  *      (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
   6  *      (c) 2002,2003 Andi Kleen, SuSE Labs.
   7  *
   8  *      i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
   9  *
  10  *      This code is released under the GNU General Public License version 2 or
  11  *      later.
  12  */
  13
  14 #include <linux/init.h>
  15
  16 #include <linux/mm.h>
  17 #include <linux/delay.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/export.h>
  20 #include <linux/kernel_stat.h>
  21 #include <linux/mc146818rtc.h>
  22 #include <linux/cache.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/cpu.h>
  25 #include <linux/gfp.h>
  26
  27 #include <asm/mtrr.h>
  28 #include <asm/tlbflush.h>
  29 #include <asm/mmu_context.h>
  30 #include <asm/proto.h>
  31 #include <asm/apic.h>
  32 #include <asm/nmi.h>
  33 #include <asm/mce.h>
  34 #include <asm/trace/irq_vectors.h>
  35 /*
  36  *      Some notes on x86 processor bugs affecting SMP operation:
  37  *
  38  *      Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
  39  *      The Linux implications for SMP are handled as follows:
  40  *
  41  *      Pentium III / [Xeon]
  42  *              None of the E1AP-E3AP errata are visible to the user.
  43  *
  44  *      E1AP.   see PII A1AP
  45  *      E2AP.   see PII A2AP
  46  *      E3AP.   see PII A3AP
  47  *
  48  *      Pentium II / [Xeon]
  49  *              None of the A1AP-A3AP errata are visible to the user.
  50  *
  51  *      A1AP.   see PPro 1AP
  52  *      A2AP.   see PPro 2AP
  53  *      A3AP.   see PPro 7AP
  54  *
  55  *      Pentium Pro
  56  *              None of 1AP-9AP errata are visible to the normal user,
  57  *      except occasional delivery of 'spurious interrupt' as trap #15.
  58  *      This is very rare and a non-problem.
  59  *
  60  *      1AP.    Linux maps APIC as non-cacheable
  61  *      2AP.    worked around in hardware
  62  *      3AP.    fixed in C0 and above steppings microcode update.
  63  *              Linux does not use excessive STARTUP_IPIs.
  64  *      4AP.    worked around in hardware
  65  *      5AP.    symmetric IO mode (normal Linux operation) not affected.
  66  *              'noapic' mode has vector 0xf filled out properly.
  67  *      6AP.    'noapic' mode might be affected - fixed in later steppings
  68  *      7AP.    We do not assume writes to the LVT deassering IRQs
  69  *      8AP.    We do not enable low power mode (deep sleep) during MP bootup
  70  *      9AP.    We do not use mixed mode
  71  *
  72  *      Pentium
  73  *              There is a marginal case where REP MOVS on 100MHz SMP
  74  *      machines with B stepping processors can fail. XXX should provide
  75  *      an L1cache=Writethrough or L1cache=off option.
  76  *
  77  *              B stepping CPUs may hang. There are hardware work arounds
  78  *      for this. We warn about it in case your board doesn't have the work
  79  *      arounds. Basically that's so I can tell anyone with a B stepping
  80  *      CPU and SMP problems "tough".
  81  *
  82  *      Specific items [From Pentium Processor Specification Update]
  83  *
  84  *      1AP.    Linux doesn't use remote read
  85  *      2AP.    Linux doesn't trust APIC errors
  86  *      3AP.    We work around this
  87  *      4AP.    Linux never generated 3 interrupts of the same priority
  88  *              to cause a lost local interrupt.
  89  *      5AP.    Remote read is never used
  90  *      6AP.    not affected - worked around in hardware
  91  *      7AP.    not affected - worked around in hardware
  92  *      8AP.    worked around in hardware - we get explicit CS errors if not
  93  *      9AP.    only 'noapic' mode affected. Might generate spurious
  94  *              interrupts, we log only the first one and count the
  95  *              rest silently.
  96  *      10AP.   not affected - worked around in hardware
  97  *      11AP.   Linux reads the APIC between writes to avoid this, as per
  98  *              the documentation. Make sure you preserve this as it affects
  99  *              the C stepping chips too.
 100  *      12AP.   not affected - worked around in hardware
 101  *      13AP.   not affected - worked around in hardware
 102  *      14AP.   we always deassert INIT during bootup
 103  *      15AP.   not affected - worked around in hardware
 104  *      16AP.   not affected - worked around in hardware
 105  *      17AP.   not affected - worked around in hardware
 106  *      18AP.   not affected - worked around in hardware
 107  *      19AP.   not affected - worked around in BIOS
 108  *
 109  *      If this sounds worrying believe me these bugs are either ___RARE___,
 110  *      or are signal timing bugs worked around in hardware and there's
 111  *      about nothing of note with C stepping upwards.
 112  */
 113
 114 static atomic_t stopping_cpu = ATOMIC_INIT(-1);
 115 static bool smp_no_nmi_ipi = false;
 116
 117 /*
 118  * this function sends a 'reschedule' IPI to another CPU.
 119  * it goes straight through and wastes no time serializing
 120  * anything. Worst case is that we lose a reschedule ...
 121  */
 122 static void native_smp_send_reschedule(int cpu)
 123 {
 124         if (unlikely(cpu_is_offline(cpu))) {
 125                 WARN_ON(1);
 126                 return;
 127         }
 128         apic->send_IPI(cpu, RESCHEDULE_VECTOR);
 129 }
 130
 131 void native_send_call_func_single_ipi(int cpu)
 132 {
 133         apic->send_IPI(cpu, CALL_FUNCTION_SINGLE_VECTOR);
 134 }
 135
 136 void native_send_call_func_ipi(const struct cpumask *mask)
 137 {
 138         cpumask_var_t allbutself;
 139
 140         if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) {
 141                 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
 142                 return;
 143         }
 144
 145         cpumask_copy(allbutself, cpu_online_mask);
 146         cpumask_clear_cpu(smp_processor_id(), allbutself);
 147
 148         if (cpumask_equal(mask, allbutself) &&
 149             cpumask_equal(cpu_online_mask, cpu_callout_mask))
 150                 apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR);
 151         else
 152                 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
 153
 154         free_cpumask_var(allbutself);
 155 }
 156
 157 static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
 158 {
 159         /* We are registered on stopping cpu too, avoid spurious NMI */
 160         if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
 161                 return NMI_HANDLED;
 162
 163         stop_this_cpu(NULL);
 164
 165         return NMI_HANDLED;
 166 }
 167
 168 /*
 169  * this function calls the 'stop' function on all other CPUs in the system.
 170  */
 171
 172 asmlinkage __visible void smp_reboot_interrupt(void)
 173 {
 174         ipi_entering_ack_irq();
 175         stop_this_cpu(NULL);
 176         irq_exit();
 177 }
 178
 179 static void native_stop_other_cpus(int wait)
 180 {
 181         unsigned long flags;
 182         unsigned long timeout;
 183
 184         if (reboot_force)
 185                 return;
 186
 187         /*
 188          * Use an own vector here because smp_call_function
 189          * does lots of things not suitable in a panic situation.
 190          */
 191
 192         /*
 193          * We start by using the REBOOT_VECTOR irq.
 194          * The irq is treated as a sync point to allow critical
 195          * regions of code on other cpus to release their spin locks
 196          * and re-enable irqs.  Jumping straight to an NMI might
 197          * accidentally cause deadlocks with further shutdown/panic
 198          * code.  By syncing, we give the cpus up to one second to
 199          * finish their work before we force them off with the NMI.
 200          */
 201         if (num_online_cpus() > 1) {
 202                 /* did someone beat us here? */
 203                 if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1)
 204                         return;
 205
 206                 /* sync above data before sending IRQ */
 207                 wmb();
 208
 209                 apic->send_IPI_allbutself(REBOOT_VECTOR);
 210
 211                 /*
 212                  * Don't wait longer than a second if the caller
 213                  * didn't ask us to wait.
 214                  */
 215                 timeout = USEC_PER_SEC;
 216                 while (num_online_cpus() > 1 && (wait || timeout--))
 217                         udelay(1);
 218         }
 219
 220         /* if the REBOOT_VECTOR didn't work, try with the NMI */
 221         if ((num_online_cpus() > 1) && (!smp_no_nmi_ipi))  {
 222                 if (register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
 223                                          NMI_FLAG_FIRST, "smp_stop"))
 224                         /* Note: we ignore failures here */
 225                         /* Hope the REBOOT_IRQ is good enough */
 226                         goto finish;
 227
 228                 /* sync above data before sending IRQ */
 229                 wmb();
 230
 231                 pr_emerg("Shutting down cpus with NMI\n");
 232
 233                 apic->send_IPI_allbutself(NMI_VECTOR);
 234
 235                 /*
 236                  * Don't wait longer than a 10 ms if the caller
 237                  * didn't ask us to wait.
 238                  */
 239                 timeout = USEC_PER_MSEC * 10;
 240                 while (num_online_cpus() > 1 && (wait || timeout--))
 241                         udelay(1);
 242         }
 243
 244 finish:
 245         local_irq_save(flags);
 246         disable_local_APIC();
 247         mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
 248         local_irq_restore(flags);
 249 }
 250
 251 /*
 252  * Reschedule call back.
 253  */
 254 static inline void __smp_reschedule_interrupt(void)
 255 {
 256         inc_irq_stat(irq_resched_count);
 257         scheduler_ipi();
 258 }
 259
 260 __visible void smp_reschedule_interrupt(struct pt_regs *regs)
 261 {
 262         ack_APIC_irq();
 263         __smp_reschedule_interrupt();
 264         /*
 265          * KVM uses this interrupt to force a cpu out of guest mode
 266          */
 267 }
 268
 269 __visible void smp_trace_reschedule_interrupt(struct pt_regs *regs)
 270 {
 271         /*
 272          * Need to call irq_enter() before calling the trace point.
 273          * __smp_reschedule_interrupt() calls irq_enter/exit() too (in
 274          * scheduler_ipi(). This is OK, since those functions are allowed
 275          * to nest.
 276          */
 277         ipi_entering_ack_irq();
 278         trace_reschedule_entry(RESCHEDULE_VECTOR);
 279         __smp_reschedule_interrupt();
 280         trace_reschedule_exit(RESCHEDULE_VECTOR);
 281         exiting_irq();
 282         /*
 283          * KVM uses this interrupt to force a cpu out of guest mode
 284          */
 285 }
 286
 287 static inline void __smp_call_function_interrupt(void)
 288 {
 289         generic_smp_call_function_interrupt();
 290         inc_irq_stat(irq_call_count);
 291 }
 292
 293 __visible void smp_call_function_interrupt(struct pt_regs *regs)
 294 {
 295         ipi_entering_ack_irq();
 296         __smp_call_function_interrupt();
 297         exiting_irq();
 298 }
 299
 300 __visible void smp_trace_call_function_interrupt(struct pt_regs *regs)
 301 {
 302         ipi_entering_ack_irq();
 303         trace_call_function_entry(CALL_FUNCTION_VECTOR);
 304         __smp_call_function_interrupt();
 305         trace_call_function_exit(CALL_FUNCTION_VECTOR);
 306         exiting_irq();
 307 }
 308
 309 static inline void __smp_call_function_single_interrupt(void)
 310 {
 311         generic_smp_call_function_single_interrupt();
 312         inc_irq_stat(irq_call_count);
 313 }
 314
 315 __visible void smp_call_function_single_interrupt(struct pt_regs *regs)
 316 {
 317         ipi_entering_ack_irq();
 318         __smp_call_function_single_interrupt();
 319         exiting_irq();
 320 }
 321
 322 __visible void smp_trace_call_function_single_interrupt(struct pt_regs *regs)
 323 {
 324         ipi_entering_ack_irq();
 325         trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR);
 326         __smp_call_function_single_interrupt();
 327         trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR);
 328         exiting_irq();
 329 }
 330
 331 static int __init nonmi_ipi_setup(char *str)
 332 {
 333         smp_no_nmi_ipi = true;
 334         return 1;
 335 }
 336
 337 __setup("nonmi_ipi", nonmi_ipi_setup);
 338
 339 struct smp_ops smp_ops = {
 340         .smp_prepare_boot_cpu   = native_smp_prepare_boot_cpu,
 341         .smp_prepare_cpus       = native_smp_prepare_cpus,
 342         .smp_cpus_done          = native_smp_cpus_done,
 343
 344         .stop_other_cpus        = native_stop_other_cpus,
 345         .smp_send_reschedule    = native_smp_send_reschedule,
 346
 347         .cpu_up                 = native_cpu_up,
 348         .cpu_die                = native_cpu_die,
 349         .cpu_disable            = native_cpu_disable,
 350         .play_dead              = native_play_dead,
 351
 352         .send_call_func_ipi     = native_send_call_func_ipi,
 353         .send_call_func_single_ipi = native_send_call_func_single_ipi,
 354 };
 355 EXPORT_SYMBOL_GPL(smp_ops);