2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
53 #include <linux/cpuidle.h>
60 #include <asm/realmode.h>
63 #include <asm/pgtable.h>
64 #include <asm/tlbflush.h>
66 #include <asm/mwait.h>
68 #include <asm/io_apic.h>
69 #include <asm/setup.h>
70 #include <asm/uv/uv.h>
71 #include <linux/mc146818rtc.h>
73 #include <asm/smpboot_hooks.h>
74 #include <asm/i8259.h>
76 #include <asm/realmode.h>
78 /* State of each CPU */
79 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
81 #ifdef CONFIG_HOTPLUG_CPU
83 * We need this for trampoline_base protection from concurrent accesses when
84 * off- and onlining cores wildly.
86 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex
);
88 void cpu_hotplug_driver_lock(void)
90 mutex_lock(&x86_cpu_hotplug_driver_mutex
);
93 void cpu_hotplug_driver_unlock(void)
95 mutex_unlock(&x86_cpu_hotplug_driver_mutex
);
98 ssize_t
arch_cpu_probe(const char *buf
, size_t count
) { return -1; }
99 ssize_t
arch_cpu_release(const char *buf
, size_t count
) { return -1; }
102 /* Number of siblings per CPU package */
103 int smp_num_siblings
= 1;
104 EXPORT_SYMBOL(smp_num_siblings
);
106 /* Last level cache ID of each logical CPU */
107 DEFINE_PER_CPU(u16
, cpu_llc_id
) = BAD_APICID
;
109 /* representing HT siblings of each logical CPU */
110 DEFINE_PER_CPU(cpumask_var_t
, cpu_sibling_map
);
111 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
113 /* representing HT and core siblings of each logical CPU */
114 DEFINE_PER_CPU(cpumask_var_t
, cpu_core_map
);
115 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
117 DEFINE_PER_CPU(cpumask_var_t
, cpu_llc_shared_map
);
119 /* Per CPU bogomips and other parameters */
120 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86
, cpu_info
);
121 EXPORT_PER_CPU_SYMBOL(cpu_info
);
123 atomic_t init_deasserted
;
126 * Report back to the Boot Processor.
129 static void __cpuinit
smp_callin(void)
132 unsigned long timeout
;
135 * If waken up by an INIT in an 82489DX configuration
136 * we may get here before an INIT-deassert IPI reaches
137 * our local APIC. We have to wait for the IPI or we'll
138 * lock up on an APIC access.
140 if (apic
->wait_for_init_deassert
)
141 apic
->wait_for_init_deassert(&init_deasserted
);
144 * (This works even if the APIC is not enabled.)
146 phys_id
= read_apic_id();
147 cpuid
= smp_processor_id();
148 if (cpumask_test_cpu(cpuid
, cpu_callin_mask
)) {
149 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__
,
152 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid
, phys_id
);
155 * STARTUP IPIs are fragile beasts as they might sometimes
156 * trigger some glue motherboard logic. Complete APIC bus
157 * silence for 1 second, this overestimates the time the
158 * boot CPU is spending to send the up to 2 STARTUP IPIs
159 * by a factor of two. This should be enough.
163 * Waiting 2s total for startup (udelay is not yet working)
165 timeout
= jiffies
+ 2*HZ
;
166 while (time_before(jiffies
, timeout
)) {
168 * Has the boot CPU finished it's STARTUP sequence?
170 if (cpumask_test_cpu(cpuid
, cpu_callout_mask
))
175 if (!time_before(jiffies
, timeout
)) {
176 panic("%s: CPU%d started up but did not get a callout!\n",
181 * the boot CPU has finished the init stage and is spinning
182 * on callin_map until we finish. We are free to set up this
183 * CPU, first the APIC. (this is probably redundant on most
187 pr_debug("CALLIN, before setup_local_APIC().\n");
188 if (apic
->smp_callin_clear_local_apic
)
189 apic
->smp_callin_clear_local_apic();
191 end_local_APIC_setup();
194 * Need to setup vector mappings before we enable interrupts.
196 setup_vector_irq(smp_processor_id());
199 * Save our processor parameters. Note: this information
200 * is needed for clock calibration.
202 smp_store_cpu_info(cpuid
);
206 * Update loops_per_jiffy in cpu_data. Previous call to
207 * smp_store_cpu_info() stored a value that is close but not as
208 * accurate as the value just calculated.
211 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
212 pr_debug("Stack at about %p\n", &cpuid
);
215 * This must be done before setting cpu_online_mask
216 * or calling notify_cpu_starting.
218 set_cpu_sibling_map(raw_smp_processor_id());
221 notify_cpu_starting(cpuid
);
224 * Allow the master to continue.
226 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
230 * Activate a secondary processor.
232 notrace
static void __cpuinit
start_secondary(void *unused
)
235 * Don't put *anything* before cpu_init(), SMP booting is too
236 * fragile that we want to limit the things done here to the
237 * most necessary things.
240 x86_cpuinit
.early_percpu_clock_init();
245 /* switch away from the initial page table */
246 load_cr3(swapper_pg_dir
);
250 /* otherwise gcc will move up smp_processor_id before the cpu_init */
253 * Check TSC synchronization with the BP:
255 check_tsc_sync_target();
258 * We need to hold call_lock, so there is no inconsistency
259 * between the time smp_call_function() determines number of
260 * IPI recipients, and the time when the determination is made
261 * for which cpus receive the IPI. Holding this
262 * lock helps us to not include this cpu in a currently in progress
263 * smp_call_function().
265 * We need to hold vector_lock so there the set of online cpus
266 * does not change while we are assigning vectors to cpus. Holding
267 * this lock ensures we don't half assign or remove an irq from a cpu.
271 set_cpu_online(smp_processor_id(), true);
272 unlock_vector_lock();
274 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
275 x86_platform
.nmi_init();
277 /* enable local interrupts */
280 /* to prevent fake stack check failure in clock setup */
281 boot_init_stack_canary();
283 x86_cpuinit
.setup_percpu_clockev();
290 * The bootstrap kernel entry code has set these up. Save them for
294 void __cpuinit
smp_store_cpu_info(int id
)
296 struct cpuinfo_x86
*c
= &cpu_data(id
);
301 identify_secondary_cpu(c
);
304 static bool __cpuinit
305 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
307 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
309 return !WARN_ONCE(cpu_to_node(cpu1
) != cpu_to_node(cpu2
),
310 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
311 "[node: %d != %d]. Ignoring dependency.\n",
312 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
315 #define link_mask(_m, c1, c2) \
317 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
318 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
321 static bool __cpuinit
match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
323 if (cpu_has(c
, X86_FEATURE_TOPOEXT
)) {
324 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
326 if (c
->phys_proc_id
== o
->phys_proc_id
&&
327 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
) &&
328 c
->compute_unit_id
== o
->compute_unit_id
)
329 return topology_sane(c
, o
, "smt");
331 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
332 c
->cpu_core_id
== o
->cpu_core_id
) {
333 return topology_sane(c
, o
, "smt");
339 static bool __cpuinit
match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
341 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
343 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
344 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
345 return topology_sane(c
, o
, "llc");
350 static bool __cpuinit
match_mc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
352 if (c
->phys_proc_id
== o
->phys_proc_id
)
353 return topology_sane(c
, o
, "mc");
358 void __cpuinit
set_cpu_sibling_map(int cpu
)
360 bool has_mc
= boot_cpu_data
.x86_max_cores
> 1;
361 bool has_smt
= smp_num_siblings
> 1;
362 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
363 struct cpuinfo_x86
*o
;
366 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
368 if (!has_smt
&& !has_mc
) {
369 cpumask_set_cpu(cpu
, cpu_sibling_mask(cpu
));
370 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
371 cpumask_set_cpu(cpu
, cpu_core_mask(cpu
));
376 for_each_cpu(i
, cpu_sibling_setup_mask
) {
379 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
380 link_mask(sibling
, cpu
, i
);
382 if ((i
== cpu
) || (has_mc
&& match_llc(c
, o
)))
383 link_mask(llc_shared
, cpu
, i
);
388 * This needs a separate iteration over the cpus because we rely on all
389 * cpu_sibling_mask links to be set-up.
391 for_each_cpu(i
, cpu_sibling_setup_mask
) {
394 if ((i
== cpu
) || (has_mc
&& match_mc(c
, o
))) {
395 link_mask(core
, cpu
, i
);
398 * Does this new cpu bringup a new core?
400 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1) {
402 * for each core in package, increment
403 * the booted_cores for this new cpu
405 if (cpumask_first(cpu_sibling_mask(i
)) == i
)
408 * increment the core count for all
409 * the other cpus in this package
412 cpu_data(i
).booted_cores
++;
413 } else if (i
!= cpu
&& !c
->booted_cores
)
414 c
->booted_cores
= cpu_data(i
).booted_cores
;
419 /* maps the cpu to the sched domain representing multi-core */
420 const struct cpumask
*cpu_coregroup_mask(int cpu
)
422 return cpu_llc_shared_mask(cpu
);
425 static void impress_friends(void)
428 unsigned long bogosum
= 0;
430 * Allow the user to impress friends.
432 pr_debug("Before bogomips.\n");
433 for_each_possible_cpu(cpu
)
434 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
435 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
437 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
440 (bogosum
/(5000/HZ
))%100);
442 pr_debug("Before bogocount - setting activated=1.\n");
445 void __inquire_remote_apic(int apicid
)
447 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
448 const char * const names
[] = { "ID", "VERSION", "SPIV" };
452 printk(KERN_INFO
"Inquiring remote APIC 0x%x...\n", apicid
);
454 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
455 printk(KERN_INFO
"... APIC 0x%x %s: ", apicid
, names
[i
]);
460 status
= safe_apic_wait_icr_idle();
463 "a previous APIC delivery may have failed\n");
465 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
470 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
471 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
474 case APIC_ICR_RR_VALID
:
475 status
= apic_read(APIC_RRR
);
476 printk(KERN_CONT
"%08x\n", status
);
479 printk(KERN_CONT
"failed\n");
485 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
486 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
487 * won't ... remember to clear down the APIC, etc later.
490 wakeup_secondary_cpu_via_nmi(int logical_apicid
, unsigned long start_eip
)
492 unsigned long send_status
, accept_status
= 0;
496 /* Boot on the stack */
497 /* Kick the second */
498 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, logical_apicid
);
500 pr_debug("Waiting for send to finish...\n");
501 send_status
= safe_apic_wait_icr_idle();
504 * Give the other CPU some time to accept the IPI.
507 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
508 maxlvt
= lapic_get_maxlvt();
509 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
510 apic_write(APIC_ESR
, 0);
511 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
513 pr_debug("NMI sent.\n");
516 printk(KERN_ERR
"APIC never delivered???\n");
518 printk(KERN_ERR
"APIC delivery error (%lx).\n", accept_status
);
520 return (send_status
| accept_status
);
524 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
526 unsigned long send_status
, accept_status
= 0;
527 int maxlvt
, num_starts
, j
;
529 maxlvt
= lapic_get_maxlvt();
532 * Be paranoid about clearing APIC errors.
534 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
535 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
536 apic_write(APIC_ESR
, 0);
540 pr_debug("Asserting INIT.\n");
543 * Turn INIT on target chip
548 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
551 pr_debug("Waiting for send to finish...\n");
552 send_status
= safe_apic_wait_icr_idle();
556 pr_debug("Deasserting INIT.\n");
560 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
562 pr_debug("Waiting for send to finish...\n");
563 send_status
= safe_apic_wait_icr_idle();
566 atomic_set(&init_deasserted
, 1);
569 * Should we send STARTUP IPIs ?
571 * Determine this based on the APIC version.
572 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
574 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
580 * Paravirt / VMI wants a startup IPI hook here to set up the
581 * target processor state.
583 startup_ipi_hook(phys_apicid
, (unsigned long) start_secondary
,
587 * Run STARTUP IPI loop.
589 pr_debug("#startup loops: %d.\n", num_starts
);
591 for (j
= 1; j
<= num_starts
; j
++) {
592 pr_debug("Sending STARTUP #%d.\n", j
);
593 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
594 apic_write(APIC_ESR
, 0);
596 pr_debug("After apic_write.\n");
603 /* Boot on the stack */
604 /* Kick the second */
605 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
609 * Give the other CPU some time to accept the IPI.
613 pr_debug("Startup point 1.\n");
615 pr_debug("Waiting for send to finish...\n");
616 send_status
= safe_apic_wait_icr_idle();
619 * Give the other CPU some time to accept the IPI.
622 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
623 apic_write(APIC_ESR
, 0);
624 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
625 if (send_status
|| accept_status
)
628 pr_debug("After Startup.\n");
631 printk(KERN_ERR
"APIC never delivered???\n");
633 printk(KERN_ERR
"APIC delivery error (%lx).\n", accept_status
);
635 return (send_status
| accept_status
);
638 /* reduce the number of lines printed when booting a large cpu count system */
639 static void __cpuinit
announce_cpu(int cpu
, int apicid
)
641 static int current_node
= -1;
642 int node
= early_cpu_to_node(cpu
);
644 if (system_state
== SYSTEM_BOOTING
) {
645 if (node
!= current_node
) {
646 if (current_node
> (-1))
649 pr_info("Booting Node %3d, Processors ", node
);
651 pr_cont(" #%d%s", cpu
, cpu
== (nr_cpu_ids
- 1) ? " Ok.\n" : "");
654 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
659 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
660 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
661 * Returns zero if CPU booted OK, else error code from
662 * ->wakeup_secondary_cpu.
664 static int __cpuinit
do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
)
666 volatile u32
*trampoline_status
=
667 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
668 /* start_ip had better be page-aligned! */
669 unsigned long start_ip
= real_mode_header
->trampoline_start
;
671 unsigned long boot_error
= 0;
674 alternatives_smp_switch(1);
676 idle
->thread
.sp
= (unsigned long) (((struct pt_regs
*)
677 (THREAD_SIZE
+ task_stack_page(idle
))) - 1);
678 per_cpu(current_task
, cpu
) = idle
;
681 /* Stack for startup_32 can be just as for start_secondary onwards */
684 clear_tsk_thread_flag(idle
, TIF_FORK
);
685 initial_gs
= per_cpu_offset(cpu
);
686 per_cpu(kernel_stack
, cpu
) =
687 (unsigned long)task_stack_page(idle
) -
688 KERNEL_STACK_OFFSET
+ THREAD_SIZE
;
690 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
691 initial_code
= (unsigned long)start_secondary
;
692 stack_start
= idle
->thread
.sp
;
694 /* So we see what's up */
695 announce_cpu(cpu
, apicid
);
698 * This grunge runs the startup process for
699 * the targeted processor.
702 atomic_set(&init_deasserted
, 0);
704 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
706 pr_debug("Setting warm reset code and vector.\n");
708 smpboot_setup_warm_reset_vector(start_ip
);
710 * Be paranoid about clearing APIC errors.
712 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
713 apic_write(APIC_ESR
, 0);
719 * Kick the secondary CPU. Use the method in the APIC driver
720 * if it's defined - or use an INIT boot APIC message otherwise:
722 if (apic
->wakeup_secondary_cpu
)
723 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
725 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
729 * allow APs to start initializing.
731 pr_debug("Before Callout %d.\n", cpu
);
732 cpumask_set_cpu(cpu
, cpu_callout_mask
);
733 pr_debug("After Callout %d.\n", cpu
);
736 * Wait 5s total for a response
738 for (timeout
= 0; timeout
< 50000; timeout
++) {
739 if (cpumask_test_cpu(cpu
, cpu_callin_mask
))
740 break; /* It has booted */
743 * Allow other tasks to run while we wait for the
744 * AP to come online. This also gives a chance
745 * for the MTRR work(triggered by the AP coming online)
746 * to be completed in the stop machine context.
751 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
752 print_cpu_msr(&cpu_data(cpu
));
753 pr_debug("CPU%d: has booted.\n", cpu
);
756 if (*trampoline_status
== 0xA5A5A5A5)
757 /* trampoline started but...? */
758 pr_err("CPU%d: Stuck ??\n", cpu
);
760 /* trampoline code not run */
761 pr_err("CPU%d: Not responding.\n", cpu
);
762 if (apic
->inquire_remote_apic
)
763 apic
->inquire_remote_apic(apicid
);
768 /* Try to put things back the way they were before ... */
769 numa_remove_cpu(cpu
); /* was set by numa_add_cpu */
771 /* was set by do_boot_cpu() */
772 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
774 /* was set by cpu_init() */
775 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
777 set_cpu_present(cpu
, false);
778 per_cpu(x86_cpu_to_apicid
, cpu
) = BAD_APICID
;
781 /* mark "stuck" area as not stuck */
782 *trampoline_status
= 0;
784 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
786 * Cleanup possible dangling ends...
788 smpboot_restore_warm_reset_vector();
793 int __cpuinit
native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
795 int apicid
= apic
->cpu_present_to_apicid(cpu
);
799 WARN_ON(irqs_disabled());
801 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
803 if (apicid
== BAD_APICID
|| apicid
== boot_cpu_physical_apicid
||
804 !physid_isset(apicid
, phys_cpu_present_map
) ||
805 !apic
->apic_id_valid(apicid
)) {
806 printk(KERN_ERR
"%s: bad cpu %d\n", __func__
, cpu
);
811 * Already booted CPU?
813 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
814 pr_debug("do_boot_cpu %d Already started\n", cpu
);
819 * Save current MTRR state in case it was changed since early boot
820 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
824 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
826 err
= do_boot_cpu(apicid
, cpu
, tidle
);
828 pr_debug("do_boot_cpu failed %d\n", err
);
833 * Check TSC synchronization with the AP (keep irqs disabled
836 local_irq_save(flags
);
837 check_tsc_sync_source(cpu
);
838 local_irq_restore(flags
);
840 while (!cpu_online(cpu
)) {
842 touch_nmi_watchdog();
849 * arch_disable_smp_support() - disables SMP support for x86 at runtime
851 void arch_disable_smp_support(void)
853 disable_ioapic_support();
857 * Fall back to non SMP mode after errors.
859 * RED-PEN audit/test this more. I bet there is more state messed up here.
861 static __init
void disable_smp(void)
863 init_cpu_present(cpumask_of(0));
864 init_cpu_possible(cpumask_of(0));
865 smpboot_clear_io_apic_irqs();
867 if (smp_found_config
)
868 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
870 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
871 cpumask_set_cpu(0, cpu_sibling_mask(0));
872 cpumask_set_cpu(0, cpu_core_mask(0));
876 * Various sanity checks.
878 static int __init
smp_sanity_check(unsigned max_cpus
)
882 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
883 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
888 "More than 8 CPUs detected - skipping them.\n"
889 "Use CONFIG_X86_BIGSMP.\n");
892 for_each_present_cpu(cpu
) {
894 set_cpu_present(cpu
, false);
899 for_each_possible_cpu(cpu
) {
901 set_cpu_possible(cpu
, false);
909 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
911 "weird, boot CPU (#%d) not listed by the BIOS.\n",
912 hard_smp_processor_id());
914 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
918 * If we couldn't find an SMP configuration at boot time,
919 * get out of here now!
921 if (!smp_found_config
&& !acpi_lapic
) {
923 printk(KERN_NOTICE
"SMP motherboard not detected.\n");
925 if (APIC_init_uniprocessor())
926 printk(KERN_NOTICE
"Local APIC not detected."
927 " Using dummy APIC emulation.\n");
932 * Should not be necessary because the MP table should list the boot
933 * CPU too, but we do it for the sake of robustness anyway.
935 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
937 "weird, boot CPU (#%d) not listed by the BIOS.\n",
938 boot_cpu_physical_apicid
);
939 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
944 * If we couldn't find a local APIC, then get out of here now!
946 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) &&
949 pr_err("BIOS bug, local APIC #%d not detected!...\n",
950 boot_cpu_physical_apicid
);
951 pr_err("... forcing use of dummy APIC emulation."
952 "(tell your hw vendor)\n");
954 smpboot_clear_io_apic();
955 disable_ioapic_support();
962 * If SMP should be disabled, then really disable it!
965 printk(KERN_INFO
"SMP mode deactivated.\n");
966 smpboot_clear_io_apic();
970 bsp_end_local_APIC_setup();
977 static void __init
smp_cpu_index_default(void)
980 struct cpuinfo_x86
*c
;
982 for_each_possible_cpu(i
) {
984 /* mark all to hotplug */
985 c
->cpu_index
= nr_cpu_ids
;
990 * Prepare for SMP bootup. The MP table or ACPI has been read
991 * earlier. Just do some sanity checking here and enable APIC mode.
993 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
998 smp_cpu_index_default();
1001 * Setup boot CPU information
1003 smp_store_cpu_info(0); /* Final full version of the data */
1004 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1007 current_thread_info()->cpu
= 0; /* needed? */
1008 for_each_possible_cpu(i
) {
1009 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1010 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1011 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1013 set_cpu_sibling_map(0);
1016 if (smp_sanity_check(max_cpus
) < 0) {
1017 printk(KERN_INFO
"SMP disabled\n");
1022 default_setup_apic_routing();
1025 if (read_apic_id() != boot_cpu_physical_apicid
) {
1026 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1027 read_apic_id(), boot_cpu_physical_apicid
);
1028 /* Or can we switch back to PIC here? */
1035 * Switch from PIC to APIC mode.
1040 * Enable IO APIC before setting up error vector
1042 if (!skip_ioapic_setup
&& nr_ioapics
)
1045 bsp_end_local_APIC_setup();
1047 if (apic
->setup_portio_remap
)
1048 apic
->setup_portio_remap();
1050 smpboot_setup_io_apic();
1052 * Set up local APIC timer on boot CPU.
1055 printk(KERN_INFO
"CPU%d: ", 0);
1056 print_cpu_info(&cpu_data(0));
1057 x86_init
.timers
.setup_percpu_clockev();
1062 set_mtrr_aps_delayed_init();
1067 void arch_disable_nonboot_cpus_begin(void)
1070 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1071 * In the suspend path, we will be back in the SMP mode shortly anyways.
1073 skip_smp_alternatives
= true;
1076 void arch_disable_nonboot_cpus_end(void)
1078 skip_smp_alternatives
= false;
1081 void arch_enable_nonboot_cpus_begin(void)
1083 set_mtrr_aps_delayed_init();
1086 void arch_enable_nonboot_cpus_end(void)
1092 * Early setup to make printk work.
1094 void __init
native_smp_prepare_boot_cpu(void)
1096 int me
= smp_processor_id();
1097 switch_to_new_gdt(me
);
1098 /* already set me in cpu_online_mask in boot_cpu_init() */
1099 cpumask_set_cpu(me
, cpu_callout_mask
);
1100 per_cpu(cpu_state
, me
) = CPU_ONLINE
;
1103 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1105 pr_debug("Boot done.\n");
1109 #ifdef CONFIG_X86_IO_APIC
1110 setup_ioapic_dest();
1115 static int __initdata setup_possible_cpus
= -1;
1116 static int __init
_setup_possible_cpus(char *str
)
1118 get_option(&str
, &setup_possible_cpus
);
1121 early_param("possible_cpus", _setup_possible_cpus
);
1125 * cpu_possible_mask should be static, it cannot change as cpu's
1126 * are onlined, or offlined. The reason is per-cpu data-structures
1127 * are allocated by some modules at init time, and dont expect to
1128 * do this dynamically on cpu arrival/departure.
1129 * cpu_present_mask on the other hand can change dynamically.
1130 * In case when cpu_hotplug is not compiled, then we resort to current
1131 * behaviour, which is cpu_possible == cpu_present.
1134 * Three ways to find out the number of additional hotplug CPUs:
1135 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1136 * - The user can overwrite it with possible_cpus=NUM
1137 * - Otherwise don't reserve additional CPUs.
1138 * We do this because additional CPUs waste a lot of memory.
1141 __init
void prefill_possible_map(void)
1145 /* no processor from mptable or madt */
1146 if (!num_processors
)
1149 i
= setup_max_cpus
?: 1;
1150 if (setup_possible_cpus
== -1) {
1151 possible
= num_processors
;
1152 #ifdef CONFIG_HOTPLUG_CPU
1154 possible
+= disabled_cpus
;
1160 possible
= setup_possible_cpus
;
1162 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1164 /* nr_cpu_ids could be reduced via nr_cpus= */
1165 if (possible
> nr_cpu_ids
) {
1167 "%d Processors exceeds NR_CPUS limit of %d\n",
1168 possible
, nr_cpu_ids
);
1169 possible
= nr_cpu_ids
;
1172 #ifdef CONFIG_HOTPLUG_CPU
1173 if (!setup_max_cpus
)
1177 "%d Processors exceeds max_cpus limit of %u\n",
1178 possible
, setup_max_cpus
);
1182 printk(KERN_INFO
"SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1183 possible
, max_t(int, possible
- num_processors
, 0));
1185 for (i
= 0; i
< possible
; i
++)
1186 set_cpu_possible(i
, true);
1187 for (; i
< NR_CPUS
; i
++)
1188 set_cpu_possible(i
, false);
1190 nr_cpu_ids
= possible
;
1193 #ifdef CONFIG_HOTPLUG_CPU
1195 static void remove_siblinginfo(int cpu
)
1198 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1200 for_each_cpu(sibling
, cpu_core_mask(cpu
)) {
1201 cpumask_clear_cpu(cpu
, cpu_core_mask(sibling
));
1203 * last thread sibling in this cpu core going down
1205 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1)
1206 cpu_data(sibling
).booted_cores
--;
1209 for_each_cpu(sibling
, cpu_sibling_mask(cpu
))
1210 cpumask_clear_cpu(cpu
, cpu_sibling_mask(sibling
));
1211 cpumask_clear(cpu_sibling_mask(cpu
));
1212 cpumask_clear(cpu_core_mask(cpu
));
1213 c
->phys_proc_id
= 0;
1215 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1218 static void __ref
remove_cpu_from_maps(int cpu
)
1220 set_cpu_online(cpu
, false);
1221 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1222 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1223 /* was set by cpu_init() */
1224 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1225 numa_remove_cpu(cpu
);
1228 void cpu_disable_common(void)
1230 int cpu
= smp_processor_id();
1232 remove_siblinginfo(cpu
);
1234 /* It's now safe to remove this processor from the online map */
1236 remove_cpu_from_maps(cpu
);
1237 unlock_vector_lock();
1241 int native_cpu_disable(void)
1243 int cpu
= smp_processor_id();
1246 * Perhaps use cpufreq to drop frequency, but that could go
1247 * into generic code.
1249 * We won't take down the boot processor on i386 due to some
1250 * interrupts only being able to be serviced by the BSP.
1251 * Especially so if we're not using an IOAPIC -zwane
1258 cpu_disable_common();
1262 void native_cpu_die(unsigned int cpu
)
1264 /* We don't do anything here: idle task is faking death itself. */
1267 for (i
= 0; i
< 10; i
++) {
1268 /* They ack this in play_dead by setting CPU_DEAD */
1269 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1270 if (system_state
== SYSTEM_RUNNING
)
1271 pr_info("CPU %u is now offline\n", cpu
);
1273 if (1 == num_online_cpus())
1274 alternatives_smp_switch(0);
1279 pr_err("CPU %u didn't die...\n", cpu
);
1282 void play_dead_common(void)
1285 reset_lazy_tlbstate();
1286 amd_e400_remove_cpu(raw_smp_processor_id());
1290 __this_cpu_write(cpu_state
, CPU_DEAD
);
1293 * With physical CPU hotplug, we should halt the cpu
1295 local_irq_disable();
1299 * We need to flush the caches before going to sleep, lest we have
1300 * dirty data in our caches when we come back up.
1302 static inline void mwait_play_dead(void)
1304 unsigned int eax
, ebx
, ecx
, edx
;
1305 unsigned int highest_cstate
= 0;
1306 unsigned int highest_subcstate
= 0;
1309 struct cpuinfo_x86
*c
= __this_cpu_ptr(&cpu_info
);
1311 if (!(this_cpu_has(X86_FEATURE_MWAIT
) && mwait_usable(c
)))
1313 if (!this_cpu_has(X86_FEATURE_CLFLSH
))
1315 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1318 eax
= CPUID_MWAIT_LEAF
;
1320 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1323 * eax will be 0 if EDX enumeration is not valid.
1324 * Initialized below to cstate, sub_cstate value when EDX is valid.
1326 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1329 edx
>>= MWAIT_SUBSTATE_SIZE
;
1330 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1331 if (edx
& MWAIT_SUBSTATE_MASK
) {
1333 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1336 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1337 (highest_subcstate
- 1);
1341 * This should be a memory location in a cache line which is
1342 * unlikely to be touched by other processors. The actual
1343 * content is immaterial as it is not actually modified in any way.
1345 mwait_ptr
= ¤t_thread_info()->flags
;
1351 * The CLFLUSH is a workaround for erratum AAI65 for
1352 * the Xeon 7400 series. It's not clear it is actually
1353 * needed, but it should be harmless in either case.
1354 * The WBINVD is insufficient due to the spurious-wakeup
1355 * case where we return around the loop.
1358 __monitor(mwait_ptr
, 0, 0);
1364 static inline void hlt_play_dead(void)
1366 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1374 void native_play_dead(void)
1377 tboot_shutdown(TB_SHUTDOWN_WFS
);
1379 mwait_play_dead(); /* Only returns on failure */
1380 if (cpuidle_play_dead())
1384 #else /* ... !CONFIG_HOTPLUG_CPU */
1385 int native_cpu_disable(void)
1390 void native_cpu_die(unsigned int cpu
)
1392 /* We said "no" in __cpu_disable */
1396 void native_play_dead(void)