2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
71 #include <asm/setup.h>
72 #include <asm/uv/uv.h>
73 #include <linux/mc146818rtc.h>
75 #include <asm/smpboot_hooks.h>
76 #include <asm/i8259.h>
78 #include <asm/realmode.h>
80 /* State of each CPU */
81 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
83 #ifdef CONFIG_HOTPLUG_CPU
85 * We need this for trampoline_base protection from concurrent accesses when
86 * off- and onlining cores wildly.
88 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex
);
90 void cpu_hotplug_driver_lock(void)
92 mutex_lock(&x86_cpu_hotplug_driver_mutex
);
95 void cpu_hotplug_driver_unlock(void)
97 mutex_unlock(&x86_cpu_hotplug_driver_mutex
);
100 ssize_t
arch_cpu_probe(const char *buf
, size_t count
) { return -1; }
101 ssize_t
arch_cpu_release(const char *buf
, size_t count
) { return -1; }
104 /* Number of siblings per CPU package */
105 int smp_num_siblings
= 1;
106 EXPORT_SYMBOL(smp_num_siblings
);
108 /* Last level cache ID of each logical CPU */
109 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
111 /* representing HT siblings of each logical CPU */
112 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
113 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
115 /* representing HT and core siblings of each logical CPU */
116 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
117 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
119 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
121 /* Per CPU bogomips and other parameters */
122 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86
, cpu_info
);
123 EXPORT_PER_CPU_SYMBOL(cpu_info
);
125 atomic_t init_deasserted
;
128 * Report back to the Boot Processor during boot time or to the caller processor
131 static void __cpuinit
smp_callin(void)
134 unsigned long timeout
;
137 * If waken up by an INIT in an 82489DX configuration
138 * we may get here before an INIT-deassert IPI reaches
139 * our local APIC. We have to wait for the IPI or we'll
140 * lock up on an APIC access.
142 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
144 cpuid
= smp_processor_id();
145 if (apic
->wait_for_init_deassert
&& cpuid
!= 0)
146 apic
->wait_for_init_deassert(&init_deasserted
);
149 * (This works even if the APIC is not enabled.)
151 phys_id
= read_apic_id();
152 if (cpumask_test_cpu(cpuid
, cpu_callin_mask
)) {
153 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__
,
156 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid
, phys_id
);
159 * STARTUP IPIs are fragile beasts as they might sometimes
160 * trigger some glue motherboard logic. Complete APIC bus
161 * silence for 1 second, this overestimates the time the
162 * boot CPU is spending to send the up to 2 STARTUP IPIs
163 * by a factor of two. This should be enough.
167 * Waiting 2s total for startup (udelay is not yet working)
169 timeout
= jiffies
+ 2*HZ
;
170 while (time_before(jiffies
, timeout
)) {
172 * Has the boot CPU finished it's STARTUP sequence?
174 if (cpumask_test_cpu(cpuid
, cpu_callout_mask
))
179 if (!time_before(jiffies
, timeout
)) {
180 panic("%s: CPU%d started up but did not get a callout!\n",
185 * the boot CPU has finished the init stage and is spinning
186 * on callin_map until we finish. We are free to set up this
187 * CPU, first the APIC. (this is probably redundant on most
191 pr_debug("CALLIN, before setup_local_APIC()\n");
192 if (apic
->smp_callin_clear_local_apic
)
193 apic
->smp_callin_clear_local_apic();
195 end_local_APIC_setup();
198 * Need to setup vector mappings before we enable interrupts.
200 setup_vector_irq(smp_processor_id());
203 * Save our processor parameters. Note: this information
204 * is needed for clock calibration.
206 smp_store_cpu_info(cpuid
);
210 * Update loops_per_jiffy in cpu_data. Previous call to
211 * smp_store_cpu_info() stored a value that is close but not as
212 * accurate as the value just calculated.
215 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
216 pr_debug("Stack at about %p\n", &cpuid
);
219 * This must be done before setting cpu_online_mask
220 * or calling notify_cpu_starting.
222 set_cpu_sibling_map(raw_smp_processor_id());
225 notify_cpu_starting(cpuid
);
228 * Allow the master to continue.
230 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
233 static int cpu0_logical_apicid
;
234 static int enable_start_cpu0
;
236 * Activate a secondary processor.
238 notrace
static void __cpuinit
start_secondary(void *unused
)
241 * Don't put *anything* before cpu_init(), SMP booting is too
242 * fragile that we want to limit the things done here to the
243 * most necessary things.
246 x86_cpuinit
.early_percpu_clock_init();
250 enable_start_cpu0
= 0;
253 /* switch away from the initial page table */
254 load_cr3(swapper_pg_dir
);
258 /* otherwise gcc will move up smp_processor_id before the cpu_init */
261 * Check TSC synchronization with the BP:
263 check_tsc_sync_target();
266 * We need to hold vector_lock so there the set of online cpus
267 * does not change while we are assigning vectors to cpus. Holding
268 * this lock ensures we don't half assign or remove an irq from a cpu.
271 set_cpu_online(smp_processor_id(), true);
272 unlock_vector_lock();
273 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
274 x86_platform
.nmi_init();
276 /* enable local interrupts */
279 /* to prevent fake stack check failure in clock setup */
280 boot_init_stack_canary();
282 x86_cpuinit
.setup_percpu_clockev();
288 void __init
smp_store_boot_cpu_info(void)
290 int id
= 0; /* CPU 0 */
291 struct cpuinfo_x86
*c
= &cpu_data(id
);
298 * The bootstrap kernel entry code has set these up. Save them for
301 void __cpuinit
smp_store_cpu_info(int id
)
303 struct cpuinfo_x86
*c
= &cpu_data(id
);
308 * During boot time, CPU0 has this setup already. Save the info when
309 * bringing up AP or offlined CPU0.
311 identify_secondary_cpu(c
);
314 static bool __cpuinit
315 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
317 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
319 return !WARN_ONCE(cpu_to_node(cpu1
) != cpu_to_node(cpu2
),
320 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
321 "[node: %d != %d]. Ignoring dependency.\n",
322 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
325 #define link_mask(_m, c1, c2) \
327 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
328 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
331 static bool __cpuinit
match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
333 if (cpu_has(c
, X86_FEATURE_TOPOEXT
)) {
334 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
336 if (c
->phys_proc_id
== o
->phys_proc_id
&&
337 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
) &&
338 c
->compute_unit_id
== o
->compute_unit_id
)
339 return topology_sane(c
, o
, "smt");
341 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
342 c
->cpu_core_id
== o
->cpu_core_id
) {
343 return topology_sane(c
, o
, "smt");
349 static bool __cpuinit
match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
351 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
353 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
354 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
355 return topology_sane(c
, o
, "llc");
360 static bool __cpuinit
match_mc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
362 if (c
->phys_proc_id
== o
->phys_proc_id
) {
363 if (cpu_has(c
, X86_FEATURE_AMD_DCM
))
366 return topology_sane(c
, o
, "mc");
371 void __cpuinit
set_cpu_sibling_map(int cpu
)
373 bool has_mc
= boot_cpu_data
.x86_max_cores
> 1;
374 bool has_smt
= smp_num_siblings
> 1;
375 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
376 struct cpuinfo_x86
*o
;
379 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
381 if (!has_smt
&& !has_mc
) {
382 cpumask_set_cpu(cpu
, cpu_sibling_mask(cpu
));
383 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
384 cpumask_set_cpu(cpu
, cpu_core_mask(cpu
));
389 for_each_cpu(i
, cpu_sibling_setup_mask
) {
392 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
393 link_mask(sibling
, cpu
, i
);
395 if ((i
== cpu
) || (has_mc
&& match_llc(c
, o
)))
396 link_mask(llc_shared
, cpu
, i
);
401 * This needs a separate iteration over the cpus because we rely on all
402 * cpu_sibling_mask links to be set-up.
404 for_each_cpu(i
, cpu_sibling_setup_mask
) {
407 if ((i
== cpu
) || (has_mc
&& match_mc(c
, o
))) {
408 link_mask(core
, cpu
, i
);
411 * Does this new cpu bringup a new core?
413 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1) {
415 * for each core in package, increment
416 * the booted_cores for this new cpu
418 if (cpumask_first(cpu_sibling_mask(i
)) == i
)
421 * increment the core count for all
422 * the other cpus in this package
425 cpu_data(i
).booted_cores
++;
426 } else if (i
!= cpu
&& !c
->booted_cores
)
427 c
->booted_cores
= cpu_data(i
).booted_cores
;
432 /* maps the cpu to the sched domain representing multi-core */
433 const struct cpumask
*cpu_coregroup_mask(int cpu
)
435 return cpu_llc_shared_mask(cpu
);
438 static void impress_friends(void)
441 unsigned long bogosum
= 0;
443 * Allow the user to impress friends.
445 pr_debug("Before bogomips\n");
446 for_each_possible_cpu(cpu
)
447 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
448 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
449 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
452 (bogosum
/(5000/HZ
))%100);
454 pr_debug("Before bogocount - setting activated=1\n");
457 void __inquire_remote_apic(int apicid
)
459 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
460 const char * const names
[] = { "ID", "VERSION", "SPIV" };
464 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
466 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
467 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
472 status
= safe_apic_wait_icr_idle();
474 pr_cont("a previous APIC delivery may have failed\n");
476 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
481 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
482 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
485 case APIC_ICR_RR_VALID
:
486 status
= apic_read(APIC_RRR
);
487 pr_cont("%08x\n", status
);
496 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
497 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
498 * won't ... remember to clear down the APIC, etc later.
501 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
503 unsigned long send_status
, accept_status
= 0;
507 /* Boot on the stack */
508 /* Kick the second */
509 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
511 pr_debug("Waiting for send to finish...\n");
512 send_status
= safe_apic_wait_icr_idle();
515 * Give the other CPU some time to accept the IPI.
518 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
519 maxlvt
= lapic_get_maxlvt();
520 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
521 apic_write(APIC_ESR
, 0);
522 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
524 pr_debug("NMI sent\n");
527 pr_err("APIC never delivered???\n");
529 pr_err("APIC delivery error (%lx)\n", accept_status
);
531 return (send_status
| accept_status
);
535 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
537 unsigned long send_status
, accept_status
= 0;
538 int maxlvt
, num_starts
, j
;
540 maxlvt
= lapic_get_maxlvt();
543 * Be paranoid about clearing APIC errors.
545 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
546 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
547 apic_write(APIC_ESR
, 0);
551 pr_debug("Asserting INIT\n");
554 * Turn INIT on target chip
559 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
562 pr_debug("Waiting for send to finish...\n");
563 send_status
= safe_apic_wait_icr_idle();
567 pr_debug("Deasserting INIT\n");
571 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
573 pr_debug("Waiting for send to finish...\n");
574 send_status
= safe_apic_wait_icr_idle();
577 atomic_set(&init_deasserted
, 1);
580 * Should we send STARTUP IPIs ?
582 * Determine this based on the APIC version.
583 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
585 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
591 * Paravirt / VMI wants a startup IPI hook here to set up the
592 * target processor state.
594 startup_ipi_hook(phys_apicid
, (unsigned long) start_secondary
,
598 * Run STARTUP IPI loop.
600 pr_debug("#startup loops: %d\n", num_starts
);
602 for (j
= 1; j
<= num_starts
; j
++) {
603 pr_debug("Sending STARTUP #%d\n", j
);
604 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
605 apic_write(APIC_ESR
, 0);
607 pr_debug("After apic_write\n");
614 /* Boot on the stack */
615 /* Kick the second */
616 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
620 * Give the other CPU some time to accept the IPI.
624 pr_debug("Startup point 1\n");
626 pr_debug("Waiting for send to finish...\n");
627 send_status
= safe_apic_wait_icr_idle();
630 * Give the other CPU some time to accept the IPI.
633 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
634 apic_write(APIC_ESR
, 0);
635 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
636 if (send_status
|| accept_status
)
639 pr_debug("After Startup\n");
642 pr_err("APIC never delivered???\n");
644 pr_err("APIC delivery error (%lx)\n", accept_status
);
646 return (send_status
| accept_status
);
649 /* reduce the number of lines printed when booting a large cpu count system */
650 static void __cpuinit
announce_cpu(int cpu
, int apicid
)
652 static int current_node
= -1;
653 int node
= early_cpu_to_node(cpu
);
655 if (system_state
== SYSTEM_BOOTING
) {
656 if (node
!= current_node
) {
657 if (current_node
> (-1))
660 pr_info("Booting Node %3d, Processors ", node
);
662 pr_cont(" #%d%s", cpu
, cpu
== (nr_cpu_ids
- 1) ? " OK\n" : "");
665 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
669 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
673 cpu
= smp_processor_id();
674 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
681 * Wake up AP by INIT, INIT, STARTUP sequence.
683 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
684 * boot-strap code which is not a desired behavior for waking up BSP. To
685 * void the boot-strap code, wake up CPU0 by NMI instead.
687 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
688 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
689 * We'll change this code in the future to wake up hard offlined CPU0 if
690 * real platform and request are available.
693 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
694 int *cpu0_nmi_registered
)
700 * Wake up AP by INIT, INIT, STARTUP sequence.
703 return wakeup_secondary_cpu_via_init(apicid
, start_ip
);
706 * Wake up BSP by nmi.
708 * Register a NMI handler to help wake up CPU0.
710 boot_error
= register_nmi_handler(NMI_LOCAL
,
711 wakeup_cpu0_nmi
, 0, "wake_cpu0");
714 enable_start_cpu0
= 1;
715 *cpu0_nmi_registered
= 1;
716 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
717 id
= cpu0_logical_apicid
;
720 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
727 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
728 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
729 * Returns zero if CPU booted OK, else error code from
730 * ->wakeup_secondary_cpu.
732 static int __cpuinit
do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
)
734 volatile u32
*trampoline_status
=
735 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
736 /* start_ip had better be page-aligned! */
737 unsigned long start_ip
= real_mode_header
->trampoline_start
;
739 unsigned long boot_error
= 0;
741 int cpu0_nmi_registered
= 0;
743 /* Just in case we booted with a single CPU. */
744 alternatives_enable_smp();
746 idle
->thread
.sp
= (unsigned long) (((struct pt_regs
*)
747 (THREAD_SIZE
+ task_stack_page(idle
))) - 1);
748 per_cpu(current_task
, cpu
) = idle
;
751 /* Stack for startup_32 can be just as for start_secondary onwards */
754 clear_tsk_thread_flag(idle
, TIF_FORK
);
755 initial_gs
= per_cpu_offset(cpu
);
756 per_cpu(kernel_stack
, cpu
) =
757 (unsigned long)task_stack_page(idle
) -
758 KERNEL_STACK_OFFSET
+ THREAD_SIZE
;
760 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
761 initial_code
= (unsigned long)start_secondary
;
762 stack_start
= idle
->thread
.sp
;
764 /* So we see what's up */
765 announce_cpu(cpu
, apicid
);
768 * This grunge runs the startup process for
769 * the targeted processor.
772 atomic_set(&init_deasserted
, 0);
774 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
776 pr_debug("Setting warm reset code and vector.\n");
778 smpboot_setup_warm_reset_vector(start_ip
);
780 * Be paranoid about clearing APIC errors.
782 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
783 apic_write(APIC_ESR
, 0);
789 * Wake up a CPU in difference cases:
790 * - Use the method in the APIC driver if it's defined
792 * - Use an INIT boot APIC message for APs or NMI for BSP.
794 if (apic
->wakeup_secondary_cpu
)
795 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
797 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
798 &cpu0_nmi_registered
);
802 * allow APs to start initializing.
804 pr_debug("Before Callout %d\n", cpu
);
805 cpumask_set_cpu(cpu
, cpu_callout_mask
);
806 pr_debug("After Callout %d\n", cpu
);
809 * Wait 5s total for a response
811 for (timeout
= 0; timeout
< 50000; timeout
++) {
812 if (cpumask_test_cpu(cpu
, cpu_callin_mask
))
813 break; /* It has booted */
816 * Allow other tasks to run while we wait for the
817 * AP to come online. This also gives a chance
818 * for the MTRR work(triggered by the AP coming online)
819 * to be completed in the stop machine context.
824 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
825 print_cpu_msr(&cpu_data(cpu
));
826 pr_debug("CPU%d: has booted.\n", cpu
);
829 if (*trampoline_status
== 0xA5A5A5A5)
830 /* trampoline started but...? */
831 pr_err("CPU%d: Stuck ??\n", cpu
);
833 /* trampoline code not run */
834 pr_err("CPU%d: Not responding\n", cpu
);
835 if (apic
->inquire_remote_apic
)
836 apic
->inquire_remote_apic(apicid
);
841 /* Try to put things back the way they were before ... */
842 numa_remove_cpu(cpu
); /* was set by numa_add_cpu */
844 /* was set by do_boot_cpu() */
845 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
847 /* was set by cpu_init() */
848 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
850 set_cpu_present(cpu
, false);
851 per_cpu(x86_cpu_to_apicid
, cpu
) = BAD_APICID
;
854 /* mark "stuck" area as not stuck */
855 *trampoline_status
= 0;
857 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
859 * Cleanup possible dangling ends...
861 smpboot_restore_warm_reset_vector();
864 * Clean up the nmi handler. Do this after the callin and callout sync
865 * to avoid impact of possible long unregister time.
867 if (cpu0_nmi_registered
)
868 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
873 int __cpuinit
native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
875 int apicid
= apic
->cpu_present_to_apicid(cpu
);
879 WARN_ON(irqs_disabled());
881 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
883 if (apicid
== BAD_APICID
||
884 !physid_isset(apicid
, phys_cpu_present_map
) ||
885 !apic
->apic_id_valid(apicid
)) {
886 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
891 * Already booted CPU?
893 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
894 pr_debug("do_boot_cpu %d Already started\n", cpu
);
899 * Save current MTRR state in case it was changed since early boot
900 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
904 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
906 err
= do_boot_cpu(apicid
, cpu
, tidle
);
908 pr_debug("do_boot_cpu failed %d\n", err
);
913 * Check TSC synchronization with the AP (keep irqs disabled
916 local_irq_save(flags
);
917 check_tsc_sync_source(cpu
);
918 local_irq_restore(flags
);
920 while (!cpu_online(cpu
)) {
922 touch_nmi_watchdog();
929 * arch_disable_smp_support() - disables SMP support for x86 at runtime
931 void arch_disable_smp_support(void)
933 disable_ioapic_support();
937 * Fall back to non SMP mode after errors.
939 * RED-PEN audit/test this more. I bet there is more state messed up here.
941 static __init
void disable_smp(void)
943 init_cpu_present(cpumask_of(0));
944 init_cpu_possible(cpumask_of(0));
945 smpboot_clear_io_apic_irqs();
947 if (smp_found_config
)
948 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
950 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
951 cpumask_set_cpu(0, cpu_sibling_mask(0));
952 cpumask_set_cpu(0, cpu_core_mask(0));
956 * Various sanity checks.
958 static int __init
smp_sanity_check(unsigned max_cpus
)
962 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
963 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
967 pr_warn("More than 8 CPUs detected - skipping them\n"
968 "Use CONFIG_X86_BIGSMP\n");
971 for_each_present_cpu(cpu
) {
973 set_cpu_present(cpu
, false);
978 for_each_possible_cpu(cpu
) {
980 set_cpu_possible(cpu
, false);
988 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
989 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
990 hard_smp_processor_id());
992 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
996 * If we couldn't find an SMP configuration at boot time,
997 * get out of here now!
999 if (!smp_found_config
&& !acpi_lapic
) {
1001 pr_notice("SMP motherboard not detected\n");
1003 if (APIC_init_uniprocessor())
1004 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1009 * Should not be necessary because the MP table should list the boot
1010 * CPU too, but we do it for the sake of robustness anyway.
1012 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1013 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1014 boot_cpu_physical_apicid
);
1015 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1020 * If we couldn't find a local APIC, then get out of here now!
1022 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) &&
1024 if (!disable_apic
) {
1025 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1026 boot_cpu_physical_apicid
);
1027 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1029 smpboot_clear_io_apic();
1030 disable_ioapic_support();
1034 verify_local_APIC();
1037 * If SMP should be disabled, then really disable it!
1040 pr_info("SMP mode deactivated\n");
1041 smpboot_clear_io_apic();
1045 bsp_end_local_APIC_setup();
1052 static void __init
smp_cpu_index_default(void)
1055 struct cpuinfo_x86
*c
;
1057 for_each_possible_cpu(i
) {
1059 /* mark all to hotplug */
1060 c
->cpu_index
= nr_cpu_ids
;
1065 * Prepare for SMP bootup. The MP table or ACPI has been read
1066 * earlier. Just do some sanity checking here and enable APIC mode.
1068 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1073 smp_cpu_index_default();
1076 * Setup boot CPU information
1078 smp_store_boot_cpu_info(); /* Final full version of the data */
1079 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1082 current_thread_info()->cpu
= 0; /* needed? */
1083 for_each_possible_cpu(i
) {
1084 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1085 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1086 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1088 set_cpu_sibling_map(0);
1091 if (smp_sanity_check(max_cpus
) < 0) {
1092 pr_info("SMP disabled\n");
1097 default_setup_apic_routing();
1100 if (read_apic_id() != boot_cpu_physical_apicid
) {
1101 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1102 read_apic_id(), boot_cpu_physical_apicid
);
1103 /* Or can we switch back to PIC here? */
1110 * Switch from PIC to APIC mode.
1115 cpu0_logical_apicid
= apic_read(APIC_LDR
);
1117 cpu0_logical_apicid
= GET_APIC_LOGICAL_ID(apic_read(APIC_LDR
));
1120 * Enable IO APIC before setting up error vector
1122 if (!skip_ioapic_setup
&& nr_ioapics
)
1125 bsp_end_local_APIC_setup();
1127 if (apic
->setup_portio_remap
)
1128 apic
->setup_portio_remap();
1130 smpboot_setup_io_apic();
1132 * Set up local APIC timer on boot CPU.
1135 pr_info("CPU%d: ", 0);
1136 print_cpu_info(&cpu_data(0));
1137 x86_init
.timers
.setup_percpu_clockev();
1142 set_mtrr_aps_delayed_init();
1147 void arch_enable_nonboot_cpus_begin(void)
1149 set_mtrr_aps_delayed_init();
1152 void arch_enable_nonboot_cpus_end(void)
1158 * Early setup to make printk work.
1160 void __init
native_smp_prepare_boot_cpu(void)
1162 int me
= smp_processor_id();
1163 switch_to_new_gdt(me
);
1164 /* already set me in cpu_online_mask in boot_cpu_init() */
1165 cpumask_set_cpu(me
, cpu_callout_mask
);
1166 per_cpu(cpu_state
, me
) = CPU_ONLINE
;
1169 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1171 pr_debug("Boot done\n");
1175 #ifdef CONFIG_X86_IO_APIC
1176 setup_ioapic_dest();
1181 static int __initdata setup_possible_cpus
= -1;
1182 static int __init
_setup_possible_cpus(char *str
)
1184 get_option(&str
, &setup_possible_cpus
);
1187 early_param("possible_cpus", _setup_possible_cpus
);
1191 * cpu_possible_mask should be static, it cannot change as cpu's
1192 * are onlined, or offlined. The reason is per-cpu data-structures
1193 * are allocated by some modules at init time, and dont expect to
1194 * do this dynamically on cpu arrival/departure.
1195 * cpu_present_mask on the other hand can change dynamically.
1196 * In case when cpu_hotplug is not compiled, then we resort to current
1197 * behaviour, which is cpu_possible == cpu_present.
1200 * Three ways to find out the number of additional hotplug CPUs:
1201 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1202 * - The user can overwrite it with possible_cpus=NUM
1203 * - Otherwise don't reserve additional CPUs.
1204 * We do this because additional CPUs waste a lot of memory.
1207 __init
void prefill_possible_map(void)
1211 /* no processor from mptable or madt */
1212 if (!num_processors
)
1215 i
= setup_max_cpus
?: 1;
1216 if (setup_possible_cpus
== -1) {
1217 possible
= num_processors
;
1218 #ifdef CONFIG_HOTPLUG_CPU
1220 possible
+= disabled_cpus
;
1226 possible
= setup_possible_cpus
;
1228 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1230 /* nr_cpu_ids could be reduced via nr_cpus= */
1231 if (possible
> nr_cpu_ids
) {
1232 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1233 possible
, nr_cpu_ids
);
1234 possible
= nr_cpu_ids
;
1237 #ifdef CONFIG_HOTPLUG_CPU
1238 if (!setup_max_cpus
)
1241 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1242 possible
, setup_max_cpus
);
1246 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1247 possible
, max_t(int, possible
- num_processors
, 0));
1249 for (i
= 0; i
< possible
; i
++)
1250 set_cpu_possible(i
, true);
1251 for (; i
< NR_CPUS
; i
++)
1252 set_cpu_possible(i
, false);
1254 nr_cpu_ids
= possible
;
1257 #ifdef CONFIG_HOTPLUG_CPU
1259 static void remove_siblinginfo(int cpu
)
1262 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1264 for_each_cpu(sibling
, cpu_core_mask(cpu
)) {
1265 cpumask_clear_cpu(cpu
, cpu_core_mask(sibling
));
1267 * last thread sibling in this cpu core going down
1269 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1)
1270 cpu_data(sibling
).booted_cores
--;
1273 for_each_cpu(sibling
, cpu_sibling_mask(cpu
))
1274 cpumask_clear_cpu(cpu
, cpu_sibling_mask(sibling
));
1275 cpumask_clear(cpu_sibling_mask(cpu
));
1276 cpumask_clear(cpu_core_mask(cpu
));
1277 c
->phys_proc_id
= 0;
1279 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1282 static void __ref
remove_cpu_from_maps(int cpu
)
1284 set_cpu_online(cpu
, false);
1285 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1286 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1287 /* was set by cpu_init() */
1288 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1289 numa_remove_cpu(cpu
);
1292 void cpu_disable_common(void)
1294 int cpu
= smp_processor_id();
1296 remove_siblinginfo(cpu
);
1298 /* It's now safe to remove this processor from the online map */
1300 remove_cpu_from_maps(cpu
);
1301 unlock_vector_lock();
1305 int native_cpu_disable(void)
1309 cpu_disable_common();
1313 void native_cpu_die(unsigned int cpu
)
1315 /* We don't do anything here: idle task is faking death itself. */
1318 for (i
= 0; i
< 10; i
++) {
1319 /* They ack this in play_dead by setting CPU_DEAD */
1320 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1321 if (system_state
== SYSTEM_RUNNING
)
1322 pr_info("CPU %u is now offline\n", cpu
);
1327 pr_err("CPU %u didn't die...\n", cpu
);
1330 void play_dead_common(void)
1333 reset_lazy_tlbstate();
1334 amd_e400_remove_cpu(raw_smp_processor_id());
1338 __this_cpu_write(cpu_state
, CPU_DEAD
);
1341 * With physical CPU hotplug, we should halt the cpu
1343 local_irq_disable();
1346 static bool wakeup_cpu0(void)
1348 if (smp_processor_id() == 0 && enable_start_cpu0
)
1355 * We need to flush the caches before going to sleep, lest we have
1356 * dirty data in our caches when we come back up.
1358 static inline void mwait_play_dead(void)
1360 unsigned int eax
, ebx
, ecx
, edx
;
1361 unsigned int highest_cstate
= 0;
1362 unsigned int highest_subcstate
= 0;
1365 struct cpuinfo_x86
*c
= __this_cpu_ptr(&cpu_info
);
1367 if (!(this_cpu_has(X86_FEATURE_MWAIT
) && mwait_usable(c
)))
1369 if (!this_cpu_has(X86_FEATURE_CLFLSH
))
1371 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1374 eax
= CPUID_MWAIT_LEAF
;
1376 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1379 * eax will be 0 if EDX enumeration is not valid.
1380 * Initialized below to cstate, sub_cstate value when EDX is valid.
1382 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1385 edx
>>= MWAIT_SUBSTATE_SIZE
;
1386 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1387 if (edx
& MWAIT_SUBSTATE_MASK
) {
1389 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1392 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1393 (highest_subcstate
- 1);
1397 * This should be a memory location in a cache line which is
1398 * unlikely to be touched by other processors. The actual
1399 * content is immaterial as it is not actually modified in any way.
1401 mwait_ptr
= ¤t_thread_info()->flags
;
1407 * The CLFLUSH is a workaround for erratum AAI65 for
1408 * the Xeon 7400 series. It's not clear it is actually
1409 * needed, but it should be harmless in either case.
1410 * The WBINVD is insufficient due to the spurious-wakeup
1411 * case where we return around the loop.
1414 __monitor(mwait_ptr
, 0, 0);
1418 * If NMI wants to wake up CPU0, start CPU0.
1425 static inline void hlt_play_dead(void)
1427 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1433 * If NMI wants to wake up CPU0, start CPU0.
1440 void native_play_dead(void)
1443 tboot_shutdown(TB_SHUTDOWN_WFS
);
1445 mwait_play_dead(); /* Only returns on failure */
1446 if (cpuidle_play_dead())
1450 #else /* ... !CONFIG_HOTPLUG_CPU */
1451 int native_cpu_disable(void)
1456 void native_cpu_die(unsigned int cpu
)
1458 /* We said "no" in __cpu_disable */
1462 void native_play_dead(void)