2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
71 #include <asm/fpu/internal.h>
72 #include <asm/setup.h>
73 #include <asm/uv/uv.h>
74 #include <linux/mc146818rtc.h>
75 #include <asm/i8259.h>
76 #include <asm/realmode.h>
79 /* Number of siblings per CPU package */
80 int smp_num_siblings
= 1;
81 EXPORT_SYMBOL(smp_num_siblings
);
83 /* Last level cache ID of each logical CPU */
84 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
86 /* representing HT siblings of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
90 /* representing HT and core siblings of each logical CPU */
91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
92 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
96 /* Per CPU bogomips and other parameters */
97 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
98 EXPORT_PER_CPU_SYMBOL(cpu_info
);
100 /* Logical package management. We might want to allocate that dynamically */
101 static int *physical_to_logical_pkg __read_mostly
;
102 static unsigned long *physical_package_map __read_mostly
;;
103 static unsigned int max_physical_pkg_id __read_mostly
;
104 unsigned int __max_logical_packages __read_mostly
;
105 EXPORT_SYMBOL(__max_logical_packages
);
106 static unsigned int logical_packages __read_mostly
;
107 static bool logical_packages_frozen __read_mostly
;
109 /* Maximum number of SMT threads on any online core */
110 int __max_smt_threads __read_mostly
;
112 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip
)
116 spin_lock_irqsave(&rtc_lock
, flags
);
117 CMOS_WRITE(0xa, 0xf);
118 spin_unlock_irqrestore(&rtc_lock
, flags
);
121 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH
)) =
124 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) =
129 static inline void smpboot_restore_warm_reset_vector(void)
134 * Install writable page 0 entry to set BIOS data area.
139 * Paranoid: Set warm reset code and vector here back
142 spin_lock_irqsave(&rtc_lock
, flags
);
144 spin_unlock_irqrestore(&rtc_lock
, flags
);
146 *((volatile u32
*)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) = 0;
150 * Report back to the Boot Processor during boot time or to the caller processor
153 static void smp_callin(void)
158 * If waken up by an INIT in an 82489DX configuration
159 * cpu_callout_mask guarantees we don't get here before
160 * an INIT_deassert IPI reaches our local APIC, so it is
161 * now safe to touch our local APIC.
163 cpuid
= smp_processor_id();
166 * (This works even if the APIC is not enabled.)
168 phys_id
= read_apic_id();
171 * the boot CPU has finished the init stage and is spinning
172 * on callin_map until we finish. We are free to set up this
173 * CPU, first the APIC. (this is probably redundant on most
179 * Save our processor parameters. Note: this information
180 * is needed for clock calibration.
182 smp_store_cpu_info(cpuid
);
186 * Update loops_per_jiffy in cpu_data. Previous call to
187 * smp_store_cpu_info() stored a value that is close but not as
188 * accurate as the value just calculated.
191 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
192 pr_debug("Stack at about %p\n", &cpuid
);
195 * This must be done before setting cpu_online_mask
196 * or calling notify_cpu_starting.
198 set_cpu_sibling_map(raw_smp_processor_id());
201 notify_cpu_starting(cpuid
);
204 * Allow the master to continue.
206 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
209 static int cpu0_logical_apicid
;
210 static int enable_start_cpu0
;
212 * Activate a secondary processor.
214 static void notrace
start_secondary(void *unused
)
217 * Don't put *anything* before cpu_init(), SMP booting is too
218 * fragile that we want to limit the things done here to the
219 * most necessary things.
222 x86_cpuinit
.early_percpu_clock_init();
226 enable_start_cpu0
= 0;
229 /* switch away from the initial page table */
230 load_cr3(swapper_pg_dir
);
234 /* otherwise gcc will move up smp_processor_id before the cpu_init */
237 * Check TSC synchronization with the BP:
239 check_tsc_sync_target();
242 * Lock vector_lock and initialize the vectors on this cpu
243 * before setting the cpu online. We must set it online with
244 * vector_lock held to prevent a concurrent setup/teardown
245 * from seeing a half valid vector space.
248 setup_vector_irq(smp_processor_id());
249 set_cpu_online(smp_processor_id(), true);
250 unlock_vector_lock();
251 cpu_set_state_online(smp_processor_id());
252 x86_platform
.nmi_init();
254 /* enable local interrupts */
257 /* to prevent fake stack check failure in clock setup */
258 boot_init_stack_canary();
260 x86_cpuinit
.setup_percpu_clockev();
263 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE
);
266 int topology_update_package_map(unsigned int apicid
, unsigned int cpu
)
268 unsigned int new, pkg
= apicid
>> boot_cpu_data
.x86_coreid_bits
;
270 /* Called from early boot ? */
271 if (!physical_package_map
)
274 if (pkg
>= max_physical_pkg_id
)
277 /* Set the logical package id */
278 if (test_and_set_bit(pkg
, physical_package_map
))
281 if (logical_packages_frozen
) {
282 physical_to_logical_pkg
[pkg
] = -1;
283 pr_warn("APIC(%x) Package %u exceeds logical package max\n",
288 new = logical_packages
++;
289 pr_info("APIC(%x) Converting physical %u to logical package %u\n",
291 physical_to_logical_pkg
[pkg
] = new;
294 cpu_data(cpu
).logical_proc_id
= physical_to_logical_pkg
[pkg
];
299 * topology_phys_to_logical_pkg - Map a physical package id to a logical
301 * Returns logical package id or -1 if not found
303 int topology_phys_to_logical_pkg(unsigned int phys_pkg
)
305 if (phys_pkg
>= max_physical_pkg_id
)
307 return physical_to_logical_pkg
[phys_pkg
];
309 EXPORT_SYMBOL(topology_phys_to_logical_pkg
);
311 static void __init
smp_init_package_map(void)
313 unsigned int ncpus
, cpu
;
317 * Today neither Intel nor AMD support heterogenous systems. That
318 * might change in the future....
320 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
321 * computation, this won't actually work since some Intel BIOSes
322 * report inconsistent HT data when they disable HT.
324 * In particular, they reduce the APIC-IDs to only include the cores,
325 * but leave the CPUID topology to say there are (2) siblings.
326 * This means we don't know how many threads there will be until
327 * after the APIC enumeration.
329 * By not including this we'll sometimes over-estimate the number of
330 * logical packages by the amount of !present siblings, but this is
331 * still better than MAX_LOCAL_APIC.
333 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
334 * on the command line leading to a similar issue as the HT disable
335 * problem because the hyperthreads are usually enumerated after the
338 ncpus
= boot_cpu_data
.x86_max_cores
;
340 pr_warn("x86_max_cores == zero !?!?");
344 __max_logical_packages
= DIV_ROUND_UP(total_cpus
, ncpus
);
345 logical_packages
= 0;
348 * Possibly larger than what we need as the number of apic ids per
349 * package can be smaller than the actual used apic ids.
351 max_physical_pkg_id
= DIV_ROUND_UP(MAX_LOCAL_APIC
, ncpus
);
352 size
= max_physical_pkg_id
* sizeof(unsigned int);
353 physical_to_logical_pkg
= kmalloc(size
, GFP_KERNEL
);
354 memset(physical_to_logical_pkg
, 0xff, size
);
355 size
= BITS_TO_LONGS(max_physical_pkg_id
) * sizeof(unsigned long);
356 physical_package_map
= kzalloc(size
, GFP_KERNEL
);
358 for_each_present_cpu(cpu
) {
359 unsigned int apicid
= apic
->cpu_present_to_apicid(cpu
);
361 if (apicid
== BAD_APICID
|| !apic
->apic_id_valid(apicid
))
363 if (!topology_update_package_map(apicid
, cpu
))
365 pr_warn("CPU %u APICId %x disabled\n", cpu
, apicid
);
366 per_cpu(x86_bios_cpu_apicid
, cpu
) = BAD_APICID
;
367 set_cpu_possible(cpu
, false);
368 set_cpu_present(cpu
, false);
371 if (logical_packages
> __max_logical_packages
) {
372 pr_warn("Detected more packages (%u), then computed by BIOS data (%u).\n",
373 logical_packages
, __max_logical_packages
);
374 logical_packages_frozen
= true;
375 __max_logical_packages
= logical_packages
;
378 pr_info("Max logical packages: %u\n", __max_logical_packages
);
381 void __init
smp_store_boot_cpu_info(void)
383 int id
= 0; /* CPU 0 */
384 struct cpuinfo_x86
*c
= &cpu_data(id
);
388 smp_init_package_map();
392 * The bootstrap kernel entry code has set these up. Save them for
395 void smp_store_cpu_info(int id
)
397 struct cpuinfo_x86
*c
= &cpu_data(id
);
402 * During boot time, CPU0 has this setup already. Save the info when
403 * bringing up AP or offlined CPU0.
405 identify_secondary_cpu(c
);
409 topology_same_node(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
411 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
413 return (cpu_to_node(cpu1
) == cpu_to_node(cpu2
));
417 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
419 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
421 return !WARN_ONCE(!topology_same_node(c
, o
),
422 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
423 "[node: %d != %d]. Ignoring dependency.\n",
424 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
427 #define link_mask(mfunc, c1, c2) \
429 cpumask_set_cpu((c1), mfunc(c2)); \
430 cpumask_set_cpu((c2), mfunc(c1)); \
433 static bool match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
435 if (boot_cpu_has(X86_FEATURE_TOPOEXT
)) {
436 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
438 if (c
->phys_proc_id
== o
->phys_proc_id
&&
439 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
) &&
440 c
->cpu_core_id
== o
->cpu_core_id
)
441 return topology_sane(c
, o
, "smt");
443 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
444 c
->cpu_core_id
== o
->cpu_core_id
) {
445 return topology_sane(c
, o
, "smt");
451 static bool match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
453 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
455 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
456 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
457 return topology_sane(c
, o
, "llc");
463 * Unlike the other levels, we do not enforce keeping a
464 * multicore group inside a NUMA node. If this happens, we will
465 * discard the MC level of the topology later.
467 static bool match_die(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
469 if (c
->phys_proc_id
== o
->phys_proc_id
)
474 static struct sched_domain_topology_level numa_inside_package_topology
[] = {
475 #ifdef CONFIG_SCHED_SMT
476 { cpu_smt_mask
, cpu_smt_flags
, SD_INIT_NAME(SMT
) },
478 #ifdef CONFIG_SCHED_MC
479 { cpu_coregroup_mask
, cpu_core_flags
, SD_INIT_NAME(MC
) },
484 * set_sched_topology() sets the topology internal to a CPU. The
485 * NUMA topologies are layered on top of it to build the full
488 * If NUMA nodes are observed to occur within a CPU package, this
489 * function should be called. It forces the sched domain code to
490 * only use the SMT level for the CPU portion of the topology.
491 * This essentially falls back to relying on NUMA information
492 * from the SRAT table to describe the entire system topology
493 * (except for hyperthreads).
495 static void primarily_use_numa_for_topology(void)
497 set_sched_topology(numa_inside_package_topology
);
500 void set_cpu_sibling_map(int cpu
)
502 bool has_smt
= smp_num_siblings
> 1;
503 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
504 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
505 struct cpuinfo_x86
*o
;
508 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
511 cpumask_set_cpu(cpu
, topology_sibling_cpumask(cpu
));
512 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
513 cpumask_set_cpu(cpu
, topology_core_cpumask(cpu
));
518 for_each_cpu(i
, cpu_sibling_setup_mask
) {
521 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
522 link_mask(topology_sibling_cpumask
, cpu
, i
);
524 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
525 link_mask(cpu_llc_shared_mask
, cpu
, i
);
530 * This needs a separate iteration over the cpus because we rely on all
531 * topology_sibling_cpumask links to be set-up.
533 for_each_cpu(i
, cpu_sibling_setup_mask
) {
536 if ((i
== cpu
) || (has_mp
&& match_die(c
, o
))) {
537 link_mask(topology_core_cpumask
, cpu
, i
);
540 * Does this new cpu bringup a new core?
543 topology_sibling_cpumask(cpu
)) == 1) {
545 * for each core in package, increment
546 * the booted_cores for this new cpu
549 topology_sibling_cpumask(i
)) == i
)
552 * increment the core count for all
553 * the other cpus in this package
556 cpu_data(i
).booted_cores
++;
557 } else if (i
!= cpu
&& !c
->booted_cores
)
558 c
->booted_cores
= cpu_data(i
).booted_cores
;
560 if (match_die(c
, o
) && !topology_same_node(c
, o
))
561 primarily_use_numa_for_topology();
564 threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
565 if (threads
> __max_smt_threads
)
566 __max_smt_threads
= threads
;
569 /* maps the cpu to the sched domain representing multi-core */
570 const struct cpumask
*cpu_coregroup_mask(int cpu
)
572 return cpu_llc_shared_mask(cpu
);
575 static void impress_friends(void)
578 unsigned long bogosum
= 0;
580 * Allow the user to impress friends.
582 pr_debug("Before bogomips\n");
583 for_each_possible_cpu(cpu
)
584 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
585 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
586 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
589 (bogosum
/(5000/HZ
))%100);
591 pr_debug("Before bogocount - setting activated=1\n");
594 void __inquire_remote_apic(int apicid
)
596 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
597 const char * const names
[] = { "ID", "VERSION", "SPIV" };
601 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
603 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
604 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
609 status
= safe_apic_wait_icr_idle();
611 pr_cont("a previous APIC delivery may have failed\n");
613 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
618 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
619 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
622 case APIC_ICR_RR_VALID
:
623 status
= apic_read(APIC_RRR
);
624 pr_cont("%08x\n", status
);
633 * The Multiprocessor Specification 1.4 (1997) example code suggests
634 * that there should be a 10ms delay between the BSP asserting INIT
635 * and de-asserting INIT, when starting a remote processor.
636 * But that slows boot and resume on modern processors, which include
637 * many cores and don't require that delay.
639 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
640 * Modern processor families are quirked to remove the delay entirely.
642 #define UDELAY_10MS_DEFAULT 10000
644 static unsigned int init_udelay
= UINT_MAX
;
646 static int __init
cpu_init_udelay(char *str
)
648 get_option(&str
, &init_udelay
);
652 early_param("cpu_init_udelay", cpu_init_udelay
);
654 static void __init
smp_quirk_init_udelay(void)
656 /* if cmdline changed it from default, leave it alone */
657 if (init_udelay
!= UINT_MAX
)
660 /* if modern processor, use no delay */
661 if (((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 6)) ||
662 ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && (boot_cpu_data
.x86
>= 0xF))) {
666 /* else, use legacy delay */
667 init_udelay
= UDELAY_10MS_DEFAULT
;
671 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
672 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
673 * won't ... remember to clear down the APIC, etc later.
676 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
678 unsigned long send_status
, accept_status
= 0;
682 /* Boot on the stack */
683 /* Kick the second */
684 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
686 pr_debug("Waiting for send to finish...\n");
687 send_status
= safe_apic_wait_icr_idle();
690 * Give the other CPU some time to accept the IPI.
693 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
694 maxlvt
= lapic_get_maxlvt();
695 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
696 apic_write(APIC_ESR
, 0);
697 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
699 pr_debug("NMI sent\n");
702 pr_err("APIC never delivered???\n");
704 pr_err("APIC delivery error (%lx)\n", accept_status
);
706 return (send_status
| accept_status
);
710 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
712 unsigned long send_status
= 0, accept_status
= 0;
713 int maxlvt
, num_starts
, j
;
715 maxlvt
= lapic_get_maxlvt();
718 * Be paranoid about clearing APIC errors.
720 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
721 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
722 apic_write(APIC_ESR
, 0);
726 pr_debug("Asserting INIT\n");
729 * Turn INIT on target chip
734 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
737 pr_debug("Waiting for send to finish...\n");
738 send_status
= safe_apic_wait_icr_idle();
742 pr_debug("Deasserting INIT\n");
746 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
748 pr_debug("Waiting for send to finish...\n");
749 send_status
= safe_apic_wait_icr_idle();
754 * Should we send STARTUP IPIs ?
756 * Determine this based on the APIC version.
757 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
759 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
765 * Run STARTUP IPI loop.
767 pr_debug("#startup loops: %d\n", num_starts
);
769 for (j
= 1; j
<= num_starts
; j
++) {
770 pr_debug("Sending STARTUP #%d\n", j
);
771 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
772 apic_write(APIC_ESR
, 0);
774 pr_debug("After apic_write\n");
781 /* Boot on the stack */
782 /* Kick the second */
783 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
787 * Give the other CPU some time to accept the IPI.
789 if (init_udelay
== 0)
794 pr_debug("Startup point 1\n");
796 pr_debug("Waiting for send to finish...\n");
797 send_status
= safe_apic_wait_icr_idle();
800 * Give the other CPU some time to accept the IPI.
802 if (init_udelay
== 0)
807 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
808 apic_write(APIC_ESR
, 0);
809 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
810 if (send_status
|| accept_status
)
813 pr_debug("After Startup\n");
816 pr_err("APIC never delivered???\n");
818 pr_err("APIC delivery error (%lx)\n", accept_status
);
820 return (send_status
| accept_status
);
823 void smp_announce(void)
825 int num_nodes
= num_online_nodes();
827 printk(KERN_INFO
"x86: Booted up %d node%s, %d CPUs\n",
828 num_nodes
, (num_nodes
> 1 ? "s" : ""), num_online_cpus());
831 /* reduce the number of lines printed when booting a large cpu count system */
832 static void announce_cpu(int cpu
, int apicid
)
834 static int current_node
= -1;
835 int node
= early_cpu_to_node(cpu
);
836 static int width
, node_width
;
839 width
= num_digits(num_possible_cpus()) + 1; /* + '#' sign */
842 node_width
= num_digits(num_possible_nodes()) + 1; /* + '#' */
845 printk(KERN_INFO
"x86: Booting SMP configuration:\n");
847 if (system_state
== SYSTEM_BOOTING
) {
848 if (node
!= current_node
) {
849 if (current_node
> (-1))
853 printk(KERN_INFO
".... node %*s#%d, CPUs: ",
854 node_width
- num_digits(node
), " ", node
);
857 /* Add padding for the BSP */
859 pr_cont("%*s", width
+ 1, " ");
861 pr_cont("%*s#%d", width
- num_digits(cpu
), " ", cpu
);
864 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
868 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
872 cpu
= smp_processor_id();
873 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
880 * Wake up AP by INIT, INIT, STARTUP sequence.
882 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
883 * boot-strap code which is not a desired behavior for waking up BSP. To
884 * void the boot-strap code, wake up CPU0 by NMI instead.
886 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
887 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
888 * We'll change this code in the future to wake up hard offlined CPU0 if
889 * real platform and request are available.
892 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
893 int *cpu0_nmi_registered
)
901 * Wake up AP by INIT, INIT, STARTUP sequence.
904 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
909 * Wake up BSP by nmi.
911 * Register a NMI handler to help wake up CPU0.
913 boot_error
= register_nmi_handler(NMI_LOCAL
,
914 wakeup_cpu0_nmi
, 0, "wake_cpu0");
917 enable_start_cpu0
= 1;
918 *cpu0_nmi_registered
= 1;
919 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
920 id
= cpu0_logical_apicid
;
923 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
932 void common_cpu_up(unsigned int cpu
, struct task_struct
*idle
)
934 /* Just in case we booted with a single CPU. */
935 alternatives_enable_smp();
937 per_cpu(current_task
, cpu
) = idle
;
940 /* Stack for startup_32 can be just as for start_secondary onwards */
942 per_cpu(cpu_current_top_of_stack
, cpu
) =
943 (unsigned long)task_stack_page(idle
) + THREAD_SIZE
;
945 clear_tsk_thread_flag(idle
, TIF_FORK
);
946 initial_gs
= per_cpu_offset(cpu
);
951 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
952 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
953 * Returns zero if CPU booted OK, else error code from
954 * ->wakeup_secondary_cpu.
956 static int do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
)
958 volatile u32
*trampoline_status
=
959 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
960 /* start_ip had better be page-aligned! */
961 unsigned long start_ip
= real_mode_header
->trampoline_start
;
963 unsigned long boot_error
= 0;
964 int cpu0_nmi_registered
= 0;
965 unsigned long timeout
;
967 idle
->thread
.sp
= (unsigned long) (((struct pt_regs
*)
968 (THREAD_SIZE
+ task_stack_page(idle
))) - 1);
970 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
971 initial_code
= (unsigned long)start_secondary
;
972 stack_start
= idle
->thread
.sp
;
975 * Enable the espfix hack for this CPU
977 #ifdef CONFIG_X86_ESPFIX64
981 /* So we see what's up */
982 announce_cpu(cpu
, apicid
);
985 * This grunge runs the startup process for
986 * the targeted processor.
989 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
991 pr_debug("Setting warm reset code and vector.\n");
993 smpboot_setup_warm_reset_vector(start_ip
);
995 * Be paranoid about clearing APIC errors.
997 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
998 apic_write(APIC_ESR
, 0);
1004 * AP might wait on cpu_callout_mask in cpu_init() with
1005 * cpu_initialized_mask set if previous attempt to online
1006 * it timed-out. Clear cpu_initialized_mask so that after
1007 * INIT/SIPI it could start with a clean state.
1009 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1013 * Wake up a CPU in difference cases:
1014 * - Use the method in the APIC driver if it's defined
1016 * - Use an INIT boot APIC message for APs or NMI for BSP.
1018 if (apic
->wakeup_secondary_cpu
)
1019 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
1021 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
1022 &cpu0_nmi_registered
);
1026 * Wait 10s total for first sign of life from AP
1029 timeout
= jiffies
+ 10*HZ
;
1030 while (time_before(jiffies
, timeout
)) {
1031 if (cpumask_test_cpu(cpu
, cpu_initialized_mask
)) {
1033 * Tell AP to proceed with initialization
1035 cpumask_set_cpu(cpu
, cpu_callout_mask
);
1045 * Wait till AP completes initial initialization
1047 while (!cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1049 * Allow other tasks to run while we wait for the
1050 * AP to come online. This also gives a chance
1051 * for the MTRR work(triggered by the AP coming online)
1052 * to be completed in the stop machine context.
1058 /* mark "stuck" area as not stuck */
1059 *trampoline_status
= 0;
1061 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
1063 * Cleanup possible dangling ends...
1065 smpboot_restore_warm_reset_vector();
1068 * Clean up the nmi handler. Do this after the callin and callout sync
1069 * to avoid impact of possible long unregister time.
1071 if (cpu0_nmi_registered
)
1072 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
1077 int native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
1079 int apicid
= apic
->cpu_present_to_apicid(cpu
);
1080 unsigned long flags
;
1083 WARN_ON(irqs_disabled());
1085 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
1087 if (apicid
== BAD_APICID
||
1088 !physid_isset(apicid
, phys_cpu_present_map
) ||
1089 !apic
->apic_id_valid(apicid
)) {
1090 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
1095 * Already booted CPU?
1097 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1098 pr_debug("do_boot_cpu %d Already started\n", cpu
);
1103 * Save current MTRR state in case it was changed since early boot
1104 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1108 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1109 err
= cpu_check_up_prepare(cpu
);
1110 if (err
&& err
!= -EBUSY
)
1113 /* the FPU context is blank, nobody can own it */
1114 __cpu_disable_lazy_restore(cpu
);
1116 common_cpu_up(cpu
, tidle
);
1119 * We have to walk the irq descriptors to setup the vector
1120 * space for the cpu which comes online. Prevent irq
1121 * alloc/free across the bringup.
1125 err
= do_boot_cpu(apicid
, cpu
, tidle
);
1128 irq_unlock_sparse();
1129 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err
, cpu
);
1134 * Check TSC synchronization with the AP (keep irqs disabled
1137 local_irq_save(flags
);
1138 check_tsc_sync_source(cpu
);
1139 local_irq_restore(flags
);
1141 while (!cpu_online(cpu
)) {
1143 touch_nmi_watchdog();
1146 irq_unlock_sparse();
1152 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1154 void arch_disable_smp_support(void)
1156 disable_ioapic_support();
1160 * Fall back to non SMP mode after errors.
1162 * RED-PEN audit/test this more. I bet there is more state messed up here.
1164 static __init
void disable_smp(void)
1166 pr_info("SMP disabled\n");
1168 disable_ioapic_support();
1170 init_cpu_present(cpumask_of(0));
1171 init_cpu_possible(cpumask_of(0));
1173 if (smp_found_config
)
1174 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1176 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
1177 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1178 cpumask_set_cpu(0, topology_core_cpumask(0));
1189 * Various sanity checks.
1191 static int __init
smp_sanity_check(unsigned max_cpus
)
1195 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1196 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
1200 pr_warn("More than 8 CPUs detected - skipping them\n"
1201 "Use CONFIG_X86_BIGSMP\n");
1204 for_each_present_cpu(cpu
) {
1206 set_cpu_present(cpu
, false);
1211 for_each_possible_cpu(cpu
) {
1213 set_cpu_possible(cpu
, false);
1221 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1222 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1223 hard_smp_processor_id());
1225 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1229 * If we couldn't find an SMP configuration at boot time,
1230 * get out of here now!
1232 if (!smp_found_config
&& !acpi_lapic
) {
1234 pr_notice("SMP motherboard not detected\n");
1235 return SMP_NO_CONFIG
;
1239 * Should not be necessary because the MP table should list the boot
1240 * CPU too, but we do it for the sake of robustness anyway.
1242 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1243 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1244 boot_cpu_physical_apicid
);
1245 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1250 * If we couldn't find a local APIC, then get out of here now!
1252 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) &&
1253 !boot_cpu_has(X86_FEATURE_APIC
)) {
1254 if (!disable_apic
) {
1255 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1256 boot_cpu_physical_apicid
);
1257 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1263 * If SMP should be disabled, then really disable it!
1266 pr_info("SMP mode deactivated\n");
1267 return SMP_FORCE_UP
;
1273 static void __init
smp_cpu_index_default(void)
1276 struct cpuinfo_x86
*c
;
1278 for_each_possible_cpu(i
) {
1280 /* mark all to hotplug */
1281 c
->cpu_index
= nr_cpu_ids
;
1286 * Prepare for SMP bootup. The MP table or ACPI has been read
1287 * earlier. Just do some sanity checking here and enable APIC mode.
1289 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1293 smp_cpu_index_default();
1296 * Setup boot CPU information
1298 smp_store_boot_cpu_info(); /* Final full version of the data */
1299 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1302 for_each_possible_cpu(i
) {
1303 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1304 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1305 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1307 set_cpu_sibling_map(0);
1309 switch (smp_sanity_check(max_cpus
)) {
1312 if (APIC_init_uniprocessor())
1313 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1320 apic_bsp_setup(false);
1326 default_setup_apic_routing();
1328 if (read_apic_id() != boot_cpu_physical_apicid
) {
1329 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1330 read_apic_id(), boot_cpu_physical_apicid
);
1331 /* Or can we switch back to PIC here? */
1334 cpu0_logical_apicid
= apic_bsp_setup(false);
1336 pr_info("CPU%d: ", 0);
1337 print_cpu_info(&cpu_data(0));
1342 set_mtrr_aps_delayed_init();
1344 smp_quirk_init_udelay();
1347 void arch_enable_nonboot_cpus_begin(void)
1349 set_mtrr_aps_delayed_init();
1352 void arch_enable_nonboot_cpus_end(void)
1358 * Early setup to make printk work.
1360 void __init
native_smp_prepare_boot_cpu(void)
1362 int me
= smp_processor_id();
1363 switch_to_new_gdt(me
);
1364 /* already set me in cpu_online_mask in boot_cpu_init() */
1365 cpumask_set_cpu(me
, cpu_callout_mask
);
1366 cpu_set_state_online(me
);
1369 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1371 pr_debug("Boot done\n");
1375 setup_ioapic_dest();
1379 static int __initdata setup_possible_cpus
= -1;
1380 static int __init
_setup_possible_cpus(char *str
)
1382 get_option(&str
, &setup_possible_cpus
);
1385 early_param("possible_cpus", _setup_possible_cpus
);
1389 * cpu_possible_mask should be static, it cannot change as cpu's
1390 * are onlined, or offlined. The reason is per-cpu data-structures
1391 * are allocated by some modules at init time, and dont expect to
1392 * do this dynamically on cpu arrival/departure.
1393 * cpu_present_mask on the other hand can change dynamically.
1394 * In case when cpu_hotplug is not compiled, then we resort to current
1395 * behaviour, which is cpu_possible == cpu_present.
1398 * Three ways to find out the number of additional hotplug CPUs:
1399 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1400 * - The user can overwrite it with possible_cpus=NUM
1401 * - Otherwise don't reserve additional CPUs.
1402 * We do this because additional CPUs waste a lot of memory.
1405 __init
void prefill_possible_map(void)
1409 /* no processor from mptable or madt */
1410 if (!num_processors
)
1413 i
= setup_max_cpus
?: 1;
1414 if (setup_possible_cpus
== -1) {
1415 possible
= num_processors
;
1416 #ifdef CONFIG_HOTPLUG_CPU
1418 possible
+= disabled_cpus
;
1424 possible
= setup_possible_cpus
;
1426 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1428 /* nr_cpu_ids could be reduced via nr_cpus= */
1429 if (possible
> nr_cpu_ids
) {
1430 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1431 possible
, nr_cpu_ids
);
1432 possible
= nr_cpu_ids
;
1435 #ifdef CONFIG_HOTPLUG_CPU
1436 if (!setup_max_cpus
)
1439 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1440 possible
, setup_max_cpus
);
1444 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1445 possible
, max_t(int, possible
- num_processors
, 0));
1447 for (i
= 0; i
< possible
; i
++)
1448 set_cpu_possible(i
, true);
1449 for (; i
< NR_CPUS
; i
++)
1450 set_cpu_possible(i
, false);
1452 nr_cpu_ids
= possible
;
1455 #ifdef CONFIG_HOTPLUG_CPU
1457 /* Recompute SMT state for all CPUs on offline */
1458 static void recompute_smt_state(void)
1460 int max_threads
, cpu
;
1463 for_each_online_cpu (cpu
) {
1464 int threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
1466 if (threads
> max_threads
)
1467 max_threads
= threads
;
1469 __max_smt_threads
= max_threads
;
1472 static void remove_siblinginfo(int cpu
)
1475 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1477 for_each_cpu(sibling
, topology_core_cpumask(cpu
)) {
1478 cpumask_clear_cpu(cpu
, topology_core_cpumask(sibling
));
1480 * last thread sibling in this cpu core going down
1482 if (cpumask_weight(topology_sibling_cpumask(cpu
)) == 1)
1483 cpu_data(sibling
).booted_cores
--;
1486 for_each_cpu(sibling
, topology_sibling_cpumask(cpu
))
1487 cpumask_clear_cpu(cpu
, topology_sibling_cpumask(sibling
));
1488 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1489 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1490 cpumask_clear(cpu_llc_shared_mask(cpu
));
1491 cpumask_clear(topology_sibling_cpumask(cpu
));
1492 cpumask_clear(topology_core_cpumask(cpu
));
1493 c
->phys_proc_id
= 0;
1495 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1496 recompute_smt_state();
1499 static void remove_cpu_from_maps(int cpu
)
1501 set_cpu_online(cpu
, false);
1502 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1503 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1504 /* was set by cpu_init() */
1505 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1506 numa_remove_cpu(cpu
);
1509 void cpu_disable_common(void)
1511 int cpu
= smp_processor_id();
1513 remove_siblinginfo(cpu
);
1515 /* It's now safe to remove this processor from the online map */
1517 remove_cpu_from_maps(cpu
);
1518 unlock_vector_lock();
1522 int native_cpu_disable(void)
1526 ret
= check_irq_vectors_for_cpu_disable();
1531 cpu_disable_common();
1536 int common_cpu_die(unsigned int cpu
)
1540 /* We don't do anything here: idle task is faking death itself. */
1542 /* They ack this in play_dead() by setting CPU_DEAD */
1543 if (cpu_wait_death(cpu
, 5)) {
1544 if (system_state
== SYSTEM_RUNNING
)
1545 pr_info("CPU %u is now offline\n", cpu
);
1547 pr_err("CPU %u didn't die...\n", cpu
);
1554 void native_cpu_die(unsigned int cpu
)
1556 common_cpu_die(cpu
);
1559 void play_dead_common(void)
1562 reset_lazy_tlbstate();
1563 amd_e400_remove_cpu(raw_smp_processor_id());
1566 (void)cpu_report_death();
1569 * With physical CPU hotplug, we should halt the cpu
1571 local_irq_disable();
1574 static bool wakeup_cpu0(void)
1576 if (smp_processor_id() == 0 && enable_start_cpu0
)
1583 * We need to flush the caches before going to sleep, lest we have
1584 * dirty data in our caches when we come back up.
1586 static inline void mwait_play_dead(void)
1588 unsigned int eax
, ebx
, ecx
, edx
;
1589 unsigned int highest_cstate
= 0;
1590 unsigned int highest_subcstate
= 0;
1594 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1596 if (!this_cpu_has(X86_FEATURE_CLFLUSH
))
1598 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1601 eax
= CPUID_MWAIT_LEAF
;
1603 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1606 * eax will be 0 if EDX enumeration is not valid.
1607 * Initialized below to cstate, sub_cstate value when EDX is valid.
1609 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1612 edx
>>= MWAIT_SUBSTATE_SIZE
;
1613 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1614 if (edx
& MWAIT_SUBSTATE_MASK
) {
1616 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1619 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1620 (highest_subcstate
- 1);
1624 * This should be a memory location in a cache line which is
1625 * unlikely to be touched by other processors. The actual
1626 * content is immaterial as it is not actually modified in any way.
1628 mwait_ptr
= ¤t_thread_info()->flags
;
1634 * The CLFLUSH is a workaround for erratum AAI65 for
1635 * the Xeon 7400 series. It's not clear it is actually
1636 * needed, but it should be harmless in either case.
1637 * The WBINVD is insufficient due to the spurious-wakeup
1638 * case where we return around the loop.
1643 __monitor(mwait_ptr
, 0, 0);
1647 * If NMI wants to wake up CPU0, start CPU0.
1654 void hlt_play_dead(void)
1656 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1662 * If NMI wants to wake up CPU0, start CPU0.
1669 void native_play_dead(void)
1672 tboot_shutdown(TB_SHUTDOWN_WFS
);
1674 mwait_play_dead(); /* Only returns on failure */
1675 if (cpuidle_play_dead())
1679 #else /* ... !CONFIG_HOTPLUG_CPU */
1680 int native_cpu_disable(void)
1685 void native_cpu_die(unsigned int cpu
)
1687 /* We said "no" in __cpu_disable */
1691 void native_play_dead(void)