2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
72 #include <asm/fpu-internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
77 #include <asm/smpboot_hooks.h>
78 #include <asm/i8259.h>
80 #include <asm/realmode.h>
82 /* State of each CPU */
83 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
85 #ifdef CONFIG_HOTPLUG_CPU
87 * We need this for trampoline_base protection from concurrent accesses when
88 * off- and onlining cores wildly.
90 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex
);
92 void cpu_hotplug_driver_lock(void)
94 mutex_lock(&x86_cpu_hotplug_driver_mutex
);
97 void cpu_hotplug_driver_unlock(void)
99 mutex_unlock(&x86_cpu_hotplug_driver_mutex
);
102 ssize_t
arch_cpu_probe(const char *buf
, size_t count
) { return -1; }
103 ssize_t
arch_cpu_release(const char *buf
, size_t count
) { return -1; }
106 /* Number of siblings per CPU package */
107 int smp_num_siblings
= 1;
108 EXPORT_SYMBOL(smp_num_siblings
);
110 /* Last level cache ID of each logical CPU */
111 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
113 /* representing HT siblings of each logical CPU */
114 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
115 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
117 /* representing HT and core siblings of each logical CPU */
118 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
119 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
121 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
123 /* Per CPU bogomips and other parameters */
124 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86
, cpu_info
);
125 EXPORT_PER_CPU_SYMBOL(cpu_info
);
127 atomic_t init_deasserted
;
130 * Report back to the Boot Processor.
133 static void __cpuinit
smp_callin(void)
136 unsigned long timeout
;
139 * If waken up by an INIT in an 82489DX configuration
140 * we may get here before an INIT-deassert IPI reaches
141 * our local APIC. We have to wait for the IPI or we'll
142 * lock up on an APIC access.
144 if (apic
->wait_for_init_deassert
)
145 apic
->wait_for_init_deassert(&init_deasserted
);
148 * (This works even if the APIC is not enabled.)
150 phys_id
= read_apic_id();
151 cpuid
= smp_processor_id();
152 if (cpumask_test_cpu(cpuid
, cpu_callin_mask
)) {
153 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__
,
156 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid
, phys_id
);
159 * STARTUP IPIs are fragile beasts as they might sometimes
160 * trigger some glue motherboard logic. Complete APIC bus
161 * silence for 1 second, this overestimates the time the
162 * boot CPU is spending to send the up to 2 STARTUP IPIs
163 * by a factor of two. This should be enough.
167 * Waiting 2s total for startup (udelay is not yet working)
169 timeout
= jiffies
+ 2*HZ
;
170 while (time_before(jiffies
, timeout
)) {
172 * Has the boot CPU finished it's STARTUP sequence?
174 if (cpumask_test_cpu(cpuid
, cpu_callout_mask
))
179 if (!time_before(jiffies
, timeout
)) {
180 panic("%s: CPU%d started up but did not get a callout!\n",
185 * the boot CPU has finished the init stage and is spinning
186 * on callin_map until we finish. We are free to set up this
187 * CPU, first the APIC. (this is probably redundant on most
191 pr_debug("CALLIN, before setup_local_APIC()\n");
192 if (apic
->smp_callin_clear_local_apic
)
193 apic
->smp_callin_clear_local_apic();
195 end_local_APIC_setup();
198 * Need to setup vector mappings before we enable interrupts.
200 setup_vector_irq(smp_processor_id());
203 * Save our processor parameters. Note: this information
204 * is needed for clock calibration.
206 smp_store_cpu_info(cpuid
);
210 * Update loops_per_jiffy in cpu_data. Previous call to
211 * smp_store_cpu_info() stored a value that is close but not as
212 * accurate as the value just calculated.
215 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
216 pr_debug("Stack at about %p\n", &cpuid
);
219 * This must be done before setting cpu_online_mask
220 * or calling notify_cpu_starting.
222 set_cpu_sibling_map(raw_smp_processor_id());
225 notify_cpu_starting(cpuid
);
228 * Allow the master to continue.
230 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
234 * Activate a secondary processor.
236 notrace
static void __cpuinit
start_secondary(void *unused
)
239 * Don't put *anything* before cpu_init(), SMP booting is too
240 * fragile that we want to limit the things done here to the
241 * most necessary things.
244 x86_cpuinit
.early_percpu_clock_init();
249 /* switch away from the initial page table */
250 load_cr3(swapper_pg_dir
);
254 /* otherwise gcc will move up smp_processor_id before the cpu_init */
257 * Check TSC synchronization with the BP:
259 check_tsc_sync_target();
262 * We need to hold vector_lock so there the set of online cpus
263 * does not change while we are assigning vectors to cpus. Holding
264 * this lock ensures we don't half assign or remove an irq from a cpu.
267 set_cpu_online(smp_processor_id(), true);
268 unlock_vector_lock();
269 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
270 x86_platform
.nmi_init();
272 /* enable local interrupts */
275 /* to prevent fake stack check failure in clock setup */
276 boot_init_stack_canary();
278 x86_cpuinit
.setup_percpu_clockev();
285 * The bootstrap kernel entry code has set these up. Save them for
289 void __cpuinit
smp_store_cpu_info(int id
)
291 struct cpuinfo_x86
*c
= &cpu_data(id
);
296 identify_secondary_cpu(c
);
299 static bool __cpuinit
300 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
302 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
304 return !WARN_ONCE(cpu_to_node(cpu1
) != cpu_to_node(cpu2
),
305 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
306 "[node: %d != %d]. Ignoring dependency.\n",
307 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
310 #define link_mask(_m, c1, c2) \
312 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
313 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
316 static bool __cpuinit
match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
318 if (cpu_has(c
, X86_FEATURE_TOPOEXT
)) {
319 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
321 if (c
->phys_proc_id
== o
->phys_proc_id
&&
322 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
) &&
323 c
->compute_unit_id
== o
->compute_unit_id
)
324 return topology_sane(c
, o
, "smt");
326 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
327 c
->cpu_core_id
== o
->cpu_core_id
) {
328 return topology_sane(c
, o
, "smt");
334 static bool __cpuinit
match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
336 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
338 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
339 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
340 return topology_sane(c
, o
, "llc");
345 static bool __cpuinit
match_mc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
347 if (c
->phys_proc_id
== o
->phys_proc_id
) {
348 if (cpu_has(c
, X86_FEATURE_AMD_DCM
))
351 return topology_sane(c
, o
, "mc");
356 void __cpuinit
set_cpu_sibling_map(int cpu
)
358 bool has_mc
= boot_cpu_data
.x86_max_cores
> 1;
359 bool has_smt
= smp_num_siblings
> 1;
360 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
361 struct cpuinfo_x86
*o
;
364 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
366 if (!has_smt
&& !has_mc
) {
367 cpumask_set_cpu(cpu
, cpu_sibling_mask(cpu
));
368 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
369 cpumask_set_cpu(cpu
, cpu_core_mask(cpu
));
374 for_each_cpu(i
, cpu_sibling_setup_mask
) {
377 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
378 link_mask(sibling
, cpu
, i
);
380 if ((i
== cpu
) || (has_mc
&& match_llc(c
, o
)))
381 link_mask(llc_shared
, cpu
, i
);
386 * This needs a separate iteration over the cpus because we rely on all
387 * cpu_sibling_mask links to be set-up.
389 for_each_cpu(i
, cpu_sibling_setup_mask
) {
392 if ((i
== cpu
) || (has_mc
&& match_mc(c
, o
))) {
393 link_mask(core
, cpu
, i
);
396 * Does this new cpu bringup a new core?
398 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1) {
400 * for each core in package, increment
401 * the booted_cores for this new cpu
403 if (cpumask_first(cpu_sibling_mask(i
)) == i
)
406 * increment the core count for all
407 * the other cpus in this package
410 cpu_data(i
).booted_cores
++;
411 } else if (i
!= cpu
&& !c
->booted_cores
)
412 c
->booted_cores
= cpu_data(i
).booted_cores
;
417 /* maps the cpu to the sched domain representing multi-core */
418 const struct cpumask
*cpu_coregroup_mask(int cpu
)
420 return cpu_llc_shared_mask(cpu
);
423 static void impress_friends(void)
426 unsigned long bogosum
= 0;
428 * Allow the user to impress friends.
430 pr_debug("Before bogomips\n");
431 for_each_possible_cpu(cpu
)
432 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
433 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
434 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
437 (bogosum
/(5000/HZ
))%100);
439 pr_debug("Before bogocount - setting activated=1\n");
442 void __inquire_remote_apic(int apicid
)
444 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
445 const char * const names
[] = { "ID", "VERSION", "SPIV" };
449 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
451 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
452 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
457 status
= safe_apic_wait_icr_idle();
459 pr_cont("a previous APIC delivery may have failed\n");
461 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
466 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
467 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
470 case APIC_ICR_RR_VALID
:
471 status
= apic_read(APIC_RRR
);
472 pr_cont("%08x\n", status
);
481 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
482 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
483 * won't ... remember to clear down the APIC, etc later.
486 wakeup_secondary_cpu_via_nmi(int logical_apicid
, unsigned long start_eip
)
488 unsigned long send_status
, accept_status
= 0;
492 /* Boot on the stack */
493 /* Kick the second */
494 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, logical_apicid
);
496 pr_debug("Waiting for send to finish...\n");
497 send_status
= safe_apic_wait_icr_idle();
500 * Give the other CPU some time to accept the IPI.
503 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
504 maxlvt
= lapic_get_maxlvt();
505 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
506 apic_write(APIC_ESR
, 0);
507 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
509 pr_debug("NMI sent\n");
512 pr_err("APIC never delivered???\n");
514 pr_err("APIC delivery error (%lx)\n", accept_status
);
516 return (send_status
| accept_status
);
520 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
522 unsigned long send_status
, accept_status
= 0;
523 int maxlvt
, num_starts
, j
;
525 maxlvt
= lapic_get_maxlvt();
528 * Be paranoid about clearing APIC errors.
530 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
531 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
532 apic_write(APIC_ESR
, 0);
536 pr_debug("Asserting INIT\n");
539 * Turn INIT on target chip
544 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
547 pr_debug("Waiting for send to finish...\n");
548 send_status
= safe_apic_wait_icr_idle();
552 pr_debug("Deasserting INIT\n");
556 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
558 pr_debug("Waiting for send to finish...\n");
559 send_status
= safe_apic_wait_icr_idle();
562 atomic_set(&init_deasserted
, 1);
565 * Should we send STARTUP IPIs ?
567 * Determine this based on the APIC version.
568 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
570 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
576 * Paravirt / VMI wants a startup IPI hook here to set up the
577 * target processor state.
579 startup_ipi_hook(phys_apicid
, (unsigned long) start_secondary
,
583 * Run STARTUP IPI loop.
585 pr_debug("#startup loops: %d\n", num_starts
);
587 for (j
= 1; j
<= num_starts
; j
++) {
588 pr_debug("Sending STARTUP #%d\n", j
);
589 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
590 apic_write(APIC_ESR
, 0);
592 pr_debug("After apic_write\n");
599 /* Boot on the stack */
600 /* Kick the second */
601 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
605 * Give the other CPU some time to accept the IPI.
609 pr_debug("Startup point 1\n");
611 pr_debug("Waiting for send to finish...\n");
612 send_status
= safe_apic_wait_icr_idle();
615 * Give the other CPU some time to accept the IPI.
618 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
619 apic_write(APIC_ESR
, 0);
620 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
621 if (send_status
|| accept_status
)
624 pr_debug("After Startup\n");
627 pr_err("APIC never delivered???\n");
629 pr_err("APIC delivery error (%lx)\n", accept_status
);
631 return (send_status
| accept_status
);
634 /* reduce the number of lines printed when booting a large cpu count system */
635 static void __cpuinit
announce_cpu(int cpu
, int apicid
)
637 static int current_node
= -1;
638 int node
= early_cpu_to_node(cpu
);
640 if (system_state
== SYSTEM_BOOTING
) {
641 if (node
!= current_node
) {
642 if (current_node
> (-1))
645 pr_info("Booting Node %3d, Processors ", node
);
647 pr_cont(" #%d%s", cpu
, cpu
== (nr_cpu_ids
- 1) ? " OK\n" : "");
650 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
655 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
656 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
657 * Returns zero if CPU booted OK, else error code from
658 * ->wakeup_secondary_cpu.
660 static int __cpuinit
do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
)
662 volatile u32
*trampoline_status
=
663 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
664 /* start_ip had better be page-aligned! */
665 unsigned long start_ip
= real_mode_header
->trampoline_start
;
667 unsigned long boot_error
= 0;
670 /* Just in case we booted with a single CPU. */
671 alternatives_enable_smp();
673 idle
->thread
.sp
= (unsigned long) (((struct pt_regs
*)
674 (THREAD_SIZE
+ task_stack_page(idle
))) - 1);
675 per_cpu(current_task
, cpu
) = idle
;
678 /* Stack for startup_32 can be just as for start_secondary onwards */
681 clear_tsk_thread_flag(idle
, TIF_FORK
);
682 initial_gs
= per_cpu_offset(cpu
);
683 per_cpu(kernel_stack
, cpu
) =
684 (unsigned long)task_stack_page(idle
) -
685 KERNEL_STACK_OFFSET
+ THREAD_SIZE
;
687 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
688 initial_code
= (unsigned long)start_secondary
;
689 stack_start
= idle
->thread
.sp
;
691 /* So we see what's up */
692 announce_cpu(cpu
, apicid
);
695 * This grunge runs the startup process for
696 * the targeted processor.
699 atomic_set(&init_deasserted
, 0);
701 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
703 pr_debug("Setting warm reset code and vector.\n");
705 smpboot_setup_warm_reset_vector(start_ip
);
707 * Be paranoid about clearing APIC errors.
709 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
710 apic_write(APIC_ESR
, 0);
716 * Kick the secondary CPU. Use the method in the APIC driver
717 * if it's defined - or use an INIT boot APIC message otherwise:
719 if (apic
->wakeup_secondary_cpu
)
720 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
722 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
726 * allow APs to start initializing.
728 pr_debug("Before Callout %d\n", cpu
);
729 cpumask_set_cpu(cpu
, cpu_callout_mask
);
730 pr_debug("After Callout %d\n", cpu
);
733 * Wait 5s total for a response
735 for (timeout
= 0; timeout
< 50000; timeout
++) {
736 if (cpumask_test_cpu(cpu
, cpu_callin_mask
))
737 break; /* It has booted */
740 * Allow other tasks to run while we wait for the
741 * AP to come online. This also gives a chance
742 * for the MTRR work(triggered by the AP coming online)
743 * to be completed in the stop machine context.
748 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
749 print_cpu_msr(&cpu_data(cpu
));
750 pr_debug("CPU%d: has booted.\n", cpu
);
753 if (*trampoline_status
== 0xA5A5A5A5)
754 /* trampoline started but...? */
755 pr_err("CPU%d: Stuck ??\n", cpu
);
757 /* trampoline code not run */
758 pr_err("CPU%d: Not responding\n", cpu
);
759 if (apic
->inquire_remote_apic
)
760 apic
->inquire_remote_apic(apicid
);
765 /* Try to put things back the way they were before ... */
766 numa_remove_cpu(cpu
); /* was set by numa_add_cpu */
768 /* was set by do_boot_cpu() */
769 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
771 /* was set by cpu_init() */
772 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
774 set_cpu_present(cpu
, false);
775 per_cpu(x86_cpu_to_apicid
, cpu
) = BAD_APICID
;
778 /* mark "stuck" area as not stuck */
779 *trampoline_status
= 0;
781 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
783 * Cleanup possible dangling ends...
785 smpboot_restore_warm_reset_vector();
790 int __cpuinit
native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
792 int apicid
= apic
->cpu_present_to_apicid(cpu
);
796 WARN_ON(irqs_disabled());
798 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
800 if (apicid
== BAD_APICID
|| apicid
== boot_cpu_physical_apicid
||
801 !physid_isset(apicid
, phys_cpu_present_map
) ||
802 !apic
->apic_id_valid(apicid
)) {
803 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
808 * Already booted CPU?
810 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
811 pr_debug("do_boot_cpu %d Already started\n", cpu
);
816 * Save current MTRR state in case it was changed since early boot
817 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
821 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
823 /* the FPU context is blank, nobody can own it */
824 __cpu_disable_lazy_restore(cpu
);
826 err
= do_boot_cpu(apicid
, cpu
, tidle
);
828 pr_debug("do_boot_cpu failed %d\n", err
);
833 * Check TSC synchronization with the AP (keep irqs disabled
836 local_irq_save(flags
);
837 check_tsc_sync_source(cpu
);
838 local_irq_restore(flags
);
840 while (!cpu_online(cpu
)) {
842 touch_nmi_watchdog();
849 * arch_disable_smp_support() - disables SMP support for x86 at runtime
851 void arch_disable_smp_support(void)
853 disable_ioapic_support();
857 * Fall back to non SMP mode after errors.
859 * RED-PEN audit/test this more. I bet there is more state messed up here.
861 static __init
void disable_smp(void)
863 init_cpu_present(cpumask_of(0));
864 init_cpu_possible(cpumask_of(0));
865 smpboot_clear_io_apic_irqs();
867 if (smp_found_config
)
868 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
870 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
871 cpumask_set_cpu(0, cpu_sibling_mask(0));
872 cpumask_set_cpu(0, cpu_core_mask(0));
876 * Various sanity checks.
878 static int __init
smp_sanity_check(unsigned max_cpus
)
882 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
883 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
887 pr_warn("More than 8 CPUs detected - skipping them\n"
888 "Use CONFIG_X86_BIGSMP\n");
891 for_each_present_cpu(cpu
) {
893 set_cpu_present(cpu
, false);
898 for_each_possible_cpu(cpu
) {
900 set_cpu_possible(cpu
, false);
908 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
909 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
910 hard_smp_processor_id());
912 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
916 * If we couldn't find an SMP configuration at boot time,
917 * get out of here now!
919 if (!smp_found_config
&& !acpi_lapic
) {
921 pr_notice("SMP motherboard not detected\n");
923 if (APIC_init_uniprocessor())
924 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
929 * Should not be necessary because the MP table should list the boot
930 * CPU too, but we do it for the sake of robustness anyway.
932 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
933 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
934 boot_cpu_physical_apicid
);
935 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
940 * If we couldn't find a local APIC, then get out of here now!
942 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) &&
945 pr_err("BIOS bug, local APIC #%d not detected!...\n",
946 boot_cpu_physical_apicid
);
947 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
949 smpboot_clear_io_apic();
950 disable_ioapic_support();
957 * If SMP should be disabled, then really disable it!
960 pr_info("SMP mode deactivated\n");
961 smpboot_clear_io_apic();
965 bsp_end_local_APIC_setup();
972 static void __init
smp_cpu_index_default(void)
975 struct cpuinfo_x86
*c
;
977 for_each_possible_cpu(i
) {
979 /* mark all to hotplug */
980 c
->cpu_index
= nr_cpu_ids
;
985 * Prepare for SMP bootup. The MP table or ACPI has been read
986 * earlier. Just do some sanity checking here and enable APIC mode.
988 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
993 smp_cpu_index_default();
996 * Setup boot CPU information
998 smp_store_cpu_info(0); /* Final full version of the data */
999 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1002 current_thread_info()->cpu
= 0; /* needed? */
1003 for_each_possible_cpu(i
) {
1004 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1005 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1006 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1008 set_cpu_sibling_map(0);
1011 if (smp_sanity_check(max_cpus
) < 0) {
1012 pr_info("SMP disabled\n");
1017 default_setup_apic_routing();
1020 if (read_apic_id() != boot_cpu_physical_apicid
) {
1021 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1022 read_apic_id(), boot_cpu_physical_apicid
);
1023 /* Or can we switch back to PIC here? */
1030 * Switch from PIC to APIC mode.
1035 * Enable IO APIC before setting up error vector
1037 if (!skip_ioapic_setup
&& nr_ioapics
)
1040 bsp_end_local_APIC_setup();
1042 if (apic
->setup_portio_remap
)
1043 apic
->setup_portio_remap();
1045 smpboot_setup_io_apic();
1047 * Set up local APIC timer on boot CPU.
1050 pr_info("CPU%d: ", 0);
1051 print_cpu_info(&cpu_data(0));
1052 x86_init
.timers
.setup_percpu_clockev();
1057 set_mtrr_aps_delayed_init();
1062 void arch_enable_nonboot_cpus_begin(void)
1064 set_mtrr_aps_delayed_init();
1067 void arch_enable_nonboot_cpus_end(void)
1073 * Early setup to make printk work.
1075 void __init
native_smp_prepare_boot_cpu(void)
1077 int me
= smp_processor_id();
1078 switch_to_new_gdt(me
);
1079 /* already set me in cpu_online_mask in boot_cpu_init() */
1080 cpumask_set_cpu(me
, cpu_callout_mask
);
1081 per_cpu(cpu_state
, me
) = CPU_ONLINE
;
1084 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1086 pr_debug("Boot done\n");
1090 #ifdef CONFIG_X86_IO_APIC
1091 setup_ioapic_dest();
1096 static int __initdata setup_possible_cpus
= -1;
1097 static int __init
_setup_possible_cpus(char *str
)
1099 get_option(&str
, &setup_possible_cpus
);
1102 early_param("possible_cpus", _setup_possible_cpus
);
1106 * cpu_possible_mask should be static, it cannot change as cpu's
1107 * are onlined, or offlined. The reason is per-cpu data-structures
1108 * are allocated by some modules at init time, and dont expect to
1109 * do this dynamically on cpu arrival/departure.
1110 * cpu_present_mask on the other hand can change dynamically.
1111 * In case when cpu_hotplug is not compiled, then we resort to current
1112 * behaviour, which is cpu_possible == cpu_present.
1115 * Three ways to find out the number of additional hotplug CPUs:
1116 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1117 * - The user can overwrite it with possible_cpus=NUM
1118 * - Otherwise don't reserve additional CPUs.
1119 * We do this because additional CPUs waste a lot of memory.
1122 __init
void prefill_possible_map(void)
1126 /* no processor from mptable or madt */
1127 if (!num_processors
)
1130 i
= setup_max_cpus
?: 1;
1131 if (setup_possible_cpus
== -1) {
1132 possible
= num_processors
;
1133 #ifdef CONFIG_HOTPLUG_CPU
1135 possible
+= disabled_cpus
;
1141 possible
= setup_possible_cpus
;
1143 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1145 /* nr_cpu_ids could be reduced via nr_cpus= */
1146 if (possible
> nr_cpu_ids
) {
1147 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1148 possible
, nr_cpu_ids
);
1149 possible
= nr_cpu_ids
;
1152 #ifdef CONFIG_HOTPLUG_CPU
1153 if (!setup_max_cpus
)
1156 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1157 possible
, setup_max_cpus
);
1161 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1162 possible
, max_t(int, possible
- num_processors
, 0));
1164 for (i
= 0; i
< possible
; i
++)
1165 set_cpu_possible(i
, true);
1166 for (; i
< NR_CPUS
; i
++)
1167 set_cpu_possible(i
, false);
1169 nr_cpu_ids
= possible
;
1172 #ifdef CONFIG_HOTPLUG_CPU
1174 static void remove_siblinginfo(int cpu
)
1177 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1179 for_each_cpu(sibling
, cpu_core_mask(cpu
)) {
1180 cpumask_clear_cpu(cpu
, cpu_core_mask(sibling
));
1182 * last thread sibling in this cpu core going down
1184 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1)
1185 cpu_data(sibling
).booted_cores
--;
1188 for_each_cpu(sibling
, cpu_sibling_mask(cpu
))
1189 cpumask_clear_cpu(cpu
, cpu_sibling_mask(sibling
));
1190 cpumask_clear(cpu_sibling_mask(cpu
));
1191 cpumask_clear(cpu_core_mask(cpu
));
1192 c
->phys_proc_id
= 0;
1194 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1197 static void __ref
remove_cpu_from_maps(int cpu
)
1199 set_cpu_online(cpu
, false);
1200 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1201 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1202 /* was set by cpu_init() */
1203 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1204 numa_remove_cpu(cpu
);
1207 void cpu_disable_common(void)
1209 int cpu
= smp_processor_id();
1211 remove_siblinginfo(cpu
);
1213 /* It's now safe to remove this processor from the online map */
1215 remove_cpu_from_maps(cpu
);
1216 unlock_vector_lock();
1220 int native_cpu_disable(void)
1222 int cpu
= smp_processor_id();
1225 * Perhaps use cpufreq to drop frequency, but that could go
1226 * into generic code.
1228 * We won't take down the boot processor on i386 due to some
1229 * interrupts only being able to be serviced by the BSP.
1230 * Especially so if we're not using an IOAPIC -zwane
1237 cpu_disable_common();
1241 void native_cpu_die(unsigned int cpu
)
1243 /* We don't do anything here: idle task is faking death itself. */
1246 for (i
= 0; i
< 10; i
++) {
1247 /* They ack this in play_dead by setting CPU_DEAD */
1248 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1249 if (system_state
== SYSTEM_RUNNING
)
1250 pr_info("CPU %u is now offline\n", cpu
);
1255 pr_err("CPU %u didn't die...\n", cpu
);
1258 void play_dead_common(void)
1261 reset_lazy_tlbstate();
1262 amd_e400_remove_cpu(raw_smp_processor_id());
1266 __this_cpu_write(cpu_state
, CPU_DEAD
);
1269 * With physical CPU hotplug, we should halt the cpu
1271 local_irq_disable();
1275 * We need to flush the caches before going to sleep, lest we have
1276 * dirty data in our caches when we come back up.
1278 static inline void mwait_play_dead(void)
1280 unsigned int eax
, ebx
, ecx
, edx
;
1281 unsigned int highest_cstate
= 0;
1282 unsigned int highest_subcstate
= 0;
1285 struct cpuinfo_x86
*c
= __this_cpu_ptr(&cpu_info
);
1287 if (!(this_cpu_has(X86_FEATURE_MWAIT
) && mwait_usable(c
)))
1289 if (!this_cpu_has(X86_FEATURE_CLFLSH
))
1291 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1294 eax
= CPUID_MWAIT_LEAF
;
1296 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1299 * eax will be 0 if EDX enumeration is not valid.
1300 * Initialized below to cstate, sub_cstate value when EDX is valid.
1302 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1305 edx
>>= MWAIT_SUBSTATE_SIZE
;
1306 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1307 if (edx
& MWAIT_SUBSTATE_MASK
) {
1309 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1312 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1313 (highest_subcstate
- 1);
1317 * This should be a memory location in a cache line which is
1318 * unlikely to be touched by other processors. The actual
1319 * content is immaterial as it is not actually modified in any way.
1321 mwait_ptr
= ¤t_thread_info()->flags
;
1327 * The CLFLUSH is a workaround for erratum AAI65 for
1328 * the Xeon 7400 series. It's not clear it is actually
1329 * needed, but it should be harmless in either case.
1330 * The WBINVD is insufficient due to the spurious-wakeup
1331 * case where we return around the loop.
1334 __monitor(mwait_ptr
, 0, 0);
1340 static inline void hlt_play_dead(void)
1342 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1350 void native_play_dead(void)
1353 tboot_shutdown(TB_SHUTDOWN_WFS
);
1355 mwait_play_dead(); /* Only returns on failure */
1356 if (cpuidle_play_dead())
1360 #else /* ... !CONFIG_HOTPLUG_CPU */
1361 int native_cpu_disable(void)
1366 void native_cpu_die(unsigned int cpu
)
1368 /* We said "no" in __cpu_disable */
1372 void native_play_dead(void)