x86-32, mm: Add an initial page table for core bootstrapping
[deliverable/linux.git] / arch / x86 / kernel / smpboot.c
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
53
54 #include <asm/acpi.h>
55 #include <asm/desc.h>
56 #include <asm/nmi.h>
57 #include <asm/irq.h>
58 #include <asm/idle.h>
59 #include <asm/trampoline.h>
60 #include <asm/cpu.h>
61 #include <asm/numa.h>
62 #include <asm/pgtable.h>
63 #include <asm/tlbflush.h>
64 #include <asm/mtrr.h>
65 #include <asm/apic.h>
66 #include <asm/setup.h>
67 #include <asm/uv/uv.h>
68 #include <linux/mc146818rtc.h>
69
70 #include <asm/smpboot_hooks.h>
71 #include <asm/i8259.h>
72
73 #ifdef CONFIG_X86_32
74 u8 apicid_2_node[MAX_APICID];
75 #endif
76
77 /* State of each CPU */
78 DEFINE_PER_CPU(int, cpu_state) = { 0 };
79
80 /* Store all idle threads, this can be reused instead of creating
81 * a new thread. Also avoids complicated thread destroy functionality
82 * for idle threads.
83 */
84 #ifdef CONFIG_HOTPLUG_CPU
85 /*
86 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
87 * removed after init for !CONFIG_HOTPLUG_CPU.
88 */
89 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
90 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
91 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
92
93 /*
94 * We need this for trampoline_base protection from concurrent accesses when
95 * off- and onlining cores wildly.
96 */
97 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
98
99 void cpu_hotplug_driver_lock()
100 {
101 mutex_lock(&x86_cpu_hotplug_driver_mutex);
102 }
103
104 void cpu_hotplug_driver_unlock()
105 {
106 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
107 }
108
109 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
110 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
111 #else
112 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
113 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
114 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
115 #endif
116
117 /* Number of siblings per CPU package */
118 int smp_num_siblings = 1;
119 EXPORT_SYMBOL(smp_num_siblings);
120
121 /* Last level cache ID of each logical CPU */
122 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
123
124 /* representing HT siblings of each logical CPU */
125 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
126 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
127
128 /* representing HT and core siblings of each logical CPU */
129 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
130 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
131
132 /* Per CPU bogomips and other parameters */
133 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
134 EXPORT_PER_CPU_SYMBOL(cpu_info);
135
136 atomic_t init_deasserted;
137
138 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
139 /* which node each logical CPU is on */
140 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
141 EXPORT_SYMBOL(cpu_to_node_map);
142
143 /* set up a mapping between cpu and node. */
144 static void map_cpu_to_node(int cpu, int node)
145 {
146 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
147 cpumask_set_cpu(cpu, node_to_cpumask_map[node]);
148 cpu_to_node_map[cpu] = node;
149 }
150
151 /* undo a mapping between cpu and node. */
152 static void unmap_cpu_to_node(int cpu)
153 {
154 int node;
155
156 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
157 for (node = 0; node < MAX_NUMNODES; node++)
158 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]);
159 cpu_to_node_map[cpu] = 0;
160 }
161 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */
162 #define map_cpu_to_node(cpu, node) ({})
163 #define unmap_cpu_to_node(cpu) ({})
164 #endif
165
166 #ifdef CONFIG_X86_32
167 static int boot_cpu_logical_apicid;
168
169 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
170 { [0 ... NR_CPUS-1] = BAD_APICID };
171
172 static void map_cpu_to_logical_apicid(void)
173 {
174 int cpu = smp_processor_id();
175 int apicid = logical_smp_processor_id();
176 int node = apic->apicid_to_node(apicid);
177
178 if (!node_online(node))
179 node = first_online_node;
180
181 cpu_2_logical_apicid[cpu] = apicid;
182 map_cpu_to_node(cpu, node);
183 }
184
185 void numa_remove_cpu(int cpu)
186 {
187 cpu_2_logical_apicid[cpu] = BAD_APICID;
188 unmap_cpu_to_node(cpu);
189 }
190 #else
191 #define map_cpu_to_logical_apicid() do {} while (0)
192 #endif
193
194 /*
195 * Report back to the Boot Processor.
196 * Running on AP.
197 */
198 static void __cpuinit smp_callin(void)
199 {
200 int cpuid, phys_id;
201 unsigned long timeout;
202
203 /*
204 * If waken up by an INIT in an 82489DX configuration
205 * we may get here before an INIT-deassert IPI reaches
206 * our local APIC. We have to wait for the IPI or we'll
207 * lock up on an APIC access.
208 */
209 if (apic->wait_for_init_deassert)
210 apic->wait_for_init_deassert(&init_deasserted);
211
212 /*
213 * (This works even if the APIC is not enabled.)
214 */
215 phys_id = read_apic_id();
216 cpuid = smp_processor_id();
217 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
218 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
219 phys_id, cpuid);
220 }
221 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
222
223 /*
224 * STARTUP IPIs are fragile beasts as they might sometimes
225 * trigger some glue motherboard logic. Complete APIC bus
226 * silence for 1 second, this overestimates the time the
227 * boot CPU is spending to send the up to 2 STARTUP IPIs
228 * by a factor of two. This should be enough.
229 */
230
231 /*
232 * Waiting 2s total for startup (udelay is not yet working)
233 */
234 timeout = jiffies + 2*HZ;
235 while (time_before(jiffies, timeout)) {
236 /*
237 * Has the boot CPU finished it's STARTUP sequence?
238 */
239 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
240 break;
241 cpu_relax();
242 }
243
244 if (!time_before(jiffies, timeout)) {
245 panic("%s: CPU%d started up but did not get a callout!\n",
246 __func__, cpuid);
247 }
248
249 /*
250 * the boot CPU has finished the init stage and is spinning
251 * on callin_map until we finish. We are free to set up this
252 * CPU, first the APIC. (this is probably redundant on most
253 * boards)
254 */
255
256 pr_debug("CALLIN, before setup_local_APIC().\n");
257 if (apic->smp_callin_clear_local_apic)
258 apic->smp_callin_clear_local_apic();
259 setup_local_APIC();
260 end_local_APIC_setup();
261 map_cpu_to_logical_apicid();
262
263 /*
264 * Need to setup vector mappings before we enable interrupts.
265 */
266 setup_vector_irq(smp_processor_id());
267 /*
268 * Get our bogomips.
269 *
270 * Need to enable IRQs because it can take longer and then
271 * the NMI watchdog might kill us.
272 */
273 local_irq_enable();
274 calibrate_delay();
275 local_irq_disable();
276 pr_debug("Stack at about %p\n", &cpuid);
277
278 /*
279 * Save our processor parameters
280 */
281 smp_store_cpu_info(cpuid);
282
283 notify_cpu_starting(cpuid);
284
285 /*
286 * Allow the master to continue.
287 */
288 cpumask_set_cpu(cpuid, cpu_callin_mask);
289 }
290
291 /*
292 * Activate a secondary processor.
293 */
294 notrace static void __cpuinit start_secondary(void *unused)
295 {
296 /*
297 * Don't put *anything* before cpu_init(), SMP booting is too
298 * fragile that we want to limit the things done here to the
299 * most necessary things.
300 */
301 cpu_init();
302 preempt_disable();
303 smp_callin();
304
305 #ifdef CONFIG_X86_32
306 /* switch away from the initial page table */
307 load_cr3(swapper_pg_dir);
308 __flush_tlb_all();
309 #endif
310
311 /* otherwise gcc will move up smp_processor_id before the cpu_init */
312 barrier();
313 /*
314 * Check TSC synchronization with the BP:
315 */
316 check_tsc_sync_target();
317
318 if (nmi_watchdog == NMI_IO_APIC) {
319 legacy_pic->chip->mask(0);
320 enable_NMI_through_LVT0();
321 legacy_pic->chip->unmask(0);
322 }
323
324 /* This must be done before setting cpu_online_mask */
325 set_cpu_sibling_map(raw_smp_processor_id());
326 wmb();
327
328 /*
329 * We need to hold call_lock, so there is no inconsistency
330 * between the time smp_call_function() determines number of
331 * IPI recipients, and the time when the determination is made
332 * for which cpus receive the IPI. Holding this
333 * lock helps us to not include this cpu in a currently in progress
334 * smp_call_function().
335 *
336 * We need to hold vector_lock so there the set of online cpus
337 * does not change while we are assigning vectors to cpus. Holding
338 * this lock ensures we don't half assign or remove an irq from a cpu.
339 */
340 ipi_call_lock();
341 lock_vector_lock();
342 set_cpu_online(smp_processor_id(), true);
343 unlock_vector_lock();
344 ipi_call_unlock();
345 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
346 x86_platform.nmi_init();
347
348 /* enable local interrupts */
349 local_irq_enable();
350
351 /* to prevent fake stack check failure in clock setup */
352 boot_init_stack_canary();
353
354 x86_cpuinit.setup_percpu_clockev();
355
356 wmb();
357 cpu_idle();
358 }
359
360 #ifdef CONFIG_CPUMASK_OFFSTACK
361 /* In this case, llc_shared_map is a pointer to a cpumask. */
362 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst,
363 const struct cpuinfo_x86 *src)
364 {
365 struct cpumask *llc = dst->llc_shared_map;
366 *dst = *src;
367 dst->llc_shared_map = llc;
368 }
369 #else
370 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst,
371 const struct cpuinfo_x86 *src)
372 {
373 *dst = *src;
374 }
375 #endif /* CONFIG_CPUMASK_OFFSTACK */
376
377 /*
378 * The bootstrap kernel entry code has set these up. Save them for
379 * a given CPU
380 */
381
382 void __cpuinit smp_store_cpu_info(int id)
383 {
384 struct cpuinfo_x86 *c = &cpu_data(id);
385
386 copy_cpuinfo_x86(c, &boot_cpu_data);
387 c->cpu_index = id;
388 if (id != 0)
389 identify_secondary_cpu(c);
390 }
391
392
393 void __cpuinit set_cpu_sibling_map(int cpu)
394 {
395 int i;
396 struct cpuinfo_x86 *c = &cpu_data(cpu);
397
398 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
399
400 if (smp_num_siblings > 1) {
401 for_each_cpu(i, cpu_sibling_setup_mask) {
402 struct cpuinfo_x86 *o = &cpu_data(i);
403
404 if (c->phys_proc_id == o->phys_proc_id &&
405 c->cpu_core_id == o->cpu_core_id) {
406 cpumask_set_cpu(i, cpu_sibling_mask(cpu));
407 cpumask_set_cpu(cpu, cpu_sibling_mask(i));
408 cpumask_set_cpu(i, cpu_core_mask(cpu));
409 cpumask_set_cpu(cpu, cpu_core_mask(i));
410 cpumask_set_cpu(i, c->llc_shared_map);
411 cpumask_set_cpu(cpu, o->llc_shared_map);
412 }
413 }
414 } else {
415 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
416 }
417
418 cpumask_set_cpu(cpu, c->llc_shared_map);
419
420 if (current_cpu_data.x86_max_cores == 1) {
421 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
422 c->booted_cores = 1;
423 return;
424 }
425
426 for_each_cpu(i, cpu_sibling_setup_mask) {
427 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
428 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
429 cpumask_set_cpu(i, c->llc_shared_map);
430 cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map);
431 }
432 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
433 cpumask_set_cpu(i, cpu_core_mask(cpu));
434 cpumask_set_cpu(cpu, cpu_core_mask(i));
435 /*
436 * Does this new cpu bringup a new core?
437 */
438 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
439 /*
440 * for each core in package, increment
441 * the booted_cores for this new cpu
442 */
443 if (cpumask_first(cpu_sibling_mask(i)) == i)
444 c->booted_cores++;
445 /*
446 * increment the core count for all
447 * the other cpus in this package
448 */
449 if (i != cpu)
450 cpu_data(i).booted_cores++;
451 } else if (i != cpu && !c->booted_cores)
452 c->booted_cores = cpu_data(i).booted_cores;
453 }
454 }
455 }
456
457 /* maps the cpu to the sched domain representing multi-core */
458 const struct cpumask *cpu_coregroup_mask(int cpu)
459 {
460 struct cpuinfo_x86 *c = &cpu_data(cpu);
461 /*
462 * For perf, we return last level cache shared map.
463 * And for power savings, we return cpu_core_map
464 */
465 if ((sched_mc_power_savings || sched_smt_power_savings) &&
466 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
467 return cpu_core_mask(cpu);
468 else
469 return c->llc_shared_map;
470 }
471
472 static void impress_friends(void)
473 {
474 int cpu;
475 unsigned long bogosum = 0;
476 /*
477 * Allow the user to impress friends.
478 */
479 pr_debug("Before bogomips.\n");
480 for_each_possible_cpu(cpu)
481 if (cpumask_test_cpu(cpu, cpu_callout_mask))
482 bogosum += cpu_data(cpu).loops_per_jiffy;
483 printk(KERN_INFO
484 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
485 num_online_cpus(),
486 bogosum/(500000/HZ),
487 (bogosum/(5000/HZ))%100);
488
489 pr_debug("Before bogocount - setting activated=1.\n");
490 }
491
492 void __inquire_remote_apic(int apicid)
493 {
494 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
495 char *names[] = { "ID", "VERSION", "SPIV" };
496 int timeout;
497 u32 status;
498
499 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
500
501 for (i = 0; i < ARRAY_SIZE(regs); i++) {
502 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
503
504 /*
505 * Wait for idle.
506 */
507 status = safe_apic_wait_icr_idle();
508 if (status)
509 printk(KERN_CONT
510 "a previous APIC delivery may have failed\n");
511
512 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
513
514 timeout = 0;
515 do {
516 udelay(100);
517 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
518 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
519
520 switch (status) {
521 case APIC_ICR_RR_VALID:
522 status = apic_read(APIC_RRR);
523 printk(KERN_CONT "%08x\n", status);
524 break;
525 default:
526 printk(KERN_CONT "failed\n");
527 }
528 }
529 }
530
531 /*
532 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
533 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
534 * won't ... remember to clear down the APIC, etc later.
535 */
536 int __cpuinit
537 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
538 {
539 unsigned long send_status, accept_status = 0;
540 int maxlvt;
541
542 /* Target chip */
543 /* Boot on the stack */
544 /* Kick the second */
545 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
546
547 pr_debug("Waiting for send to finish...\n");
548 send_status = safe_apic_wait_icr_idle();
549
550 /*
551 * Give the other CPU some time to accept the IPI.
552 */
553 udelay(200);
554 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
555 maxlvt = lapic_get_maxlvt();
556 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
557 apic_write(APIC_ESR, 0);
558 accept_status = (apic_read(APIC_ESR) & 0xEF);
559 }
560 pr_debug("NMI sent.\n");
561
562 if (send_status)
563 printk(KERN_ERR "APIC never delivered???\n");
564 if (accept_status)
565 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
566
567 return (send_status | accept_status);
568 }
569
570 static int __cpuinit
571 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
572 {
573 unsigned long send_status, accept_status = 0;
574 int maxlvt, num_starts, j;
575
576 maxlvt = lapic_get_maxlvt();
577
578 /*
579 * Be paranoid about clearing APIC errors.
580 */
581 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
582 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
583 apic_write(APIC_ESR, 0);
584 apic_read(APIC_ESR);
585 }
586
587 pr_debug("Asserting INIT.\n");
588
589 /*
590 * Turn INIT on target chip
591 */
592 /*
593 * Send IPI
594 */
595 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
596 phys_apicid);
597
598 pr_debug("Waiting for send to finish...\n");
599 send_status = safe_apic_wait_icr_idle();
600
601 mdelay(10);
602
603 pr_debug("Deasserting INIT.\n");
604
605 /* Target chip */
606 /* Send IPI */
607 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
608
609 pr_debug("Waiting for send to finish...\n");
610 send_status = safe_apic_wait_icr_idle();
611
612 mb();
613 atomic_set(&init_deasserted, 1);
614
615 /*
616 * Should we send STARTUP IPIs ?
617 *
618 * Determine this based on the APIC version.
619 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
620 */
621 if (APIC_INTEGRATED(apic_version[phys_apicid]))
622 num_starts = 2;
623 else
624 num_starts = 0;
625
626 /*
627 * Paravirt / VMI wants a startup IPI hook here to set up the
628 * target processor state.
629 */
630 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
631 (unsigned long)stack_start.sp);
632
633 /*
634 * Run STARTUP IPI loop.
635 */
636 pr_debug("#startup loops: %d.\n", num_starts);
637
638 for (j = 1; j <= num_starts; j++) {
639 pr_debug("Sending STARTUP #%d.\n", j);
640 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
641 apic_write(APIC_ESR, 0);
642 apic_read(APIC_ESR);
643 pr_debug("After apic_write.\n");
644
645 /*
646 * STARTUP IPI
647 */
648
649 /* Target chip */
650 /* Boot on the stack */
651 /* Kick the second */
652 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
653 phys_apicid);
654
655 /*
656 * Give the other CPU some time to accept the IPI.
657 */
658 udelay(300);
659
660 pr_debug("Startup point 1.\n");
661
662 pr_debug("Waiting for send to finish...\n");
663 send_status = safe_apic_wait_icr_idle();
664
665 /*
666 * Give the other CPU some time to accept the IPI.
667 */
668 udelay(200);
669 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
670 apic_write(APIC_ESR, 0);
671 accept_status = (apic_read(APIC_ESR) & 0xEF);
672 if (send_status || accept_status)
673 break;
674 }
675 pr_debug("After Startup.\n");
676
677 if (send_status)
678 printk(KERN_ERR "APIC never delivered???\n");
679 if (accept_status)
680 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
681
682 return (send_status | accept_status);
683 }
684
685 struct create_idle {
686 struct work_struct work;
687 struct task_struct *idle;
688 struct completion done;
689 int cpu;
690 };
691
692 static void __cpuinit do_fork_idle(struct work_struct *work)
693 {
694 struct create_idle *c_idle =
695 container_of(work, struct create_idle, work);
696
697 c_idle->idle = fork_idle(c_idle->cpu);
698 complete(&c_idle->done);
699 }
700
701 /* reduce the number of lines printed when booting a large cpu count system */
702 static void __cpuinit announce_cpu(int cpu, int apicid)
703 {
704 static int current_node = -1;
705 int node = early_cpu_to_node(cpu);
706
707 if (system_state == SYSTEM_BOOTING) {
708 if (node != current_node) {
709 if (current_node > (-1))
710 pr_cont(" Ok.\n");
711 current_node = node;
712 pr_info("Booting Node %3d, Processors ", node);
713 }
714 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
715 return;
716 } else
717 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
718 node, cpu, apicid);
719 }
720
721 /*
722 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
723 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
724 * Returns zero if CPU booted OK, else error code from
725 * ->wakeup_secondary_cpu.
726 */
727 static int __cpuinit do_boot_cpu(int apicid, int cpu)
728 {
729 unsigned long boot_error = 0;
730 unsigned long start_ip;
731 int timeout;
732 struct create_idle c_idle = {
733 .cpu = cpu,
734 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
735 };
736
737 INIT_WORK_ON_STACK(&c_idle.work, do_fork_idle);
738
739 alternatives_smp_switch(1);
740
741 c_idle.idle = get_idle_for_cpu(cpu);
742
743 /*
744 * We can't use kernel_thread since we must avoid to
745 * reschedule the child.
746 */
747 if (c_idle.idle) {
748 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
749 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
750 init_idle(c_idle.idle, cpu);
751 goto do_rest;
752 }
753
754 schedule_work(&c_idle.work);
755 wait_for_completion(&c_idle.done);
756
757 if (IS_ERR(c_idle.idle)) {
758 printk("failed fork for CPU %d\n", cpu);
759 destroy_work_on_stack(&c_idle.work);
760 return PTR_ERR(c_idle.idle);
761 }
762
763 set_idle_for_cpu(cpu, c_idle.idle);
764 do_rest:
765 per_cpu(current_task, cpu) = c_idle.idle;
766 #ifdef CONFIG_X86_32
767 /* Stack for startup_32 can be just as for start_secondary onwards */
768 irq_ctx_init(cpu);
769 #else
770 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
771 initial_gs = per_cpu_offset(cpu);
772 per_cpu(kernel_stack, cpu) =
773 (unsigned long)task_stack_page(c_idle.idle) -
774 KERNEL_STACK_OFFSET + THREAD_SIZE;
775 #endif
776 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
777 initial_code = (unsigned long)start_secondary;
778 stack_start.sp = (void *) c_idle.idle->thread.sp;
779
780 /* start_ip had better be page-aligned! */
781 start_ip = setup_trampoline();
782
783 /* So we see what's up */
784 announce_cpu(cpu, apicid);
785
786 /*
787 * This grunge runs the startup process for
788 * the targeted processor.
789 */
790
791 atomic_set(&init_deasserted, 0);
792
793 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
794
795 pr_debug("Setting warm reset code and vector.\n");
796
797 smpboot_setup_warm_reset_vector(start_ip);
798 /*
799 * Be paranoid about clearing APIC errors.
800 */
801 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
802 apic_write(APIC_ESR, 0);
803 apic_read(APIC_ESR);
804 }
805 }
806
807 /*
808 * Kick the secondary CPU. Use the method in the APIC driver
809 * if it's defined - or use an INIT boot APIC message otherwise:
810 */
811 if (apic->wakeup_secondary_cpu)
812 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
813 else
814 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
815
816 if (!boot_error) {
817 /*
818 * allow APs to start initializing.
819 */
820 pr_debug("Before Callout %d.\n", cpu);
821 cpumask_set_cpu(cpu, cpu_callout_mask);
822 pr_debug("After Callout %d.\n", cpu);
823
824 /*
825 * Wait 5s total for a response
826 */
827 for (timeout = 0; timeout < 50000; timeout++) {
828 if (cpumask_test_cpu(cpu, cpu_callin_mask))
829 break; /* It has booted */
830 udelay(100);
831 /*
832 * Allow other tasks to run while we wait for the
833 * AP to come online. This also gives a chance
834 * for the MTRR work(triggered by the AP coming online)
835 * to be completed in the stop machine context.
836 */
837 schedule();
838 }
839
840 if (cpumask_test_cpu(cpu, cpu_callin_mask))
841 pr_debug("CPU%d: has booted.\n", cpu);
842 else {
843 boot_error = 1;
844 if (*((volatile unsigned char *)trampoline_base)
845 == 0xA5)
846 /* trampoline started but...? */
847 pr_err("CPU%d: Stuck ??\n", cpu);
848 else
849 /* trampoline code not run */
850 pr_err("CPU%d: Not responding.\n", cpu);
851 if (apic->inquire_remote_apic)
852 apic->inquire_remote_apic(apicid);
853 }
854 }
855
856 if (boot_error) {
857 /* Try to put things back the way they were before ... */
858 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
859
860 /* was set by do_boot_cpu() */
861 cpumask_clear_cpu(cpu, cpu_callout_mask);
862
863 /* was set by cpu_init() */
864 cpumask_clear_cpu(cpu, cpu_initialized_mask);
865
866 set_cpu_present(cpu, false);
867 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
868 }
869
870 /* mark "stuck" area as not stuck */
871 *((volatile unsigned long *)trampoline_base) = 0;
872
873 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
874 /*
875 * Cleanup possible dangling ends...
876 */
877 smpboot_restore_warm_reset_vector();
878 }
879
880 destroy_work_on_stack(&c_idle.work);
881 return boot_error;
882 }
883
884 int __cpuinit native_cpu_up(unsigned int cpu)
885 {
886 int apicid = apic->cpu_present_to_apicid(cpu);
887 unsigned long flags;
888 int err;
889
890 WARN_ON(irqs_disabled());
891
892 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
893
894 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
895 !physid_isset(apicid, phys_cpu_present_map)) {
896 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
897 return -EINVAL;
898 }
899
900 /*
901 * Already booted CPU?
902 */
903 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
904 pr_debug("do_boot_cpu %d Already started\n", cpu);
905 return -ENOSYS;
906 }
907
908 /*
909 * Save current MTRR state in case it was changed since early boot
910 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
911 */
912 mtrr_save_state();
913
914 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
915
916 err = do_boot_cpu(apicid, cpu);
917 if (err) {
918 pr_debug("do_boot_cpu failed %d\n", err);
919 return -EIO;
920 }
921
922 /*
923 * Check TSC synchronization with the AP (keep irqs disabled
924 * while doing so):
925 */
926 local_irq_save(flags);
927 check_tsc_sync_source(cpu);
928 local_irq_restore(flags);
929
930 while (!cpu_online(cpu)) {
931 cpu_relax();
932 touch_nmi_watchdog();
933 }
934
935 return 0;
936 }
937
938 /*
939 * Fall back to non SMP mode after errors.
940 *
941 * RED-PEN audit/test this more. I bet there is more state messed up here.
942 */
943 static __init void disable_smp(void)
944 {
945 init_cpu_present(cpumask_of(0));
946 init_cpu_possible(cpumask_of(0));
947 smpboot_clear_io_apic_irqs();
948
949 if (smp_found_config)
950 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
951 else
952 physid_set_mask_of_physid(0, &phys_cpu_present_map);
953 map_cpu_to_logical_apicid();
954 cpumask_set_cpu(0, cpu_sibling_mask(0));
955 cpumask_set_cpu(0, cpu_core_mask(0));
956 }
957
958 /*
959 * Various sanity checks.
960 */
961 static int __init smp_sanity_check(unsigned max_cpus)
962 {
963 preempt_disable();
964
965 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
966 if (def_to_bigsmp && nr_cpu_ids > 8) {
967 unsigned int cpu;
968 unsigned nr;
969
970 printk(KERN_WARNING
971 "More than 8 CPUs detected - skipping them.\n"
972 "Use CONFIG_X86_BIGSMP.\n");
973
974 nr = 0;
975 for_each_present_cpu(cpu) {
976 if (nr >= 8)
977 set_cpu_present(cpu, false);
978 nr++;
979 }
980
981 nr = 0;
982 for_each_possible_cpu(cpu) {
983 if (nr >= 8)
984 set_cpu_possible(cpu, false);
985 nr++;
986 }
987
988 nr_cpu_ids = 8;
989 }
990 #endif
991
992 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
993 printk(KERN_WARNING
994 "weird, boot CPU (#%d) not listed by the BIOS.\n",
995 hard_smp_processor_id());
996
997 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
998 }
999
1000 /*
1001 * If we couldn't find an SMP configuration at boot time,
1002 * get out of here now!
1003 */
1004 if (!smp_found_config && !acpi_lapic) {
1005 preempt_enable();
1006 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1007 disable_smp();
1008 if (APIC_init_uniprocessor())
1009 printk(KERN_NOTICE "Local APIC not detected."
1010 " Using dummy APIC emulation.\n");
1011 return -1;
1012 }
1013
1014 /*
1015 * Should not be necessary because the MP table should list the boot
1016 * CPU too, but we do it for the sake of robustness anyway.
1017 */
1018 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1019 printk(KERN_NOTICE
1020 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1021 boot_cpu_physical_apicid);
1022 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1023 }
1024 preempt_enable();
1025
1026 /*
1027 * If we couldn't find a local APIC, then get out of here now!
1028 */
1029 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1030 !cpu_has_apic) {
1031 if (!disable_apic) {
1032 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1033 boot_cpu_physical_apicid);
1034 pr_err("... forcing use of dummy APIC emulation."
1035 "(tell your hw vendor)\n");
1036 }
1037 smpboot_clear_io_apic();
1038 arch_disable_smp_support();
1039 return -1;
1040 }
1041
1042 verify_local_APIC();
1043
1044 /*
1045 * If SMP should be disabled, then really disable it!
1046 */
1047 if (!max_cpus) {
1048 printk(KERN_INFO "SMP mode deactivated.\n");
1049 smpboot_clear_io_apic();
1050
1051 localise_nmi_watchdog();
1052
1053 connect_bsp_APIC();
1054 setup_local_APIC();
1055 end_local_APIC_setup();
1056 return -1;
1057 }
1058
1059 return 0;
1060 }
1061
1062 static void __init smp_cpu_index_default(void)
1063 {
1064 int i;
1065 struct cpuinfo_x86 *c;
1066
1067 for_each_possible_cpu(i) {
1068 c = &cpu_data(i);
1069 /* mark all to hotplug */
1070 c->cpu_index = nr_cpu_ids;
1071 }
1072 }
1073
1074 /*
1075 * Prepare for SMP bootup. The MP table or ACPI has been read
1076 * earlier. Just do some sanity checking here and enable APIC mode.
1077 */
1078 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1079 {
1080 unsigned int i;
1081
1082 preempt_disable();
1083 smp_cpu_index_default();
1084 current_cpu_data = boot_cpu_data;
1085 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1086 mb();
1087 /*
1088 * Setup boot CPU information
1089 */
1090 smp_store_cpu_info(0); /* Final full version of the data */
1091 #ifdef CONFIG_X86_32
1092 boot_cpu_logical_apicid = logical_smp_processor_id();
1093 #endif
1094 current_thread_info()->cpu = 0; /* needed? */
1095 for_each_possible_cpu(i) {
1096 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1097 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1098 zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL);
1099 }
1100 set_cpu_sibling_map(0);
1101
1102 enable_IR_x2apic();
1103 default_setup_apic_routing();
1104
1105 if (smp_sanity_check(max_cpus) < 0) {
1106 printk(KERN_INFO "SMP disabled\n");
1107 disable_smp();
1108 goto out;
1109 }
1110
1111 preempt_disable();
1112 if (read_apic_id() != boot_cpu_physical_apicid) {
1113 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1114 read_apic_id(), boot_cpu_physical_apicid);
1115 /* Or can we switch back to PIC here? */
1116 }
1117 preempt_enable();
1118
1119 connect_bsp_APIC();
1120
1121 /*
1122 * Switch from PIC to APIC mode.
1123 */
1124 setup_local_APIC();
1125
1126 /*
1127 * Enable IO APIC before setting up error vector
1128 */
1129 if (!skip_ioapic_setup && nr_ioapics)
1130 enable_IO_APIC();
1131
1132 end_local_APIC_setup();
1133
1134 map_cpu_to_logical_apicid();
1135
1136 if (apic->setup_portio_remap)
1137 apic->setup_portio_remap();
1138
1139 smpboot_setup_io_apic();
1140 /*
1141 * Set up local APIC timer on boot CPU.
1142 */
1143
1144 printk(KERN_INFO "CPU%d: ", 0);
1145 print_cpu_info(&cpu_data(0));
1146 x86_init.timers.setup_percpu_clockev();
1147
1148 if (is_uv_system())
1149 uv_system_init();
1150
1151 set_mtrr_aps_delayed_init();
1152 out:
1153 preempt_enable();
1154 }
1155
1156 void arch_enable_nonboot_cpus_begin(void)
1157 {
1158 set_mtrr_aps_delayed_init();
1159 }
1160
1161 void arch_enable_nonboot_cpus_end(void)
1162 {
1163 mtrr_aps_init();
1164 }
1165
1166 /*
1167 * Early setup to make printk work.
1168 */
1169 void __init native_smp_prepare_boot_cpu(void)
1170 {
1171 int me = smp_processor_id();
1172 switch_to_new_gdt(me);
1173 /* already set me in cpu_online_mask in boot_cpu_init() */
1174 cpumask_set_cpu(me, cpu_callout_mask);
1175 per_cpu(cpu_state, me) = CPU_ONLINE;
1176 }
1177
1178 void __init native_smp_cpus_done(unsigned int max_cpus)
1179 {
1180 pr_debug("Boot done.\n");
1181
1182 impress_friends();
1183 #ifdef CONFIG_X86_IO_APIC
1184 setup_ioapic_dest();
1185 #endif
1186 check_nmi_watchdog();
1187 mtrr_aps_init();
1188 }
1189
1190 static int __initdata setup_possible_cpus = -1;
1191 static int __init _setup_possible_cpus(char *str)
1192 {
1193 get_option(&str, &setup_possible_cpus);
1194 return 0;
1195 }
1196 early_param("possible_cpus", _setup_possible_cpus);
1197
1198
1199 /*
1200 * cpu_possible_mask should be static, it cannot change as cpu's
1201 * are onlined, or offlined. The reason is per-cpu data-structures
1202 * are allocated by some modules at init time, and dont expect to
1203 * do this dynamically on cpu arrival/departure.
1204 * cpu_present_mask on the other hand can change dynamically.
1205 * In case when cpu_hotplug is not compiled, then we resort to current
1206 * behaviour, which is cpu_possible == cpu_present.
1207 * - Ashok Raj
1208 *
1209 * Three ways to find out the number of additional hotplug CPUs:
1210 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1211 * - The user can overwrite it with possible_cpus=NUM
1212 * - Otherwise don't reserve additional CPUs.
1213 * We do this because additional CPUs waste a lot of memory.
1214 * -AK
1215 */
1216 __init void prefill_possible_map(void)
1217 {
1218 int i, possible;
1219
1220 /* no processor from mptable or madt */
1221 if (!num_processors)
1222 num_processors = 1;
1223
1224 i = setup_max_cpus ?: 1;
1225 if (setup_possible_cpus == -1) {
1226 possible = num_processors;
1227 #ifdef CONFIG_HOTPLUG_CPU
1228 if (setup_max_cpus)
1229 possible += disabled_cpus;
1230 #else
1231 if (possible > i)
1232 possible = i;
1233 #endif
1234 } else
1235 possible = setup_possible_cpus;
1236
1237 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1238
1239 /* nr_cpu_ids could be reduced via nr_cpus= */
1240 if (possible > nr_cpu_ids) {
1241 printk(KERN_WARNING
1242 "%d Processors exceeds NR_CPUS limit of %d\n",
1243 possible, nr_cpu_ids);
1244 possible = nr_cpu_ids;
1245 }
1246
1247 #ifdef CONFIG_HOTPLUG_CPU
1248 if (!setup_max_cpus)
1249 #endif
1250 if (possible > i) {
1251 printk(KERN_WARNING
1252 "%d Processors exceeds max_cpus limit of %u\n",
1253 possible, setup_max_cpus);
1254 possible = i;
1255 }
1256
1257 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1258 possible, max_t(int, possible - num_processors, 0));
1259
1260 for (i = 0; i < possible; i++)
1261 set_cpu_possible(i, true);
1262 for (; i < NR_CPUS; i++)
1263 set_cpu_possible(i, false);
1264
1265 nr_cpu_ids = possible;
1266 }
1267
1268 #ifdef CONFIG_HOTPLUG_CPU
1269
1270 static void remove_siblinginfo(int cpu)
1271 {
1272 int sibling;
1273 struct cpuinfo_x86 *c = &cpu_data(cpu);
1274
1275 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1276 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1277 /*/
1278 * last thread sibling in this cpu core going down
1279 */
1280 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1281 cpu_data(sibling).booted_cores--;
1282 }
1283
1284 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1285 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1286 cpumask_clear(cpu_sibling_mask(cpu));
1287 cpumask_clear(cpu_core_mask(cpu));
1288 c->phys_proc_id = 0;
1289 c->cpu_core_id = 0;
1290 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1291 }
1292
1293 static void __ref remove_cpu_from_maps(int cpu)
1294 {
1295 set_cpu_online(cpu, false);
1296 cpumask_clear_cpu(cpu, cpu_callout_mask);
1297 cpumask_clear_cpu(cpu, cpu_callin_mask);
1298 /* was set by cpu_init() */
1299 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1300 numa_remove_cpu(cpu);
1301 }
1302
1303 void cpu_disable_common(void)
1304 {
1305 int cpu = smp_processor_id();
1306
1307 remove_siblinginfo(cpu);
1308
1309 /* It's now safe to remove this processor from the online map */
1310 lock_vector_lock();
1311 remove_cpu_from_maps(cpu);
1312 unlock_vector_lock();
1313 fixup_irqs();
1314 }
1315
1316 int native_cpu_disable(void)
1317 {
1318 int cpu = smp_processor_id();
1319
1320 /*
1321 * Perhaps use cpufreq to drop frequency, but that could go
1322 * into generic code.
1323 *
1324 * We won't take down the boot processor on i386 due to some
1325 * interrupts only being able to be serviced by the BSP.
1326 * Especially so if we're not using an IOAPIC -zwane
1327 */
1328 if (cpu == 0)
1329 return -EBUSY;
1330
1331 if (nmi_watchdog == NMI_LOCAL_APIC)
1332 stop_apic_nmi_watchdog(NULL);
1333 clear_local_APIC();
1334
1335 cpu_disable_common();
1336 return 0;
1337 }
1338
1339 void native_cpu_die(unsigned int cpu)
1340 {
1341 /* We don't do anything here: idle task is faking death itself. */
1342 unsigned int i;
1343
1344 for (i = 0; i < 10; i++) {
1345 /* They ack this in play_dead by setting CPU_DEAD */
1346 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1347 if (system_state == SYSTEM_RUNNING)
1348 pr_info("CPU %u is now offline\n", cpu);
1349
1350 if (1 == num_online_cpus())
1351 alternatives_smp_switch(0);
1352 return;
1353 }
1354 msleep(100);
1355 }
1356 pr_err("CPU %u didn't die...\n", cpu);
1357 }
1358
1359 void play_dead_common(void)
1360 {
1361 idle_task_exit();
1362 reset_lazy_tlbstate();
1363 irq_ctx_exit(raw_smp_processor_id());
1364 c1e_remove_cpu(raw_smp_processor_id());
1365
1366 mb();
1367 /* Ack it */
1368 __get_cpu_var(cpu_state) = CPU_DEAD;
1369
1370 /*
1371 * With physical CPU hotplug, we should halt the cpu
1372 */
1373 local_irq_disable();
1374 }
1375
1376 void native_play_dead(void)
1377 {
1378 play_dead_common();
1379 tboot_shutdown(TB_SHUTDOWN_WFS);
1380 wbinvd_halt();
1381 }
1382
1383 #else /* ... !CONFIG_HOTPLUG_CPU */
1384 int native_cpu_disable(void)
1385 {
1386 return -ENOSYS;
1387 }
1388
1389 void native_cpu_die(unsigned int cpu)
1390 {
1391 /* We said "no" in __cpu_disable */
1392 BUG();
1393 }
1394
1395 void native_play_dead(void)
1396 {
1397 BUG();
1398 }
1399
1400 #endif
This page took 0.062832 seconds and 6 git commands to generate.