1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/kernel.h>
4 #include <linux/sched.h>
5 #include <linux/init.h>
6 #include <linux/export.h>
7 #include <linux/timer.h>
8 #include <linux/acpi_pmtmr.h>
9 #include <linux/cpufreq.h>
10 #include <linux/delay.h>
11 #include <linux/clocksource.h>
12 #include <linux/percpu.h>
13 #include <linux/timex.h>
14 #include <linux/static_key.h>
17 #include <asm/timer.h>
18 #include <asm/vgtod.h>
20 #include <asm/delay.h>
21 #include <asm/hypervisor.h>
23 #include <asm/x86_init.h>
24 #include <asm/geode.h>
27 unsigned int __read_mostly cpu_khz
; /* TSC clocks / usec, not used here */
28 EXPORT_SYMBOL(cpu_khz
);
30 unsigned int __read_mostly tsc_khz
;
31 EXPORT_SYMBOL(tsc_khz
);
34 * TSC can be unstable due to cpufreq or due to unsynced TSCs
36 static int __read_mostly tsc_unstable
;
38 /* native_sched_clock() is called before tsc_init(), so
39 we must start with the TSC soft disabled to prevent
40 erroneous rdtsc usage on !boot_cpu_has(X86_FEATURE_TSC) processors */
41 static int __read_mostly tsc_disabled
= -1;
43 static DEFINE_STATIC_KEY_FALSE(__use_tsc
);
45 int tsc_clocksource_reliable
;
47 static u32 art_to_tsc_numerator
;
48 static u32 art_to_tsc_denominator
;
49 static u64 art_to_tsc_offset
;
50 struct clocksource
*art_related_clocksource
;
53 * Use a ring-buffer like data structure, where a writer advances the head by
54 * writing a new data entry and a reader advances the tail when it observes a
57 * Writers are made to wait on readers until there's space to write a new
60 * This means that we can always use an {offset, mul} pair to compute a ns
61 * value that is 'roughly' in the right direction, even if we're writing a new
62 * {offset, mul} pair during the clock read.
64 * The down-side is that we can no longer guarantee strict monotonicity anymore
65 * (assuming the TSC was that to begin with), because while we compute the
66 * intersection point of the two clock slopes and make sure the time is
67 * continuous at the point of switching; we can no longer guarantee a reader is
68 * strictly before or after the switch point.
70 * It does mean a reader no longer needs to disable IRQs in order to avoid
71 * CPU-Freq updates messing with his times, and similarly an NMI reader will
72 * no longer run the risk of hitting half-written state.
76 struct cyc2ns_data data
[2]; /* 0 + 2*24 = 48 */
77 struct cyc2ns_data
*head
; /* 48 + 8 = 56 */
78 struct cyc2ns_data
*tail
; /* 56 + 8 = 64 */
79 }; /* exactly fits one cacheline */
81 static DEFINE_PER_CPU_ALIGNED(struct cyc2ns
, cyc2ns
);
83 struct cyc2ns_data
*cyc2ns_read_begin(void)
85 struct cyc2ns_data
*head
;
89 head
= this_cpu_read(cyc2ns
.head
);
91 * Ensure we observe the entry when we observe the pointer to it.
92 * matches the wmb from cyc2ns_write_end().
94 smp_read_barrier_depends();
101 void cyc2ns_read_end(struct cyc2ns_data
*head
)
105 * If we're the outer most nested read; update the tail pointer
106 * when we're done. This notifies possible pending writers
107 * that we've observed the head pointer and that the other
110 if (!--head
->__count
) {
112 * x86-TSO does not reorder writes with older reads;
113 * therefore once this write becomes visible to another
114 * cpu, we must be finished reading the cyc2ns_data.
116 * matches with cyc2ns_write_begin().
118 this_cpu_write(cyc2ns
.tail
, head
);
124 * Begin writing a new @data entry for @cpu.
126 * Assumes some sort of write side lock; currently 'provided' by the assumption
127 * that cpufreq will call its notifiers sequentially.
129 static struct cyc2ns_data
*cyc2ns_write_begin(int cpu
)
131 struct cyc2ns
*c2n
= &per_cpu(cyc2ns
, cpu
);
132 struct cyc2ns_data
*data
= c2n
->data
;
134 if (data
== c2n
->head
)
137 /* XXX send an IPI to @cpu in order to guarantee a read? */
140 * When we observe the tail write from cyc2ns_read_end(),
141 * the cpu must be done with that entry and its safe
142 * to start writing to it.
144 while (c2n
->tail
== data
)
150 static void cyc2ns_write_end(int cpu
, struct cyc2ns_data
*data
)
152 struct cyc2ns
*c2n
= &per_cpu(cyc2ns
, cpu
);
155 * Ensure the @data writes are visible before we publish the
156 * entry. Matches the data-depencency in cyc2ns_read_begin().
160 ACCESS_ONCE(c2n
->head
) = data
;
164 * Accelerators for sched_clock()
165 * convert from cycles(64bits) => nanoseconds (64bits)
167 * ns = cycles / (freq / ns_per_sec)
168 * ns = cycles * (ns_per_sec / freq)
169 * ns = cycles * (10^9 / (cpu_khz * 10^3))
170 * ns = cycles * (10^6 / cpu_khz)
172 * Then we use scaling math (suggested by george@mvista.com) to get:
173 * ns = cycles * (10^6 * SC / cpu_khz) / SC
174 * ns = cycles * cyc2ns_scale / SC
176 * And since SC is a constant power of two, we can convert the div
177 * into a shift. The larger SC is, the more accurate the conversion, but
178 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
179 * (64-bit result) can be used.
181 * We can use khz divisor instead of mhz to keep a better precision.
182 * (mathieu.desnoyers@polymtl.ca)
184 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
187 static void cyc2ns_data_init(struct cyc2ns_data
*data
)
189 data
->cyc2ns_mul
= 0;
190 data
->cyc2ns_shift
= 0;
191 data
->cyc2ns_offset
= 0;
195 static void cyc2ns_init(int cpu
)
197 struct cyc2ns
*c2n
= &per_cpu(cyc2ns
, cpu
);
199 cyc2ns_data_init(&c2n
->data
[0]);
200 cyc2ns_data_init(&c2n
->data
[1]);
202 c2n
->head
= c2n
->data
;
203 c2n
->tail
= c2n
->data
;
206 static inline unsigned long long cycles_2_ns(unsigned long long cyc
)
208 struct cyc2ns_data
*data
, *tail
;
209 unsigned long long ns
;
212 * See cyc2ns_read_*() for details; replicated in order to avoid
213 * an extra few instructions that came with the abstraction.
214 * Notable, it allows us to only do the __count and tail update
215 * dance when its actually needed.
218 preempt_disable_notrace();
219 data
= this_cpu_read(cyc2ns
.head
);
220 tail
= this_cpu_read(cyc2ns
.tail
);
222 if (likely(data
== tail
)) {
223 ns
= data
->cyc2ns_offset
;
224 ns
+= mul_u64_u32_shr(cyc
, data
->cyc2ns_mul
, data
->cyc2ns_shift
);
230 ns
= data
->cyc2ns_offset
;
231 ns
+= mul_u64_u32_shr(cyc
, data
->cyc2ns_mul
, data
->cyc2ns_shift
);
235 if (!--data
->__count
)
236 this_cpu_write(cyc2ns
.tail
, data
);
238 preempt_enable_notrace();
243 static void set_cyc2ns_scale(unsigned long khz
, int cpu
)
245 unsigned long long tsc_now
, ns_now
;
246 struct cyc2ns_data
*data
;
249 local_irq_save(flags
);
250 sched_clock_idle_sleep_event();
255 data
= cyc2ns_write_begin(cpu
);
258 ns_now
= cycles_2_ns(tsc_now
);
261 * Compute a new multiplier as per the above comment and ensure our
262 * time function is continuous; see the comment near struct
265 clocks_calc_mult_shift(&data
->cyc2ns_mul
, &data
->cyc2ns_shift
, khz
,
269 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is
270 * not expected to be greater than 31 due to the original published
271 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit
272 * value) - refer perf_event_mmap_page documentation in perf_event.h.
274 if (data
->cyc2ns_shift
== 32) {
275 data
->cyc2ns_shift
= 31;
276 data
->cyc2ns_mul
>>= 1;
279 data
->cyc2ns_offset
= ns_now
-
280 mul_u64_u32_shr(tsc_now
, data
->cyc2ns_mul
, data
->cyc2ns_shift
);
282 cyc2ns_write_end(cpu
, data
);
285 sched_clock_idle_wakeup_event(0);
286 local_irq_restore(flags
);
289 * Scheduler clock - returns current time in nanosec units.
291 u64
native_sched_clock(void)
293 if (static_branch_likely(&__use_tsc
)) {
294 u64 tsc_now
= rdtsc();
296 /* return the value in ns */
297 return cycles_2_ns(tsc_now
);
301 * Fall back to jiffies if there's no TSC available:
302 * ( But note that we still use it if the TSC is marked
303 * unstable. We do this because unlike Time Of Day,
304 * the scheduler clock tolerates small errors and it's
305 * very important for it to be as fast as the platform
309 /* No locking but a rare wrong value is not a big deal: */
310 return (jiffies_64
- INITIAL_JIFFIES
) * (1000000000 / HZ
);
314 * Generate a sched_clock if you already have a TSC value.
316 u64
native_sched_clock_from_tsc(u64 tsc
)
318 return cycles_2_ns(tsc
);
321 /* We need to define a real function for sched_clock, to override the
322 weak default version */
323 #ifdef CONFIG_PARAVIRT
324 unsigned long long sched_clock(void)
326 return paravirt_sched_clock();
330 sched_clock(void) __attribute__((alias("native_sched_clock")));
333 int check_tsc_unstable(void)
337 EXPORT_SYMBOL_GPL(check_tsc_unstable
);
339 #ifdef CONFIG_X86_TSC
340 int __init
notsc_setup(char *str
)
342 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
348 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
351 int __init
notsc_setup(char *str
)
353 setup_clear_cpu_cap(X86_FEATURE_TSC
);
358 __setup("notsc", notsc_setup
);
360 static int no_sched_irq_time
;
362 static int __init
tsc_setup(char *str
)
364 if (!strcmp(str
, "reliable"))
365 tsc_clocksource_reliable
= 1;
366 if (!strncmp(str
, "noirqtime", 9))
367 no_sched_irq_time
= 1;
371 __setup("tsc=", tsc_setup
);
373 #define MAX_RETRIES 5
374 #define SMI_TRESHOLD 50000
377 * Read TSC and the reference counters. Take care of SMI disturbance
379 static u64
tsc_read_refs(u64
*p
, int hpet
)
384 for (i
= 0; i
< MAX_RETRIES
; i
++) {
387 *p
= hpet_readl(HPET_COUNTER
) & 0xFFFFFFFF;
389 *p
= acpi_pm_read_early();
391 if ((t2
- t1
) < SMI_TRESHOLD
)
398 * Calculate the TSC frequency from HPET reference
400 static unsigned long calc_hpet_ref(u64 deltatsc
, u64 hpet1
, u64 hpet2
)
405 hpet2
+= 0x100000000ULL
;
407 tmp
= ((u64
)hpet2
* hpet_readl(HPET_PERIOD
));
408 do_div(tmp
, 1000000);
409 do_div(deltatsc
, tmp
);
411 return (unsigned long) deltatsc
;
415 * Calculate the TSC frequency from PMTimer reference
417 static unsigned long calc_pmtimer_ref(u64 deltatsc
, u64 pm1
, u64 pm2
)
425 pm2
+= (u64
)ACPI_PM_OVRRUN
;
427 tmp
= pm2
* 1000000000LL;
428 do_div(tmp
, PMTMR_TICKS_PER_SEC
);
429 do_div(deltatsc
, tmp
);
431 return (unsigned long) deltatsc
;
435 #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
436 #define CAL_PIT_LOOPS 1000
439 #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
440 #define CAL2_PIT_LOOPS 5000
444 * Try to calibrate the TSC against the Programmable
445 * Interrupt Timer and return the frequency of the TSC
448 * Return ULONG_MAX on failure to calibrate.
450 static unsigned long pit_calibrate_tsc(u32 latch
, unsigned long ms
, int loopmin
)
452 u64 tsc
, t1
, t2
, delta
;
453 unsigned long tscmin
, tscmax
;
456 /* Set the Gate high, disable speaker */
457 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
460 * Setup CTC channel 2* for mode 0, (interrupt on terminal
461 * count mode), binary count. Set the latch register to 50ms
462 * (LSB then MSB) to begin countdown.
465 outb(latch
& 0xff, 0x42);
466 outb(latch
>> 8, 0x42);
468 tsc
= t1
= t2
= get_cycles();
473 while ((inb(0x61) & 0x20) == 0) {
477 if ((unsigned long) delta
< tscmin
)
478 tscmin
= (unsigned int) delta
;
479 if ((unsigned long) delta
> tscmax
)
480 tscmax
= (unsigned int) delta
;
487 * If we were not able to read the PIT more than loopmin
488 * times, then we have been hit by a massive SMI
490 * If the maximum is 10 times larger than the minimum,
491 * then we got hit by an SMI as well.
493 if (pitcnt
< loopmin
|| tscmax
> 10 * tscmin
)
496 /* Calculate the PIT value */
503 * This reads the current MSB of the PIT counter, and
504 * checks if we are running on sufficiently fast and
505 * non-virtualized hardware.
507 * Our expectations are:
509 * - the PIT is running at roughly 1.19MHz
511 * - each IO is going to take about 1us on real hardware,
512 * but we allow it to be much faster (by a factor of 10) or
513 * _slightly_ slower (ie we allow up to a 2us read+counter
514 * update - anything else implies a unacceptably slow CPU
515 * or PIT for the fast calibration to work.
517 * - with 256 PIT ticks to read the value, we have 214us to
518 * see the same MSB (and overhead like doing a single TSC
519 * read per MSB value etc).
521 * - We're doing 2 reads per loop (LSB, MSB), and we expect
522 * them each to take about a microsecond on real hardware.
523 * So we expect a count value of around 100. But we'll be
524 * generous, and accept anything over 50.
526 * - if the PIT is stuck, and we see *many* more reads, we
527 * return early (and the next caller of pit_expect_msb()
528 * then consider it a failure when they don't see the
529 * next expected value).
531 * These expectations mean that we know that we have seen the
532 * transition from one expected value to another with a fairly
533 * high accuracy, and we didn't miss any events. We can thus
534 * use the TSC value at the transitions to calculate a pretty
535 * good value for the TSC frequencty.
537 static inline int pit_verify_msb(unsigned char val
)
541 return inb(0x42) == val
;
544 static inline int pit_expect_msb(unsigned char val
, u64
*tscp
, unsigned long *deltap
)
547 u64 tsc
= 0, prev_tsc
= 0;
549 for (count
= 0; count
< 50000; count
++) {
550 if (!pit_verify_msb(val
))
555 *deltap
= get_cycles() - prev_tsc
;
559 * We require _some_ success, but the quality control
560 * will be based on the error terms on the TSC values.
566 * How many MSB values do we want to see? We aim for
567 * a maximum error rate of 500ppm (in practice the
568 * real error is much smaller), but refuse to spend
569 * more than 50ms on it.
571 #define MAX_QUICK_PIT_MS 50
572 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
574 static unsigned long quick_pit_calibrate(void)
578 unsigned long d1
, d2
;
580 /* Set the Gate high, disable speaker */
581 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
584 * Counter 2, mode 0 (one-shot), binary count
586 * NOTE! Mode 2 decrements by two (and then the
587 * output is flipped each time, giving the same
588 * final output frequency as a decrement-by-one),
589 * so mode 0 is much better when looking at the
594 /* Start at 0xffff */
599 * The PIT starts counting at the next edge, so we
600 * need to delay for a microsecond. The easiest way
601 * to do that is to just read back the 16-bit counter
606 if (pit_expect_msb(0xff, &tsc
, &d1
)) {
607 for (i
= 1; i
<= MAX_QUICK_PIT_ITERATIONS
; i
++) {
608 if (!pit_expect_msb(0xff-i
, &delta
, &d2
))
614 * Extrapolate the error and fail fast if the error will
615 * never be below 500 ppm.
618 d1
+ d2
>= (delta
* MAX_QUICK_PIT_ITERATIONS
) >> 11)
622 * Iterate until the error is less than 500 ppm
624 if (d1
+d2
>= delta
>> 11)
628 * Check the PIT one more time to verify that
629 * all TSC reads were stable wrt the PIT.
631 * This also guarantees serialization of the
632 * last cycle read ('d2') in pit_expect_msb.
634 if (!pit_verify_msb(0xfe - i
))
639 pr_info("Fast TSC calibration failed\n");
644 * Ok, if we get here, then we've seen the
645 * MSB of the PIT decrement 'i' times, and the
646 * error has shrunk to less than 500 ppm.
648 * As a result, we can depend on there not being
649 * any odd delays anywhere, and the TSC reads are
650 * reliable (within the error).
652 * kHz = ticks / time-in-seconds / 1000;
653 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
654 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
656 delta
*= PIT_TICK_RATE
;
657 do_div(delta
, i
*256*1000);
658 pr_info("Fast TSC calibration using PIT\n");
663 * native_calibrate_tsc
664 * Determine TSC frequency via CPUID, else return 0.
666 unsigned long native_calibrate_tsc(void)
668 unsigned int eax_denominator
, ebx_numerator
, ecx_hz
, edx
;
669 unsigned int crystal_khz
;
671 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
)
674 if (boot_cpu_data
.cpuid_level
< 0x15)
677 eax_denominator
= ebx_numerator
= ecx_hz
= edx
= 0;
679 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
680 cpuid(0x15, &eax_denominator
, &ebx_numerator
, &ecx_hz
, &edx
);
682 if (ebx_numerator
== 0 || eax_denominator
== 0)
685 crystal_khz
= ecx_hz
/ 1000;
687 if (crystal_khz
== 0) {
688 switch (boot_cpu_data
.x86_model
) {
691 crystal_khz
= 24000; /* 24.0 MHz */
694 crystal_khz
= 19200; /* 19.2 MHz */
699 return crystal_khz
* ebx_numerator
/ eax_denominator
;
702 static unsigned long cpu_khz_from_cpuid(void)
704 unsigned int eax_base_mhz
, ebx_max_mhz
, ecx_bus_mhz
, edx
;
706 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
)
709 if (boot_cpu_data
.cpuid_level
< 0x16)
712 eax_base_mhz
= ebx_max_mhz
= ecx_bus_mhz
= edx
= 0;
714 cpuid(0x16, &eax_base_mhz
, &ebx_max_mhz
, &ecx_bus_mhz
, &edx
);
716 return eax_base_mhz
* 1000;
720 * native_calibrate_cpu - calibrate the cpu on boot
722 unsigned long native_calibrate_cpu(void)
724 u64 tsc1
, tsc2
, delta
, ref1
, ref2
;
725 unsigned long tsc_pit_min
= ULONG_MAX
, tsc_ref_min
= ULONG_MAX
;
726 unsigned long flags
, latch
, ms
, fast_calibrate
;
727 int hpet
= is_hpet_enabled(), i
, loopmin
;
729 fast_calibrate
= cpu_khz_from_cpuid();
731 return fast_calibrate
;
733 fast_calibrate
= cpu_khz_from_msr();
735 return fast_calibrate
;
737 local_irq_save(flags
);
738 fast_calibrate
= quick_pit_calibrate();
739 local_irq_restore(flags
);
741 return fast_calibrate
;
744 * Run 5 calibration loops to get the lowest frequency value
745 * (the best estimate). We use two different calibration modes
748 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
749 * load a timeout of 50ms. We read the time right after we
750 * started the timer and wait until the PIT count down reaches
751 * zero. In each wait loop iteration we read the TSC and check
752 * the delta to the previous read. We keep track of the min
753 * and max values of that delta. The delta is mostly defined
754 * by the IO time of the PIT access, so we can detect when a
755 * SMI/SMM disturbance happened between the two reads. If the
756 * maximum time is significantly larger than the minimum time,
757 * then we discard the result and have another try.
759 * 2) Reference counter. If available we use the HPET or the
760 * PMTIMER as a reference to check the sanity of that value.
761 * We use separate TSC readouts and check inside of the
762 * reference read for a SMI/SMM disturbance. We dicard
763 * disturbed values here as well. We do that around the PIT
764 * calibration delay loop as we have to wait for a certain
765 * amount of time anyway.
768 /* Preset PIT loop values */
771 loopmin
= CAL_PIT_LOOPS
;
773 for (i
= 0; i
< 3; i
++) {
774 unsigned long tsc_pit_khz
;
777 * Read the start value and the reference count of
778 * hpet/pmtimer when available. Then do the PIT
779 * calibration, which will take at least 50ms, and
780 * read the end value.
782 local_irq_save(flags
);
783 tsc1
= tsc_read_refs(&ref1
, hpet
);
784 tsc_pit_khz
= pit_calibrate_tsc(latch
, ms
, loopmin
);
785 tsc2
= tsc_read_refs(&ref2
, hpet
);
786 local_irq_restore(flags
);
788 /* Pick the lowest PIT TSC calibration so far */
789 tsc_pit_min
= min(tsc_pit_min
, tsc_pit_khz
);
791 /* hpet or pmtimer available ? */
795 /* Check, whether the sampling was disturbed by an SMI */
796 if (tsc1
== ULLONG_MAX
|| tsc2
== ULLONG_MAX
)
799 tsc2
= (tsc2
- tsc1
) * 1000000LL;
801 tsc2
= calc_hpet_ref(tsc2
, ref1
, ref2
);
803 tsc2
= calc_pmtimer_ref(tsc2
, ref1
, ref2
);
805 tsc_ref_min
= min(tsc_ref_min
, (unsigned long) tsc2
);
807 /* Check the reference deviation */
808 delta
= ((u64
) tsc_pit_min
) * 100;
809 do_div(delta
, tsc_ref_min
);
812 * If both calibration results are inside a 10% window
813 * then we can be sure, that the calibration
814 * succeeded. We break out of the loop right away. We
815 * use the reference value, as it is more precise.
817 if (delta
>= 90 && delta
<= 110) {
818 pr_info("PIT calibration matches %s. %d loops\n",
819 hpet
? "HPET" : "PMTIMER", i
+ 1);
824 * Check whether PIT failed more than once. This
825 * happens in virtualized environments. We need to
826 * give the virtual PC a slightly longer timeframe for
827 * the HPET/PMTIMER to make the result precise.
829 if (i
== 1 && tsc_pit_min
== ULONG_MAX
) {
832 loopmin
= CAL2_PIT_LOOPS
;
837 * Now check the results.
839 if (tsc_pit_min
== ULONG_MAX
) {
840 /* PIT gave no useful value */
841 pr_warn("Unable to calibrate against PIT\n");
843 /* We don't have an alternative source, disable TSC */
844 if (!hpet
&& !ref1
&& !ref2
) {
845 pr_notice("No reference (HPET/PMTIMER) available\n");
849 /* The alternative source failed as well, disable TSC */
850 if (tsc_ref_min
== ULONG_MAX
) {
851 pr_warn("HPET/PMTIMER calibration failed\n");
855 /* Use the alternative source */
856 pr_info("using %s reference calibration\n",
857 hpet
? "HPET" : "PMTIMER");
862 /* We don't have an alternative source, use the PIT calibration value */
863 if (!hpet
&& !ref1
&& !ref2
) {
864 pr_info("Using PIT calibration value\n");
868 /* The alternative source failed, use the PIT calibration value */
869 if (tsc_ref_min
== ULONG_MAX
) {
870 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
875 * The calibration values differ too much. In doubt, we use
876 * the PIT value as we know that there are PMTIMERs around
877 * running at double speed. At least we let the user know:
879 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
880 hpet
? "HPET" : "PMTIMER", tsc_pit_min
, tsc_ref_min
);
881 pr_info("Using PIT calibration value\n");
885 int recalibrate_cpu_khz(void)
888 unsigned long cpu_khz_old
= cpu_khz
;
890 if (!boot_cpu_has(X86_FEATURE_TSC
))
893 cpu_khz
= x86_platform
.calibrate_cpu();
894 tsc_khz
= x86_platform
.calibrate_tsc();
897 else if (abs(cpu_khz
- tsc_khz
) * 10 > tsc_khz
)
899 cpu_data(0).loops_per_jiffy
= cpufreq_scale(cpu_data(0).loops_per_jiffy
,
900 cpu_khz_old
, cpu_khz
);
908 EXPORT_SYMBOL(recalibrate_cpu_khz
);
911 static unsigned long long cyc2ns_suspend
;
913 void tsc_save_sched_clock_state(void)
915 if (!sched_clock_stable())
918 cyc2ns_suspend
= sched_clock();
922 * Even on processors with invariant TSC, TSC gets reset in some the
923 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
924 * arbitrary value (still sync'd across cpu's) during resume from such sleep
925 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
926 * that sched_clock() continues from the point where it was left off during
929 void tsc_restore_sched_clock_state(void)
931 unsigned long long offset
;
935 if (!sched_clock_stable())
938 local_irq_save(flags
);
941 * We're coming out of suspend, there's no concurrency yet; don't
942 * bother being nice about the RCU stuff, just write to both
946 this_cpu_write(cyc2ns
.data
[0].cyc2ns_offset
, 0);
947 this_cpu_write(cyc2ns
.data
[1].cyc2ns_offset
, 0);
949 offset
= cyc2ns_suspend
- sched_clock();
951 for_each_possible_cpu(cpu
) {
952 per_cpu(cyc2ns
.data
[0].cyc2ns_offset
, cpu
) = offset
;
953 per_cpu(cyc2ns
.data
[1].cyc2ns_offset
, cpu
) = offset
;
956 local_irq_restore(flags
);
959 #ifdef CONFIG_CPU_FREQ
961 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
964 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
965 * not that important because current Opteron setups do not support
966 * scaling on SMP anyroads.
968 * Should fix up last_tsc too. Currently gettimeofday in the
969 * first tick after the change will be slightly wrong.
972 static unsigned int ref_freq
;
973 static unsigned long loops_per_jiffy_ref
;
974 static unsigned long tsc_khz_ref
;
976 static int time_cpufreq_notifier(struct notifier_block
*nb
, unsigned long val
,
979 struct cpufreq_freqs
*freq
= data
;
982 lpj
= &boot_cpu_data
.loops_per_jiffy
;
984 if (!(freq
->flags
& CPUFREQ_CONST_LOOPS
))
985 lpj
= &cpu_data(freq
->cpu
).loops_per_jiffy
;
989 ref_freq
= freq
->old
;
990 loops_per_jiffy_ref
= *lpj
;
991 tsc_khz_ref
= tsc_khz
;
993 if ((val
== CPUFREQ_PRECHANGE
&& freq
->old
< freq
->new) ||
994 (val
== CPUFREQ_POSTCHANGE
&& freq
->old
> freq
->new)) {
995 *lpj
= cpufreq_scale(loops_per_jiffy_ref
, ref_freq
, freq
->new);
997 tsc_khz
= cpufreq_scale(tsc_khz_ref
, ref_freq
, freq
->new);
998 if (!(freq
->flags
& CPUFREQ_CONST_LOOPS
))
999 mark_tsc_unstable("cpufreq changes");
1001 set_cyc2ns_scale(tsc_khz
, freq
->cpu
);
1007 static struct notifier_block time_cpufreq_notifier_block
= {
1008 .notifier_call
= time_cpufreq_notifier
1011 static int __init
cpufreq_register_tsc_scaling(void)
1013 if (!boot_cpu_has(X86_FEATURE_TSC
))
1015 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC
))
1017 cpufreq_register_notifier(&time_cpufreq_notifier_block
,
1018 CPUFREQ_TRANSITION_NOTIFIER
);
1022 core_initcall(cpufreq_register_tsc_scaling
);
1024 #endif /* CONFIG_CPU_FREQ */
1026 #define ART_CPUID_LEAF (0x15)
1027 #define ART_MIN_DENOMINATOR (1)
1031 * If ART is present detect the numerator:denominator to convert to TSC
1033 static void detect_art(void)
1035 unsigned int unused
[2];
1037 if (boot_cpu_data
.cpuid_level
< ART_CPUID_LEAF
)
1040 cpuid(ART_CPUID_LEAF
, &art_to_tsc_denominator
,
1041 &art_to_tsc_numerator
, unused
, unused
+1);
1043 /* Don't enable ART in a VM, non-stop TSC required */
1044 if (boot_cpu_has(X86_FEATURE_HYPERVISOR
) ||
1045 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC
) ||
1046 art_to_tsc_denominator
< ART_MIN_DENOMINATOR
)
1049 if (rdmsrl_safe(MSR_IA32_TSC_ADJUST
, &art_to_tsc_offset
))
1052 /* Make this sticky over multiple CPU init calls */
1053 setup_force_cpu_cap(X86_FEATURE_ART
);
1057 /* clocksource code */
1059 static struct clocksource clocksource_tsc
;
1062 * We used to compare the TSC to the cycle_last value in the clocksource
1063 * structure to avoid a nasty time-warp. This can be observed in a
1064 * very small window right after one CPU updated cycle_last under
1065 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1066 * is smaller than the cycle_last reference value due to a TSC which
1067 * is slighty behind. This delta is nowhere else observable, but in
1068 * that case it results in a forward time jump in the range of hours
1069 * due to the unsigned delta calculation of the time keeping core
1070 * code, which is necessary to support wrapping clocksources like pm
1073 * This sanity check is now done in the core timekeeping code.
1074 * checking the result of read_tsc() - cycle_last for being negative.
1075 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
1077 static cycle_t
read_tsc(struct clocksource
*cs
)
1079 return (cycle_t
)rdtsc_ordered();
1083 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
1085 static struct clocksource clocksource_tsc
= {
1089 .mask
= CLOCKSOURCE_MASK(64),
1090 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
|
1091 CLOCK_SOURCE_MUST_VERIFY
,
1092 .archdata
= { .vclock_mode
= VCLOCK_TSC
},
1095 void mark_tsc_unstable(char *reason
)
1097 if (!tsc_unstable
) {
1099 clear_sched_clock_stable();
1100 disable_sched_clock_irqtime();
1101 pr_info("Marking TSC unstable due to %s\n", reason
);
1102 /* Change only the rating, when not registered */
1103 if (clocksource_tsc
.mult
)
1104 clocksource_mark_unstable(&clocksource_tsc
);
1106 clocksource_tsc
.flags
|= CLOCK_SOURCE_UNSTABLE
;
1107 clocksource_tsc
.rating
= 0;
1112 EXPORT_SYMBOL_GPL(mark_tsc_unstable
);
1114 static void __init
check_system_tsc_reliable(void)
1116 #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1117 if (is_geode_lx()) {
1118 /* RTSC counts during suspend */
1119 #define RTSC_SUSP 0x100
1120 unsigned long res_low
, res_high
;
1122 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0
, &res_low
, &res_high
);
1123 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1124 if (res_low
& RTSC_SUSP
)
1125 tsc_clocksource_reliable
= 1;
1128 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE
))
1129 tsc_clocksource_reliable
= 1;
1133 * Make an educated guess if the TSC is trustworthy and synchronized
1136 int unsynchronized_tsc(void)
1138 if (!boot_cpu_has(X86_FEATURE_TSC
) || tsc_unstable
)
1142 if (apic_is_clustered_box())
1146 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC
))
1149 if (tsc_clocksource_reliable
)
1152 * Intel systems are normally all synchronized.
1153 * Exceptions must mark TSC as unstable:
1155 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
) {
1156 /* assume multi socket systems are not synchronized: */
1157 if (num_possible_cpus() > 1)
1165 * Convert ART to TSC given numerator/denominator found in detect_art()
1167 struct system_counterval_t
convert_art_to_tsc(cycle_t art
)
1171 rem
= do_div(art
, art_to_tsc_denominator
);
1173 res
= art
* art_to_tsc_numerator
;
1174 tmp
= rem
* art_to_tsc_numerator
;
1176 do_div(tmp
, art_to_tsc_denominator
);
1177 res
+= tmp
+ art_to_tsc_offset
;
1179 return (struct system_counterval_t
) {.cs
= art_related_clocksource
,
1182 EXPORT_SYMBOL(convert_art_to_tsc
);
1184 static void tsc_refine_calibration_work(struct work_struct
*work
);
1185 static DECLARE_DELAYED_WORK(tsc_irqwork
, tsc_refine_calibration_work
);
1187 * tsc_refine_calibration_work - Further refine tsc freq calibration
1190 * This functions uses delayed work over a period of a
1191 * second to further refine the TSC freq value. Since this is
1192 * timer based, instead of loop based, we don't block the boot
1193 * process while this longer calibration is done.
1195 * If there are any calibration anomalies (too many SMIs, etc),
1196 * or the refined calibration is off by 1% of the fast early
1197 * calibration, we throw out the new calibration and use the
1198 * early calibration.
1200 static void tsc_refine_calibration_work(struct work_struct
*work
)
1202 static u64 tsc_start
= -1, ref_start
;
1204 u64 tsc_stop
, ref_stop
, delta
;
1207 /* Don't bother refining TSC on unstable systems */
1208 if (check_tsc_unstable())
1212 * Since the work is started early in boot, we may be
1213 * delayed the first time we expire. So set the workqueue
1214 * again once we know timers are working.
1216 if (tsc_start
== -1) {
1218 * Only set hpet once, to avoid mixing hardware
1219 * if the hpet becomes enabled later.
1221 hpet
= is_hpet_enabled();
1222 schedule_delayed_work(&tsc_irqwork
, HZ
);
1223 tsc_start
= tsc_read_refs(&ref_start
, hpet
);
1227 tsc_stop
= tsc_read_refs(&ref_stop
, hpet
);
1229 /* hpet or pmtimer available ? */
1230 if (ref_start
== ref_stop
)
1233 /* Check, whether the sampling was disturbed by an SMI */
1234 if (tsc_start
== ULLONG_MAX
|| tsc_stop
== ULLONG_MAX
)
1237 delta
= tsc_stop
- tsc_start
;
1240 freq
= calc_hpet_ref(delta
, ref_start
, ref_stop
);
1242 freq
= calc_pmtimer_ref(delta
, ref_start
, ref_stop
);
1244 /* Make sure we're within 1% */
1245 if (abs(tsc_khz
- freq
) > tsc_khz
/100)
1249 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1250 (unsigned long)tsc_khz
/ 1000,
1251 (unsigned long)tsc_khz
% 1000);
1253 /* Inform the TSC deadline clockevent devices about the recalibration */
1254 lapic_update_tsc_freq();
1257 if (boot_cpu_has(X86_FEATURE_ART
))
1258 art_related_clocksource
= &clocksource_tsc
;
1259 clocksource_register_khz(&clocksource_tsc
, tsc_khz
);
1263 static int __init
init_tsc_clocksource(void)
1265 if (!boot_cpu_has(X86_FEATURE_TSC
) || tsc_disabled
> 0 || !tsc_khz
)
1268 if (tsc_clocksource_reliable
)
1269 clocksource_tsc
.flags
&= ~CLOCK_SOURCE_MUST_VERIFY
;
1270 /* lower the rating if we already know its unstable: */
1271 if (check_tsc_unstable()) {
1272 clocksource_tsc
.rating
= 0;
1273 clocksource_tsc
.flags
&= ~CLOCK_SOURCE_IS_CONTINUOUS
;
1276 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3
))
1277 clocksource_tsc
.flags
|= CLOCK_SOURCE_SUSPEND_NONSTOP
;
1280 * Trust the results of the earlier calibration on systems
1281 * exporting a reliable TSC.
1283 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE
)) {
1284 clocksource_register_khz(&clocksource_tsc
, tsc_khz
);
1288 schedule_delayed_work(&tsc_irqwork
, 0);
1292 * We use device_initcall here, to ensure we run after the hpet
1293 * is fully initialized, which may occur at fs_initcall time.
1295 device_initcall(init_tsc_clocksource
);
1297 void __init
tsc_init(void)
1302 if (!boot_cpu_has(X86_FEATURE_TSC
)) {
1303 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER
);
1307 cpu_khz
= x86_platform
.calibrate_cpu();
1308 tsc_khz
= x86_platform
.calibrate_tsc();
1311 * Trust non-zero tsc_khz as authorative,
1312 * and use it to sanity check cpu_khz,
1313 * which will be off if system timer is off.
1317 else if (abs(cpu_khz
- tsc_khz
) * 10 > tsc_khz
)
1321 mark_tsc_unstable("could not calculate TSC khz");
1322 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER
);
1326 pr_info("Detected %lu.%03lu MHz processor\n",
1327 (unsigned long)cpu_khz
/ 1000,
1328 (unsigned long)cpu_khz
% 1000);
1331 * Secondary CPUs do not run through tsc_init(), so set up
1332 * all the scale factors for all CPUs, assuming the same
1333 * speed as the bootup CPU. (cpufreq notifiers will fix this
1334 * up if their speed diverges)
1336 for_each_possible_cpu(cpu
) {
1338 set_cyc2ns_scale(tsc_khz
, cpu
);
1341 if (tsc_disabled
> 0)
1344 /* now allow native_sched_clock() to use rdtsc */
1347 static_branch_enable(&__use_tsc
);
1349 if (!no_sched_irq_time
)
1350 enable_sched_clock_irqtime();
1352 lpj
= ((u64
)tsc_khz
* 1000);
1358 if (unsynchronized_tsc())
1359 mark_tsc_unstable("TSCs unsynchronized");
1361 check_system_tsc_reliable();
1368 * If we have a constant TSC and are using the TSC for the delay loop,
1369 * we can skip clock calibration if another cpu in the same socket has already
1370 * been calibrated. This assumes that CONSTANT_TSC applies to all
1371 * cpus in the socket - this should be a safe assumption.
1373 unsigned long calibrate_delay_is_known(void)
1375 int sibling
, cpu
= smp_processor_id();
1376 struct cpumask
*mask
= topology_core_cpumask(cpu
);
1378 if (!tsc_disabled
&& !cpu_has(&cpu_data(cpu
), X86_FEATURE_CONSTANT_TSC
))
1384 sibling
= cpumask_any_but(mask
, cpu
);
1385 if (sibling
< nr_cpu_ids
)
1386 return cpu_data(sibling
).loops_per_jiffy
;