1 #include <linux/kernel.h>
2 #include <linux/sched.h>
3 #include <linux/init.h>
4 #include <linux/module.h>
5 #include <linux/timer.h>
6 #include <linux/acpi_pmtmr.h>
7 #include <linux/cpufreq.h>
9 #include <linux/delay.h>
10 #include <linux/clocksource.h>
11 #include <linux/percpu.h>
14 #include <asm/timer.h>
15 #include <asm/vgtod.h>
17 #include <asm/delay.h>
18 #include <asm/hypervisor.h>
20 unsigned int __read_mostly cpu_khz
; /* TSC clocks / usec, not used here */
21 EXPORT_SYMBOL(cpu_khz
);
23 unsigned int __read_mostly tsc_khz
;
24 EXPORT_SYMBOL(tsc_khz
);
27 * TSC can be unstable due to cpufreq or due to unsynced TSCs
29 static int __read_mostly tsc_unstable
;
31 /* native_sched_clock() is called before tsc_init(), so
32 we must start with the TSC soft disabled to prevent
33 erroneous rdtsc usage on !cpu_has_tsc processors */
34 static int __read_mostly tsc_disabled
= -1;
36 static int tsc_clocksource_reliable
;
38 * Scheduler clock - returns current time in nanosec units.
40 u64
native_sched_clock(void)
45 * Fall back to jiffies if there's no TSC available:
46 * ( But note that we still use it if the TSC is marked
47 * unstable. We do this because unlike Time Of Day,
48 * the scheduler clock tolerates small errors and it's
49 * very important for it to be as fast as the platform
52 if (unlikely(tsc_disabled
)) {
53 /* No locking but a rare wrong value is not a big deal: */
54 return (jiffies_64
- INITIAL_JIFFIES
) * (1000000000 / HZ
);
57 /* read the Time Stamp Counter: */
60 /* return the value in ns */
61 return __cycles_2_ns(this_offset
);
64 /* We need to define a real function for sched_clock, to override the
65 weak default version */
66 #ifdef CONFIG_PARAVIRT
67 unsigned long long sched_clock(void)
69 return paravirt_sched_clock();
73 sched_clock(void) __attribute__((alias("native_sched_clock")));
76 int check_tsc_unstable(void)
80 EXPORT_SYMBOL_GPL(check_tsc_unstable
);
83 int __init
notsc_setup(char *str
)
85 printk(KERN_WARNING
"notsc: Kernel compiled with CONFIG_X86_TSC, "
86 "cannot disable TSC completely.\n");
92 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
95 int __init
notsc_setup(char *str
)
97 setup_clear_cpu_cap(X86_FEATURE_TSC
);
102 __setup("notsc", notsc_setup
);
104 static int __init
tsc_setup(char *str
)
106 if (!strcmp(str
, "reliable"))
107 tsc_clocksource_reliable
= 1;
111 __setup("tsc=", tsc_setup
);
113 #define MAX_RETRIES 5
114 #define SMI_TRESHOLD 50000
117 * Read TSC and the reference counters. Take care of SMI disturbance
119 static u64
tsc_read_refs(u64
*p
, int hpet
)
124 for (i
= 0; i
< MAX_RETRIES
; i
++) {
127 *p
= hpet_readl(HPET_COUNTER
) & 0xFFFFFFFF;
129 *p
= acpi_pm_read_early();
131 if ((t2
- t1
) < SMI_TRESHOLD
)
138 * Calculate the TSC frequency from HPET reference
140 static unsigned long calc_hpet_ref(u64 deltatsc
, u64 hpet1
, u64 hpet2
)
145 hpet2
+= 0x100000000ULL
;
147 tmp
= ((u64
)hpet2
* hpet_readl(HPET_PERIOD
));
148 do_div(tmp
, 1000000);
149 do_div(deltatsc
, tmp
);
151 return (unsigned long) deltatsc
;
155 * Calculate the TSC frequency from PMTimer reference
157 static unsigned long calc_pmtimer_ref(u64 deltatsc
, u64 pm1
, u64 pm2
)
165 pm2
+= (u64
)ACPI_PM_OVRRUN
;
167 tmp
= pm2
* 1000000000LL;
168 do_div(tmp
, PMTMR_TICKS_PER_SEC
);
169 do_div(deltatsc
, tmp
);
171 return (unsigned long) deltatsc
;
175 #define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS))
176 #define CAL_PIT_LOOPS 1000
179 #define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS))
180 #define CAL2_PIT_LOOPS 5000
184 * Try to calibrate the TSC against the Programmable
185 * Interrupt Timer and return the frequency of the TSC
188 * Return ULONG_MAX on failure to calibrate.
190 static unsigned long pit_calibrate_tsc(u32 latch
, unsigned long ms
, int loopmin
)
192 u64 tsc
, t1
, t2
, delta
;
193 unsigned long tscmin
, tscmax
;
196 /* Set the Gate high, disable speaker */
197 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
200 * Setup CTC channel 2* for mode 0, (interrupt on terminal
201 * count mode), binary count. Set the latch register to 50ms
202 * (LSB then MSB) to begin countdown.
205 outb(latch
& 0xff, 0x42);
206 outb(latch
>> 8, 0x42);
208 tsc
= t1
= t2
= get_cycles();
213 while ((inb(0x61) & 0x20) == 0) {
217 if ((unsigned long) delta
< tscmin
)
218 tscmin
= (unsigned int) delta
;
219 if ((unsigned long) delta
> tscmax
)
220 tscmax
= (unsigned int) delta
;
227 * If we were not able to read the PIT more than loopmin
228 * times, then we have been hit by a massive SMI
230 * If the maximum is 10 times larger than the minimum,
231 * then we got hit by an SMI as well.
233 if (pitcnt
< loopmin
|| tscmax
> 10 * tscmin
)
236 /* Calculate the PIT value */
243 * This reads the current MSB of the PIT counter, and
244 * checks if we are running on sufficiently fast and
245 * non-virtualized hardware.
247 * Our expectations are:
249 * - the PIT is running at roughly 1.19MHz
251 * - each IO is going to take about 1us on real hardware,
252 * but we allow it to be much faster (by a factor of 10) or
253 * _slightly_ slower (ie we allow up to a 2us read+counter
254 * update - anything else implies a unacceptably slow CPU
255 * or PIT for the fast calibration to work.
257 * - with 256 PIT ticks to read the value, we have 214us to
258 * see the same MSB (and overhead like doing a single TSC
259 * read per MSB value etc).
261 * - We're doing 2 reads per loop (LSB, MSB), and we expect
262 * them each to take about a microsecond on real hardware.
263 * So we expect a count value of around 100. But we'll be
264 * generous, and accept anything over 50.
266 * - if the PIT is stuck, and we see *many* more reads, we
267 * return early (and the next caller of pit_expect_msb()
268 * then consider it a failure when they don't see the
269 * next expected value).
271 * These expectations mean that we know that we have seen the
272 * transition from one expected value to another with a fairly
273 * high accuracy, and we didn't miss any events. We can thus
274 * use the TSC value at the transitions to calculate a pretty
275 * good value for the TSC frequencty.
277 static inline int pit_expect_msb(unsigned char val
, u64
*tscp
, unsigned long *deltap
)
282 for (count
= 0; count
< 50000; count
++) {
285 if (inb(0x42) != val
)
289 *deltap
= get_cycles() - tsc
;
293 * We require _some_ success, but the quality control
294 * will be based on the error terms on the TSC values.
300 * How many MSB values do we want to see? We aim for
301 * a maximum error rate of 500ppm (in practice the
302 * real error is much smaller), but refuse to spend
303 * more than 25ms on it.
305 #define MAX_QUICK_PIT_MS 25
306 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
308 static unsigned long quick_pit_calibrate(void)
312 unsigned long d1
, d2
;
314 /* Set the Gate high, disable speaker */
315 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
318 * Counter 2, mode 0 (one-shot), binary count
320 * NOTE! Mode 2 decrements by two (and then the
321 * output is flipped each time, giving the same
322 * final output frequency as a decrement-by-one),
323 * so mode 0 is much better when looking at the
328 /* Start at 0xffff */
333 * The PIT starts counting at the next edge, so we
334 * need to delay for a microsecond. The easiest way
335 * to do that is to just read back the 16-bit counter
341 if (pit_expect_msb(0xff, &tsc
, &d1
)) {
342 for (i
= 1; i
<= MAX_QUICK_PIT_ITERATIONS
; i
++) {
343 if (!pit_expect_msb(0xff-i
, &delta
, &d2
))
347 * Iterate until the error is less than 500 ppm
350 if (d1
+d2
< delta
>> 11)
354 printk("Fast TSC calibration failed\n");
359 * Ok, if we get here, then we've seen the
360 * MSB of the PIT decrement 'i' times, and the
361 * error has shrunk to less than 500 ppm.
363 * As a result, we can depend on there not being
364 * any odd delays anywhere, and the TSC reads are
365 * reliable (within the error). We also adjust the
366 * delta to the middle of the error bars, just
367 * because it looks nicer.
369 * kHz = ticks / time-in-seconds / 1000;
370 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
371 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
373 delta
+= (long)(d2
- d1
)/2;
374 delta
*= PIT_TICK_RATE
;
375 do_div(delta
, i
*256*1000);
376 printk("Fast TSC calibration using PIT\n");
381 * native_calibrate_tsc - calibrate the tsc on boot
383 unsigned long native_calibrate_tsc(void)
385 u64 tsc1
, tsc2
, delta
, ref1
, ref2
;
386 unsigned long tsc_pit_min
= ULONG_MAX
, tsc_ref_min
= ULONG_MAX
;
387 unsigned long flags
, latch
, ms
, fast_calibrate
, tsc_khz
;
388 int hpet
= is_hpet_enabled(), i
, loopmin
;
390 tsc_khz
= get_hypervisor_tsc_freq();
392 printk(KERN_INFO
"TSC: Frequency read from the hypervisor\n");
396 local_irq_save(flags
);
397 fast_calibrate
= quick_pit_calibrate();
398 local_irq_restore(flags
);
400 return fast_calibrate
;
403 * Run 5 calibration loops to get the lowest frequency value
404 * (the best estimate). We use two different calibration modes
407 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
408 * load a timeout of 50ms. We read the time right after we
409 * started the timer and wait until the PIT count down reaches
410 * zero. In each wait loop iteration we read the TSC and check
411 * the delta to the previous read. We keep track of the min
412 * and max values of that delta. The delta is mostly defined
413 * by the IO time of the PIT access, so we can detect when a
414 * SMI/SMM disturbance happend between the two reads. If the
415 * maximum time is significantly larger than the minimum time,
416 * then we discard the result and have another try.
418 * 2) Reference counter. If available we use the HPET or the
419 * PMTIMER as a reference to check the sanity of that value.
420 * We use separate TSC readouts and check inside of the
421 * reference read for a SMI/SMM disturbance. We dicard
422 * disturbed values here as well. We do that around the PIT
423 * calibration delay loop as we have to wait for a certain
424 * amount of time anyway.
427 /* Preset PIT loop values */
430 loopmin
= CAL_PIT_LOOPS
;
432 for (i
= 0; i
< 3; i
++) {
433 unsigned long tsc_pit_khz
;
436 * Read the start value and the reference count of
437 * hpet/pmtimer when available. Then do the PIT
438 * calibration, which will take at least 50ms, and
439 * read the end value.
441 local_irq_save(flags
);
442 tsc1
= tsc_read_refs(&ref1
, hpet
);
443 tsc_pit_khz
= pit_calibrate_tsc(latch
, ms
, loopmin
);
444 tsc2
= tsc_read_refs(&ref2
, hpet
);
445 local_irq_restore(flags
);
447 /* Pick the lowest PIT TSC calibration so far */
448 tsc_pit_min
= min(tsc_pit_min
, tsc_pit_khz
);
450 /* hpet or pmtimer available ? */
451 if (!hpet
&& !ref1
&& !ref2
)
454 /* Check, whether the sampling was disturbed by an SMI */
455 if (tsc1
== ULLONG_MAX
|| tsc2
== ULLONG_MAX
)
458 tsc2
= (tsc2
- tsc1
) * 1000000LL;
460 tsc2
= calc_hpet_ref(tsc2
, ref1
, ref2
);
462 tsc2
= calc_pmtimer_ref(tsc2
, ref1
, ref2
);
464 tsc_ref_min
= min(tsc_ref_min
, (unsigned long) tsc2
);
466 /* Check the reference deviation */
467 delta
= ((u64
) tsc_pit_min
) * 100;
468 do_div(delta
, tsc_ref_min
);
471 * If both calibration results are inside a 10% window
472 * then we can be sure, that the calibration
473 * succeeded. We break out of the loop right away. We
474 * use the reference value, as it is more precise.
476 if (delta
>= 90 && delta
<= 110) {
478 "TSC: PIT calibration matches %s. %d loops\n",
479 hpet
? "HPET" : "PMTIMER", i
+ 1);
484 * Check whether PIT failed more than once. This
485 * happens in virtualized environments. We need to
486 * give the virtual PC a slightly longer timeframe for
487 * the HPET/PMTIMER to make the result precise.
489 if (i
== 1 && tsc_pit_min
== ULONG_MAX
) {
492 loopmin
= CAL2_PIT_LOOPS
;
497 * Now check the results.
499 if (tsc_pit_min
== ULONG_MAX
) {
500 /* PIT gave no useful value */
501 printk(KERN_WARNING
"TSC: Unable to calibrate against PIT\n");
503 /* We don't have an alternative source, disable TSC */
504 if (!hpet
&& !ref1
&& !ref2
) {
505 printk("TSC: No reference (HPET/PMTIMER) available\n");
509 /* The alternative source failed as well, disable TSC */
510 if (tsc_ref_min
== ULONG_MAX
) {
511 printk(KERN_WARNING
"TSC: HPET/PMTIMER calibration "
516 /* Use the alternative source */
517 printk(KERN_INFO
"TSC: using %s reference calibration\n",
518 hpet
? "HPET" : "PMTIMER");
523 /* We don't have an alternative source, use the PIT calibration value */
524 if (!hpet
&& !ref1
&& !ref2
) {
525 printk(KERN_INFO
"TSC: Using PIT calibration value\n");
529 /* The alternative source failed, use the PIT calibration value */
530 if (tsc_ref_min
== ULONG_MAX
) {
531 printk(KERN_WARNING
"TSC: HPET/PMTIMER calibration failed. "
532 "Using PIT calibration\n");
537 * The calibration values differ too much. In doubt, we use
538 * the PIT value as we know that there are PMTIMERs around
539 * running at double speed. At least we let the user know:
541 printk(KERN_WARNING
"TSC: PIT calibration deviates from %s: %lu %lu.\n",
542 hpet
? "HPET" : "PMTIMER", tsc_pit_min
, tsc_ref_min
);
543 printk(KERN_INFO
"TSC: Using PIT calibration value\n");
547 int recalibrate_cpu_khz(void)
550 unsigned long cpu_khz_old
= cpu_khz
;
553 tsc_khz
= calibrate_tsc();
555 cpu_data(0).loops_per_jiffy
=
556 cpufreq_scale(cpu_data(0).loops_per_jiffy
,
557 cpu_khz_old
, cpu_khz
);
566 EXPORT_SYMBOL(recalibrate_cpu_khz
);
569 /* Accelerators for sched_clock()
570 * convert from cycles(64bits) => nanoseconds (64bits)
572 * ns = cycles / (freq / ns_per_sec)
573 * ns = cycles * (ns_per_sec / freq)
574 * ns = cycles * (10^9 / (cpu_khz * 10^3))
575 * ns = cycles * (10^6 / cpu_khz)
577 * Then we use scaling math (suggested by george@mvista.com) to get:
578 * ns = cycles * (10^6 * SC / cpu_khz) / SC
579 * ns = cycles * cyc2ns_scale / SC
581 * And since SC is a constant power of two, we can convert the div
584 * We can use khz divisor instead of mhz to keep a better precision, since
585 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
586 * (mathieu.desnoyers@polymtl.ca)
588 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
591 DEFINE_PER_CPU(unsigned long, cyc2ns
);
593 static void set_cyc2ns_scale(unsigned long cpu_khz
, int cpu
)
595 unsigned long long tsc_now
, ns_now
;
596 unsigned long flags
, *scale
;
598 local_irq_save(flags
);
599 sched_clock_idle_sleep_event();
601 scale
= &per_cpu(cyc2ns
, cpu
);
604 ns_now
= __cycles_2_ns(tsc_now
);
607 *scale
= (NSEC_PER_MSEC
<< CYC2NS_SCALE_FACTOR
)/cpu_khz
;
609 sched_clock_idle_wakeup_event(0);
610 local_irq_restore(flags
);
613 #ifdef CONFIG_CPU_FREQ
615 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
618 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
619 * not that important because current Opteron setups do not support
620 * scaling on SMP anyroads.
622 * Should fix up last_tsc too. Currently gettimeofday in the
623 * first tick after the change will be slightly wrong.
626 static unsigned int ref_freq
;
627 static unsigned long loops_per_jiffy_ref
;
628 static unsigned long tsc_khz_ref
;
630 static int time_cpufreq_notifier(struct notifier_block
*nb
, unsigned long val
,
633 struct cpufreq_freqs
*freq
= data
;
634 unsigned long *lpj
, dummy
;
636 if (cpu_has(&cpu_data(freq
->cpu
), X86_FEATURE_CONSTANT_TSC
))
640 if (!(freq
->flags
& CPUFREQ_CONST_LOOPS
))
642 lpj
= &cpu_data(freq
->cpu
).loops_per_jiffy
;
644 lpj
= &boot_cpu_data
.loops_per_jiffy
;
648 ref_freq
= freq
->old
;
649 loops_per_jiffy_ref
= *lpj
;
650 tsc_khz_ref
= tsc_khz
;
652 if ((val
== CPUFREQ_PRECHANGE
&& freq
->old
< freq
->new) ||
653 (val
== CPUFREQ_POSTCHANGE
&& freq
->old
> freq
->new) ||
654 (val
== CPUFREQ_RESUMECHANGE
)) {
655 *lpj
= cpufreq_scale(loops_per_jiffy_ref
, ref_freq
, freq
->new);
657 tsc_khz
= cpufreq_scale(tsc_khz_ref
, ref_freq
, freq
->new);
658 if (!(freq
->flags
& CPUFREQ_CONST_LOOPS
))
659 mark_tsc_unstable("cpufreq changes");
662 set_cyc2ns_scale(tsc_khz
, freq
->cpu
);
667 static struct notifier_block time_cpufreq_notifier_block
= {
668 .notifier_call
= time_cpufreq_notifier
671 static int __init
cpufreq_tsc(void)
675 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC
))
677 cpufreq_register_notifier(&time_cpufreq_notifier_block
,
678 CPUFREQ_TRANSITION_NOTIFIER
);
682 core_initcall(cpufreq_tsc
);
684 #endif /* CONFIG_CPU_FREQ */
686 /* clocksource code */
688 static struct clocksource clocksource_tsc
;
691 * We compare the TSC to the cycle_last value in the clocksource
692 * structure to avoid a nasty time-warp. This can be observed in a
693 * very small window right after one CPU updated cycle_last under
694 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
695 * is smaller than the cycle_last reference value due to a TSC which
696 * is slighty behind. This delta is nowhere else observable, but in
697 * that case it results in a forward time jump in the range of hours
698 * due to the unsigned delta calculation of the time keeping core
699 * code, which is necessary to support wrapping clocksources like pm
702 static cycle_t
read_tsc(struct clocksource
*cs
)
704 cycle_t ret
= (cycle_t
)get_cycles();
706 return ret
>= clocksource_tsc
.cycle_last
?
707 ret
: clocksource_tsc
.cycle_last
;
711 static cycle_t __vsyscall_fn
vread_tsc(void)
716 * Surround the RDTSC by barriers, to make sure it's not
717 * speculated to outside the seqlock critical section and
718 * does not cause time warps:
721 ret
= (cycle_t
)vget_cycles();
724 return ret
>= __vsyscall_gtod_data
.clock
.cycle_last
?
725 ret
: __vsyscall_gtod_data
.clock
.cycle_last
;
729 static struct clocksource clocksource_tsc
= {
733 .mask
= CLOCKSOURCE_MASK(64),
735 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
|
736 CLOCK_SOURCE_MUST_VERIFY
,
742 void mark_tsc_unstable(char *reason
)
746 printk("Marking TSC unstable due to %s\n", reason
);
747 /* Change only the rating, when not registered */
748 if (clocksource_tsc
.mult
)
749 clocksource_change_rating(&clocksource_tsc
, 0);
751 clocksource_tsc
.rating
= 0;
755 EXPORT_SYMBOL_GPL(mark_tsc_unstable
);
757 static int __init
dmi_mark_tsc_unstable(const struct dmi_system_id
*d
)
759 printk(KERN_NOTICE
"%s detected: marking TSC unstable.\n",
765 /* List of systems that have known TSC problems */
766 static struct dmi_system_id __initdata bad_tsc_dmi_table
[] = {
768 .callback
= dmi_mark_tsc_unstable
,
769 .ident
= "IBM Thinkpad 380XD",
771 DMI_MATCH(DMI_BOARD_VENDOR
, "IBM"),
772 DMI_MATCH(DMI_BOARD_NAME
, "2635FA0"),
778 static void __init
check_system_tsc_reliable(void)
780 #ifdef CONFIG_MGEODE_LX
781 /* RTSC counts during suspend */
782 #define RTSC_SUSP 0x100
783 unsigned long res_low
, res_high
;
785 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0
, &res_low
, &res_high
);
786 /* Geode_LX - the OLPC CPU has a possibly a very reliable TSC */
787 if (res_low
& RTSC_SUSP
)
788 tsc_clocksource_reliable
= 1;
790 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE
))
791 tsc_clocksource_reliable
= 1;
795 * Make an educated guess if the TSC is trustworthy and synchronized
798 __cpuinit
int unsynchronized_tsc(void)
800 if (!cpu_has_tsc
|| tsc_unstable
)
804 if (apic_is_clustered_box())
808 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC
))
811 * Intel systems are normally all synchronized.
812 * Exceptions must mark TSC as unstable:
814 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
) {
815 /* assume multi socket systems are not synchronized: */
816 if (num_possible_cpus() > 1)
823 static void __init
init_tsc_clocksource(void)
825 clocksource_tsc
.mult
= clocksource_khz2mult(tsc_khz
,
826 clocksource_tsc
.shift
);
827 if (tsc_clocksource_reliable
)
828 clocksource_tsc
.flags
&= ~CLOCK_SOURCE_MUST_VERIFY
;
829 /* lower the rating if we already know its unstable: */
830 if (check_tsc_unstable()) {
831 clocksource_tsc
.rating
= 0;
832 clocksource_tsc
.flags
&= ~CLOCK_SOURCE_IS_CONTINUOUS
;
834 clocksource_register(&clocksource_tsc
);
837 void __init
tsc_init(void)
845 tsc_khz
= calibrate_tsc();
849 mark_tsc_unstable("could not calculate TSC khz");
854 if (cpu_has(&boot_cpu_data
, X86_FEATURE_CONSTANT_TSC
) &&
855 (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
))
856 cpu_khz
= calibrate_cpu();
859 printk("Detected %lu.%03lu MHz processor.\n",
860 (unsigned long)cpu_khz
/ 1000,
861 (unsigned long)cpu_khz
% 1000);
864 * Secondary CPUs do not run through tsc_init(), so set up
865 * all the scale factors for all CPUs, assuming the same
866 * speed as the bootup CPU. (cpufreq notifiers will fix this
867 * up if their speed diverges)
869 for_each_possible_cpu(cpu
)
870 set_cyc2ns_scale(cpu_khz
, cpu
);
872 if (tsc_disabled
> 0)
875 /* now allow native_sched_clock() to use rdtsc */
878 lpj
= ((u64
)tsc_khz
* 1000);
883 /* Check and install the TSC clocksource */
884 dmi_check_system(bad_tsc_dmi_table
);
886 if (unsynchronized_tsc())
887 mark_tsc_unstable("TSCs unsynchronized");
889 check_system_tsc_reliable();
890 init_tsc_clocksource();