x86, 32-bit: trim memory not covered by wb mtrrs
[deliverable/linux.git] / arch / x86 / kernel / tsc_32.c
1 #include <linux/sched.h>
2 #include <linux/clocksource.h>
3 #include <linux/workqueue.h>
4 #include <linux/cpufreq.h>
5 #include <linux/jiffies.h>
6 #include <linux/init.h>
7 #include <linux/dmi.h>
8 #include <linux/percpu.h>
9
10 #include <asm/delay.h>
11 #include <asm/tsc.h>
12 #include <asm/io.h>
13 #include <asm/timer.h>
14
15 #include "mach_timer.h"
16
17 static int tsc_enabled;
18
19 /*
20 * On some systems the TSC frequency does not
21 * change with the cpu frequency. So we need
22 * an extra value to store the TSC freq
23 */
24 unsigned int tsc_khz;
25 EXPORT_SYMBOL_GPL(tsc_khz);
26
27 int tsc_disable;
28
29 #ifdef CONFIG_X86_TSC
30 static int __init tsc_setup(char *str)
31 {
32 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
33 "cannot disable TSC.\n");
34 return 1;
35 }
36 #else
37 /*
38 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
39 * in cpu/common.c
40 */
41 static int __init tsc_setup(char *str)
42 {
43 tsc_disable = 1;
44
45 return 1;
46 }
47 #endif
48
49 __setup("notsc", tsc_setup);
50
51 /*
52 * code to mark and check if the TSC is unstable
53 * due to cpufreq or due to unsynced TSCs
54 */
55 static int tsc_unstable;
56
57 int check_tsc_unstable(void)
58 {
59 return tsc_unstable;
60 }
61 EXPORT_SYMBOL_GPL(check_tsc_unstable);
62
63 /* Accelerators for sched_clock()
64 * convert from cycles(64bits) => nanoseconds (64bits)
65 * basic equation:
66 * ns = cycles / (freq / ns_per_sec)
67 * ns = cycles * (ns_per_sec / freq)
68 * ns = cycles * (10^9 / (cpu_khz * 10^3))
69 * ns = cycles * (10^6 / cpu_khz)
70 *
71 * Then we use scaling math (suggested by george@mvista.com) to get:
72 * ns = cycles * (10^6 * SC / cpu_khz) / SC
73 * ns = cycles * cyc2ns_scale / SC
74 *
75 * And since SC is a constant power of two, we can convert the div
76 * into a shift.
77 *
78 * We can use khz divisor instead of mhz to keep a better precision, since
79 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
80 * (mathieu.desnoyers@polymtl.ca)
81 *
82 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
83 */
84
85 DEFINE_PER_CPU(unsigned long, cyc2ns);
86
87 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
88 {
89 unsigned long flags, prev_scale, *scale;
90 unsigned long long tsc_now, ns_now;
91
92 local_irq_save(flags);
93 sched_clock_idle_sleep_event();
94
95 scale = &per_cpu(cyc2ns, cpu);
96
97 rdtscll(tsc_now);
98 ns_now = __cycles_2_ns(tsc_now);
99
100 prev_scale = *scale;
101 if (cpu_khz)
102 *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
103
104 /*
105 * Start smoothly with the new frequency:
106 */
107 sched_clock_idle_wakeup_event(0);
108 local_irq_restore(flags);
109 }
110
111 /*
112 * Scheduler clock - returns current time in nanosec units.
113 */
114 unsigned long long native_sched_clock(void)
115 {
116 unsigned long long this_offset;
117
118 /*
119 * Fall back to jiffies if there's no TSC available:
120 * ( But note that we still use it if the TSC is marked
121 * unstable. We do this because unlike Time Of Day,
122 * the scheduler clock tolerates small errors and it's
123 * very important for it to be as fast as the platform
124 * can achive it. )
125 */
126 if (unlikely(!tsc_enabled && !tsc_unstable))
127 /* No locking but a rare wrong value is not a big deal: */
128 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
129
130 /* read the Time Stamp Counter: */
131 rdtscll(this_offset);
132
133 /* return the value in ns */
134 return cycles_2_ns(this_offset);
135 }
136
137 /* We need to define a real function for sched_clock, to override the
138 weak default version */
139 #ifdef CONFIG_PARAVIRT
140 unsigned long long sched_clock(void)
141 {
142 return paravirt_sched_clock();
143 }
144 #else
145 unsigned long long sched_clock(void)
146 __attribute__((alias("native_sched_clock")));
147 #endif
148
149 unsigned long native_calculate_cpu_khz(void)
150 {
151 unsigned long long start, end;
152 unsigned long count;
153 u64 delta64 = (u64)ULLONG_MAX;
154 int i;
155 unsigned long flags;
156
157 local_irq_save(flags);
158
159 /* run 3 times to ensure the cache is warm and to get an accurate reading */
160 for (i = 0; i < 3; i++) {
161 mach_prepare_counter();
162 rdtscll(start);
163 mach_countup(&count);
164 rdtscll(end);
165
166 /*
167 * Error: ECTCNEVERSET
168 * The CTC wasn't reliable: we got a hit on the very first read,
169 * or the CPU was so fast/slow that the quotient wouldn't fit in
170 * 32 bits..
171 */
172 if (count <= 1)
173 continue;
174
175 /* cpu freq too slow: */
176 if ((end - start) <= CALIBRATE_TIME_MSEC)
177 continue;
178
179 /*
180 * We want the minimum time of all runs in case one of them
181 * is inaccurate due to SMI or other delay
182 */
183 delta64 = min(delta64, (end - start));
184 }
185
186 /* cpu freq too fast (or every run was bad): */
187 if (delta64 > (1ULL<<32))
188 goto err;
189
190 delta64 += CALIBRATE_TIME_MSEC/2; /* round for do_div */
191 do_div(delta64,CALIBRATE_TIME_MSEC);
192
193 local_irq_restore(flags);
194 return (unsigned long)delta64;
195 err:
196 local_irq_restore(flags);
197 return 0;
198 }
199
200 int recalibrate_cpu_khz(void)
201 {
202 #ifndef CONFIG_SMP
203 unsigned long cpu_khz_old = cpu_khz;
204
205 if (cpu_has_tsc) {
206 cpu_khz = calculate_cpu_khz();
207 tsc_khz = cpu_khz;
208 cpu_data(0).loops_per_jiffy =
209 cpufreq_scale(cpu_data(0).loops_per_jiffy,
210 cpu_khz_old, cpu_khz);
211 return 0;
212 } else
213 return -ENODEV;
214 #else
215 return -ENODEV;
216 #endif
217 }
218
219 EXPORT_SYMBOL(recalibrate_cpu_khz);
220
221 #ifdef CONFIG_CPU_FREQ
222
223 /*
224 * if the CPU frequency is scaled, TSC-based delays will need a different
225 * loops_per_jiffy value to function properly.
226 */
227 static unsigned int ref_freq = 0;
228 static unsigned long loops_per_jiffy_ref = 0;
229 static unsigned long cpu_khz_ref = 0;
230
231 static int
232 time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
233 {
234 struct cpufreq_freqs *freq = data;
235
236 if (!ref_freq) {
237 if (!freq->old){
238 ref_freq = freq->new;
239 return 0;
240 }
241 ref_freq = freq->old;
242 loops_per_jiffy_ref = cpu_data(freq->cpu).loops_per_jiffy;
243 cpu_khz_ref = cpu_khz;
244 }
245
246 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
247 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
248 (val == CPUFREQ_RESUMECHANGE)) {
249 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
250 cpu_data(freq->cpu).loops_per_jiffy =
251 cpufreq_scale(loops_per_jiffy_ref,
252 ref_freq, freq->new);
253
254 if (cpu_khz) {
255
256 if (num_online_cpus() == 1)
257 cpu_khz = cpufreq_scale(cpu_khz_ref,
258 ref_freq, freq->new);
259 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) {
260 tsc_khz = cpu_khz;
261 preempt_disable();
262 set_cyc2ns_scale(cpu_khz, smp_processor_id());
263 preempt_enable();
264 /*
265 * TSC based sched_clock turns
266 * to junk w/ cpufreq
267 */
268 mark_tsc_unstable("cpufreq changes");
269 }
270 }
271 }
272
273 return 0;
274 }
275
276 static struct notifier_block time_cpufreq_notifier_block = {
277 .notifier_call = time_cpufreq_notifier
278 };
279
280 static int __init cpufreq_tsc(void)
281 {
282 return cpufreq_register_notifier(&time_cpufreq_notifier_block,
283 CPUFREQ_TRANSITION_NOTIFIER);
284 }
285 core_initcall(cpufreq_tsc);
286
287 #endif
288
289 /* clock source code */
290
291 static unsigned long current_tsc_khz = 0;
292
293 static cycle_t read_tsc(void)
294 {
295 cycle_t ret;
296
297 rdtscll(ret);
298
299 return ret;
300 }
301
302 static struct clocksource clocksource_tsc = {
303 .name = "tsc",
304 .rating = 300,
305 .read = read_tsc,
306 .mask = CLOCKSOURCE_MASK(64),
307 .mult = 0, /* to be set */
308 .shift = 22,
309 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
310 CLOCK_SOURCE_MUST_VERIFY,
311 };
312
313 void mark_tsc_unstable(char *reason)
314 {
315 if (!tsc_unstable) {
316 tsc_unstable = 1;
317 tsc_enabled = 0;
318 printk("Marking TSC unstable due to: %s.\n", reason);
319 /* Can be called before registration */
320 if (clocksource_tsc.mult)
321 clocksource_change_rating(&clocksource_tsc, 0);
322 else
323 clocksource_tsc.rating = 0;
324 }
325 }
326 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
327
328 static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
329 {
330 printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
331 d->ident);
332 tsc_unstable = 1;
333 return 0;
334 }
335
336 /* List of systems that have known TSC problems */
337 static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
338 {
339 .callback = dmi_mark_tsc_unstable,
340 .ident = "IBM Thinkpad 380XD",
341 .matches = {
342 DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
343 DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
344 },
345 },
346 {}
347 };
348
349 /*
350 * Make an educated guess if the TSC is trustworthy and synchronized
351 * over all CPUs.
352 */
353 __cpuinit int unsynchronized_tsc(void)
354 {
355 if (!cpu_has_tsc || tsc_unstable)
356 return 1;
357
358 /* Anything with constant TSC should be synchronized */
359 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
360 return 0;
361
362 /*
363 * Intel systems are normally all synchronized.
364 * Exceptions must mark TSC as unstable:
365 */
366 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
367 /* assume multi socket systems are not synchronized: */
368 if (num_possible_cpus() > 1)
369 tsc_unstable = 1;
370 }
371 return tsc_unstable;
372 }
373
374 /*
375 * Geode_LX - the OLPC CPU has a possibly a very reliable TSC
376 */
377 #ifdef CONFIG_MGEODE_LX
378 /* RTSC counts during suspend */
379 #define RTSC_SUSP 0x100
380
381 static void __init check_geode_tsc_reliable(void)
382 {
383 unsigned long res_low, res_high;
384
385 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
386 if (res_low & RTSC_SUSP)
387 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
388 }
389 #else
390 static inline void check_geode_tsc_reliable(void) { }
391 #endif
392
393
394 void __init tsc_init(void)
395 {
396 int cpu;
397
398 if (!cpu_has_tsc || tsc_disable)
399 goto out_no_tsc;
400
401 cpu_khz = calculate_cpu_khz();
402 tsc_khz = cpu_khz;
403
404 if (!cpu_khz)
405 goto out_no_tsc;
406
407 printk("Detected %lu.%03lu MHz processor.\n",
408 (unsigned long)cpu_khz / 1000,
409 (unsigned long)cpu_khz % 1000);
410
411 /*
412 * Secondary CPUs do not run through tsc_init(), so set up
413 * all the scale factors for all CPUs, assuming the same
414 * speed as the bootup CPU. (cpufreq notifiers will fix this
415 * up if their speed diverges)
416 */
417 for_each_possible_cpu(cpu)
418 set_cyc2ns_scale(cpu_khz, cpu);
419
420 use_tsc_delay();
421
422 /* Check and install the TSC clocksource */
423 dmi_check_system(bad_tsc_dmi_table);
424
425 unsynchronized_tsc();
426 check_geode_tsc_reliable();
427 current_tsc_khz = tsc_khz;
428 clocksource_tsc.mult = clocksource_khz2mult(current_tsc_khz,
429 clocksource_tsc.shift);
430 /* lower the rating if we already know its unstable: */
431 if (check_tsc_unstable()) {
432 clocksource_tsc.rating = 0;
433 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
434 } else
435 tsc_enabled = 1;
436
437 clocksource_register(&clocksource_tsc);
438
439 return;
440
441 out_no_tsc:
442 /*
443 * Set the tsc_disable flag if there's no TSC support, this
444 * makes it a fast flag for the kernel to see whether it
445 * should be using the TSC.
446 */
447 tsc_disable = 1;
448 }
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