2 * SGI RTC clock/timer routines.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 * Copyright (c) 2009 Silicon Graphics, Inc. All Rights Reserved.
19 * Copyright (c) Dimitri Sivanich
21 #include <linux/clockchips.h>
23 #include <asm/uv/uv_mmrs.h>
24 #include <asm/uv/uv_hub.h>
25 #include <asm/uv/bios.h>
26 #include <asm/uv/uv.h>
30 #define RTC_NAME "sgi_rtc"
32 static cycle_t
uv_read_rtc(struct clocksource
*cs
);
33 static int uv_rtc_next_event(unsigned long, struct clock_event_device
*);
34 static void uv_rtc_timer_setup(enum clock_event_mode
,
35 struct clock_event_device
*);
37 static struct clocksource clocksource_uv
= {
41 .mask
= (cycle_t
)UVH_RTC_REAL_TIME_CLOCK_MASK
,
43 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
46 static struct clock_event_device clock_event_device_uv
= {
48 .features
= CLOCK_EVT_FEAT_ONESHOT
,
52 .set_next_event
= uv_rtc_next_event
,
53 .set_mode
= uv_rtc_timer_setup
,
54 .event_handler
= NULL
,
57 static DEFINE_PER_CPU(struct clock_event_device
, cpu_ced
);
59 /* There is one of these allocated per node */
60 struct uv_rtc_timer_head
{
62 /* next cpu waiting for timer, local node relative: */
64 /* number of cpus on this node: */
67 int lcpu
; /* systemwide logical cpu number */
68 u64 expires
; /* next timer expiration for this cpu */
73 * Access to uv_rtc_timer_head via blade id.
75 static struct uv_rtc_timer_head
**blade_info __read_mostly
;
77 static int uv_rtc_evt_enable
;
80 * Hardware interface routines
83 /* Send IPIs to another node */
84 static void uv_rtc_send_IPI(int cpu
)
86 unsigned long apicid
, val
;
89 apicid
= cpu_physical_id(cpu
);
90 pnode
= uv_apicid_to_pnode(apicid
);
91 val
= (1UL << UVH_IPI_INT_SEND_SHFT
) |
92 (apicid
<< UVH_IPI_INT_APIC_ID_SHFT
) |
93 (X86_PLATFORM_IPI_VECTOR
<< UVH_IPI_INT_VECTOR_SHFT
);
95 uv_write_global_mmr64(pnode
, UVH_IPI_INT
, val
);
98 /* Check for an RTC interrupt pending */
99 static int uv_intr_pending(int pnode
)
101 return uv_read_global_mmr64(pnode
, UVH_EVENT_OCCURRED0
) &
102 UVH_EVENT_OCCURRED0_RTC1_MASK
;
105 /* Setup interrupt and return non-zero if early expiration occurred. */
106 static int uv_setup_intr(int cpu
, u64 expires
)
109 int pnode
= uv_cpu_to_pnode(cpu
);
111 uv_write_global_mmr64(pnode
, UVH_RTC1_INT_CONFIG
,
112 UVH_RTC1_INT_CONFIG_M_MASK
);
113 uv_write_global_mmr64(pnode
, UVH_INT_CMPB
, -1L);
115 uv_write_global_mmr64(pnode
, UVH_EVENT_OCCURRED0_ALIAS
,
116 UVH_EVENT_OCCURRED0_RTC1_MASK
);
118 val
= (X86_PLATFORM_IPI_VECTOR
<< UVH_RTC1_INT_CONFIG_VECTOR_SHFT
) |
119 ((u64
)cpu_physical_id(cpu
) << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT
);
121 /* Set configuration */
122 uv_write_global_mmr64(pnode
, UVH_RTC1_INT_CONFIG
, val
);
123 /* Initialize comparator value */
124 uv_write_global_mmr64(pnode
, UVH_INT_CMPB
, expires
);
126 if (uv_read_rtc(NULL
) <= expires
)
129 return !uv_intr_pending(pnode
);
133 * Per-cpu timer tracking routines
136 static __init
void uv_rtc_deallocate_timers(void)
140 for_each_possible_blade(bid
) {
141 kfree(blade_info
[bid
]);
146 /* Allocate per-node list of cpu timer expiration times. */
147 static __init
int uv_rtc_allocate_timers(void)
151 blade_info
= kmalloc(uv_possible_blades
* sizeof(void *), GFP_KERNEL
);
154 memset(blade_info
, 0, uv_possible_blades
* sizeof(void *));
156 for_each_present_cpu(cpu
) {
157 int nid
= cpu_to_node(cpu
);
158 int bid
= uv_cpu_to_blade_id(cpu
);
159 int bcpu
= uv_cpu_hub_info(cpu
)->blade_processor_id
;
160 struct uv_rtc_timer_head
*head
= blade_info
[bid
];
163 head
= kmalloc_node(sizeof(struct uv_rtc_timer_head
) +
164 (uv_blade_nr_possible_cpus(bid
) *
168 uv_rtc_deallocate_timers();
171 spin_lock_init(&head
->lock
);
172 head
->ncpus
= uv_blade_nr_possible_cpus(bid
);
174 blade_info
[bid
] = head
;
177 head
->cpu
[bcpu
].lcpu
= cpu
;
178 head
->cpu
[bcpu
].expires
= ULLONG_MAX
;
184 /* Find and set the next expiring timer. */
185 static void uv_rtc_find_next_timer(struct uv_rtc_timer_head
*head
, int pnode
)
187 u64 lowest
= ULLONG_MAX
;
191 for (c
= 0; c
< head
->ncpus
; c
++) {
192 u64 exp
= head
->cpu
[c
].expires
;
199 head
->next_cpu
= bcpu
;
200 c
= head
->cpu
[bcpu
].lcpu
;
201 if (uv_setup_intr(c
, lowest
))
202 /* If we didn't set it up in time, trigger */
205 uv_write_global_mmr64(pnode
, UVH_RTC1_INT_CONFIG
,
206 UVH_RTC1_INT_CONFIG_M_MASK
);
211 * Set expiration time for current cpu.
213 * Returns 1 if we missed the expiration time.
215 static int uv_rtc_set_timer(int cpu
, u64 expires
)
217 int pnode
= uv_cpu_to_pnode(cpu
);
218 int bid
= uv_cpu_to_blade_id(cpu
);
219 struct uv_rtc_timer_head
*head
= blade_info
[bid
];
220 int bcpu
= uv_cpu_hub_info(cpu
)->blade_processor_id
;
221 u64
*t
= &head
->cpu
[bcpu
].expires
;
225 spin_lock_irqsave(&head
->lock
, flags
);
227 next_cpu
= head
->next_cpu
;
230 /* Will this one be next to go off? */
231 if (next_cpu
< 0 || bcpu
== next_cpu
||
232 expires
< head
->cpu
[next_cpu
].expires
) {
233 head
->next_cpu
= bcpu
;
234 if (uv_setup_intr(cpu
, expires
)) {
236 uv_rtc_find_next_timer(head
, pnode
);
237 spin_unlock_irqrestore(&head
->lock
, flags
);
242 spin_unlock_irqrestore(&head
->lock
, flags
);
247 * Unset expiration time for current cpu.
249 * Returns 1 if this timer was pending.
251 static int uv_rtc_unset_timer(int cpu
, int force
)
253 int pnode
= uv_cpu_to_pnode(cpu
);
254 int bid
= uv_cpu_to_blade_id(cpu
);
255 struct uv_rtc_timer_head
*head
= blade_info
[bid
];
256 int bcpu
= uv_cpu_hub_info(cpu
)->blade_processor_id
;
257 u64
*t
= &head
->cpu
[bcpu
].expires
;
261 spin_lock_irqsave(&head
->lock
, flags
);
263 if ((head
->next_cpu
== bcpu
&& uv_read_rtc(NULL
) >= *t
) || force
)
268 /* Was the hardware setup for this timer? */
269 if (head
->next_cpu
== bcpu
)
270 uv_rtc_find_next_timer(head
, pnode
);
273 spin_unlock_irqrestore(&head
->lock
, flags
);
280 * Kernel interface routines.
286 static cycle_t
uv_read_rtc(struct clocksource
*cs
)
288 return (cycle_t
)uv_read_local_mmr(UVH_RTC
);
292 * Program the next event, relative to now
294 static int uv_rtc_next_event(unsigned long delta
,
295 struct clock_event_device
*ced
)
297 int ced_cpu
= cpumask_first(ced
->cpumask
);
299 return uv_rtc_set_timer(ced_cpu
, delta
+ uv_read_rtc(NULL
));
303 * Setup the RTC timer in oneshot mode
305 static void uv_rtc_timer_setup(enum clock_event_mode mode
,
306 struct clock_event_device
*evt
)
308 int ced_cpu
= cpumask_first(evt
->cpumask
);
311 case CLOCK_EVT_MODE_PERIODIC
:
312 case CLOCK_EVT_MODE_ONESHOT
:
313 case CLOCK_EVT_MODE_RESUME
:
314 /* Nothing to do here yet */
316 case CLOCK_EVT_MODE_UNUSED
:
317 case CLOCK_EVT_MODE_SHUTDOWN
:
318 uv_rtc_unset_timer(ced_cpu
, 1);
323 static void uv_rtc_interrupt(void)
325 int cpu
= smp_processor_id();
326 struct clock_event_device
*ced
= &per_cpu(cpu_ced
, cpu
);
328 if (!ced
|| !ced
->event_handler
)
331 if (uv_rtc_unset_timer(cpu
, 0) != 1)
334 ced
->event_handler(ced
);
337 static int __init
uv_enable_evt_rtc(char *str
)
339 uv_rtc_evt_enable
= 1;
343 __setup("uvrtcevt", uv_enable_evt_rtc
);
345 static __init
void uv_rtc_register_clockevents(struct work_struct
*dummy
)
347 struct clock_event_device
*ced
= &__get_cpu_var(cpu_ced
);
349 *ced
= clock_event_device_uv
;
350 ced
->cpumask
= cpumask_of(smp_processor_id());
351 clockevents_register_device(ced
);
354 static __init
int uv_rtc_setup_clock(void)
361 clocksource_uv
.mult
= clocksource_hz2mult(sn_rtc_cycles_per_second
,
362 clocksource_uv
.shift
);
364 /* If single blade, prefer tsc */
365 if (uv_num_possible_blades() == 1)
366 clocksource_uv
.rating
= 250;
368 rc
= clocksource_register(&clocksource_uv
);
370 printk(KERN_INFO
"UV RTC clocksource failed rc %d\n", rc
);
372 printk(KERN_INFO
"UV RTC clocksource registered freq %lu MHz\n",
373 sn_rtc_cycles_per_second
/(unsigned long)1E6
);
375 if (rc
|| !uv_rtc_evt_enable
|| x86_platform_ipi_callback
)
378 /* Setup and register clockevents */
379 rc
= uv_rtc_allocate_timers();
383 x86_platform_ipi_callback
= uv_rtc_interrupt
;
385 clock_event_device_uv
.mult
= div_sc(sn_rtc_cycles_per_second
,
386 NSEC_PER_SEC
, clock_event_device_uv
.shift
);
388 clock_event_device_uv
.min_delta_ns
= NSEC_PER_SEC
/
389 sn_rtc_cycles_per_second
;
391 clock_event_device_uv
.max_delta_ns
= clocksource_uv
.mask
*
392 (NSEC_PER_SEC
/ sn_rtc_cycles_per_second
);
394 rc
= schedule_on_each_cpu(uv_rtc_register_clockevents
);
396 x86_platform_ipi_callback
= NULL
;
397 uv_rtc_deallocate_timers();
401 printk(KERN_INFO
"UV RTC clockevents registered\n");
406 clocksource_unregister(&clocksource_uv
);
407 printk(KERN_INFO
"UV RTC clockevents failed rc %d\n", rc
);
411 arch_initcall(uv_rtc_setup_clock
);