arch/x86/kernel/visws_quirks.c

   1 /*
   2  *  Unmaintained SGI Visual Workstation support.
   3  *  Split out from setup.c by davej@suse.de
   4  */
   5
   6 #include <linux/interrupt.h>
   7 #include <linux/module.h>
   8 #include <linux/init.h>
   9 #include <linux/smp.h>
  10
  11 #include <asm/visws/cobalt.h>
  12 #include <asm/visws/piix4.h>
  13 #include <asm/arch_hooks.h>
  14 #include <asm/fixmap.h>
  15 #include <asm/reboot.h>
  16 #include <asm/setup.h>
  17 #include <asm/e820.h>
  18 #include <asm/smp.h>
  19 #include <asm/io.h>
  20
  21 #include <mach_ipi.h>
  22
  23 #include "mach_apic.h"
  24
  25 #include <linux/init.h>
  26 #include <linux/smp.h>
  27
  28 char visws_board_type   = -1;
  29 char visws_board_rev    = -1;
  30
  31 int is_visws_box(void)
  32 {
  33         return visws_board_type >= 0;
  34 }
  35
  36 static int __init visws_time_init_quirk(void)
  37 {
  38         printk(KERN_INFO "Starting Cobalt Timer system clock\n");
  39
  40         /* Set the countdown value */
  41         co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
  42
  43         /* Start the timer */
  44         co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
  45
  46         /* Enable (unmask) the timer interrupt */
  47         co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
  48
  49         /*
  50          * Zero return means the generic timer setup code will set up
  51          * the standard vector:
  52          */
  53         return 0;
  54 }
  55
  56 static int __init visws_pre_intr_init_quirk(void)
  57 {
  58         init_VISWS_APIC_irqs();
  59
  60         /*
  61          * We dont want ISA irqs to be set up by the generic code:
  62          */
  63         return 1;
  64 }
  65
  66 /* Quirk for machine specific memory setup. */
  67
  68 #define MB (1024 * 1024)
  69
  70 unsigned long sgivwfb_mem_phys;
  71 unsigned long sgivwfb_mem_size;
  72 EXPORT_SYMBOL(sgivwfb_mem_phys);
  73 EXPORT_SYMBOL(sgivwfb_mem_size);
  74
  75 long long mem_size __initdata = 0;
  76
  77 static char * __init visws_memory_setup_quirk(void)
  78 {
  79         long long gfx_mem_size = 8 * MB;
  80
  81         mem_size = boot_params.alt_mem_k;
  82
  83         if (!mem_size) {
  84                 printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
  85                 mem_size = 128 * MB;
  86         }
  87
  88         /*
  89          * this hardcodes the graphics memory to 8 MB
  90          * it really should be sized dynamically (or at least
  91          * set as a boot param)
  92          */
  93         if (!sgivwfb_mem_size) {
  94                 printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
  95                 sgivwfb_mem_size = 8 * MB;
  96         }
  97
  98         /*
  99          * Trim to nearest MB
 100          */
 101         sgivwfb_mem_size &= ~((1 << 20) - 1);
 102         sgivwfb_mem_phys = mem_size - gfx_mem_size;
 103
 104         e820_add_region(0, LOWMEMSIZE(), E820_RAM);
 105         e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
 106         e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
 107
 108         return "PROM";
 109 }
 110
 111 static void visws_machine_emergency_restart(void)
 112 {
 113         /*
 114          * Visual Workstations restart after this
 115          * register is poked on the PIIX4
 116          */
 117         outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
 118 }
 119
 120 static void visws_machine_power_off(void)
 121 {
 122         unsigned short pm_status;
 123 /*      extern unsigned int pci_bus0; */
 124
 125         while ((pm_status = inw(PMSTS_PORT)) & 0x100)
 126                 outw(pm_status, PMSTS_PORT);
 127
 128         outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);
 129
 130         mdelay(10);
 131
 132 #define PCI_CONF1_ADDRESS(bus, devfn, reg) \
 133         (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
 134
 135 /*      outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
 136         outl(PIIX_SPECIAL_STOP, 0xCFC);
 137 }
 138
 139 static int __init visws_get_smp_config_quirk(unsigned int early)
 140 {
 141         /*
 142          * Prevent MP-table parsing by the generic code:
 143          */
 144         return 1;
 145 }
 146
 147 extern unsigned int __cpuinitdata maxcpus;
 148
 149 /*
 150  * The Visual Workstation is Intel MP compliant in the hardware
 151  * sense, but it doesn't have a BIOS(-configuration table).
 152  * No problem for Linux.
 153  */
 154
 155 static void __init MP_processor_info (struct mpc_config_processor *m)
 156 {
 157         int ver, logical_apicid;
 158         physid_mask_t apic_cpus;
 159
 160         if (!(m->mpc_cpuflag & CPU_ENABLED))
 161                 return;
 162
 163         logical_apicid = m->mpc_apicid;
 164         printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
 165                m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
 166                m->mpc_apicid,
 167                (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
 168                (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
 169                m->mpc_apicver);
 170
 171         if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)
 172                 boot_cpu_physical_apicid = m->mpc_apicid;
 173
 174         ver = m->mpc_apicver;
 175         if ((ver >= 0x14 && m->mpc_apicid >= 0xff) || m->mpc_apicid >= 0xf) {
 176                 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
 177                         m->mpc_apicid, MAX_APICS);
 178                 return;
 179         }
 180
 181         apic_cpus = apicid_to_cpu_present(m->mpc_apicid);
 182         physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
 183         /*
 184          * Validate version
 185          */
 186         if (ver == 0x0) {
 187                 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
 188                         "fixing up to 0x10. (tell your hw vendor)\n",
 189                         m->mpc_apicid);
 190                 ver = 0x10;
 191         }
 192         apic_version[m->mpc_apicid] = ver;
 193 }
 194
 195 int __init visws_find_smp_config_quirk(unsigned int reserve)
 196 {
 197         struct mpc_config_processor *mp = phys_to_virt(CO_CPU_TAB_PHYS);
 198         unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));
 199
 200         if (ncpus > CO_CPU_MAX) {
 201                 printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",
 202                         ncpus, mp);
 203
 204                 ncpus = CO_CPU_MAX;
 205         }
 206
 207         if (ncpus > maxcpus)
 208                 ncpus = maxcpus;
 209
 210 #ifdef CONFIG_X86_LOCAL_APIC
 211         smp_found_config = 1;
 212 #endif
 213         while (ncpus--)
 214                 MP_processor_info(mp++);
 215
 216         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
 217
 218         return 1;
 219 }
 220
 221 extern int visws_trap_init_quirk(void);
 222
 223 void __init visws_early_detect(void)
 224 {
 225         int raw;
 226
 227         visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
 228                                                          >> PIIX_GPI_BD_SHIFT;
 229
 230         if (visws_board_type < 0)
 231                 return;
 232
 233         /*
 234          * Install special quirks for timer, interrupt and memory setup:
 235          */
 236         arch_time_init_quirk            = visws_time_init_quirk;
 237         arch_pre_intr_init_quirk        = visws_pre_intr_init_quirk;
 238         arch_memory_setup_quirk         = visws_memory_setup_quirk;
 239
 240         /*
 241          * Fall back to generic behavior for traps:
 242          */
 243         arch_intr_init_quirk            = NULL;
 244         arch_trap_init_quirk            = visws_trap_init_quirk;
 245
 246         /*
 247          * Install reboot quirks:
 248          */
 249         pm_power_off                    = visws_machine_power_off;
 250         machine_ops.emergency_restart   = visws_machine_emergency_restart;
 251
 252         /*
 253          * Do not use broadcast IPIs:
 254          */
 255         no_broadcast = 0;
 256
 257         /*
 258          * Override generic MP-table parsing:
 259          */
 260         mach_get_smp_config_quirk       = visws_get_smp_config_quirk;
 261         mach_find_smp_config_quirk      = visws_find_smp_config_quirk;
 262
 263 #ifdef CONFIG_X86_IO_APIC
 264         /*
 265          * Turn off IO-APIC detection and initialization:
 266          */
 267         skip_ioapic_setup               = 1;
 268 #endif
 269
 270         /*
 271          * Get Board rev.
 272          * First, we have to initialize the 307 part to allow us access
 273          * to the GPIO registers.  Let's map them at 0x0fc0 which is right
 274          * after the PIIX4 PM section.
 275          */
 276         outb_p(SIO_DEV_SEL, SIO_INDEX);
 277         outb_p(SIO_GP_DEV, SIO_DATA);   /* Talk to GPIO regs. */
 278
 279         outb_p(SIO_DEV_MSB, SIO_INDEX);
 280         outb_p(SIO_GP_MSB, SIO_DATA);   /* MSB of GPIO base address */
 281
 282         outb_p(SIO_DEV_LSB, SIO_INDEX);
 283         outb_p(SIO_GP_LSB, SIO_DATA);   /* LSB of GPIO base address */
 284
 285         outb_p(SIO_DEV_ENB, SIO_INDEX);
 286         outb_p(1, SIO_DATA);            /* Enable GPIO registers. */
 287
 288         /*
 289          * Now, we have to map the power management section to write
 290          * a bit which enables access to the GPIO registers.
 291          * What lunatic came up with this shit?
 292          */
 293         outb_p(SIO_DEV_SEL, SIO_INDEX);
 294         outb_p(SIO_PM_DEV, SIO_DATA);   /* Talk to GPIO regs. */
 295
 296         outb_p(SIO_DEV_MSB, SIO_INDEX);
 297         outb_p(SIO_PM_MSB, SIO_DATA);   /* MSB of PM base address */
 298
 299         outb_p(SIO_DEV_LSB, SIO_INDEX);
 300         outb_p(SIO_PM_LSB, SIO_DATA);   /* LSB of PM base address */
 301
 302         outb_p(SIO_DEV_ENB, SIO_INDEX);
 303         outb_p(1, SIO_DATA);            /* Enable PM registers. */
 304
 305         /*
 306          * Now, write the PM register which enables the GPIO registers.
 307          */
 308         outb_p(SIO_PM_FER2, SIO_PM_INDEX);
 309         outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
 310
 311         /*
 312          * Now, initialize the GPIO registers.
 313          * We want them all to be inputs which is the
 314          * power on default, so let's leave them alone.
 315          * So, let's just read the board rev!
 316          */
 317         raw = inb_p(SIO_GP_DATA1);
 318         raw &= 0x7f;    /* 7 bits of valid board revision ID. */
 319
 320         if (visws_board_type == VISWS_320) {
 321                 if (raw < 0x6) {
 322                         visws_board_rev = 4;
 323                 } else if (raw < 0xc) {
 324                         visws_board_rev = 5;
 325                 } else {
 326                         visws_board_rev = 6;
 327                 }
 328         } else if (visws_board_type == VISWS_540) {
 329                         visws_board_rev = 2;
 330                 } else {
 331                         visws_board_rev = raw;
 332                 }
 333
 334         printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
 335                (visws_board_type == VISWS_320 ? "320" :
 336                (visws_board_type == VISWS_540 ? "540" :
 337                 "unknown")), visws_board_rev);
 338 }