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KVM: x86 emulator: Move string pio emulation into emulator.c
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22 #ifndef __KERNEL__
23 #include <stdio.h>
24 #include <stdint.h>
25 #include <public/xen.h>
26 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
27 #else
28 #include <linux/kvm_host.h>
29 #include "kvm_cache_regs.h"
30 #define DPRINTF(x...) do {} while (0)
31 #endif
32 #include <linux/module.h>
33 #include <asm/kvm_emulate.h>
34
35 #include "x86.h"
36 #include "tss.h"
37
38 /*
39 * Opcode effective-address decode tables.
40 * Note that we only emulate instructions that have at least one memory
41 * operand (excluding implicit stack references). We assume that stack
42 * references and instruction fetches will never occur in special memory
43 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
44 * not be handled.
45 */
46
47 /* Operand sizes: 8-bit operands or specified/overridden size. */
48 #define ByteOp (1<<0) /* 8-bit operands. */
49 /* Destination operand type. */
50 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
51 #define DstReg (2<<1) /* Register operand. */
52 #define DstMem (3<<1) /* Memory operand. */
53 #define DstAcc (4<<1) /* Destination Accumulator */
54 #define DstDI (5<<1) /* Destination is in ES:(E)DI */
55 #define DstMask (7<<1)
56 /* Source operand type. */
57 #define SrcNone (0<<4) /* No source operand. */
58 #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
59 #define SrcReg (1<<4) /* Register operand. */
60 #define SrcMem (2<<4) /* Memory operand. */
61 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
62 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
63 #define SrcImm (5<<4) /* Immediate operand. */
64 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
65 #define SrcOne (7<<4) /* Implied '1' */
66 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
67 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
68 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */
69 #define SrcMask (0xf<<4)
70 /* Generic ModRM decode. */
71 #define ModRM (1<<8)
72 /* Destination is only written; never read. */
73 #define Mov (1<<9)
74 #define BitOp (1<<10)
75 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
76 #define String (1<<12) /* String instruction (rep capable) */
77 #define Stack (1<<13) /* Stack instruction (push/pop) */
78 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
79 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
80 #define GroupMask 0xff /* Group number stored in bits 0:7 */
81 /* Misc flags */
82 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
83 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
84 #define No64 (1<<28)
85 /* Source 2 operand type */
86 #define Src2None (0<<29)
87 #define Src2CL (1<<29)
88 #define Src2ImmByte (2<<29)
89 #define Src2One (3<<29)
90 #define Src2Imm16 (4<<29)
91 #define Src2Mem16 (5<<29) /* Used for Ep encoding. First argument has to be
92 in memory and second argument is located
93 immediately after the first one in memory. */
94 #define Src2Mask (7<<29)
95
96 enum {
97 Group1_80, Group1_81, Group1_82, Group1_83,
98 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
99 Group8, Group9,
100 };
101
102 static u32 opcode_table[256] = {
103 /* 0x00 - 0x07 */
104 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
105 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
106 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
107 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
108 /* 0x08 - 0x0F */
109 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
110 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
111 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
112 ImplicitOps | Stack | No64, 0,
113 /* 0x10 - 0x17 */
114 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
115 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
116 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
117 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
118 /* 0x18 - 0x1F */
119 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
120 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
121 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
122 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
123 /* 0x20 - 0x27 */
124 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
125 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
126 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
127 /* 0x28 - 0x2F */
128 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
129 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
130 0, 0, 0, 0,
131 /* 0x30 - 0x37 */
132 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
133 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
134 0, 0, 0, 0,
135 /* 0x38 - 0x3F */
136 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
137 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
138 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
139 0, 0,
140 /* 0x40 - 0x47 */
141 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
142 /* 0x48 - 0x4F */
143 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
144 /* 0x50 - 0x57 */
145 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
146 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
147 /* 0x58 - 0x5F */
148 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
149 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
150 /* 0x60 - 0x67 */
151 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
152 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
153 0, 0, 0, 0,
154 /* 0x68 - 0x6F */
155 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
156 DstDI | ByteOp | Mov | String, DstDI | Mov | String, /* insb, insw/insd */
157 SrcSI | ByteOp | ImplicitOps | String, SrcSI | ImplicitOps | String, /* outsb, outsw/outsd */
158 /* 0x70 - 0x77 */
159 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
160 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
161 /* 0x78 - 0x7F */
162 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
163 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
164 /* 0x80 - 0x87 */
165 Group | Group1_80, Group | Group1_81,
166 Group | Group1_82, Group | Group1_83,
167 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
168 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
169 /* 0x88 - 0x8F */
170 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
171 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
172 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
173 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
174 /* 0x90 - 0x97 */
175 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
176 /* 0x98 - 0x9F */
177 0, 0, SrcImm | Src2Imm16 | No64, 0,
178 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
179 /* 0xA0 - 0xA7 */
180 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
181 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
182 ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String,
183 ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String,
184 /* 0xA8 - 0xAF */
185 0, 0, ByteOp | DstDI | Mov | String, DstDI | Mov | String,
186 ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String,
187 ByteOp | DstDI | String, DstDI | String,
188 /* 0xB0 - 0xB7 */
189 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
190 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
191 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
192 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
193 /* 0xB8 - 0xBF */
194 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
195 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
196 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
197 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
198 /* 0xC0 - 0xC7 */
199 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
200 0, ImplicitOps | Stack, 0, 0,
201 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
202 /* 0xC8 - 0xCF */
203 0, 0, 0, ImplicitOps | Stack,
204 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
205 /* 0xD0 - 0xD7 */
206 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
207 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
208 0, 0, 0, 0,
209 /* 0xD8 - 0xDF */
210 0, 0, 0, 0, 0, 0, 0, 0,
211 /* 0xE0 - 0xE7 */
212 0, 0, 0, 0,
213 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
214 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
215 /* 0xE8 - 0xEF */
216 SrcImm | Stack, SrcImm | ImplicitOps,
217 SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps,
218 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
219 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
220 /* 0xF0 - 0xF7 */
221 0, 0, 0, 0,
222 ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3,
223 /* 0xF8 - 0xFF */
224 ImplicitOps, 0, ImplicitOps, ImplicitOps,
225 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
226 };
227
228 static u32 twobyte_table[256] = {
229 /* 0x00 - 0x0F */
230 0, Group | GroupDual | Group7, 0, 0,
231 0, ImplicitOps, ImplicitOps | Priv, 0,
232 ImplicitOps | Priv, ImplicitOps | Priv, 0, 0,
233 0, ImplicitOps | ModRM, 0, 0,
234 /* 0x10 - 0x1F */
235 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
236 /* 0x20 - 0x2F */
237 ModRM | ImplicitOps | Priv, ModRM | Priv,
238 ModRM | ImplicitOps | Priv, ModRM | Priv,
239 0, 0, 0, 0,
240 0, 0, 0, 0, 0, 0, 0, 0,
241 /* 0x30 - 0x3F */
242 ImplicitOps | Priv, 0, ImplicitOps | Priv, 0,
243 ImplicitOps, ImplicitOps | Priv, 0, 0,
244 0, 0, 0, 0, 0, 0, 0, 0,
245 /* 0x40 - 0x47 */
246 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
247 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
248 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
249 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
250 /* 0x48 - 0x4F */
251 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
252 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
253 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
254 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
255 /* 0x50 - 0x5F */
256 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
257 /* 0x60 - 0x6F */
258 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
259 /* 0x70 - 0x7F */
260 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
261 /* 0x80 - 0x8F */
262 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
263 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
264 /* 0x90 - 0x9F */
265 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
266 /* 0xA0 - 0xA7 */
267 ImplicitOps | Stack, ImplicitOps | Stack,
268 0, DstMem | SrcReg | ModRM | BitOp,
269 DstMem | SrcReg | Src2ImmByte | ModRM,
270 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
271 /* 0xA8 - 0xAF */
272 ImplicitOps | Stack, ImplicitOps | Stack,
273 0, DstMem | SrcReg | ModRM | BitOp | Lock,
274 DstMem | SrcReg | Src2ImmByte | ModRM,
275 DstMem | SrcReg | Src2CL | ModRM,
276 ModRM, 0,
277 /* 0xB0 - 0xB7 */
278 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
279 0, DstMem | SrcReg | ModRM | BitOp | Lock,
280 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
281 DstReg | SrcMem16 | ModRM | Mov,
282 /* 0xB8 - 0xBF */
283 0, 0,
284 Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock,
285 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
286 DstReg | SrcMem16 | ModRM | Mov,
287 /* 0xC0 - 0xCF */
288 0, 0, 0, DstMem | SrcReg | ModRM | Mov,
289 0, 0, 0, Group | GroupDual | Group9,
290 0, 0, 0, 0, 0, 0, 0, 0,
291 /* 0xD0 - 0xDF */
292 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
293 /* 0xE0 - 0xEF */
294 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
295 /* 0xF0 - 0xFF */
296 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
297 };
298
299 static u32 group_table[] = {
300 [Group1_80*8] =
301 ByteOp | DstMem | SrcImm | ModRM | Lock,
302 ByteOp | DstMem | SrcImm | ModRM | Lock,
303 ByteOp | DstMem | SrcImm | ModRM | Lock,
304 ByteOp | DstMem | SrcImm | ModRM | Lock,
305 ByteOp | DstMem | SrcImm | ModRM | Lock,
306 ByteOp | DstMem | SrcImm | ModRM | Lock,
307 ByteOp | DstMem | SrcImm | ModRM | Lock,
308 ByteOp | DstMem | SrcImm | ModRM,
309 [Group1_81*8] =
310 DstMem | SrcImm | ModRM | Lock,
311 DstMem | SrcImm | ModRM | Lock,
312 DstMem | SrcImm | ModRM | Lock,
313 DstMem | SrcImm | ModRM | Lock,
314 DstMem | SrcImm | ModRM | Lock,
315 DstMem | SrcImm | ModRM | Lock,
316 DstMem | SrcImm | ModRM | Lock,
317 DstMem | SrcImm | ModRM,
318 [Group1_82*8] =
319 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
320 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
321 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
322 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
323 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
324 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
325 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
326 ByteOp | DstMem | SrcImm | ModRM | No64,
327 [Group1_83*8] =
328 DstMem | SrcImmByte | ModRM | Lock,
329 DstMem | SrcImmByte | ModRM | Lock,
330 DstMem | SrcImmByte | ModRM | Lock,
331 DstMem | SrcImmByte | ModRM | Lock,
332 DstMem | SrcImmByte | ModRM | Lock,
333 DstMem | SrcImmByte | ModRM | Lock,
334 DstMem | SrcImmByte | ModRM | Lock,
335 DstMem | SrcImmByte | ModRM,
336 [Group1A*8] =
337 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
338 [Group3_Byte*8] =
339 ByteOp | SrcImm | DstMem | ModRM, 0,
340 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
341 0, 0, 0, 0,
342 [Group3*8] =
343 DstMem | SrcImm | ModRM, 0,
344 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
345 0, 0, 0, 0,
346 [Group4*8] =
347 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
348 0, 0, 0, 0, 0, 0,
349 [Group5*8] =
350 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
351 SrcMem | ModRM | Stack, 0,
352 SrcMem | ModRM | Stack, SrcMem | ModRM | Src2Mem16 | ImplicitOps,
353 SrcMem | ModRM | Stack, 0,
354 [Group7*8] =
355 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv,
356 SrcNone | ModRM | DstMem | Mov, 0,
357 SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv,
358 [Group8*8] =
359 0, 0, 0, 0,
360 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock,
361 DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock,
362 [Group9*8] =
363 0, ImplicitOps | ModRM | Lock, 0, 0, 0, 0, 0, 0,
364 };
365
366 static u32 group2_table[] = {
367 [Group7*8] =
368 SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv,
369 SrcNone | ModRM | DstMem | Mov, 0,
370 SrcMem16 | ModRM | Mov | Priv, 0,
371 [Group9*8] =
372 0, 0, 0, 0, 0, 0, 0, 0,
373 };
374
375 /* EFLAGS bit definitions. */
376 #define EFLG_ID (1<<21)
377 #define EFLG_VIP (1<<20)
378 #define EFLG_VIF (1<<19)
379 #define EFLG_AC (1<<18)
380 #define EFLG_VM (1<<17)
381 #define EFLG_RF (1<<16)
382 #define EFLG_IOPL (3<<12)
383 #define EFLG_NT (1<<14)
384 #define EFLG_OF (1<<11)
385 #define EFLG_DF (1<<10)
386 #define EFLG_IF (1<<9)
387 #define EFLG_TF (1<<8)
388 #define EFLG_SF (1<<7)
389 #define EFLG_ZF (1<<6)
390 #define EFLG_AF (1<<4)
391 #define EFLG_PF (1<<2)
392 #define EFLG_CF (1<<0)
393
394 /*
395 * Instruction emulation:
396 * Most instructions are emulated directly via a fragment of inline assembly
397 * code. This allows us to save/restore EFLAGS and thus very easily pick up
398 * any modified flags.
399 */
400
401 #if defined(CONFIG_X86_64)
402 #define _LO32 "k" /* force 32-bit operand */
403 #define _STK "%%rsp" /* stack pointer */
404 #elif defined(__i386__)
405 #define _LO32 "" /* force 32-bit operand */
406 #define _STK "%%esp" /* stack pointer */
407 #endif
408
409 /*
410 * These EFLAGS bits are restored from saved value during emulation, and
411 * any changes are written back to the saved value after emulation.
412 */
413 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
414
415 /* Before executing instruction: restore necessary bits in EFLAGS. */
416 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
417 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
418 "movl %"_sav",%"_LO32 _tmp"; " \
419 "push %"_tmp"; " \
420 "push %"_tmp"; " \
421 "movl %"_msk",%"_LO32 _tmp"; " \
422 "andl %"_LO32 _tmp",("_STK"); " \
423 "pushf; " \
424 "notl %"_LO32 _tmp"; " \
425 "andl %"_LO32 _tmp",("_STK"); " \
426 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
427 "pop %"_tmp"; " \
428 "orl %"_LO32 _tmp",("_STK"); " \
429 "popf; " \
430 "pop %"_sav"; "
431
432 /* After executing instruction: write-back necessary bits in EFLAGS. */
433 #define _POST_EFLAGS(_sav, _msk, _tmp) \
434 /* _sav |= EFLAGS & _msk; */ \
435 "pushf; " \
436 "pop %"_tmp"; " \
437 "andl %"_msk",%"_LO32 _tmp"; " \
438 "orl %"_LO32 _tmp",%"_sav"; "
439
440 #ifdef CONFIG_X86_64
441 #define ON64(x) x
442 #else
443 #define ON64(x)
444 #endif
445
446 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
447 do { \
448 __asm__ __volatile__ ( \
449 _PRE_EFLAGS("0", "4", "2") \
450 _op _suffix " %"_x"3,%1; " \
451 _POST_EFLAGS("0", "4", "2") \
452 : "=m" (_eflags), "=m" ((_dst).val), \
453 "=&r" (_tmp) \
454 : _y ((_src).val), "i" (EFLAGS_MASK)); \
455 } while (0)
456
457
458 /* Raw emulation: instruction has two explicit operands. */
459 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
460 do { \
461 unsigned long _tmp; \
462 \
463 switch ((_dst).bytes) { \
464 case 2: \
465 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
466 break; \
467 case 4: \
468 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
469 break; \
470 case 8: \
471 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
472 break; \
473 } \
474 } while (0)
475
476 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
477 do { \
478 unsigned long _tmp; \
479 switch ((_dst).bytes) { \
480 case 1: \
481 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
482 break; \
483 default: \
484 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
485 _wx, _wy, _lx, _ly, _qx, _qy); \
486 break; \
487 } \
488 } while (0)
489
490 /* Source operand is byte-sized and may be restricted to just %cl. */
491 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
492 __emulate_2op(_op, _src, _dst, _eflags, \
493 "b", "c", "b", "c", "b", "c", "b", "c")
494
495 /* Source operand is byte, word, long or quad sized. */
496 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
497 __emulate_2op(_op, _src, _dst, _eflags, \
498 "b", "q", "w", "r", _LO32, "r", "", "r")
499
500 /* Source operand is word, long or quad sized. */
501 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
502 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
503 "w", "r", _LO32, "r", "", "r")
504
505 /* Instruction has three operands and one operand is stored in ECX register */
506 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
507 do { \
508 unsigned long _tmp; \
509 _type _clv = (_cl).val; \
510 _type _srcv = (_src).val; \
511 _type _dstv = (_dst).val; \
512 \
513 __asm__ __volatile__ ( \
514 _PRE_EFLAGS("0", "5", "2") \
515 _op _suffix " %4,%1 \n" \
516 _POST_EFLAGS("0", "5", "2") \
517 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
518 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
519 ); \
520 \
521 (_cl).val = (unsigned long) _clv; \
522 (_src).val = (unsigned long) _srcv; \
523 (_dst).val = (unsigned long) _dstv; \
524 } while (0)
525
526 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
527 do { \
528 switch ((_dst).bytes) { \
529 case 2: \
530 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
531 "w", unsigned short); \
532 break; \
533 case 4: \
534 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
535 "l", unsigned int); \
536 break; \
537 case 8: \
538 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
539 "q", unsigned long)); \
540 break; \
541 } \
542 } while (0)
543
544 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
545 do { \
546 unsigned long _tmp; \
547 \
548 __asm__ __volatile__ ( \
549 _PRE_EFLAGS("0", "3", "2") \
550 _op _suffix " %1; " \
551 _POST_EFLAGS("0", "3", "2") \
552 : "=m" (_eflags), "+m" ((_dst).val), \
553 "=&r" (_tmp) \
554 : "i" (EFLAGS_MASK)); \
555 } while (0)
556
557 /* Instruction has only one explicit operand (no source operand). */
558 #define emulate_1op(_op, _dst, _eflags) \
559 do { \
560 switch ((_dst).bytes) { \
561 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
562 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
563 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
564 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
565 } \
566 } while (0)
567
568 /* Fetch next part of the instruction being emulated. */
569 #define insn_fetch(_type, _size, _eip) \
570 ({ unsigned long _x; \
571 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
572 if (rc != X86EMUL_CONTINUE) \
573 goto done; \
574 (_eip) += (_size); \
575 (_type)_x; \
576 })
577
578 static inline unsigned long ad_mask(struct decode_cache *c)
579 {
580 return (1UL << (c->ad_bytes << 3)) - 1;
581 }
582
583 /* Access/update address held in a register, based on addressing mode. */
584 static inline unsigned long
585 address_mask(struct decode_cache *c, unsigned long reg)
586 {
587 if (c->ad_bytes == sizeof(unsigned long))
588 return reg;
589 else
590 return reg & ad_mask(c);
591 }
592
593 static inline unsigned long
594 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
595 {
596 return base + address_mask(c, reg);
597 }
598
599 static inline void
600 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
601 {
602 if (c->ad_bytes == sizeof(unsigned long))
603 *reg += inc;
604 else
605 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
606 }
607
608 static inline void jmp_rel(struct decode_cache *c, int rel)
609 {
610 register_address_increment(c, &c->eip, rel);
611 }
612
613 static void set_seg_override(struct decode_cache *c, int seg)
614 {
615 c->has_seg_override = true;
616 c->seg_override = seg;
617 }
618
619 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
620 {
621 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
622 return 0;
623
624 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
625 }
626
627 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
628 struct decode_cache *c)
629 {
630 if (!c->has_seg_override)
631 return 0;
632
633 return seg_base(ctxt, c->seg_override);
634 }
635
636 static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
637 {
638 return seg_base(ctxt, VCPU_SREG_ES);
639 }
640
641 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
642 {
643 return seg_base(ctxt, VCPU_SREG_SS);
644 }
645
646 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
647 struct x86_emulate_ops *ops,
648 unsigned long linear, u8 *dest)
649 {
650 struct fetch_cache *fc = &ctxt->decode.fetch;
651 int rc;
652 int size;
653
654 if (linear < fc->start || linear >= fc->end) {
655 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
656 rc = ops->fetch(linear, fc->data, size, ctxt->vcpu, NULL);
657 if (rc != X86EMUL_CONTINUE)
658 return rc;
659 fc->start = linear;
660 fc->end = linear + size;
661 }
662 *dest = fc->data[linear - fc->start];
663 return X86EMUL_CONTINUE;
664 }
665
666 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
667 struct x86_emulate_ops *ops,
668 unsigned long eip, void *dest, unsigned size)
669 {
670 int rc;
671
672 /* x86 instructions are limited to 15 bytes. */
673 if (eip + size - ctxt->eip > 15)
674 return X86EMUL_UNHANDLEABLE;
675 eip += ctxt->cs_base;
676 while (size--) {
677 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
678 if (rc != X86EMUL_CONTINUE)
679 return rc;
680 }
681 return X86EMUL_CONTINUE;
682 }
683
684 /*
685 * Given the 'reg' portion of a ModRM byte, and a register block, return a
686 * pointer into the block that addresses the relevant register.
687 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
688 */
689 static void *decode_register(u8 modrm_reg, unsigned long *regs,
690 int highbyte_regs)
691 {
692 void *p;
693
694 p = &regs[modrm_reg];
695 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
696 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
697 return p;
698 }
699
700 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
701 struct x86_emulate_ops *ops,
702 void *ptr,
703 u16 *size, unsigned long *address, int op_bytes)
704 {
705 int rc;
706
707 if (op_bytes == 2)
708 op_bytes = 3;
709 *address = 0;
710 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
711 ctxt->vcpu, NULL);
712 if (rc != X86EMUL_CONTINUE)
713 return rc;
714 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
715 ctxt->vcpu, NULL);
716 return rc;
717 }
718
719 static int test_cc(unsigned int condition, unsigned int flags)
720 {
721 int rc = 0;
722
723 switch ((condition & 15) >> 1) {
724 case 0: /* o */
725 rc |= (flags & EFLG_OF);
726 break;
727 case 1: /* b/c/nae */
728 rc |= (flags & EFLG_CF);
729 break;
730 case 2: /* z/e */
731 rc |= (flags & EFLG_ZF);
732 break;
733 case 3: /* be/na */
734 rc |= (flags & (EFLG_CF|EFLG_ZF));
735 break;
736 case 4: /* s */
737 rc |= (flags & EFLG_SF);
738 break;
739 case 5: /* p/pe */
740 rc |= (flags & EFLG_PF);
741 break;
742 case 7: /* le/ng */
743 rc |= (flags & EFLG_ZF);
744 /* fall through */
745 case 6: /* l/nge */
746 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
747 break;
748 }
749
750 /* Odd condition identifiers (lsb == 1) have inverted sense. */
751 return (!!rc ^ (condition & 1));
752 }
753
754 static void decode_register_operand(struct operand *op,
755 struct decode_cache *c,
756 int inhibit_bytereg)
757 {
758 unsigned reg = c->modrm_reg;
759 int highbyte_regs = c->rex_prefix == 0;
760
761 if (!(c->d & ModRM))
762 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
763 op->type = OP_REG;
764 if ((c->d & ByteOp) && !inhibit_bytereg) {
765 op->ptr = decode_register(reg, c->regs, highbyte_regs);
766 op->val = *(u8 *)op->ptr;
767 op->bytes = 1;
768 } else {
769 op->ptr = decode_register(reg, c->regs, 0);
770 op->bytes = c->op_bytes;
771 switch (op->bytes) {
772 case 2:
773 op->val = *(u16 *)op->ptr;
774 break;
775 case 4:
776 op->val = *(u32 *)op->ptr;
777 break;
778 case 8:
779 op->val = *(u64 *) op->ptr;
780 break;
781 }
782 }
783 op->orig_val = op->val;
784 }
785
786 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
787 struct x86_emulate_ops *ops)
788 {
789 struct decode_cache *c = &ctxt->decode;
790 u8 sib;
791 int index_reg = 0, base_reg = 0, scale;
792 int rc = X86EMUL_CONTINUE;
793
794 if (c->rex_prefix) {
795 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
796 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
797 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
798 }
799
800 c->modrm = insn_fetch(u8, 1, c->eip);
801 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
802 c->modrm_reg |= (c->modrm & 0x38) >> 3;
803 c->modrm_rm |= (c->modrm & 0x07);
804 c->modrm_ea = 0;
805 c->use_modrm_ea = 1;
806
807 if (c->modrm_mod == 3) {
808 c->modrm_ptr = decode_register(c->modrm_rm,
809 c->regs, c->d & ByteOp);
810 c->modrm_val = *(unsigned long *)c->modrm_ptr;
811 return rc;
812 }
813
814 if (c->ad_bytes == 2) {
815 unsigned bx = c->regs[VCPU_REGS_RBX];
816 unsigned bp = c->regs[VCPU_REGS_RBP];
817 unsigned si = c->regs[VCPU_REGS_RSI];
818 unsigned di = c->regs[VCPU_REGS_RDI];
819
820 /* 16-bit ModR/M decode. */
821 switch (c->modrm_mod) {
822 case 0:
823 if (c->modrm_rm == 6)
824 c->modrm_ea += insn_fetch(u16, 2, c->eip);
825 break;
826 case 1:
827 c->modrm_ea += insn_fetch(s8, 1, c->eip);
828 break;
829 case 2:
830 c->modrm_ea += insn_fetch(u16, 2, c->eip);
831 break;
832 }
833 switch (c->modrm_rm) {
834 case 0:
835 c->modrm_ea += bx + si;
836 break;
837 case 1:
838 c->modrm_ea += bx + di;
839 break;
840 case 2:
841 c->modrm_ea += bp + si;
842 break;
843 case 3:
844 c->modrm_ea += bp + di;
845 break;
846 case 4:
847 c->modrm_ea += si;
848 break;
849 case 5:
850 c->modrm_ea += di;
851 break;
852 case 6:
853 if (c->modrm_mod != 0)
854 c->modrm_ea += bp;
855 break;
856 case 7:
857 c->modrm_ea += bx;
858 break;
859 }
860 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
861 (c->modrm_rm == 6 && c->modrm_mod != 0))
862 if (!c->has_seg_override)
863 set_seg_override(c, VCPU_SREG_SS);
864 c->modrm_ea = (u16)c->modrm_ea;
865 } else {
866 /* 32/64-bit ModR/M decode. */
867 if ((c->modrm_rm & 7) == 4) {
868 sib = insn_fetch(u8, 1, c->eip);
869 index_reg |= (sib >> 3) & 7;
870 base_reg |= sib & 7;
871 scale = sib >> 6;
872
873 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
874 c->modrm_ea += insn_fetch(s32, 4, c->eip);
875 else
876 c->modrm_ea += c->regs[base_reg];
877 if (index_reg != 4)
878 c->modrm_ea += c->regs[index_reg] << scale;
879 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
880 if (ctxt->mode == X86EMUL_MODE_PROT64)
881 c->rip_relative = 1;
882 } else
883 c->modrm_ea += c->regs[c->modrm_rm];
884 switch (c->modrm_mod) {
885 case 0:
886 if (c->modrm_rm == 5)
887 c->modrm_ea += insn_fetch(s32, 4, c->eip);
888 break;
889 case 1:
890 c->modrm_ea += insn_fetch(s8, 1, c->eip);
891 break;
892 case 2:
893 c->modrm_ea += insn_fetch(s32, 4, c->eip);
894 break;
895 }
896 }
897 done:
898 return rc;
899 }
900
901 static int decode_abs(struct x86_emulate_ctxt *ctxt,
902 struct x86_emulate_ops *ops)
903 {
904 struct decode_cache *c = &ctxt->decode;
905 int rc = X86EMUL_CONTINUE;
906
907 switch (c->ad_bytes) {
908 case 2:
909 c->modrm_ea = insn_fetch(u16, 2, c->eip);
910 break;
911 case 4:
912 c->modrm_ea = insn_fetch(u32, 4, c->eip);
913 break;
914 case 8:
915 c->modrm_ea = insn_fetch(u64, 8, c->eip);
916 break;
917 }
918 done:
919 return rc;
920 }
921
922 int
923 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
924 {
925 struct decode_cache *c = &ctxt->decode;
926 int rc = X86EMUL_CONTINUE;
927 int mode = ctxt->mode;
928 int def_op_bytes, def_ad_bytes, group;
929
930 /* Shadow copy of register state. Committed on successful emulation. */
931
932 memset(c, 0, sizeof(struct decode_cache));
933 c->eip = ctxt->eip;
934 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
935 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
936
937 switch (mode) {
938 case X86EMUL_MODE_REAL:
939 case X86EMUL_MODE_VM86:
940 case X86EMUL_MODE_PROT16:
941 def_op_bytes = def_ad_bytes = 2;
942 break;
943 case X86EMUL_MODE_PROT32:
944 def_op_bytes = def_ad_bytes = 4;
945 break;
946 #ifdef CONFIG_X86_64
947 case X86EMUL_MODE_PROT64:
948 def_op_bytes = 4;
949 def_ad_bytes = 8;
950 break;
951 #endif
952 default:
953 return -1;
954 }
955
956 c->op_bytes = def_op_bytes;
957 c->ad_bytes = def_ad_bytes;
958
959 /* Legacy prefixes. */
960 for (;;) {
961 switch (c->b = insn_fetch(u8, 1, c->eip)) {
962 case 0x66: /* operand-size override */
963 /* switch between 2/4 bytes */
964 c->op_bytes = def_op_bytes ^ 6;
965 break;
966 case 0x67: /* address-size override */
967 if (mode == X86EMUL_MODE_PROT64)
968 /* switch between 4/8 bytes */
969 c->ad_bytes = def_ad_bytes ^ 12;
970 else
971 /* switch between 2/4 bytes */
972 c->ad_bytes = def_ad_bytes ^ 6;
973 break;
974 case 0x26: /* ES override */
975 case 0x2e: /* CS override */
976 case 0x36: /* SS override */
977 case 0x3e: /* DS override */
978 set_seg_override(c, (c->b >> 3) & 3);
979 break;
980 case 0x64: /* FS override */
981 case 0x65: /* GS override */
982 set_seg_override(c, c->b & 7);
983 break;
984 case 0x40 ... 0x4f: /* REX */
985 if (mode != X86EMUL_MODE_PROT64)
986 goto done_prefixes;
987 c->rex_prefix = c->b;
988 continue;
989 case 0xf0: /* LOCK */
990 c->lock_prefix = 1;
991 break;
992 case 0xf2: /* REPNE/REPNZ */
993 c->rep_prefix = REPNE_PREFIX;
994 break;
995 case 0xf3: /* REP/REPE/REPZ */
996 c->rep_prefix = REPE_PREFIX;
997 break;
998 default:
999 goto done_prefixes;
1000 }
1001
1002 /* Any legacy prefix after a REX prefix nullifies its effect. */
1003
1004 c->rex_prefix = 0;
1005 }
1006
1007 done_prefixes:
1008
1009 /* REX prefix. */
1010 if (c->rex_prefix)
1011 if (c->rex_prefix & 8)
1012 c->op_bytes = 8; /* REX.W */
1013
1014 /* Opcode byte(s). */
1015 c->d = opcode_table[c->b];
1016 if (c->d == 0) {
1017 /* Two-byte opcode? */
1018 if (c->b == 0x0f) {
1019 c->twobyte = 1;
1020 c->b = insn_fetch(u8, 1, c->eip);
1021 c->d = twobyte_table[c->b];
1022 }
1023 }
1024
1025 if (c->d & Group) {
1026 group = c->d & GroupMask;
1027 c->modrm = insn_fetch(u8, 1, c->eip);
1028 --c->eip;
1029
1030 group = (group << 3) + ((c->modrm >> 3) & 7);
1031 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
1032 c->d = group2_table[group];
1033 else
1034 c->d = group_table[group];
1035 }
1036
1037 /* Unrecognised? */
1038 if (c->d == 0) {
1039 DPRINTF("Cannot emulate %02x\n", c->b);
1040 return -1;
1041 }
1042
1043 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1044 c->op_bytes = 8;
1045
1046 /* ModRM and SIB bytes. */
1047 if (c->d & ModRM)
1048 rc = decode_modrm(ctxt, ops);
1049 else if (c->d & MemAbs)
1050 rc = decode_abs(ctxt, ops);
1051 if (rc != X86EMUL_CONTINUE)
1052 goto done;
1053
1054 if (!c->has_seg_override)
1055 set_seg_override(c, VCPU_SREG_DS);
1056
1057 if (!(!c->twobyte && c->b == 0x8d))
1058 c->modrm_ea += seg_override_base(ctxt, c);
1059
1060 if (c->ad_bytes != 8)
1061 c->modrm_ea = (u32)c->modrm_ea;
1062
1063 if (c->rip_relative)
1064 c->modrm_ea += c->eip;
1065
1066 /*
1067 * Decode and fetch the source operand: register, memory
1068 * or immediate.
1069 */
1070 switch (c->d & SrcMask) {
1071 case SrcNone:
1072 break;
1073 case SrcReg:
1074 decode_register_operand(&c->src, c, 0);
1075 break;
1076 case SrcMem16:
1077 c->src.bytes = 2;
1078 goto srcmem_common;
1079 case SrcMem32:
1080 c->src.bytes = 4;
1081 goto srcmem_common;
1082 case SrcMem:
1083 c->src.bytes = (c->d & ByteOp) ? 1 :
1084 c->op_bytes;
1085 /* Don't fetch the address for invlpg: it could be unmapped. */
1086 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
1087 break;
1088 srcmem_common:
1089 /*
1090 * For instructions with a ModR/M byte, switch to register
1091 * access if Mod = 3.
1092 */
1093 if ((c->d & ModRM) && c->modrm_mod == 3) {
1094 c->src.type = OP_REG;
1095 c->src.val = c->modrm_val;
1096 c->src.ptr = c->modrm_ptr;
1097 break;
1098 }
1099 c->src.type = OP_MEM;
1100 c->src.ptr = (unsigned long *)c->modrm_ea;
1101 c->src.val = 0;
1102 break;
1103 case SrcImm:
1104 case SrcImmU:
1105 c->src.type = OP_IMM;
1106 c->src.ptr = (unsigned long *)c->eip;
1107 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1108 if (c->src.bytes == 8)
1109 c->src.bytes = 4;
1110 /* NB. Immediates are sign-extended as necessary. */
1111 switch (c->src.bytes) {
1112 case 1:
1113 c->src.val = insn_fetch(s8, 1, c->eip);
1114 break;
1115 case 2:
1116 c->src.val = insn_fetch(s16, 2, c->eip);
1117 break;
1118 case 4:
1119 c->src.val = insn_fetch(s32, 4, c->eip);
1120 break;
1121 }
1122 if ((c->d & SrcMask) == SrcImmU) {
1123 switch (c->src.bytes) {
1124 case 1:
1125 c->src.val &= 0xff;
1126 break;
1127 case 2:
1128 c->src.val &= 0xffff;
1129 break;
1130 case 4:
1131 c->src.val &= 0xffffffff;
1132 break;
1133 }
1134 }
1135 break;
1136 case SrcImmByte:
1137 case SrcImmUByte:
1138 c->src.type = OP_IMM;
1139 c->src.ptr = (unsigned long *)c->eip;
1140 c->src.bytes = 1;
1141 if ((c->d & SrcMask) == SrcImmByte)
1142 c->src.val = insn_fetch(s8, 1, c->eip);
1143 else
1144 c->src.val = insn_fetch(u8, 1, c->eip);
1145 break;
1146 case SrcOne:
1147 c->src.bytes = 1;
1148 c->src.val = 1;
1149 break;
1150 case SrcSI:
1151 c->src.type = OP_MEM;
1152 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1153 c->src.ptr = (unsigned long *)
1154 register_address(c, seg_override_base(ctxt, c),
1155 c->regs[VCPU_REGS_RSI]);
1156 c->src.val = 0;
1157 break;
1158 }
1159
1160 /*
1161 * Decode and fetch the second source operand: register, memory
1162 * or immediate.
1163 */
1164 switch (c->d & Src2Mask) {
1165 case Src2None:
1166 break;
1167 case Src2CL:
1168 c->src2.bytes = 1;
1169 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1170 break;
1171 case Src2ImmByte:
1172 c->src2.type = OP_IMM;
1173 c->src2.ptr = (unsigned long *)c->eip;
1174 c->src2.bytes = 1;
1175 c->src2.val = insn_fetch(u8, 1, c->eip);
1176 break;
1177 case Src2Imm16:
1178 c->src2.type = OP_IMM;
1179 c->src2.ptr = (unsigned long *)c->eip;
1180 c->src2.bytes = 2;
1181 c->src2.val = insn_fetch(u16, 2, c->eip);
1182 break;
1183 case Src2One:
1184 c->src2.bytes = 1;
1185 c->src2.val = 1;
1186 break;
1187 case Src2Mem16:
1188 c->src2.type = OP_MEM;
1189 c->src2.bytes = 2;
1190 c->src2.ptr = (unsigned long *)(c->modrm_ea + c->src.bytes);
1191 c->src2.val = 0;
1192 break;
1193 }
1194
1195 /* Decode and fetch the destination operand: register or memory. */
1196 switch (c->d & DstMask) {
1197 case ImplicitOps:
1198 /* Special instructions do their own operand decoding. */
1199 return 0;
1200 case DstReg:
1201 decode_register_operand(&c->dst, c,
1202 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
1203 break;
1204 case DstMem:
1205 if ((c->d & ModRM) && c->modrm_mod == 3) {
1206 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1207 c->dst.type = OP_REG;
1208 c->dst.val = c->dst.orig_val = c->modrm_val;
1209 c->dst.ptr = c->modrm_ptr;
1210 break;
1211 }
1212 c->dst.type = OP_MEM;
1213 c->dst.ptr = (unsigned long *)c->modrm_ea;
1214 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1215 c->dst.val = 0;
1216 if (c->d & BitOp) {
1217 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1218
1219 c->dst.ptr = (void *)c->dst.ptr +
1220 (c->src.val & mask) / 8;
1221 }
1222 break;
1223 case DstAcc:
1224 c->dst.type = OP_REG;
1225 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1226 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1227 switch (c->dst.bytes) {
1228 case 1:
1229 c->dst.val = *(u8 *)c->dst.ptr;
1230 break;
1231 case 2:
1232 c->dst.val = *(u16 *)c->dst.ptr;
1233 break;
1234 case 4:
1235 c->dst.val = *(u32 *)c->dst.ptr;
1236 break;
1237 case 8:
1238 c->dst.val = *(u64 *)c->dst.ptr;
1239 break;
1240 }
1241 c->dst.orig_val = c->dst.val;
1242 break;
1243 case DstDI:
1244 c->dst.type = OP_MEM;
1245 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1246 c->dst.ptr = (unsigned long *)
1247 register_address(c, es_base(ctxt),
1248 c->regs[VCPU_REGS_RDI]);
1249 c->dst.val = 0;
1250 break;
1251 }
1252
1253 done:
1254 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1255 }
1256
1257 static u32 desc_limit_scaled(struct desc_struct *desc)
1258 {
1259 u32 limit = get_desc_limit(desc);
1260
1261 return desc->g ? (limit << 12) | 0xfff : limit;
1262 }
1263
1264 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1265 struct x86_emulate_ops *ops,
1266 u16 selector, struct desc_ptr *dt)
1267 {
1268 if (selector & 1 << 2) {
1269 struct desc_struct desc;
1270 memset (dt, 0, sizeof *dt);
1271 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1272 return;
1273
1274 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1275 dt->address = get_desc_base(&desc);
1276 } else
1277 ops->get_gdt(dt, ctxt->vcpu);
1278 }
1279
1280 /* allowed just for 8 bytes segments */
1281 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1282 struct x86_emulate_ops *ops,
1283 u16 selector, struct desc_struct *desc)
1284 {
1285 struct desc_ptr dt;
1286 u16 index = selector >> 3;
1287 int ret;
1288 u32 err;
1289 ulong addr;
1290
1291 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1292
1293 if (dt.size < index * 8 + 7) {
1294 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
1295 return X86EMUL_PROPAGATE_FAULT;
1296 }
1297 addr = dt.address + index * 8;
1298 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1299 if (ret == X86EMUL_PROPAGATE_FAULT)
1300 kvm_inject_page_fault(ctxt->vcpu, addr, err);
1301
1302 return ret;
1303 }
1304
1305 /* allowed just for 8 bytes segments */
1306 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1307 struct x86_emulate_ops *ops,
1308 u16 selector, struct desc_struct *desc)
1309 {
1310 struct desc_ptr dt;
1311 u16 index = selector >> 3;
1312 u32 err;
1313 ulong addr;
1314 int ret;
1315
1316 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1317
1318 if (dt.size < index * 8 + 7) {
1319 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
1320 return X86EMUL_PROPAGATE_FAULT;
1321 }
1322
1323 addr = dt.address + index * 8;
1324 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1325 if (ret == X86EMUL_PROPAGATE_FAULT)
1326 kvm_inject_page_fault(ctxt->vcpu, addr, err);
1327
1328 return ret;
1329 }
1330
1331 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1332 struct x86_emulate_ops *ops,
1333 u16 selector, int seg)
1334 {
1335 struct desc_struct seg_desc;
1336 u8 dpl, rpl, cpl;
1337 unsigned err_vec = GP_VECTOR;
1338 u32 err_code = 0;
1339 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1340 int ret;
1341
1342 memset(&seg_desc, 0, sizeof seg_desc);
1343
1344 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1345 || ctxt->mode == X86EMUL_MODE_REAL) {
1346 /* set real mode segment descriptor */
1347 set_desc_base(&seg_desc, selector << 4);
1348 set_desc_limit(&seg_desc, 0xffff);
1349 seg_desc.type = 3;
1350 seg_desc.p = 1;
1351 seg_desc.s = 1;
1352 goto load;
1353 }
1354
1355 /* NULL selector is not valid for TR, CS and SS */
1356 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1357 && null_selector)
1358 goto exception;
1359
1360 /* TR should be in GDT only */
1361 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1362 goto exception;
1363
1364 if (null_selector) /* for NULL selector skip all following checks */
1365 goto load;
1366
1367 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1368 if (ret != X86EMUL_CONTINUE)
1369 return ret;
1370
1371 err_code = selector & 0xfffc;
1372 err_vec = GP_VECTOR;
1373
1374 /* can't load system descriptor into segment selecor */
1375 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1376 goto exception;
1377
1378 if (!seg_desc.p) {
1379 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1380 goto exception;
1381 }
1382
1383 rpl = selector & 3;
1384 dpl = seg_desc.dpl;
1385 cpl = ops->cpl(ctxt->vcpu);
1386
1387 switch (seg) {
1388 case VCPU_SREG_SS:
1389 /*
1390 * segment is not a writable data segment or segment
1391 * selector's RPL != CPL or segment selector's RPL != CPL
1392 */
1393 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1394 goto exception;
1395 break;
1396 case VCPU_SREG_CS:
1397 if (!(seg_desc.type & 8))
1398 goto exception;
1399
1400 if (seg_desc.type & 4) {
1401 /* conforming */
1402 if (dpl > cpl)
1403 goto exception;
1404 } else {
1405 /* nonconforming */
1406 if (rpl > cpl || dpl != cpl)
1407 goto exception;
1408 }
1409 /* CS(RPL) <- CPL */
1410 selector = (selector & 0xfffc) | cpl;
1411 break;
1412 case VCPU_SREG_TR:
1413 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1414 goto exception;
1415 break;
1416 case VCPU_SREG_LDTR:
1417 if (seg_desc.s || seg_desc.type != 2)
1418 goto exception;
1419 break;
1420 default: /* DS, ES, FS, or GS */
1421 /*
1422 * segment is not a data or readable code segment or
1423 * ((segment is a data or nonconforming code segment)
1424 * and (both RPL and CPL > DPL))
1425 */
1426 if ((seg_desc.type & 0xa) == 0x8 ||
1427 (((seg_desc.type & 0xc) != 0xc) &&
1428 (rpl > dpl && cpl > dpl)))
1429 goto exception;
1430 break;
1431 }
1432
1433 if (seg_desc.s) {
1434 /* mark segment as accessed */
1435 seg_desc.type |= 1;
1436 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1437 if (ret != X86EMUL_CONTINUE)
1438 return ret;
1439 }
1440 load:
1441 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1442 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1443 return X86EMUL_CONTINUE;
1444 exception:
1445 kvm_queue_exception_e(ctxt->vcpu, err_vec, err_code);
1446 return X86EMUL_PROPAGATE_FAULT;
1447 }
1448
1449 static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1450 {
1451 struct decode_cache *c = &ctxt->decode;
1452
1453 c->dst.type = OP_MEM;
1454 c->dst.bytes = c->op_bytes;
1455 c->dst.val = c->src.val;
1456 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1457 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
1458 c->regs[VCPU_REGS_RSP]);
1459 }
1460
1461 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1462 struct x86_emulate_ops *ops,
1463 void *dest, int len)
1464 {
1465 struct decode_cache *c = &ctxt->decode;
1466 int rc;
1467
1468 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1469 c->regs[VCPU_REGS_RSP]),
1470 dest, len, ctxt->vcpu);
1471 if (rc != X86EMUL_CONTINUE)
1472 return rc;
1473
1474 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1475 return rc;
1476 }
1477
1478 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1479 struct x86_emulate_ops *ops,
1480 void *dest, int len)
1481 {
1482 int rc;
1483 unsigned long val, change_mask;
1484 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1485 int cpl = ops->cpl(ctxt->vcpu);
1486
1487 rc = emulate_pop(ctxt, ops, &val, len);
1488 if (rc != X86EMUL_CONTINUE)
1489 return rc;
1490
1491 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1492 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1493
1494 switch(ctxt->mode) {
1495 case X86EMUL_MODE_PROT64:
1496 case X86EMUL_MODE_PROT32:
1497 case X86EMUL_MODE_PROT16:
1498 if (cpl == 0)
1499 change_mask |= EFLG_IOPL;
1500 if (cpl <= iopl)
1501 change_mask |= EFLG_IF;
1502 break;
1503 case X86EMUL_MODE_VM86:
1504 if (iopl < 3) {
1505 kvm_inject_gp(ctxt->vcpu, 0);
1506 return X86EMUL_PROPAGATE_FAULT;
1507 }
1508 change_mask |= EFLG_IF;
1509 break;
1510 default: /* real mode */
1511 change_mask |= (EFLG_IOPL | EFLG_IF);
1512 break;
1513 }
1514
1515 *(unsigned long *)dest =
1516 (ctxt->eflags & ~change_mask) | (val & change_mask);
1517
1518 return rc;
1519 }
1520
1521 static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1522 {
1523 struct decode_cache *c = &ctxt->decode;
1524 struct kvm_segment segment;
1525
1526 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
1527
1528 c->src.val = segment.selector;
1529 emulate_push(ctxt);
1530 }
1531
1532 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1533 struct x86_emulate_ops *ops, int seg)
1534 {
1535 struct decode_cache *c = &ctxt->decode;
1536 unsigned long selector;
1537 int rc;
1538
1539 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1540 if (rc != X86EMUL_CONTINUE)
1541 return rc;
1542
1543 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1544 return rc;
1545 }
1546
1547 static void emulate_pusha(struct x86_emulate_ctxt *ctxt)
1548 {
1549 struct decode_cache *c = &ctxt->decode;
1550 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1551 int reg = VCPU_REGS_RAX;
1552
1553 while (reg <= VCPU_REGS_RDI) {
1554 (reg == VCPU_REGS_RSP) ?
1555 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1556
1557 emulate_push(ctxt);
1558 ++reg;
1559 }
1560 }
1561
1562 static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1563 struct x86_emulate_ops *ops)
1564 {
1565 struct decode_cache *c = &ctxt->decode;
1566 int rc = X86EMUL_CONTINUE;
1567 int reg = VCPU_REGS_RDI;
1568
1569 while (reg >= VCPU_REGS_RAX) {
1570 if (reg == VCPU_REGS_RSP) {
1571 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1572 c->op_bytes);
1573 --reg;
1574 }
1575
1576 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1577 if (rc != X86EMUL_CONTINUE)
1578 break;
1579 --reg;
1580 }
1581 return rc;
1582 }
1583
1584 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1585 struct x86_emulate_ops *ops)
1586 {
1587 struct decode_cache *c = &ctxt->decode;
1588
1589 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1590 }
1591
1592 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1593 {
1594 struct decode_cache *c = &ctxt->decode;
1595 switch (c->modrm_reg) {
1596 case 0: /* rol */
1597 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1598 break;
1599 case 1: /* ror */
1600 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1601 break;
1602 case 2: /* rcl */
1603 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1604 break;
1605 case 3: /* rcr */
1606 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1607 break;
1608 case 4: /* sal/shl */
1609 case 6: /* sal/shl */
1610 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1611 break;
1612 case 5: /* shr */
1613 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1614 break;
1615 case 7: /* sar */
1616 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1617 break;
1618 }
1619 }
1620
1621 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1622 struct x86_emulate_ops *ops)
1623 {
1624 struct decode_cache *c = &ctxt->decode;
1625
1626 switch (c->modrm_reg) {
1627 case 0 ... 1: /* test */
1628 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1629 break;
1630 case 2: /* not */
1631 c->dst.val = ~c->dst.val;
1632 break;
1633 case 3: /* neg */
1634 emulate_1op("neg", c->dst, ctxt->eflags);
1635 break;
1636 default:
1637 return 0;
1638 }
1639 return 1;
1640 }
1641
1642 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1643 struct x86_emulate_ops *ops)
1644 {
1645 struct decode_cache *c = &ctxt->decode;
1646
1647 switch (c->modrm_reg) {
1648 case 0: /* inc */
1649 emulate_1op("inc", c->dst, ctxt->eflags);
1650 break;
1651 case 1: /* dec */
1652 emulate_1op("dec", c->dst, ctxt->eflags);
1653 break;
1654 case 2: /* call near abs */ {
1655 long int old_eip;
1656 old_eip = c->eip;
1657 c->eip = c->src.val;
1658 c->src.val = old_eip;
1659 emulate_push(ctxt);
1660 break;
1661 }
1662 case 4: /* jmp abs */
1663 c->eip = c->src.val;
1664 break;
1665 case 6: /* push */
1666 emulate_push(ctxt);
1667 break;
1668 }
1669 return X86EMUL_CONTINUE;
1670 }
1671
1672 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1673 struct x86_emulate_ops *ops)
1674 {
1675 struct decode_cache *c = &ctxt->decode;
1676 u64 old, new;
1677 int rc;
1678
1679 rc = ops->read_emulated(c->modrm_ea, &old, 8, ctxt->vcpu);
1680 if (rc != X86EMUL_CONTINUE)
1681 return rc;
1682
1683 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1684 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1685
1686 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1687 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1688 ctxt->eflags &= ~EFLG_ZF;
1689
1690 } else {
1691 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1692 (u32) c->regs[VCPU_REGS_RBX];
1693
1694 rc = ops->cmpxchg_emulated(c->modrm_ea, &old, &new, 8, ctxt->vcpu);
1695 if (rc != X86EMUL_CONTINUE)
1696 return rc;
1697 ctxt->eflags |= EFLG_ZF;
1698 }
1699 return X86EMUL_CONTINUE;
1700 }
1701
1702 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1703 struct x86_emulate_ops *ops)
1704 {
1705 struct decode_cache *c = &ctxt->decode;
1706 int rc;
1707 unsigned long cs;
1708
1709 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1710 if (rc != X86EMUL_CONTINUE)
1711 return rc;
1712 if (c->op_bytes == 4)
1713 c->eip = (u32)c->eip;
1714 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1715 if (rc != X86EMUL_CONTINUE)
1716 return rc;
1717 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1718 return rc;
1719 }
1720
1721 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1722 struct x86_emulate_ops *ops)
1723 {
1724 int rc;
1725 struct decode_cache *c = &ctxt->decode;
1726
1727 switch (c->dst.type) {
1728 case OP_REG:
1729 /* The 4-byte case *is* correct:
1730 * in 64-bit mode we zero-extend.
1731 */
1732 switch (c->dst.bytes) {
1733 case 1:
1734 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1735 break;
1736 case 2:
1737 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1738 break;
1739 case 4:
1740 *c->dst.ptr = (u32)c->dst.val;
1741 break; /* 64b: zero-ext */
1742 case 8:
1743 *c->dst.ptr = c->dst.val;
1744 break;
1745 }
1746 break;
1747 case OP_MEM:
1748 if (c->lock_prefix)
1749 rc = ops->cmpxchg_emulated(
1750 (unsigned long)c->dst.ptr,
1751 &c->dst.orig_val,
1752 &c->dst.val,
1753 c->dst.bytes,
1754 ctxt->vcpu);
1755 else
1756 rc = ops->write_emulated(
1757 (unsigned long)c->dst.ptr,
1758 &c->dst.val,
1759 c->dst.bytes,
1760 ctxt->vcpu);
1761 if (rc != X86EMUL_CONTINUE)
1762 return rc;
1763 break;
1764 case OP_NONE:
1765 /* no writeback */
1766 break;
1767 default:
1768 break;
1769 }
1770 return X86EMUL_CONTINUE;
1771 }
1772
1773 static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
1774 {
1775 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1776 /*
1777 * an sti; sti; sequence only disable interrupts for the first
1778 * instruction. So, if the last instruction, be it emulated or
1779 * not, left the system with the INT_STI flag enabled, it
1780 * means that the last instruction is an sti. We should not
1781 * leave the flag on in this case. The same goes for mov ss
1782 */
1783 if (!(int_shadow & mask))
1784 ctxt->interruptibility = mask;
1785 }
1786
1787 static inline void
1788 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1789 struct kvm_segment *cs, struct kvm_segment *ss)
1790 {
1791 memset(cs, 0, sizeof(struct kvm_segment));
1792 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
1793 memset(ss, 0, sizeof(struct kvm_segment));
1794
1795 cs->l = 0; /* will be adjusted later */
1796 cs->base = 0; /* flat segment */
1797 cs->g = 1; /* 4kb granularity */
1798 cs->limit = 0xffffffff; /* 4GB limit */
1799 cs->type = 0x0b; /* Read, Execute, Accessed */
1800 cs->s = 1;
1801 cs->dpl = 0; /* will be adjusted later */
1802 cs->present = 1;
1803 cs->db = 1;
1804
1805 ss->unusable = 0;
1806 ss->base = 0; /* flat segment */
1807 ss->limit = 0xffffffff; /* 4GB limit */
1808 ss->g = 1; /* 4kb granularity */
1809 ss->s = 1;
1810 ss->type = 0x03; /* Read/Write, Accessed */
1811 ss->db = 1; /* 32bit stack segment */
1812 ss->dpl = 0;
1813 ss->present = 1;
1814 }
1815
1816 static int
1817 emulate_syscall(struct x86_emulate_ctxt *ctxt)
1818 {
1819 struct decode_cache *c = &ctxt->decode;
1820 struct kvm_segment cs, ss;
1821 u64 msr_data;
1822
1823 /* syscall is not available in real mode */
1824 if (ctxt->mode == X86EMUL_MODE_REAL ||
1825 ctxt->mode == X86EMUL_MODE_VM86) {
1826 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1827 return X86EMUL_PROPAGATE_FAULT;
1828 }
1829
1830 setup_syscalls_segments(ctxt, &cs, &ss);
1831
1832 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1833 msr_data >>= 32;
1834 cs.selector = (u16)(msr_data & 0xfffc);
1835 ss.selector = (u16)(msr_data + 8);
1836
1837 if (is_long_mode(ctxt->vcpu)) {
1838 cs.db = 0;
1839 cs.l = 1;
1840 }
1841 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1842 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1843
1844 c->regs[VCPU_REGS_RCX] = c->eip;
1845 if (is_long_mode(ctxt->vcpu)) {
1846 #ifdef CONFIG_X86_64
1847 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1848
1849 kvm_x86_ops->get_msr(ctxt->vcpu,
1850 ctxt->mode == X86EMUL_MODE_PROT64 ?
1851 MSR_LSTAR : MSR_CSTAR, &msr_data);
1852 c->eip = msr_data;
1853
1854 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1855 ctxt->eflags &= ~(msr_data | EFLG_RF);
1856 #endif
1857 } else {
1858 /* legacy mode */
1859 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1860 c->eip = (u32)msr_data;
1861
1862 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1863 }
1864
1865 return X86EMUL_CONTINUE;
1866 }
1867
1868 static int
1869 emulate_sysenter(struct x86_emulate_ctxt *ctxt)
1870 {
1871 struct decode_cache *c = &ctxt->decode;
1872 struct kvm_segment cs, ss;
1873 u64 msr_data;
1874
1875 /* inject #GP if in real mode */
1876 if (ctxt->mode == X86EMUL_MODE_REAL) {
1877 kvm_inject_gp(ctxt->vcpu, 0);
1878 return X86EMUL_PROPAGATE_FAULT;
1879 }
1880
1881 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1882 * Therefore, we inject an #UD.
1883 */
1884 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1885 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1886 return X86EMUL_PROPAGATE_FAULT;
1887 }
1888
1889 setup_syscalls_segments(ctxt, &cs, &ss);
1890
1891 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1892 switch (ctxt->mode) {
1893 case X86EMUL_MODE_PROT32:
1894 if ((msr_data & 0xfffc) == 0x0) {
1895 kvm_inject_gp(ctxt->vcpu, 0);
1896 return X86EMUL_PROPAGATE_FAULT;
1897 }
1898 break;
1899 case X86EMUL_MODE_PROT64:
1900 if (msr_data == 0x0) {
1901 kvm_inject_gp(ctxt->vcpu, 0);
1902 return X86EMUL_PROPAGATE_FAULT;
1903 }
1904 break;
1905 }
1906
1907 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1908 cs.selector = (u16)msr_data;
1909 cs.selector &= ~SELECTOR_RPL_MASK;
1910 ss.selector = cs.selector + 8;
1911 ss.selector &= ~SELECTOR_RPL_MASK;
1912 if (ctxt->mode == X86EMUL_MODE_PROT64
1913 || is_long_mode(ctxt->vcpu)) {
1914 cs.db = 0;
1915 cs.l = 1;
1916 }
1917
1918 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1919 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1920
1921 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1922 c->eip = msr_data;
1923
1924 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1925 c->regs[VCPU_REGS_RSP] = msr_data;
1926
1927 return X86EMUL_CONTINUE;
1928 }
1929
1930 static int
1931 emulate_sysexit(struct x86_emulate_ctxt *ctxt)
1932 {
1933 struct decode_cache *c = &ctxt->decode;
1934 struct kvm_segment cs, ss;
1935 u64 msr_data;
1936 int usermode;
1937
1938 /* inject #GP if in real mode or Virtual 8086 mode */
1939 if (ctxt->mode == X86EMUL_MODE_REAL ||
1940 ctxt->mode == X86EMUL_MODE_VM86) {
1941 kvm_inject_gp(ctxt->vcpu, 0);
1942 return X86EMUL_PROPAGATE_FAULT;
1943 }
1944
1945 setup_syscalls_segments(ctxt, &cs, &ss);
1946
1947 if ((c->rex_prefix & 0x8) != 0x0)
1948 usermode = X86EMUL_MODE_PROT64;
1949 else
1950 usermode = X86EMUL_MODE_PROT32;
1951
1952 cs.dpl = 3;
1953 ss.dpl = 3;
1954 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1955 switch (usermode) {
1956 case X86EMUL_MODE_PROT32:
1957 cs.selector = (u16)(msr_data + 16);
1958 if ((msr_data & 0xfffc) == 0x0) {
1959 kvm_inject_gp(ctxt->vcpu, 0);
1960 return X86EMUL_PROPAGATE_FAULT;
1961 }
1962 ss.selector = (u16)(msr_data + 24);
1963 break;
1964 case X86EMUL_MODE_PROT64:
1965 cs.selector = (u16)(msr_data + 32);
1966 if (msr_data == 0x0) {
1967 kvm_inject_gp(ctxt->vcpu, 0);
1968 return X86EMUL_PROPAGATE_FAULT;
1969 }
1970 ss.selector = cs.selector + 8;
1971 cs.db = 0;
1972 cs.l = 1;
1973 break;
1974 }
1975 cs.selector |= SELECTOR_RPL_MASK;
1976 ss.selector |= SELECTOR_RPL_MASK;
1977
1978 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1979 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1980
1981 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
1982 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
1983
1984 return X86EMUL_CONTINUE;
1985 }
1986
1987 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1988 struct x86_emulate_ops *ops)
1989 {
1990 int iopl;
1991 if (ctxt->mode == X86EMUL_MODE_REAL)
1992 return false;
1993 if (ctxt->mode == X86EMUL_MODE_VM86)
1994 return true;
1995 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1996 return ops->cpl(ctxt->vcpu) > iopl;
1997 }
1998
1999 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2000 struct x86_emulate_ops *ops,
2001 u16 port, u16 len)
2002 {
2003 struct kvm_segment tr_seg;
2004 int r;
2005 u16 io_bitmap_ptr;
2006 u8 perm, bit_idx = port & 0x7;
2007 unsigned mask = (1 << len) - 1;
2008
2009 kvm_get_segment(ctxt->vcpu, &tr_seg, VCPU_SREG_TR);
2010 if (tr_seg.unusable)
2011 return false;
2012 if (tr_seg.limit < 103)
2013 return false;
2014 r = ops->read_std(tr_seg.base + 102, &io_bitmap_ptr, 2, ctxt->vcpu,
2015 NULL);
2016 if (r != X86EMUL_CONTINUE)
2017 return false;
2018 if (io_bitmap_ptr + port/8 > tr_seg.limit)
2019 return false;
2020 r = ops->read_std(tr_seg.base + io_bitmap_ptr + port/8, &perm, 1,
2021 ctxt->vcpu, NULL);
2022 if (r != X86EMUL_CONTINUE)
2023 return false;
2024 if ((perm >> bit_idx) & mask)
2025 return false;
2026 return true;
2027 }
2028
2029 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2030 struct x86_emulate_ops *ops,
2031 u16 port, u16 len)
2032 {
2033 if (emulator_bad_iopl(ctxt, ops))
2034 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2035 return false;
2036 return true;
2037 }
2038
2039 static u32 get_cached_descriptor_base(struct x86_emulate_ctxt *ctxt,
2040 struct x86_emulate_ops *ops,
2041 int seg)
2042 {
2043 struct desc_struct desc;
2044 if (ops->get_cached_descriptor(&desc, seg, ctxt->vcpu))
2045 return get_desc_base(&desc);
2046 else
2047 return ~0;
2048 }
2049
2050 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2051 struct x86_emulate_ops *ops,
2052 struct tss_segment_16 *tss)
2053 {
2054 struct decode_cache *c = &ctxt->decode;
2055
2056 tss->ip = c->eip;
2057 tss->flag = ctxt->eflags;
2058 tss->ax = c->regs[VCPU_REGS_RAX];
2059 tss->cx = c->regs[VCPU_REGS_RCX];
2060 tss->dx = c->regs[VCPU_REGS_RDX];
2061 tss->bx = c->regs[VCPU_REGS_RBX];
2062 tss->sp = c->regs[VCPU_REGS_RSP];
2063 tss->bp = c->regs[VCPU_REGS_RBP];
2064 tss->si = c->regs[VCPU_REGS_RSI];
2065 tss->di = c->regs[VCPU_REGS_RDI];
2066
2067 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2068 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2069 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2070 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2071 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2072 }
2073
2074 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2075 struct x86_emulate_ops *ops,
2076 struct tss_segment_16 *tss)
2077 {
2078 struct decode_cache *c = &ctxt->decode;
2079 int ret;
2080
2081 c->eip = tss->ip;
2082 ctxt->eflags = tss->flag | 2;
2083 c->regs[VCPU_REGS_RAX] = tss->ax;
2084 c->regs[VCPU_REGS_RCX] = tss->cx;
2085 c->regs[VCPU_REGS_RDX] = tss->dx;
2086 c->regs[VCPU_REGS_RBX] = tss->bx;
2087 c->regs[VCPU_REGS_RSP] = tss->sp;
2088 c->regs[VCPU_REGS_RBP] = tss->bp;
2089 c->regs[VCPU_REGS_RSI] = tss->si;
2090 c->regs[VCPU_REGS_RDI] = tss->di;
2091
2092 /*
2093 * SDM says that segment selectors are loaded before segment
2094 * descriptors
2095 */
2096 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2097 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2098 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2099 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2100 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2101
2102 /*
2103 * Now load segment descriptors. If fault happenes at this stage
2104 * it is handled in a context of new task
2105 */
2106 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2107 if (ret != X86EMUL_CONTINUE)
2108 return ret;
2109 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2110 if (ret != X86EMUL_CONTINUE)
2111 return ret;
2112 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2113 if (ret != X86EMUL_CONTINUE)
2114 return ret;
2115 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2116 if (ret != X86EMUL_CONTINUE)
2117 return ret;
2118 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2119 if (ret != X86EMUL_CONTINUE)
2120 return ret;
2121
2122 return X86EMUL_CONTINUE;
2123 }
2124
2125 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2126 struct x86_emulate_ops *ops,
2127 u16 tss_selector, u16 old_tss_sel,
2128 ulong old_tss_base, struct desc_struct *new_desc)
2129 {
2130 struct tss_segment_16 tss_seg;
2131 int ret;
2132 u32 err, new_tss_base = get_desc_base(new_desc);
2133
2134 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2135 &err);
2136 if (ret == X86EMUL_PROPAGATE_FAULT) {
2137 /* FIXME: need to provide precise fault address */
2138 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2139 return ret;
2140 }
2141
2142 save_state_to_tss16(ctxt, ops, &tss_seg);
2143
2144 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2145 &err);
2146 if (ret == X86EMUL_PROPAGATE_FAULT) {
2147 /* FIXME: need to provide precise fault address */
2148 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2149 return ret;
2150 }
2151
2152 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2153 &err);
2154 if (ret == X86EMUL_PROPAGATE_FAULT) {
2155 /* FIXME: need to provide precise fault address */
2156 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2157 return ret;
2158 }
2159
2160 if (old_tss_sel != 0xffff) {
2161 tss_seg.prev_task_link = old_tss_sel;
2162
2163 ret = ops->write_std(new_tss_base,
2164 &tss_seg.prev_task_link,
2165 sizeof tss_seg.prev_task_link,
2166 ctxt->vcpu, &err);
2167 if (ret == X86EMUL_PROPAGATE_FAULT) {
2168 /* FIXME: need to provide precise fault address */
2169 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2170 return ret;
2171 }
2172 }
2173
2174 return load_state_from_tss16(ctxt, ops, &tss_seg);
2175 }
2176
2177 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2178 struct x86_emulate_ops *ops,
2179 struct tss_segment_32 *tss)
2180 {
2181 struct decode_cache *c = &ctxt->decode;
2182
2183 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2184 tss->eip = c->eip;
2185 tss->eflags = ctxt->eflags;
2186 tss->eax = c->regs[VCPU_REGS_RAX];
2187 tss->ecx = c->regs[VCPU_REGS_RCX];
2188 tss->edx = c->regs[VCPU_REGS_RDX];
2189 tss->ebx = c->regs[VCPU_REGS_RBX];
2190 tss->esp = c->regs[VCPU_REGS_RSP];
2191 tss->ebp = c->regs[VCPU_REGS_RBP];
2192 tss->esi = c->regs[VCPU_REGS_RSI];
2193 tss->edi = c->regs[VCPU_REGS_RDI];
2194
2195 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2196 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2197 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2198 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2199 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2200 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2201 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2202 }
2203
2204 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2205 struct x86_emulate_ops *ops,
2206 struct tss_segment_32 *tss)
2207 {
2208 struct decode_cache *c = &ctxt->decode;
2209 int ret;
2210
2211 ops->set_cr(3, tss->cr3, ctxt->vcpu);
2212 c->eip = tss->eip;
2213 ctxt->eflags = tss->eflags | 2;
2214 c->regs[VCPU_REGS_RAX] = tss->eax;
2215 c->regs[VCPU_REGS_RCX] = tss->ecx;
2216 c->regs[VCPU_REGS_RDX] = tss->edx;
2217 c->regs[VCPU_REGS_RBX] = tss->ebx;
2218 c->regs[VCPU_REGS_RSP] = tss->esp;
2219 c->regs[VCPU_REGS_RBP] = tss->ebp;
2220 c->regs[VCPU_REGS_RSI] = tss->esi;
2221 c->regs[VCPU_REGS_RDI] = tss->edi;
2222
2223 /*
2224 * SDM says that segment selectors are loaded before segment
2225 * descriptors
2226 */
2227 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2228 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2229 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2230 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2231 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2232 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2233 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2234
2235 /*
2236 * Now load segment descriptors. If fault happenes at this stage
2237 * it is handled in a context of new task
2238 */
2239 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2240 if (ret != X86EMUL_CONTINUE)
2241 return ret;
2242 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2243 if (ret != X86EMUL_CONTINUE)
2244 return ret;
2245 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2246 if (ret != X86EMUL_CONTINUE)
2247 return ret;
2248 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2249 if (ret != X86EMUL_CONTINUE)
2250 return ret;
2251 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2252 if (ret != X86EMUL_CONTINUE)
2253 return ret;
2254 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2255 if (ret != X86EMUL_CONTINUE)
2256 return ret;
2257 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2258 if (ret != X86EMUL_CONTINUE)
2259 return ret;
2260
2261 return X86EMUL_CONTINUE;
2262 }
2263
2264 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2265 struct x86_emulate_ops *ops,
2266 u16 tss_selector, u16 old_tss_sel,
2267 ulong old_tss_base, struct desc_struct *new_desc)
2268 {
2269 struct tss_segment_32 tss_seg;
2270 int ret;
2271 u32 err, new_tss_base = get_desc_base(new_desc);
2272
2273 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2274 &err);
2275 if (ret == X86EMUL_PROPAGATE_FAULT) {
2276 /* FIXME: need to provide precise fault address */
2277 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2278 return ret;
2279 }
2280
2281 save_state_to_tss32(ctxt, ops, &tss_seg);
2282
2283 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2284 &err);
2285 if (ret == X86EMUL_PROPAGATE_FAULT) {
2286 /* FIXME: need to provide precise fault address */
2287 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2288 return ret;
2289 }
2290
2291 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2292 &err);
2293 if (ret == X86EMUL_PROPAGATE_FAULT) {
2294 /* FIXME: need to provide precise fault address */
2295 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2296 return ret;
2297 }
2298
2299 if (old_tss_sel != 0xffff) {
2300 tss_seg.prev_task_link = old_tss_sel;
2301
2302 ret = ops->write_std(new_tss_base,
2303 &tss_seg.prev_task_link,
2304 sizeof tss_seg.prev_task_link,
2305 ctxt->vcpu, &err);
2306 if (ret == X86EMUL_PROPAGATE_FAULT) {
2307 /* FIXME: need to provide precise fault address */
2308 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2309 return ret;
2310 }
2311 }
2312
2313 return load_state_from_tss32(ctxt, ops, &tss_seg);
2314 }
2315
2316 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2317 struct x86_emulate_ops *ops,
2318 u16 tss_selector, int reason)
2319 {
2320 struct desc_struct curr_tss_desc, next_tss_desc;
2321 int ret;
2322 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2323 ulong old_tss_base =
2324 get_cached_descriptor_base(ctxt, ops, VCPU_SREG_TR);
2325 u32 desc_limit;
2326
2327 /* FIXME: old_tss_base == ~0 ? */
2328
2329 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2330 if (ret != X86EMUL_CONTINUE)
2331 return ret;
2332 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2333 if (ret != X86EMUL_CONTINUE)
2334 return ret;
2335
2336 /* FIXME: check that next_tss_desc is tss */
2337
2338 if (reason != TASK_SWITCH_IRET) {
2339 if ((tss_selector & 3) > next_tss_desc.dpl ||
2340 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
2341 kvm_inject_gp(ctxt->vcpu, 0);
2342 return X86EMUL_PROPAGATE_FAULT;
2343 }
2344 }
2345
2346 desc_limit = desc_limit_scaled(&next_tss_desc);
2347 if (!next_tss_desc.p ||
2348 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2349 desc_limit < 0x2b)) {
2350 kvm_queue_exception_e(ctxt->vcpu, TS_VECTOR,
2351 tss_selector & 0xfffc);
2352 return X86EMUL_PROPAGATE_FAULT;
2353 }
2354
2355 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2356 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2357 write_segment_descriptor(ctxt, ops, old_tss_sel,
2358 &curr_tss_desc);
2359 }
2360
2361 if (reason == TASK_SWITCH_IRET)
2362 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2363
2364 /* set back link to prev task only if NT bit is set in eflags
2365 note that old_tss_sel is not used afetr this point */
2366 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2367 old_tss_sel = 0xffff;
2368
2369 if (next_tss_desc.type & 8)
2370 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2371 old_tss_base, &next_tss_desc);
2372 else
2373 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2374 old_tss_base, &next_tss_desc);
2375
2376 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2377 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2378
2379 if (reason != TASK_SWITCH_IRET) {
2380 next_tss_desc.type |= (1 << 1); /* set busy flag */
2381 write_segment_descriptor(ctxt, ops, tss_selector,
2382 &next_tss_desc);
2383 }
2384
2385 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2386 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2387 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2388
2389 return ret;
2390 }
2391
2392 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2393 struct x86_emulate_ops *ops,
2394 u16 tss_selector, int reason)
2395 {
2396 struct decode_cache *c = &ctxt->decode;
2397 int rc;
2398
2399 memset(c, 0, sizeof(struct decode_cache));
2400 c->eip = ctxt->eip;
2401 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
2402
2403 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason);
2404
2405 if (rc == X86EMUL_CONTINUE) {
2406 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
2407 kvm_rip_write(ctxt->vcpu, c->eip);
2408 }
2409
2410 return rc;
2411 }
2412
2413 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
2414 int reg, struct operand *op)
2415 {
2416 struct decode_cache *c = &ctxt->decode;
2417 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2418
2419 register_address_increment(c, &c->regs[reg], df * op->bytes);
2420 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
2421 }
2422
2423 int
2424 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
2425 {
2426 u64 msr_data;
2427 unsigned long saved_eip = 0;
2428 struct decode_cache *c = &ctxt->decode;
2429 int rc = X86EMUL_CONTINUE;
2430
2431 ctxt->interruptibility = 0;
2432
2433 /* Shadow copy of register state. Committed on successful emulation.
2434 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
2435 * modify them.
2436 */
2437
2438 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
2439 saved_eip = c->eip;
2440
2441 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
2442 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2443 goto done;
2444 }
2445
2446 /* LOCK prefix is allowed only with some instructions */
2447 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
2448 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2449 goto done;
2450 }
2451
2452 /* Privileged instruction can be executed only in CPL=0 */
2453 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
2454 kvm_inject_gp(ctxt->vcpu, 0);
2455 goto done;
2456 }
2457
2458 if (c->rep_prefix && (c->d & String)) {
2459 /* All REP prefixes have the same first termination condition */
2460 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
2461 kvm_rip_write(ctxt->vcpu, c->eip);
2462 goto done;
2463 }
2464 /* The second termination condition only applies for REPE
2465 * and REPNE. Test if the repeat string operation prefix is
2466 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2467 * corresponding termination condition according to:
2468 * - if REPE/REPZ and ZF = 0 then done
2469 * - if REPNE/REPNZ and ZF = 1 then done
2470 */
2471 if ((c->b == 0xa6) || (c->b == 0xa7) ||
2472 (c->b == 0xae) || (c->b == 0xaf)) {
2473 if ((c->rep_prefix == REPE_PREFIX) &&
2474 ((ctxt->eflags & EFLG_ZF) == 0)) {
2475 kvm_rip_write(ctxt->vcpu, c->eip);
2476 goto done;
2477 }
2478 if ((c->rep_prefix == REPNE_PREFIX) &&
2479 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
2480 kvm_rip_write(ctxt->vcpu, c->eip);
2481 goto done;
2482 }
2483 }
2484 c->eip = ctxt->eip;
2485 }
2486
2487 if (c->src.type == OP_MEM) {
2488 rc = ops->read_emulated((unsigned long)c->src.ptr,
2489 &c->src.val,
2490 c->src.bytes,
2491 ctxt->vcpu);
2492 if (rc != X86EMUL_CONTINUE)
2493 goto done;
2494 c->src.orig_val = c->src.val;
2495 }
2496
2497 if (c->src2.type == OP_MEM) {
2498 rc = ops->read_emulated((unsigned long)c->src2.ptr,
2499 &c->src2.val,
2500 c->src2.bytes,
2501 ctxt->vcpu);
2502 if (rc != X86EMUL_CONTINUE)
2503 goto done;
2504 }
2505
2506 if ((c->d & DstMask) == ImplicitOps)
2507 goto special_insn;
2508
2509
2510 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2511 /* optimisation - avoid slow emulated read if Mov */
2512 rc = ops->read_emulated((unsigned long)c->dst.ptr, &c->dst.val,
2513 c->dst.bytes, ctxt->vcpu);
2514 if (rc != X86EMUL_CONTINUE)
2515 goto done;
2516 }
2517 c->dst.orig_val = c->dst.val;
2518
2519 special_insn:
2520
2521 if (c->twobyte)
2522 goto twobyte_insn;
2523
2524 switch (c->b) {
2525 case 0x00 ... 0x05:
2526 add: /* add */
2527 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2528 break;
2529 case 0x06: /* push es */
2530 emulate_push_sreg(ctxt, VCPU_SREG_ES);
2531 break;
2532 case 0x07: /* pop es */
2533 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
2534 if (rc != X86EMUL_CONTINUE)
2535 goto done;
2536 break;
2537 case 0x08 ... 0x0d:
2538 or: /* or */
2539 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2540 break;
2541 case 0x0e: /* push cs */
2542 emulate_push_sreg(ctxt, VCPU_SREG_CS);
2543 break;
2544 case 0x10 ... 0x15:
2545 adc: /* adc */
2546 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2547 break;
2548 case 0x16: /* push ss */
2549 emulate_push_sreg(ctxt, VCPU_SREG_SS);
2550 break;
2551 case 0x17: /* pop ss */
2552 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
2553 if (rc != X86EMUL_CONTINUE)
2554 goto done;
2555 break;
2556 case 0x18 ... 0x1d:
2557 sbb: /* sbb */
2558 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2559 break;
2560 case 0x1e: /* push ds */
2561 emulate_push_sreg(ctxt, VCPU_SREG_DS);
2562 break;
2563 case 0x1f: /* pop ds */
2564 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
2565 if (rc != X86EMUL_CONTINUE)
2566 goto done;
2567 break;
2568 case 0x20 ... 0x25:
2569 and: /* and */
2570 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2571 break;
2572 case 0x28 ... 0x2d:
2573 sub: /* sub */
2574 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2575 break;
2576 case 0x30 ... 0x35:
2577 xor: /* xor */
2578 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2579 break;
2580 case 0x38 ... 0x3d:
2581 cmp: /* cmp */
2582 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2583 break;
2584 case 0x40 ... 0x47: /* inc r16/r32 */
2585 emulate_1op("inc", c->dst, ctxt->eflags);
2586 break;
2587 case 0x48 ... 0x4f: /* dec r16/r32 */
2588 emulate_1op("dec", c->dst, ctxt->eflags);
2589 break;
2590 case 0x50 ... 0x57: /* push reg */
2591 emulate_push(ctxt);
2592 break;
2593 case 0x58 ... 0x5f: /* pop reg */
2594 pop_instruction:
2595 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
2596 if (rc != X86EMUL_CONTINUE)
2597 goto done;
2598 break;
2599 case 0x60: /* pusha */
2600 emulate_pusha(ctxt);
2601 break;
2602 case 0x61: /* popa */
2603 rc = emulate_popa(ctxt, ops);
2604 if (rc != X86EMUL_CONTINUE)
2605 goto done;
2606 break;
2607 case 0x63: /* movsxd */
2608 if (ctxt->mode != X86EMUL_MODE_PROT64)
2609 goto cannot_emulate;
2610 c->dst.val = (s32) c->src.val;
2611 break;
2612 case 0x68: /* push imm */
2613 case 0x6a: /* push imm8 */
2614 emulate_push(ctxt);
2615 break;
2616 case 0x6c: /* insb */
2617 case 0x6d: /* insw/insd */
2618 c->dst.bytes = min(c->dst.bytes, 4u);
2619 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2620 c->dst.bytes)) {
2621 kvm_inject_gp(ctxt->vcpu, 0);
2622 goto done;
2623 }
2624 if (!ops->pio_in_emulated(c->dst.bytes, c->regs[VCPU_REGS_RDX],
2625 &c->dst.val, 1, ctxt->vcpu))
2626 goto done; /* IO is needed, skip writeback */
2627 break;
2628 case 0x6e: /* outsb */
2629 case 0x6f: /* outsw/outsd */
2630 c->src.bytes = min(c->src.bytes, 4u);
2631 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2632 c->src.bytes)) {
2633 kvm_inject_gp(ctxt->vcpu, 0);
2634 goto done;
2635 }
2636 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2637 &c->src.val, 1, ctxt->vcpu);
2638
2639 c->dst.type = OP_NONE; /* nothing to writeback */
2640 break;
2641 case 0x70 ... 0x7f: /* jcc (short) */
2642 if (test_cc(c->b, ctxt->eflags))
2643 jmp_rel(c, c->src.val);
2644 break;
2645 case 0x80 ... 0x83: /* Grp1 */
2646 switch (c->modrm_reg) {
2647 case 0:
2648 goto add;
2649 case 1:
2650 goto or;
2651 case 2:
2652 goto adc;
2653 case 3:
2654 goto sbb;
2655 case 4:
2656 goto and;
2657 case 5:
2658 goto sub;
2659 case 6:
2660 goto xor;
2661 case 7:
2662 goto cmp;
2663 }
2664 break;
2665 case 0x84 ... 0x85:
2666 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
2667 break;
2668 case 0x86 ... 0x87: /* xchg */
2669 xchg:
2670 /* Write back the register source. */
2671 switch (c->dst.bytes) {
2672 case 1:
2673 *(u8 *) c->src.ptr = (u8) c->dst.val;
2674 break;
2675 case 2:
2676 *(u16 *) c->src.ptr = (u16) c->dst.val;
2677 break;
2678 case 4:
2679 *c->src.ptr = (u32) c->dst.val;
2680 break; /* 64b reg: zero-extend */
2681 case 8:
2682 *c->src.ptr = c->dst.val;
2683 break;
2684 }
2685 /*
2686 * Write back the memory destination with implicit LOCK
2687 * prefix.
2688 */
2689 c->dst.val = c->src.val;
2690 c->lock_prefix = 1;
2691 break;
2692 case 0x88 ... 0x8b: /* mov */
2693 goto mov;
2694 case 0x8c: { /* mov r/m, sreg */
2695 struct kvm_segment segreg;
2696
2697 if (c->modrm_reg <= VCPU_SREG_GS)
2698 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
2699 else {
2700 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2701 goto done;
2702 }
2703 c->dst.val = segreg.selector;
2704 break;
2705 }
2706 case 0x8d: /* lea r16/r32, m */
2707 c->dst.val = c->modrm_ea;
2708 break;
2709 case 0x8e: { /* mov seg, r/m16 */
2710 uint16_t sel;
2711
2712 sel = c->src.val;
2713
2714 if (c->modrm_reg == VCPU_SREG_CS ||
2715 c->modrm_reg > VCPU_SREG_GS) {
2716 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2717 goto done;
2718 }
2719
2720 if (c->modrm_reg == VCPU_SREG_SS)
2721 toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_MOV_SS);
2722
2723 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
2724
2725 c->dst.type = OP_NONE; /* Disable writeback. */
2726 break;
2727 }
2728 case 0x8f: /* pop (sole member of Grp1a) */
2729 rc = emulate_grp1a(ctxt, ops);
2730 if (rc != X86EMUL_CONTINUE)
2731 goto done;
2732 break;
2733 case 0x90: /* nop / xchg r8,rax */
2734 if (!(c->rex_prefix & 1)) { /* nop */
2735 c->dst.type = OP_NONE;
2736 break;
2737 }
2738 case 0x91 ... 0x97: /* xchg reg,rax */
2739 c->src.type = c->dst.type = OP_REG;
2740 c->src.bytes = c->dst.bytes = c->op_bytes;
2741 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2742 c->src.val = *(c->src.ptr);
2743 goto xchg;
2744 case 0x9c: /* pushf */
2745 c->src.val = (unsigned long) ctxt->eflags;
2746 emulate_push(ctxt);
2747 break;
2748 case 0x9d: /* popf */
2749 c->dst.type = OP_REG;
2750 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2751 c->dst.bytes = c->op_bytes;
2752 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2753 if (rc != X86EMUL_CONTINUE)
2754 goto done;
2755 break;
2756 case 0xa0 ... 0xa1: /* mov */
2757 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2758 c->dst.val = c->src.val;
2759 break;
2760 case 0xa2 ... 0xa3: /* mov */
2761 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
2762 break;
2763 case 0xa4 ... 0xa5: /* movs */
2764 goto mov;
2765 case 0xa6 ... 0xa7: /* cmps */
2766 c->dst.type = OP_NONE; /* Disable writeback. */
2767 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
2768 goto cmp;
2769 case 0xaa ... 0xab: /* stos */
2770 c->dst.val = c->regs[VCPU_REGS_RAX];
2771 break;
2772 case 0xac ... 0xad: /* lods */
2773 goto mov;
2774 case 0xae ... 0xaf: /* scas */
2775 DPRINTF("Urk! I don't handle SCAS.\n");
2776 goto cannot_emulate;
2777 case 0xb0 ... 0xbf: /* mov r, imm */
2778 goto mov;
2779 case 0xc0 ... 0xc1:
2780 emulate_grp2(ctxt);
2781 break;
2782 case 0xc3: /* ret */
2783 c->dst.type = OP_REG;
2784 c->dst.ptr = &c->eip;
2785 c->dst.bytes = c->op_bytes;
2786 goto pop_instruction;
2787 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2788 mov:
2789 c->dst.val = c->src.val;
2790 break;
2791 case 0xcb: /* ret far */
2792 rc = emulate_ret_far(ctxt, ops);
2793 if (rc != X86EMUL_CONTINUE)
2794 goto done;
2795 break;
2796 case 0xd0 ... 0xd1: /* Grp2 */
2797 c->src.val = 1;
2798 emulate_grp2(ctxt);
2799 break;
2800 case 0xd2 ... 0xd3: /* Grp2 */
2801 c->src.val = c->regs[VCPU_REGS_RCX];
2802 emulate_grp2(ctxt);
2803 break;
2804 case 0xe4: /* inb */
2805 case 0xe5: /* in */
2806 goto do_io_in;
2807 case 0xe6: /* outb */
2808 case 0xe7: /* out */
2809 goto do_io_out;
2810 case 0xe8: /* call (near) */ {
2811 long int rel = c->src.val;
2812 c->src.val = (unsigned long) c->eip;
2813 jmp_rel(c, rel);
2814 emulate_push(ctxt);
2815 break;
2816 }
2817 case 0xe9: /* jmp rel */
2818 goto jmp;
2819 case 0xea: /* jmp far */
2820 jump_far:
2821 if (load_segment_descriptor(ctxt, ops, c->src2.val,
2822 VCPU_SREG_CS))
2823 goto done;
2824
2825 c->eip = c->src.val;
2826 break;
2827 case 0xeb:
2828 jmp: /* jmp rel short */
2829 jmp_rel(c, c->src.val);
2830 c->dst.type = OP_NONE; /* Disable writeback. */
2831 break;
2832 case 0xec: /* in al,dx */
2833 case 0xed: /* in (e/r)ax,dx */
2834 c->src.val = c->regs[VCPU_REGS_RDX];
2835 do_io_in:
2836 c->dst.bytes = min(c->dst.bytes, 4u);
2837 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
2838 kvm_inject_gp(ctxt->vcpu, 0);
2839 goto done;
2840 }
2841 if (!ops->pio_in_emulated(c->dst.bytes, c->src.val,
2842 &c->dst.val, 1, ctxt->vcpu))
2843 goto done; /* IO is needed */
2844 break;
2845 case 0xee: /* out al,dx */
2846 case 0xef: /* out (e/r)ax,dx */
2847 c->src.val = c->regs[VCPU_REGS_RDX];
2848 do_io_out:
2849 c->dst.bytes = min(c->dst.bytes, 4u);
2850 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
2851 kvm_inject_gp(ctxt->vcpu, 0);
2852 goto done;
2853 }
2854 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
2855 ctxt->vcpu);
2856 c->dst.type = OP_NONE; /* Disable writeback. */
2857 break;
2858 case 0xf4: /* hlt */
2859 ctxt->vcpu->arch.halt_request = 1;
2860 break;
2861 case 0xf5: /* cmc */
2862 /* complement carry flag from eflags reg */
2863 ctxt->eflags ^= EFLG_CF;
2864 c->dst.type = OP_NONE; /* Disable writeback. */
2865 break;
2866 case 0xf6 ... 0xf7: /* Grp3 */
2867 if (!emulate_grp3(ctxt, ops))
2868 goto cannot_emulate;
2869 break;
2870 case 0xf8: /* clc */
2871 ctxt->eflags &= ~EFLG_CF;
2872 c->dst.type = OP_NONE; /* Disable writeback. */
2873 break;
2874 case 0xfa: /* cli */
2875 if (emulator_bad_iopl(ctxt, ops))
2876 kvm_inject_gp(ctxt->vcpu, 0);
2877 else {
2878 ctxt->eflags &= ~X86_EFLAGS_IF;
2879 c->dst.type = OP_NONE; /* Disable writeback. */
2880 }
2881 break;
2882 case 0xfb: /* sti */
2883 if (emulator_bad_iopl(ctxt, ops))
2884 kvm_inject_gp(ctxt->vcpu, 0);
2885 else {
2886 toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_STI);
2887 ctxt->eflags |= X86_EFLAGS_IF;
2888 c->dst.type = OP_NONE; /* Disable writeback. */
2889 }
2890 break;
2891 case 0xfc: /* cld */
2892 ctxt->eflags &= ~EFLG_DF;
2893 c->dst.type = OP_NONE; /* Disable writeback. */
2894 break;
2895 case 0xfd: /* std */
2896 ctxt->eflags |= EFLG_DF;
2897 c->dst.type = OP_NONE; /* Disable writeback. */
2898 break;
2899 case 0xfe: /* Grp4 */
2900 grp45:
2901 rc = emulate_grp45(ctxt, ops);
2902 if (rc != X86EMUL_CONTINUE)
2903 goto done;
2904 break;
2905 case 0xff: /* Grp5 */
2906 if (c->modrm_reg == 5)
2907 goto jump_far;
2908 goto grp45;
2909 }
2910
2911 writeback:
2912 rc = writeback(ctxt, ops);
2913 if (rc != X86EMUL_CONTINUE)
2914 goto done;
2915
2916 if ((c->d & SrcMask) == SrcSI)
2917 string_addr_inc(ctxt, seg_override_base(ctxt, c), VCPU_REGS_RSI,
2918 &c->src);
2919
2920 if ((c->d & DstMask) == DstDI)
2921 string_addr_inc(ctxt, es_base(ctxt), VCPU_REGS_RDI, &c->dst);
2922
2923 if (c->rep_prefix && (c->d & String))
2924 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
2925
2926 /* Commit shadow register state. */
2927 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
2928 kvm_rip_write(ctxt->vcpu, c->eip);
2929
2930 done:
2931 if (rc == X86EMUL_UNHANDLEABLE) {
2932 c->eip = saved_eip;
2933 return -1;
2934 }
2935 return 0;
2936
2937 twobyte_insn:
2938 switch (c->b) {
2939 case 0x01: /* lgdt, lidt, lmsw */
2940 switch (c->modrm_reg) {
2941 u16 size;
2942 unsigned long address;
2943
2944 case 0: /* vmcall */
2945 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2946 goto cannot_emulate;
2947
2948 rc = kvm_fix_hypercall(ctxt->vcpu);
2949 if (rc != X86EMUL_CONTINUE)
2950 goto done;
2951
2952 /* Let the processor re-execute the fixed hypercall */
2953 c->eip = ctxt->eip;
2954 /* Disable writeback. */
2955 c->dst.type = OP_NONE;
2956 break;
2957 case 2: /* lgdt */
2958 rc = read_descriptor(ctxt, ops, c->src.ptr,
2959 &size, &address, c->op_bytes);
2960 if (rc != X86EMUL_CONTINUE)
2961 goto done;
2962 realmode_lgdt(ctxt->vcpu, size, address);
2963 /* Disable writeback. */
2964 c->dst.type = OP_NONE;
2965 break;
2966 case 3: /* lidt/vmmcall */
2967 if (c->modrm_mod == 3) {
2968 switch (c->modrm_rm) {
2969 case 1:
2970 rc = kvm_fix_hypercall(ctxt->vcpu);
2971 if (rc != X86EMUL_CONTINUE)
2972 goto done;
2973 break;
2974 default:
2975 goto cannot_emulate;
2976 }
2977 } else {
2978 rc = read_descriptor(ctxt, ops, c->src.ptr,
2979 &size, &address,
2980 c->op_bytes);
2981 if (rc != X86EMUL_CONTINUE)
2982 goto done;
2983 realmode_lidt(ctxt->vcpu, size, address);
2984 }
2985 /* Disable writeback. */
2986 c->dst.type = OP_NONE;
2987 break;
2988 case 4: /* smsw */
2989 c->dst.bytes = 2;
2990 c->dst.val = ops->get_cr(0, ctxt->vcpu);
2991 break;
2992 case 6: /* lmsw */
2993 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
2994 (c->src.val & 0x0f), ctxt->vcpu);
2995 c->dst.type = OP_NONE;
2996 break;
2997 case 5: /* not defined */
2998 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2999 goto done;
3000 case 7: /* invlpg*/
3001 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
3002 /* Disable writeback. */
3003 c->dst.type = OP_NONE;
3004 break;
3005 default:
3006 goto cannot_emulate;
3007 }
3008 break;
3009 case 0x05: /* syscall */
3010 rc = emulate_syscall(ctxt);
3011 if (rc != X86EMUL_CONTINUE)
3012 goto done;
3013 else
3014 goto writeback;
3015 break;
3016 case 0x06:
3017 emulate_clts(ctxt->vcpu);
3018 c->dst.type = OP_NONE;
3019 break;
3020 case 0x08: /* invd */
3021 case 0x09: /* wbinvd */
3022 case 0x0d: /* GrpP (prefetch) */
3023 case 0x18: /* Grp16 (prefetch/nop) */
3024 c->dst.type = OP_NONE;
3025 break;
3026 case 0x20: /* mov cr, reg */
3027 switch (c->modrm_reg) {
3028 case 1:
3029 case 5 ... 7:
3030 case 9 ... 15:
3031 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3032 goto done;
3033 }
3034 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
3035 c->dst.type = OP_NONE; /* no writeback */
3036 break;
3037 case 0x21: /* mov from dr to reg */
3038 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3039 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3040 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3041 goto done;
3042 }
3043 emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
3044 c->dst.type = OP_NONE; /* no writeback */
3045 break;
3046 case 0x22: /* mov reg, cr */
3047 ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu);
3048 c->dst.type = OP_NONE;
3049 break;
3050 case 0x23: /* mov from reg to dr */
3051 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3052 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3053 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3054 goto done;
3055 }
3056 emulator_set_dr(ctxt, c->modrm_reg, c->regs[c->modrm_rm]);
3057 c->dst.type = OP_NONE; /* no writeback */
3058 break;
3059 case 0x30:
3060 /* wrmsr */
3061 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3062 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3063 if (kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
3064 kvm_inject_gp(ctxt->vcpu, 0);
3065 goto done;
3066 }
3067 rc = X86EMUL_CONTINUE;
3068 c->dst.type = OP_NONE;
3069 break;
3070 case 0x32:
3071 /* rdmsr */
3072 if (kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
3073 kvm_inject_gp(ctxt->vcpu, 0);
3074 goto done;
3075 } else {
3076 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3077 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3078 }
3079 rc = X86EMUL_CONTINUE;
3080 c->dst.type = OP_NONE;
3081 break;
3082 case 0x34: /* sysenter */
3083 rc = emulate_sysenter(ctxt);
3084 if (rc != X86EMUL_CONTINUE)
3085 goto done;
3086 else
3087 goto writeback;
3088 break;
3089 case 0x35: /* sysexit */
3090 rc = emulate_sysexit(ctxt);
3091 if (rc != X86EMUL_CONTINUE)
3092 goto done;
3093 else
3094 goto writeback;
3095 break;
3096 case 0x40 ... 0x4f: /* cmov */
3097 c->dst.val = c->dst.orig_val = c->src.val;
3098 if (!test_cc(c->b, ctxt->eflags))
3099 c->dst.type = OP_NONE; /* no writeback */
3100 break;
3101 case 0x80 ... 0x8f: /* jnz rel, etc*/
3102 if (test_cc(c->b, ctxt->eflags))
3103 jmp_rel(c, c->src.val);
3104 c->dst.type = OP_NONE;
3105 break;
3106 case 0xa0: /* push fs */
3107 emulate_push_sreg(ctxt, VCPU_SREG_FS);
3108 break;
3109 case 0xa1: /* pop fs */
3110 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
3111 if (rc != X86EMUL_CONTINUE)
3112 goto done;
3113 break;
3114 case 0xa3:
3115 bt: /* bt */
3116 c->dst.type = OP_NONE;
3117 /* only subword offset */
3118 c->src.val &= (c->dst.bytes << 3) - 1;
3119 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
3120 break;
3121 case 0xa4: /* shld imm8, r, r/m */
3122 case 0xa5: /* shld cl, r, r/m */
3123 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3124 break;
3125 case 0xa8: /* push gs */
3126 emulate_push_sreg(ctxt, VCPU_SREG_GS);
3127 break;
3128 case 0xa9: /* pop gs */
3129 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
3130 if (rc != X86EMUL_CONTINUE)
3131 goto done;
3132 break;
3133 case 0xab:
3134 bts: /* bts */
3135 /* only subword offset */
3136 c->src.val &= (c->dst.bytes << 3) - 1;
3137 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
3138 break;
3139 case 0xac: /* shrd imm8, r, r/m */
3140 case 0xad: /* shrd cl, r, r/m */
3141 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3142 break;
3143 case 0xae: /* clflush */
3144 break;
3145 case 0xb0 ... 0xb1: /* cmpxchg */
3146 /*
3147 * Save real source value, then compare EAX against
3148 * destination.
3149 */
3150 c->src.orig_val = c->src.val;
3151 c->src.val = c->regs[VCPU_REGS_RAX];
3152 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3153 if (ctxt->eflags & EFLG_ZF) {
3154 /* Success: write back to memory. */
3155 c->dst.val = c->src.orig_val;
3156 } else {
3157 /* Failure: write the value we saw to EAX. */
3158 c->dst.type = OP_REG;
3159 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
3160 }
3161 break;
3162 case 0xb3:
3163 btr: /* btr */
3164 /* only subword offset */
3165 c->src.val &= (c->dst.bytes << 3) - 1;
3166 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
3167 break;
3168 case 0xb6 ... 0xb7: /* movzx */
3169 c->dst.bytes = c->op_bytes;
3170 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3171 : (u16) c->src.val;
3172 break;
3173 case 0xba: /* Grp8 */
3174 switch (c->modrm_reg & 3) {
3175 case 0:
3176 goto bt;
3177 case 1:
3178 goto bts;
3179 case 2:
3180 goto btr;
3181 case 3:
3182 goto btc;
3183 }
3184 break;
3185 case 0xbb:
3186 btc: /* btc */
3187 /* only subword offset */
3188 c->src.val &= (c->dst.bytes << 3) - 1;
3189 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
3190 break;
3191 case 0xbe ... 0xbf: /* movsx */
3192 c->dst.bytes = c->op_bytes;
3193 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3194 (s16) c->src.val;
3195 break;
3196 case 0xc3: /* movnti */
3197 c->dst.bytes = c->op_bytes;
3198 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3199 (u64) c->src.val;
3200 break;
3201 case 0xc7: /* Grp9 (cmpxchg8b) */
3202 rc = emulate_grp9(ctxt, ops);
3203 if (rc != X86EMUL_CONTINUE)
3204 goto done;
3205 c->dst.type = OP_NONE;
3206 break;
3207 }
3208 goto writeback;
3209
3210 cannot_emulate:
3211 DPRINTF("Cannot emulate %02x\n", c->b);
3212 c->eip = saved_eip;
3213 return -1;
3214 }
Linux kernel - Deliverables
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