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KVM: Add a helper for checking if the guest is in protected mode
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22 #ifndef __KERNEL__
23 #include <stdio.h>
24 #include <stdint.h>
25 #include <public/xen.h>
26 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
27 #else
28 #include <linux/kvm_host.h>
29 #include "kvm_cache_regs.h"
30 #define DPRINTF(x...) do {} while (0)
31 #endif
32 #include <linux/module.h>
33 #include <asm/kvm_emulate.h>
34
35 #include "x86.h"
36 #include "mmu.h" /* for is_long_mode() */
37
38 /*
39 * Opcode effective-address decode tables.
40 * Note that we only emulate instructions that have at least one memory
41 * operand (excluding implicit stack references). We assume that stack
42 * references and instruction fetches will never occur in special memory
43 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
44 * not be handled.
45 */
46
47 /* Operand sizes: 8-bit operands or specified/overridden size. */
48 #define ByteOp (1<<0) /* 8-bit operands. */
49 /* Destination operand type. */
50 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
51 #define DstReg (2<<1) /* Register operand. */
52 #define DstMem (3<<1) /* Memory operand. */
53 #define DstAcc (4<<1) /* Destination Accumulator */
54 #define DstMask (7<<1)
55 /* Source operand type. */
56 #define SrcNone (0<<4) /* No source operand. */
57 #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
58 #define SrcReg (1<<4) /* Register operand. */
59 #define SrcMem (2<<4) /* Memory operand. */
60 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
61 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
62 #define SrcImm (5<<4) /* Immediate operand. */
63 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
64 #define SrcOne (7<<4) /* Implied '1' */
65 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
66 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
67 #define SrcMask (0xf<<4)
68 /* Generic ModRM decode. */
69 #define ModRM (1<<8)
70 /* Destination is only written; never read. */
71 #define Mov (1<<9)
72 #define BitOp (1<<10)
73 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
74 #define String (1<<12) /* String instruction (rep capable) */
75 #define Stack (1<<13) /* Stack instruction (push/pop) */
76 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
78 #define GroupMask 0xff /* Group number stored in bits 0:7 */
79 /* Misc flags */
80 #define No64 (1<<28)
81 /* Source 2 operand type */
82 #define Src2None (0<<29)
83 #define Src2CL (1<<29)
84 #define Src2ImmByte (2<<29)
85 #define Src2One (3<<29)
86 #define Src2Imm16 (4<<29)
87 #define Src2Mask (7<<29)
88
89 enum {
90 Group1_80, Group1_81, Group1_82, Group1_83,
91 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
92 };
93
94 static u32 opcode_table[256] = {
95 /* 0x00 - 0x07 */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
98 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
99 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
100 /* 0x08 - 0x0F */
101 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
102 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
103 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
104 ImplicitOps | Stack | No64, 0,
105 /* 0x10 - 0x17 */
106 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
107 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
108 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
109 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
110 /* 0x18 - 0x1F */
111 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
112 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
113 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
114 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
115 /* 0x20 - 0x27 */
116 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
117 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
118 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
119 /* 0x28 - 0x2F */
120 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
121 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
122 0, 0, 0, 0,
123 /* 0x30 - 0x37 */
124 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
125 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
126 0, 0, 0, 0,
127 /* 0x38 - 0x3F */
128 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
129 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
130 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
131 0, 0,
132 /* 0x40 - 0x47 */
133 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
134 /* 0x48 - 0x4F */
135 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
136 /* 0x50 - 0x57 */
137 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
138 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
139 /* 0x58 - 0x5F */
140 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
141 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
142 /* 0x60 - 0x67 */
143 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
144 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
145 0, 0, 0, 0,
146 /* 0x68 - 0x6F */
147 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
148 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
149 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
150 /* 0x70 - 0x77 */
151 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
152 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
153 /* 0x78 - 0x7F */
154 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
155 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
156 /* 0x80 - 0x87 */
157 Group | Group1_80, Group | Group1_81,
158 Group | Group1_82, Group | Group1_83,
159 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
160 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
161 /* 0x88 - 0x8F */
162 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
163 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
164 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
165 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
166 /* 0x90 - 0x97 */
167 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
168 /* 0x98 - 0x9F */
169 0, 0, SrcImm | Src2Imm16 | No64, 0,
170 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
171 /* 0xA0 - 0xA7 */
172 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
173 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
174 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
175 ByteOp | ImplicitOps | String, ImplicitOps | String,
176 /* 0xA8 - 0xAF */
177 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
178 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
179 ByteOp | ImplicitOps | String, ImplicitOps | String,
180 /* 0xB0 - 0xB7 */
181 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
182 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
183 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
184 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
185 /* 0xB8 - 0xBF */
186 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
187 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
188 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
189 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
190 /* 0xC0 - 0xC7 */
191 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
192 0, ImplicitOps | Stack, 0, 0,
193 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
194 /* 0xC8 - 0xCF */
195 0, 0, 0, ImplicitOps | Stack,
196 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
197 /* 0xD0 - 0xD7 */
198 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
199 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
200 0, 0, 0, 0,
201 /* 0xD8 - 0xDF */
202 0, 0, 0, 0, 0, 0, 0, 0,
203 /* 0xE0 - 0xE7 */
204 0, 0, 0, 0,
205 ByteOp | SrcImmUByte, SrcImmUByte,
206 ByteOp | SrcImmUByte, SrcImmUByte,
207 /* 0xE8 - 0xEF */
208 SrcImm | Stack, SrcImm | ImplicitOps,
209 SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps,
210 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
211 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
212 /* 0xF0 - 0xF7 */
213 0, 0, 0, 0,
214 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
215 /* 0xF8 - 0xFF */
216 ImplicitOps, 0, ImplicitOps, ImplicitOps,
217 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
218 };
219
220 static u32 twobyte_table[256] = {
221 /* 0x00 - 0x0F */
222 0, Group | GroupDual | Group7, 0, 0, 0, ImplicitOps, ImplicitOps, 0,
223 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
224 /* 0x10 - 0x1F */
225 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
226 /* 0x20 - 0x2F */
227 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
228 0, 0, 0, 0, 0, 0, 0, 0,
229 /* 0x30 - 0x3F */
230 ImplicitOps, 0, ImplicitOps, 0,
231 ImplicitOps, ImplicitOps, 0, 0,
232 0, 0, 0, 0, 0, 0, 0, 0,
233 /* 0x40 - 0x47 */
234 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
235 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
236 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
237 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
238 /* 0x48 - 0x4F */
239 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
240 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
241 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
242 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
243 /* 0x50 - 0x5F */
244 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
245 /* 0x60 - 0x6F */
246 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
247 /* 0x70 - 0x7F */
248 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
249 /* 0x80 - 0x8F */
250 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
251 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
252 /* 0x90 - 0x9F */
253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
254 /* 0xA0 - 0xA7 */
255 ImplicitOps | Stack, ImplicitOps | Stack,
256 0, DstMem | SrcReg | ModRM | BitOp,
257 DstMem | SrcReg | Src2ImmByte | ModRM,
258 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
259 /* 0xA8 - 0xAF */
260 ImplicitOps | Stack, ImplicitOps | Stack,
261 0, DstMem | SrcReg | ModRM | BitOp,
262 DstMem | SrcReg | Src2ImmByte | ModRM,
263 DstMem | SrcReg | Src2CL | ModRM,
264 ModRM, 0,
265 /* 0xB0 - 0xB7 */
266 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
267 DstMem | SrcReg | ModRM | BitOp,
268 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
269 DstReg | SrcMem16 | ModRM | Mov,
270 /* 0xB8 - 0xBF */
271 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
272 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
273 DstReg | SrcMem16 | ModRM | Mov,
274 /* 0xC0 - 0xCF */
275 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
276 0, 0, 0, 0, 0, 0, 0, 0,
277 /* 0xD0 - 0xDF */
278 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
279 /* 0xE0 - 0xEF */
280 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
281 /* 0xF0 - 0xFF */
282 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
283 };
284
285 static u32 group_table[] = {
286 [Group1_80*8] =
287 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
288 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
289 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
290 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
291 [Group1_81*8] =
292 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
293 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
294 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
295 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
296 [Group1_82*8] =
297 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
298 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
299 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
300 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
301 [Group1_83*8] =
302 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
303 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
304 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
305 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
306 [Group1A*8] =
307 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
308 [Group3_Byte*8] =
309 ByteOp | SrcImm | DstMem | ModRM, 0,
310 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
311 0, 0, 0, 0,
312 [Group3*8] =
313 DstMem | SrcImm | ModRM, 0,
314 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
315 0, 0, 0, 0,
316 [Group4*8] =
317 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
318 0, 0, 0, 0, 0, 0,
319 [Group5*8] =
320 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
321 SrcMem | ModRM | Stack, 0,
322 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
323 [Group7*8] =
324 0, 0, ModRM | SrcMem, ModRM | SrcMem,
325 SrcNone | ModRM | DstMem | Mov, 0,
326 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
327 };
328
329 static u32 group2_table[] = {
330 [Group7*8] =
331 SrcNone | ModRM, 0, 0, SrcNone | ModRM,
332 SrcNone | ModRM | DstMem | Mov, 0,
333 SrcMem16 | ModRM | Mov, 0,
334 };
335
336 /* EFLAGS bit definitions. */
337 #define EFLG_VM (1<<17)
338 #define EFLG_RF (1<<16)
339 #define EFLG_OF (1<<11)
340 #define EFLG_DF (1<<10)
341 #define EFLG_IF (1<<9)
342 #define EFLG_SF (1<<7)
343 #define EFLG_ZF (1<<6)
344 #define EFLG_AF (1<<4)
345 #define EFLG_PF (1<<2)
346 #define EFLG_CF (1<<0)
347
348 /*
349 * Instruction emulation:
350 * Most instructions are emulated directly via a fragment of inline assembly
351 * code. This allows us to save/restore EFLAGS and thus very easily pick up
352 * any modified flags.
353 */
354
355 #if defined(CONFIG_X86_64)
356 #define _LO32 "k" /* force 32-bit operand */
357 #define _STK "%%rsp" /* stack pointer */
358 #elif defined(__i386__)
359 #define _LO32 "" /* force 32-bit operand */
360 #define _STK "%%esp" /* stack pointer */
361 #endif
362
363 /*
364 * These EFLAGS bits are restored from saved value during emulation, and
365 * any changes are written back to the saved value after emulation.
366 */
367 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
368
369 /* Before executing instruction: restore necessary bits in EFLAGS. */
370 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
371 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
372 "movl %"_sav",%"_LO32 _tmp"; " \
373 "push %"_tmp"; " \
374 "push %"_tmp"; " \
375 "movl %"_msk",%"_LO32 _tmp"; " \
376 "andl %"_LO32 _tmp",("_STK"); " \
377 "pushf; " \
378 "notl %"_LO32 _tmp"; " \
379 "andl %"_LO32 _tmp",("_STK"); " \
380 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
381 "pop %"_tmp"; " \
382 "orl %"_LO32 _tmp",("_STK"); " \
383 "popf; " \
384 "pop %"_sav"; "
385
386 /* After executing instruction: write-back necessary bits in EFLAGS. */
387 #define _POST_EFLAGS(_sav, _msk, _tmp) \
388 /* _sav |= EFLAGS & _msk; */ \
389 "pushf; " \
390 "pop %"_tmp"; " \
391 "andl %"_msk",%"_LO32 _tmp"; " \
392 "orl %"_LO32 _tmp",%"_sav"; "
393
394 #ifdef CONFIG_X86_64
395 #define ON64(x) x
396 #else
397 #define ON64(x)
398 #endif
399
400 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
401 do { \
402 __asm__ __volatile__ ( \
403 _PRE_EFLAGS("0", "4", "2") \
404 _op _suffix " %"_x"3,%1; " \
405 _POST_EFLAGS("0", "4", "2") \
406 : "=m" (_eflags), "=m" ((_dst).val), \
407 "=&r" (_tmp) \
408 : _y ((_src).val), "i" (EFLAGS_MASK)); \
409 } while (0)
410
411
412 /* Raw emulation: instruction has two explicit operands. */
413 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
414 do { \
415 unsigned long _tmp; \
416 \
417 switch ((_dst).bytes) { \
418 case 2: \
419 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
420 break; \
421 case 4: \
422 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
423 break; \
424 case 8: \
425 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
426 break; \
427 } \
428 } while (0)
429
430 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
431 do { \
432 unsigned long _tmp; \
433 switch ((_dst).bytes) { \
434 case 1: \
435 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
436 break; \
437 default: \
438 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
439 _wx, _wy, _lx, _ly, _qx, _qy); \
440 break; \
441 } \
442 } while (0)
443
444 /* Source operand is byte-sized and may be restricted to just %cl. */
445 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
446 __emulate_2op(_op, _src, _dst, _eflags, \
447 "b", "c", "b", "c", "b", "c", "b", "c")
448
449 /* Source operand is byte, word, long or quad sized. */
450 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
451 __emulate_2op(_op, _src, _dst, _eflags, \
452 "b", "q", "w", "r", _LO32, "r", "", "r")
453
454 /* Source operand is word, long or quad sized. */
455 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
456 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
457 "w", "r", _LO32, "r", "", "r")
458
459 /* Instruction has three operands and one operand is stored in ECX register */
460 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
461 do { \
462 unsigned long _tmp; \
463 _type _clv = (_cl).val; \
464 _type _srcv = (_src).val; \
465 _type _dstv = (_dst).val; \
466 \
467 __asm__ __volatile__ ( \
468 _PRE_EFLAGS("0", "5", "2") \
469 _op _suffix " %4,%1 \n" \
470 _POST_EFLAGS("0", "5", "2") \
471 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
472 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
473 ); \
474 \
475 (_cl).val = (unsigned long) _clv; \
476 (_src).val = (unsigned long) _srcv; \
477 (_dst).val = (unsigned long) _dstv; \
478 } while (0)
479
480 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
481 do { \
482 switch ((_dst).bytes) { \
483 case 2: \
484 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
485 "w", unsigned short); \
486 break; \
487 case 4: \
488 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
489 "l", unsigned int); \
490 break; \
491 case 8: \
492 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
493 "q", unsigned long)); \
494 break; \
495 } \
496 } while (0)
497
498 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
499 do { \
500 unsigned long _tmp; \
501 \
502 __asm__ __volatile__ ( \
503 _PRE_EFLAGS("0", "3", "2") \
504 _op _suffix " %1; " \
505 _POST_EFLAGS("0", "3", "2") \
506 : "=m" (_eflags), "+m" ((_dst).val), \
507 "=&r" (_tmp) \
508 : "i" (EFLAGS_MASK)); \
509 } while (0)
510
511 /* Instruction has only one explicit operand (no source operand). */
512 #define emulate_1op(_op, _dst, _eflags) \
513 do { \
514 switch ((_dst).bytes) { \
515 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
516 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
517 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
518 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
519 } \
520 } while (0)
521
522 /* Fetch next part of the instruction being emulated. */
523 #define insn_fetch(_type, _size, _eip) \
524 ({ unsigned long _x; \
525 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
526 if (rc != 0) \
527 goto done; \
528 (_eip) += (_size); \
529 (_type)_x; \
530 })
531
532 static inline unsigned long ad_mask(struct decode_cache *c)
533 {
534 return (1UL << (c->ad_bytes << 3)) - 1;
535 }
536
537 /* Access/update address held in a register, based on addressing mode. */
538 static inline unsigned long
539 address_mask(struct decode_cache *c, unsigned long reg)
540 {
541 if (c->ad_bytes == sizeof(unsigned long))
542 return reg;
543 else
544 return reg & ad_mask(c);
545 }
546
547 static inline unsigned long
548 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
549 {
550 return base + address_mask(c, reg);
551 }
552
553 static inline void
554 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
555 {
556 if (c->ad_bytes == sizeof(unsigned long))
557 *reg += inc;
558 else
559 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
560 }
561
562 static inline void jmp_rel(struct decode_cache *c, int rel)
563 {
564 register_address_increment(c, &c->eip, rel);
565 }
566
567 static void set_seg_override(struct decode_cache *c, int seg)
568 {
569 c->has_seg_override = true;
570 c->seg_override = seg;
571 }
572
573 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
574 {
575 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
576 return 0;
577
578 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
579 }
580
581 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
582 struct decode_cache *c)
583 {
584 if (!c->has_seg_override)
585 return 0;
586
587 return seg_base(ctxt, c->seg_override);
588 }
589
590 static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
591 {
592 return seg_base(ctxt, VCPU_SREG_ES);
593 }
594
595 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
596 {
597 return seg_base(ctxt, VCPU_SREG_SS);
598 }
599
600 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
601 struct x86_emulate_ops *ops,
602 unsigned long linear, u8 *dest)
603 {
604 struct fetch_cache *fc = &ctxt->decode.fetch;
605 int rc;
606 int size;
607
608 if (linear < fc->start || linear >= fc->end) {
609 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
610 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
611 if (rc)
612 return rc;
613 fc->start = linear;
614 fc->end = linear + size;
615 }
616 *dest = fc->data[linear - fc->start];
617 return 0;
618 }
619
620 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
621 struct x86_emulate_ops *ops,
622 unsigned long eip, void *dest, unsigned size)
623 {
624 int rc = 0;
625
626 /* x86 instructions are limited to 15 bytes. */
627 if (eip + size - ctxt->decode.eip_orig > 15)
628 return X86EMUL_UNHANDLEABLE;
629 eip += ctxt->cs_base;
630 while (size--) {
631 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
632 if (rc)
633 return rc;
634 }
635 return 0;
636 }
637
638 /*
639 * Given the 'reg' portion of a ModRM byte, and a register block, return a
640 * pointer into the block that addresses the relevant register.
641 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
642 */
643 static void *decode_register(u8 modrm_reg, unsigned long *regs,
644 int highbyte_regs)
645 {
646 void *p;
647
648 p = &regs[modrm_reg];
649 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
650 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
651 return p;
652 }
653
654 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
655 struct x86_emulate_ops *ops,
656 void *ptr,
657 u16 *size, unsigned long *address, int op_bytes)
658 {
659 int rc;
660
661 if (op_bytes == 2)
662 op_bytes = 3;
663 *address = 0;
664 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
665 ctxt->vcpu);
666 if (rc)
667 return rc;
668 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
669 ctxt->vcpu);
670 return rc;
671 }
672
673 static int test_cc(unsigned int condition, unsigned int flags)
674 {
675 int rc = 0;
676
677 switch ((condition & 15) >> 1) {
678 case 0: /* o */
679 rc |= (flags & EFLG_OF);
680 break;
681 case 1: /* b/c/nae */
682 rc |= (flags & EFLG_CF);
683 break;
684 case 2: /* z/e */
685 rc |= (flags & EFLG_ZF);
686 break;
687 case 3: /* be/na */
688 rc |= (flags & (EFLG_CF|EFLG_ZF));
689 break;
690 case 4: /* s */
691 rc |= (flags & EFLG_SF);
692 break;
693 case 5: /* p/pe */
694 rc |= (flags & EFLG_PF);
695 break;
696 case 7: /* le/ng */
697 rc |= (flags & EFLG_ZF);
698 /* fall through */
699 case 6: /* l/nge */
700 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
701 break;
702 }
703
704 /* Odd condition identifiers (lsb == 1) have inverted sense. */
705 return (!!rc ^ (condition & 1));
706 }
707
708 static void decode_register_operand(struct operand *op,
709 struct decode_cache *c,
710 int inhibit_bytereg)
711 {
712 unsigned reg = c->modrm_reg;
713 int highbyte_regs = c->rex_prefix == 0;
714
715 if (!(c->d & ModRM))
716 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
717 op->type = OP_REG;
718 if ((c->d & ByteOp) && !inhibit_bytereg) {
719 op->ptr = decode_register(reg, c->regs, highbyte_regs);
720 op->val = *(u8 *)op->ptr;
721 op->bytes = 1;
722 } else {
723 op->ptr = decode_register(reg, c->regs, 0);
724 op->bytes = c->op_bytes;
725 switch (op->bytes) {
726 case 2:
727 op->val = *(u16 *)op->ptr;
728 break;
729 case 4:
730 op->val = *(u32 *)op->ptr;
731 break;
732 case 8:
733 op->val = *(u64 *) op->ptr;
734 break;
735 }
736 }
737 op->orig_val = op->val;
738 }
739
740 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
741 struct x86_emulate_ops *ops)
742 {
743 struct decode_cache *c = &ctxt->decode;
744 u8 sib;
745 int index_reg = 0, base_reg = 0, scale;
746 int rc = 0;
747
748 if (c->rex_prefix) {
749 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
750 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
751 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
752 }
753
754 c->modrm = insn_fetch(u8, 1, c->eip);
755 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
756 c->modrm_reg |= (c->modrm & 0x38) >> 3;
757 c->modrm_rm |= (c->modrm & 0x07);
758 c->modrm_ea = 0;
759 c->use_modrm_ea = 1;
760
761 if (c->modrm_mod == 3) {
762 c->modrm_ptr = decode_register(c->modrm_rm,
763 c->regs, c->d & ByteOp);
764 c->modrm_val = *(unsigned long *)c->modrm_ptr;
765 return rc;
766 }
767
768 if (c->ad_bytes == 2) {
769 unsigned bx = c->regs[VCPU_REGS_RBX];
770 unsigned bp = c->regs[VCPU_REGS_RBP];
771 unsigned si = c->regs[VCPU_REGS_RSI];
772 unsigned di = c->regs[VCPU_REGS_RDI];
773
774 /* 16-bit ModR/M decode. */
775 switch (c->modrm_mod) {
776 case 0:
777 if (c->modrm_rm == 6)
778 c->modrm_ea += insn_fetch(u16, 2, c->eip);
779 break;
780 case 1:
781 c->modrm_ea += insn_fetch(s8, 1, c->eip);
782 break;
783 case 2:
784 c->modrm_ea += insn_fetch(u16, 2, c->eip);
785 break;
786 }
787 switch (c->modrm_rm) {
788 case 0:
789 c->modrm_ea += bx + si;
790 break;
791 case 1:
792 c->modrm_ea += bx + di;
793 break;
794 case 2:
795 c->modrm_ea += bp + si;
796 break;
797 case 3:
798 c->modrm_ea += bp + di;
799 break;
800 case 4:
801 c->modrm_ea += si;
802 break;
803 case 5:
804 c->modrm_ea += di;
805 break;
806 case 6:
807 if (c->modrm_mod != 0)
808 c->modrm_ea += bp;
809 break;
810 case 7:
811 c->modrm_ea += bx;
812 break;
813 }
814 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
815 (c->modrm_rm == 6 && c->modrm_mod != 0))
816 if (!c->has_seg_override)
817 set_seg_override(c, VCPU_SREG_SS);
818 c->modrm_ea = (u16)c->modrm_ea;
819 } else {
820 /* 32/64-bit ModR/M decode. */
821 if ((c->modrm_rm & 7) == 4) {
822 sib = insn_fetch(u8, 1, c->eip);
823 index_reg |= (sib >> 3) & 7;
824 base_reg |= sib & 7;
825 scale = sib >> 6;
826
827 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
828 c->modrm_ea += insn_fetch(s32, 4, c->eip);
829 else
830 c->modrm_ea += c->regs[base_reg];
831 if (index_reg != 4)
832 c->modrm_ea += c->regs[index_reg] << scale;
833 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
834 if (ctxt->mode == X86EMUL_MODE_PROT64)
835 c->rip_relative = 1;
836 } else
837 c->modrm_ea += c->regs[c->modrm_rm];
838 switch (c->modrm_mod) {
839 case 0:
840 if (c->modrm_rm == 5)
841 c->modrm_ea += insn_fetch(s32, 4, c->eip);
842 break;
843 case 1:
844 c->modrm_ea += insn_fetch(s8, 1, c->eip);
845 break;
846 case 2:
847 c->modrm_ea += insn_fetch(s32, 4, c->eip);
848 break;
849 }
850 }
851 done:
852 return rc;
853 }
854
855 static int decode_abs(struct x86_emulate_ctxt *ctxt,
856 struct x86_emulate_ops *ops)
857 {
858 struct decode_cache *c = &ctxt->decode;
859 int rc = 0;
860
861 switch (c->ad_bytes) {
862 case 2:
863 c->modrm_ea = insn_fetch(u16, 2, c->eip);
864 break;
865 case 4:
866 c->modrm_ea = insn_fetch(u32, 4, c->eip);
867 break;
868 case 8:
869 c->modrm_ea = insn_fetch(u64, 8, c->eip);
870 break;
871 }
872 done:
873 return rc;
874 }
875
876 int
877 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
878 {
879 struct decode_cache *c = &ctxt->decode;
880 int rc = 0;
881 int mode = ctxt->mode;
882 int def_op_bytes, def_ad_bytes, group;
883
884 /* Shadow copy of register state. Committed on successful emulation. */
885
886 memset(c, 0, sizeof(struct decode_cache));
887 c->eip = c->eip_orig = kvm_rip_read(ctxt->vcpu);
888 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
889 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
890
891 switch (mode) {
892 case X86EMUL_MODE_REAL:
893 case X86EMUL_MODE_PROT16:
894 def_op_bytes = def_ad_bytes = 2;
895 break;
896 case X86EMUL_MODE_PROT32:
897 def_op_bytes = def_ad_bytes = 4;
898 break;
899 #ifdef CONFIG_X86_64
900 case X86EMUL_MODE_PROT64:
901 def_op_bytes = 4;
902 def_ad_bytes = 8;
903 break;
904 #endif
905 default:
906 return -1;
907 }
908
909 c->op_bytes = def_op_bytes;
910 c->ad_bytes = def_ad_bytes;
911
912 /* Legacy prefixes. */
913 for (;;) {
914 switch (c->b = insn_fetch(u8, 1, c->eip)) {
915 case 0x66: /* operand-size override */
916 /* switch between 2/4 bytes */
917 c->op_bytes = def_op_bytes ^ 6;
918 break;
919 case 0x67: /* address-size override */
920 if (mode == X86EMUL_MODE_PROT64)
921 /* switch between 4/8 bytes */
922 c->ad_bytes = def_ad_bytes ^ 12;
923 else
924 /* switch between 2/4 bytes */
925 c->ad_bytes = def_ad_bytes ^ 6;
926 break;
927 case 0x26: /* ES override */
928 case 0x2e: /* CS override */
929 case 0x36: /* SS override */
930 case 0x3e: /* DS override */
931 set_seg_override(c, (c->b >> 3) & 3);
932 break;
933 case 0x64: /* FS override */
934 case 0x65: /* GS override */
935 set_seg_override(c, c->b & 7);
936 break;
937 case 0x40 ... 0x4f: /* REX */
938 if (mode != X86EMUL_MODE_PROT64)
939 goto done_prefixes;
940 c->rex_prefix = c->b;
941 continue;
942 case 0xf0: /* LOCK */
943 c->lock_prefix = 1;
944 break;
945 case 0xf2: /* REPNE/REPNZ */
946 c->rep_prefix = REPNE_PREFIX;
947 break;
948 case 0xf3: /* REP/REPE/REPZ */
949 c->rep_prefix = REPE_PREFIX;
950 break;
951 default:
952 goto done_prefixes;
953 }
954
955 /* Any legacy prefix after a REX prefix nullifies its effect. */
956
957 c->rex_prefix = 0;
958 }
959
960 done_prefixes:
961
962 /* REX prefix. */
963 if (c->rex_prefix)
964 if (c->rex_prefix & 8)
965 c->op_bytes = 8; /* REX.W */
966
967 /* Opcode byte(s). */
968 c->d = opcode_table[c->b];
969 if (c->d == 0) {
970 /* Two-byte opcode? */
971 if (c->b == 0x0f) {
972 c->twobyte = 1;
973 c->b = insn_fetch(u8, 1, c->eip);
974 c->d = twobyte_table[c->b];
975 }
976 }
977
978 if (mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
979 kvm_report_emulation_failure(ctxt->vcpu, "invalid x86/64 instruction");;
980 return -1;
981 }
982
983 if (c->d & Group) {
984 group = c->d & GroupMask;
985 c->modrm = insn_fetch(u8, 1, c->eip);
986 --c->eip;
987
988 group = (group << 3) + ((c->modrm >> 3) & 7);
989 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
990 c->d = group2_table[group];
991 else
992 c->d = group_table[group];
993 }
994
995 /* Unrecognised? */
996 if (c->d == 0) {
997 DPRINTF("Cannot emulate %02x\n", c->b);
998 return -1;
999 }
1000
1001 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1002 c->op_bytes = 8;
1003
1004 /* ModRM and SIB bytes. */
1005 if (c->d & ModRM)
1006 rc = decode_modrm(ctxt, ops);
1007 else if (c->d & MemAbs)
1008 rc = decode_abs(ctxt, ops);
1009 if (rc)
1010 goto done;
1011
1012 if (!c->has_seg_override)
1013 set_seg_override(c, VCPU_SREG_DS);
1014
1015 if (!(!c->twobyte && c->b == 0x8d))
1016 c->modrm_ea += seg_override_base(ctxt, c);
1017
1018 if (c->ad_bytes != 8)
1019 c->modrm_ea = (u32)c->modrm_ea;
1020 /*
1021 * Decode and fetch the source operand: register, memory
1022 * or immediate.
1023 */
1024 switch (c->d & SrcMask) {
1025 case SrcNone:
1026 break;
1027 case SrcReg:
1028 decode_register_operand(&c->src, c, 0);
1029 break;
1030 case SrcMem16:
1031 c->src.bytes = 2;
1032 goto srcmem_common;
1033 case SrcMem32:
1034 c->src.bytes = 4;
1035 goto srcmem_common;
1036 case SrcMem:
1037 c->src.bytes = (c->d & ByteOp) ? 1 :
1038 c->op_bytes;
1039 /* Don't fetch the address for invlpg: it could be unmapped. */
1040 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
1041 break;
1042 srcmem_common:
1043 /*
1044 * For instructions with a ModR/M byte, switch to register
1045 * access if Mod = 3.
1046 */
1047 if ((c->d & ModRM) && c->modrm_mod == 3) {
1048 c->src.type = OP_REG;
1049 c->src.val = c->modrm_val;
1050 c->src.ptr = c->modrm_ptr;
1051 break;
1052 }
1053 c->src.type = OP_MEM;
1054 break;
1055 case SrcImm:
1056 case SrcImmU:
1057 c->src.type = OP_IMM;
1058 c->src.ptr = (unsigned long *)c->eip;
1059 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1060 if (c->src.bytes == 8)
1061 c->src.bytes = 4;
1062 /* NB. Immediates are sign-extended as necessary. */
1063 switch (c->src.bytes) {
1064 case 1:
1065 c->src.val = insn_fetch(s8, 1, c->eip);
1066 break;
1067 case 2:
1068 c->src.val = insn_fetch(s16, 2, c->eip);
1069 break;
1070 case 4:
1071 c->src.val = insn_fetch(s32, 4, c->eip);
1072 break;
1073 }
1074 if ((c->d & SrcMask) == SrcImmU) {
1075 switch (c->src.bytes) {
1076 case 1:
1077 c->src.val &= 0xff;
1078 break;
1079 case 2:
1080 c->src.val &= 0xffff;
1081 break;
1082 case 4:
1083 c->src.val &= 0xffffffff;
1084 break;
1085 }
1086 }
1087 break;
1088 case SrcImmByte:
1089 case SrcImmUByte:
1090 c->src.type = OP_IMM;
1091 c->src.ptr = (unsigned long *)c->eip;
1092 c->src.bytes = 1;
1093 if ((c->d & SrcMask) == SrcImmByte)
1094 c->src.val = insn_fetch(s8, 1, c->eip);
1095 else
1096 c->src.val = insn_fetch(u8, 1, c->eip);
1097 break;
1098 case SrcOne:
1099 c->src.bytes = 1;
1100 c->src.val = 1;
1101 break;
1102 }
1103
1104 /*
1105 * Decode and fetch the second source operand: register, memory
1106 * or immediate.
1107 */
1108 switch (c->d & Src2Mask) {
1109 case Src2None:
1110 break;
1111 case Src2CL:
1112 c->src2.bytes = 1;
1113 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1114 break;
1115 case Src2ImmByte:
1116 c->src2.type = OP_IMM;
1117 c->src2.ptr = (unsigned long *)c->eip;
1118 c->src2.bytes = 1;
1119 c->src2.val = insn_fetch(u8, 1, c->eip);
1120 break;
1121 case Src2Imm16:
1122 c->src2.type = OP_IMM;
1123 c->src2.ptr = (unsigned long *)c->eip;
1124 c->src2.bytes = 2;
1125 c->src2.val = insn_fetch(u16, 2, c->eip);
1126 break;
1127 case Src2One:
1128 c->src2.bytes = 1;
1129 c->src2.val = 1;
1130 break;
1131 }
1132
1133 /* Decode and fetch the destination operand: register or memory. */
1134 switch (c->d & DstMask) {
1135 case ImplicitOps:
1136 /* Special instructions do their own operand decoding. */
1137 return 0;
1138 case DstReg:
1139 decode_register_operand(&c->dst, c,
1140 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
1141 break;
1142 case DstMem:
1143 if ((c->d & ModRM) && c->modrm_mod == 3) {
1144 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1145 c->dst.type = OP_REG;
1146 c->dst.val = c->dst.orig_val = c->modrm_val;
1147 c->dst.ptr = c->modrm_ptr;
1148 break;
1149 }
1150 c->dst.type = OP_MEM;
1151 break;
1152 case DstAcc:
1153 c->dst.type = OP_REG;
1154 c->dst.bytes = c->op_bytes;
1155 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1156 switch (c->op_bytes) {
1157 case 1:
1158 c->dst.val = *(u8 *)c->dst.ptr;
1159 break;
1160 case 2:
1161 c->dst.val = *(u16 *)c->dst.ptr;
1162 break;
1163 case 4:
1164 c->dst.val = *(u32 *)c->dst.ptr;
1165 break;
1166 }
1167 c->dst.orig_val = c->dst.val;
1168 break;
1169 }
1170
1171 if (c->rip_relative)
1172 c->modrm_ea += c->eip;
1173
1174 done:
1175 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1176 }
1177
1178 static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1179 {
1180 struct decode_cache *c = &ctxt->decode;
1181
1182 c->dst.type = OP_MEM;
1183 c->dst.bytes = c->op_bytes;
1184 c->dst.val = c->src.val;
1185 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1186 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
1187 c->regs[VCPU_REGS_RSP]);
1188 }
1189
1190 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1191 struct x86_emulate_ops *ops,
1192 void *dest, int len)
1193 {
1194 struct decode_cache *c = &ctxt->decode;
1195 int rc;
1196
1197 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1198 c->regs[VCPU_REGS_RSP]),
1199 dest, len, ctxt->vcpu);
1200 if (rc != X86EMUL_CONTINUE)
1201 return rc;
1202
1203 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1204 return rc;
1205 }
1206
1207 static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1208 {
1209 struct decode_cache *c = &ctxt->decode;
1210 struct kvm_segment segment;
1211
1212 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
1213
1214 c->src.val = segment.selector;
1215 emulate_push(ctxt);
1216 }
1217
1218 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1219 struct x86_emulate_ops *ops, int seg)
1220 {
1221 struct decode_cache *c = &ctxt->decode;
1222 unsigned long selector;
1223 int rc;
1224
1225 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1226 if (rc != 0)
1227 return rc;
1228
1229 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)selector, 1, seg);
1230 return rc;
1231 }
1232
1233 static void emulate_pusha(struct x86_emulate_ctxt *ctxt)
1234 {
1235 struct decode_cache *c = &ctxt->decode;
1236 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1237 int reg = VCPU_REGS_RAX;
1238
1239 while (reg <= VCPU_REGS_RDI) {
1240 (reg == VCPU_REGS_RSP) ?
1241 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1242
1243 emulate_push(ctxt);
1244 ++reg;
1245 }
1246 }
1247
1248 static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1249 struct x86_emulate_ops *ops)
1250 {
1251 struct decode_cache *c = &ctxt->decode;
1252 int rc = 0;
1253 int reg = VCPU_REGS_RDI;
1254
1255 while (reg >= VCPU_REGS_RAX) {
1256 if (reg == VCPU_REGS_RSP) {
1257 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1258 c->op_bytes);
1259 --reg;
1260 }
1261
1262 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1263 if (rc != 0)
1264 break;
1265 --reg;
1266 }
1267 return rc;
1268 }
1269
1270 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1271 struct x86_emulate_ops *ops)
1272 {
1273 struct decode_cache *c = &ctxt->decode;
1274 int rc;
1275
1276 rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1277 if (rc != 0)
1278 return rc;
1279 return 0;
1280 }
1281
1282 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1283 {
1284 struct decode_cache *c = &ctxt->decode;
1285 switch (c->modrm_reg) {
1286 case 0: /* rol */
1287 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1288 break;
1289 case 1: /* ror */
1290 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1291 break;
1292 case 2: /* rcl */
1293 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1294 break;
1295 case 3: /* rcr */
1296 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1297 break;
1298 case 4: /* sal/shl */
1299 case 6: /* sal/shl */
1300 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1301 break;
1302 case 5: /* shr */
1303 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1304 break;
1305 case 7: /* sar */
1306 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1307 break;
1308 }
1309 }
1310
1311 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1312 struct x86_emulate_ops *ops)
1313 {
1314 struct decode_cache *c = &ctxt->decode;
1315 int rc = 0;
1316
1317 switch (c->modrm_reg) {
1318 case 0 ... 1: /* test */
1319 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1320 break;
1321 case 2: /* not */
1322 c->dst.val = ~c->dst.val;
1323 break;
1324 case 3: /* neg */
1325 emulate_1op("neg", c->dst, ctxt->eflags);
1326 break;
1327 default:
1328 DPRINTF("Cannot emulate %02x\n", c->b);
1329 rc = X86EMUL_UNHANDLEABLE;
1330 break;
1331 }
1332 return rc;
1333 }
1334
1335 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1336 struct x86_emulate_ops *ops)
1337 {
1338 struct decode_cache *c = &ctxt->decode;
1339
1340 switch (c->modrm_reg) {
1341 case 0: /* inc */
1342 emulate_1op("inc", c->dst, ctxt->eflags);
1343 break;
1344 case 1: /* dec */
1345 emulate_1op("dec", c->dst, ctxt->eflags);
1346 break;
1347 case 2: /* call near abs */ {
1348 long int old_eip;
1349 old_eip = c->eip;
1350 c->eip = c->src.val;
1351 c->src.val = old_eip;
1352 emulate_push(ctxt);
1353 break;
1354 }
1355 case 4: /* jmp abs */
1356 c->eip = c->src.val;
1357 break;
1358 case 6: /* push */
1359 emulate_push(ctxt);
1360 break;
1361 }
1362 return 0;
1363 }
1364
1365 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1366 struct x86_emulate_ops *ops,
1367 unsigned long memop)
1368 {
1369 struct decode_cache *c = &ctxt->decode;
1370 u64 old, new;
1371 int rc;
1372
1373 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
1374 if (rc != X86EMUL_CONTINUE)
1375 return rc;
1376
1377 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1378 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1379
1380 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1381 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1382 ctxt->eflags &= ~EFLG_ZF;
1383
1384 } else {
1385 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1386 (u32) c->regs[VCPU_REGS_RBX];
1387
1388 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
1389 if (rc != X86EMUL_CONTINUE)
1390 return rc;
1391 ctxt->eflags |= EFLG_ZF;
1392 }
1393 return 0;
1394 }
1395
1396 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1397 struct x86_emulate_ops *ops)
1398 {
1399 struct decode_cache *c = &ctxt->decode;
1400 int rc;
1401 unsigned long cs;
1402
1403 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1404 if (rc)
1405 return rc;
1406 if (c->op_bytes == 4)
1407 c->eip = (u32)c->eip;
1408 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1409 if (rc)
1410 return rc;
1411 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, 1, VCPU_SREG_CS);
1412 return rc;
1413 }
1414
1415 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1416 struct x86_emulate_ops *ops)
1417 {
1418 int rc;
1419 struct decode_cache *c = &ctxt->decode;
1420
1421 switch (c->dst.type) {
1422 case OP_REG:
1423 /* The 4-byte case *is* correct:
1424 * in 64-bit mode we zero-extend.
1425 */
1426 switch (c->dst.bytes) {
1427 case 1:
1428 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1429 break;
1430 case 2:
1431 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1432 break;
1433 case 4:
1434 *c->dst.ptr = (u32)c->dst.val;
1435 break; /* 64b: zero-ext */
1436 case 8:
1437 *c->dst.ptr = c->dst.val;
1438 break;
1439 }
1440 break;
1441 case OP_MEM:
1442 if (c->lock_prefix)
1443 rc = ops->cmpxchg_emulated(
1444 (unsigned long)c->dst.ptr,
1445 &c->dst.orig_val,
1446 &c->dst.val,
1447 c->dst.bytes,
1448 ctxt->vcpu);
1449 else
1450 rc = ops->write_emulated(
1451 (unsigned long)c->dst.ptr,
1452 &c->dst.val,
1453 c->dst.bytes,
1454 ctxt->vcpu);
1455 if (rc != X86EMUL_CONTINUE)
1456 return rc;
1457 break;
1458 case OP_NONE:
1459 /* no writeback */
1460 break;
1461 default:
1462 break;
1463 }
1464 return 0;
1465 }
1466
1467 static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
1468 {
1469 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1470 /*
1471 * an sti; sti; sequence only disable interrupts for the first
1472 * instruction. So, if the last instruction, be it emulated or
1473 * not, left the system with the INT_STI flag enabled, it
1474 * means that the last instruction is an sti. We should not
1475 * leave the flag on in this case. The same goes for mov ss
1476 */
1477 if (!(int_shadow & mask))
1478 ctxt->interruptibility = mask;
1479 }
1480
1481 static inline void
1482 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1483 struct kvm_segment *cs, struct kvm_segment *ss)
1484 {
1485 memset(cs, 0, sizeof(struct kvm_segment));
1486 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
1487 memset(ss, 0, sizeof(struct kvm_segment));
1488
1489 cs->l = 0; /* will be adjusted later */
1490 cs->base = 0; /* flat segment */
1491 cs->g = 1; /* 4kb granularity */
1492 cs->limit = 0xffffffff; /* 4GB limit */
1493 cs->type = 0x0b; /* Read, Execute, Accessed */
1494 cs->s = 1;
1495 cs->dpl = 0; /* will be adjusted later */
1496 cs->present = 1;
1497 cs->db = 1;
1498
1499 ss->unusable = 0;
1500 ss->base = 0; /* flat segment */
1501 ss->limit = 0xffffffff; /* 4GB limit */
1502 ss->g = 1; /* 4kb granularity */
1503 ss->s = 1;
1504 ss->type = 0x03; /* Read/Write, Accessed */
1505 ss->db = 1; /* 32bit stack segment */
1506 ss->dpl = 0;
1507 ss->present = 1;
1508 }
1509
1510 static int
1511 emulate_syscall(struct x86_emulate_ctxt *ctxt)
1512 {
1513 struct decode_cache *c = &ctxt->decode;
1514 struct kvm_segment cs, ss;
1515 u64 msr_data;
1516
1517 /* syscall is not available in real mode */
1518 if (c->lock_prefix || ctxt->mode == X86EMUL_MODE_REAL
1519 || !is_protmode(ctxt->vcpu))
1520 return -1;
1521
1522 setup_syscalls_segments(ctxt, &cs, &ss);
1523
1524 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1525 msr_data >>= 32;
1526 cs.selector = (u16)(msr_data & 0xfffc);
1527 ss.selector = (u16)(msr_data + 8);
1528
1529 if (is_long_mode(ctxt->vcpu)) {
1530 cs.db = 0;
1531 cs.l = 1;
1532 }
1533 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1534 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1535
1536 c->regs[VCPU_REGS_RCX] = c->eip;
1537 if (is_long_mode(ctxt->vcpu)) {
1538 #ifdef CONFIG_X86_64
1539 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1540
1541 kvm_x86_ops->get_msr(ctxt->vcpu,
1542 ctxt->mode == X86EMUL_MODE_PROT64 ?
1543 MSR_LSTAR : MSR_CSTAR, &msr_data);
1544 c->eip = msr_data;
1545
1546 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1547 ctxt->eflags &= ~(msr_data | EFLG_RF);
1548 #endif
1549 } else {
1550 /* legacy mode */
1551 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1552 c->eip = (u32)msr_data;
1553
1554 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1555 }
1556
1557 return 0;
1558 }
1559
1560 static int
1561 emulate_sysenter(struct x86_emulate_ctxt *ctxt)
1562 {
1563 struct decode_cache *c = &ctxt->decode;
1564 struct kvm_segment cs, ss;
1565 u64 msr_data;
1566
1567 /* inject #UD if LOCK prefix is used */
1568 if (c->lock_prefix)
1569 return -1;
1570
1571 /* inject #GP if in real mode or paging is disabled */
1572 if (ctxt->mode == X86EMUL_MODE_REAL || !is_protmode(ctxt->vcpu)) {
1573 kvm_inject_gp(ctxt->vcpu, 0);
1574 return -1;
1575 }
1576
1577 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1578 * Therefore, we inject an #UD.
1579 */
1580 if (ctxt->mode == X86EMUL_MODE_PROT64)
1581 return -1;
1582
1583 setup_syscalls_segments(ctxt, &cs, &ss);
1584
1585 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1586 switch (ctxt->mode) {
1587 case X86EMUL_MODE_PROT32:
1588 if ((msr_data & 0xfffc) == 0x0) {
1589 kvm_inject_gp(ctxt->vcpu, 0);
1590 return -1;
1591 }
1592 break;
1593 case X86EMUL_MODE_PROT64:
1594 if (msr_data == 0x0) {
1595 kvm_inject_gp(ctxt->vcpu, 0);
1596 return -1;
1597 }
1598 break;
1599 }
1600
1601 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1602 cs.selector = (u16)msr_data;
1603 cs.selector &= ~SELECTOR_RPL_MASK;
1604 ss.selector = cs.selector + 8;
1605 ss.selector &= ~SELECTOR_RPL_MASK;
1606 if (ctxt->mode == X86EMUL_MODE_PROT64
1607 || is_long_mode(ctxt->vcpu)) {
1608 cs.db = 0;
1609 cs.l = 1;
1610 }
1611
1612 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1613 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1614
1615 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1616 c->eip = msr_data;
1617
1618 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1619 c->regs[VCPU_REGS_RSP] = msr_data;
1620
1621 return 0;
1622 }
1623
1624 static int
1625 emulate_sysexit(struct x86_emulate_ctxt *ctxt)
1626 {
1627 struct decode_cache *c = &ctxt->decode;
1628 struct kvm_segment cs, ss;
1629 u64 msr_data;
1630 int usermode;
1631
1632 /* inject #UD if LOCK prefix is used */
1633 if (c->lock_prefix)
1634 return -1;
1635
1636 /* inject #GP if in real mode or paging is disabled */
1637 if (ctxt->mode == X86EMUL_MODE_REAL || !is_protmode(ctxt->vcpu)) {
1638 kvm_inject_gp(ctxt->vcpu, 0);
1639 return -1;
1640 }
1641
1642 /* sysexit must be called from CPL 0 */
1643 if (kvm_x86_ops->get_cpl(ctxt->vcpu) != 0) {
1644 kvm_inject_gp(ctxt->vcpu, 0);
1645 return -1;
1646 }
1647
1648 setup_syscalls_segments(ctxt, &cs, &ss);
1649
1650 if ((c->rex_prefix & 0x8) != 0x0)
1651 usermode = X86EMUL_MODE_PROT64;
1652 else
1653 usermode = X86EMUL_MODE_PROT32;
1654
1655 cs.dpl = 3;
1656 ss.dpl = 3;
1657 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1658 switch (usermode) {
1659 case X86EMUL_MODE_PROT32:
1660 cs.selector = (u16)(msr_data + 16);
1661 if ((msr_data & 0xfffc) == 0x0) {
1662 kvm_inject_gp(ctxt->vcpu, 0);
1663 return -1;
1664 }
1665 ss.selector = (u16)(msr_data + 24);
1666 break;
1667 case X86EMUL_MODE_PROT64:
1668 cs.selector = (u16)(msr_data + 32);
1669 if (msr_data == 0x0) {
1670 kvm_inject_gp(ctxt->vcpu, 0);
1671 return -1;
1672 }
1673 ss.selector = cs.selector + 8;
1674 cs.db = 0;
1675 cs.l = 1;
1676 break;
1677 }
1678 cs.selector |= SELECTOR_RPL_MASK;
1679 ss.selector |= SELECTOR_RPL_MASK;
1680
1681 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1682 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1683
1684 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
1685 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
1686
1687 return 0;
1688 }
1689
1690 int
1691 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1692 {
1693 unsigned long memop = 0;
1694 u64 msr_data;
1695 unsigned long saved_eip = 0;
1696 struct decode_cache *c = &ctxt->decode;
1697 unsigned int port;
1698 int io_dir_in;
1699 int rc = 0;
1700
1701 ctxt->interruptibility = 0;
1702
1703 /* Shadow copy of register state. Committed on successful emulation.
1704 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1705 * modify them.
1706 */
1707
1708 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
1709 saved_eip = c->eip;
1710
1711 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
1712 memop = c->modrm_ea;
1713
1714 if (c->rep_prefix && (c->d & String)) {
1715 /* All REP prefixes have the same first termination condition */
1716 if (c->regs[VCPU_REGS_RCX] == 0) {
1717 kvm_rip_write(ctxt->vcpu, c->eip);
1718 goto done;
1719 }
1720 /* The second termination condition only applies for REPE
1721 * and REPNE. Test if the repeat string operation prefix is
1722 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1723 * corresponding termination condition according to:
1724 * - if REPE/REPZ and ZF = 0 then done
1725 * - if REPNE/REPNZ and ZF = 1 then done
1726 */
1727 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1728 (c->b == 0xae) || (c->b == 0xaf)) {
1729 if ((c->rep_prefix == REPE_PREFIX) &&
1730 ((ctxt->eflags & EFLG_ZF) == 0)) {
1731 kvm_rip_write(ctxt->vcpu, c->eip);
1732 goto done;
1733 }
1734 if ((c->rep_prefix == REPNE_PREFIX) &&
1735 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
1736 kvm_rip_write(ctxt->vcpu, c->eip);
1737 goto done;
1738 }
1739 }
1740 c->regs[VCPU_REGS_RCX]--;
1741 c->eip = kvm_rip_read(ctxt->vcpu);
1742 }
1743
1744 if (c->src.type == OP_MEM) {
1745 c->src.ptr = (unsigned long *)memop;
1746 c->src.val = 0;
1747 rc = ops->read_emulated((unsigned long)c->src.ptr,
1748 &c->src.val,
1749 c->src.bytes,
1750 ctxt->vcpu);
1751 if (rc != X86EMUL_CONTINUE)
1752 goto done;
1753 c->src.orig_val = c->src.val;
1754 }
1755
1756 if ((c->d & DstMask) == ImplicitOps)
1757 goto special_insn;
1758
1759
1760 if (c->dst.type == OP_MEM) {
1761 c->dst.ptr = (unsigned long *)memop;
1762 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1763 c->dst.val = 0;
1764 if (c->d & BitOp) {
1765 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1766
1767 c->dst.ptr = (void *)c->dst.ptr +
1768 (c->src.val & mask) / 8;
1769 }
1770 if (!(c->d & Mov)) {
1771 /* optimisation - avoid slow emulated read */
1772 rc = ops->read_emulated((unsigned long)c->dst.ptr,
1773 &c->dst.val,
1774 c->dst.bytes,
1775 ctxt->vcpu);
1776 if (rc != X86EMUL_CONTINUE)
1777 goto done;
1778 }
1779 }
1780 c->dst.orig_val = c->dst.val;
1781
1782 special_insn:
1783
1784 if (c->twobyte)
1785 goto twobyte_insn;
1786
1787 switch (c->b) {
1788 case 0x00 ... 0x05:
1789 add: /* add */
1790 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
1791 break;
1792 case 0x06: /* push es */
1793 emulate_push_sreg(ctxt, VCPU_SREG_ES);
1794 break;
1795 case 0x07: /* pop es */
1796 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1797 if (rc != 0)
1798 goto done;
1799 break;
1800 case 0x08 ... 0x0d:
1801 or: /* or */
1802 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
1803 break;
1804 case 0x0e: /* push cs */
1805 emulate_push_sreg(ctxt, VCPU_SREG_CS);
1806 break;
1807 case 0x10 ... 0x15:
1808 adc: /* adc */
1809 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
1810 break;
1811 case 0x16: /* push ss */
1812 emulate_push_sreg(ctxt, VCPU_SREG_SS);
1813 break;
1814 case 0x17: /* pop ss */
1815 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1816 if (rc != 0)
1817 goto done;
1818 break;
1819 case 0x18 ... 0x1d:
1820 sbb: /* sbb */
1821 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
1822 break;
1823 case 0x1e: /* push ds */
1824 emulate_push_sreg(ctxt, VCPU_SREG_DS);
1825 break;
1826 case 0x1f: /* pop ds */
1827 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1828 if (rc != 0)
1829 goto done;
1830 break;
1831 case 0x20 ... 0x25:
1832 and: /* and */
1833 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
1834 break;
1835 case 0x28 ... 0x2d:
1836 sub: /* sub */
1837 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
1838 break;
1839 case 0x30 ... 0x35:
1840 xor: /* xor */
1841 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
1842 break;
1843 case 0x38 ... 0x3d:
1844 cmp: /* cmp */
1845 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1846 break;
1847 case 0x40 ... 0x47: /* inc r16/r32 */
1848 emulate_1op("inc", c->dst, ctxt->eflags);
1849 break;
1850 case 0x48 ... 0x4f: /* dec r16/r32 */
1851 emulate_1op("dec", c->dst, ctxt->eflags);
1852 break;
1853 case 0x50 ... 0x57: /* push reg */
1854 emulate_push(ctxt);
1855 break;
1856 case 0x58 ... 0x5f: /* pop reg */
1857 pop_instruction:
1858 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1859 if (rc != 0)
1860 goto done;
1861 break;
1862 case 0x60: /* pusha */
1863 emulate_pusha(ctxt);
1864 break;
1865 case 0x61: /* popa */
1866 rc = emulate_popa(ctxt, ops);
1867 if (rc != 0)
1868 goto done;
1869 break;
1870 case 0x63: /* movsxd */
1871 if (ctxt->mode != X86EMUL_MODE_PROT64)
1872 goto cannot_emulate;
1873 c->dst.val = (s32) c->src.val;
1874 break;
1875 case 0x68: /* push imm */
1876 case 0x6a: /* push imm8 */
1877 emulate_push(ctxt);
1878 break;
1879 case 0x6c: /* insb */
1880 case 0x6d: /* insw/insd */
1881 if (kvm_emulate_pio_string(ctxt->vcpu,
1882 1,
1883 (c->d & ByteOp) ? 1 : c->op_bytes,
1884 c->rep_prefix ?
1885 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1886 (ctxt->eflags & EFLG_DF),
1887 register_address(c, es_base(ctxt),
1888 c->regs[VCPU_REGS_RDI]),
1889 c->rep_prefix,
1890 c->regs[VCPU_REGS_RDX]) == 0) {
1891 c->eip = saved_eip;
1892 return -1;
1893 }
1894 return 0;
1895 case 0x6e: /* outsb */
1896 case 0x6f: /* outsw/outsd */
1897 if (kvm_emulate_pio_string(ctxt->vcpu,
1898 0,
1899 (c->d & ByteOp) ? 1 : c->op_bytes,
1900 c->rep_prefix ?
1901 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1902 (ctxt->eflags & EFLG_DF),
1903 register_address(c,
1904 seg_override_base(ctxt, c),
1905 c->regs[VCPU_REGS_RSI]),
1906 c->rep_prefix,
1907 c->regs[VCPU_REGS_RDX]) == 0) {
1908 c->eip = saved_eip;
1909 return -1;
1910 }
1911 return 0;
1912 case 0x70 ... 0x7f: /* jcc (short) */
1913 if (test_cc(c->b, ctxt->eflags))
1914 jmp_rel(c, c->src.val);
1915 break;
1916 case 0x80 ... 0x83: /* Grp1 */
1917 switch (c->modrm_reg) {
1918 case 0:
1919 goto add;
1920 case 1:
1921 goto or;
1922 case 2:
1923 goto adc;
1924 case 3:
1925 goto sbb;
1926 case 4:
1927 goto and;
1928 case 5:
1929 goto sub;
1930 case 6:
1931 goto xor;
1932 case 7:
1933 goto cmp;
1934 }
1935 break;
1936 case 0x84 ... 0x85:
1937 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1938 break;
1939 case 0x86 ... 0x87: /* xchg */
1940 xchg:
1941 /* Write back the register source. */
1942 switch (c->dst.bytes) {
1943 case 1:
1944 *(u8 *) c->src.ptr = (u8) c->dst.val;
1945 break;
1946 case 2:
1947 *(u16 *) c->src.ptr = (u16) c->dst.val;
1948 break;
1949 case 4:
1950 *c->src.ptr = (u32) c->dst.val;
1951 break; /* 64b reg: zero-extend */
1952 case 8:
1953 *c->src.ptr = c->dst.val;
1954 break;
1955 }
1956 /*
1957 * Write back the memory destination with implicit LOCK
1958 * prefix.
1959 */
1960 c->dst.val = c->src.val;
1961 c->lock_prefix = 1;
1962 break;
1963 case 0x88 ... 0x8b: /* mov */
1964 goto mov;
1965 case 0x8c: { /* mov r/m, sreg */
1966 struct kvm_segment segreg;
1967
1968 if (c->modrm_reg <= 5)
1969 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1970 else {
1971 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1972 c->modrm);
1973 goto cannot_emulate;
1974 }
1975 c->dst.val = segreg.selector;
1976 break;
1977 }
1978 case 0x8d: /* lea r16/r32, m */
1979 c->dst.val = c->modrm_ea;
1980 break;
1981 case 0x8e: { /* mov seg, r/m16 */
1982 uint16_t sel;
1983 int type_bits;
1984 int err;
1985
1986 sel = c->src.val;
1987 if (c->modrm_reg == VCPU_SREG_SS)
1988 toggle_interruptibility(ctxt, X86_SHADOW_INT_MOV_SS);
1989
1990 if (c->modrm_reg <= 5) {
1991 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1992 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1993 type_bits, c->modrm_reg);
1994 } else {
1995 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1996 c->modrm);
1997 goto cannot_emulate;
1998 }
1999
2000 if (err < 0)
2001 goto cannot_emulate;
2002
2003 c->dst.type = OP_NONE; /* Disable writeback. */
2004 break;
2005 }
2006 case 0x8f: /* pop (sole member of Grp1a) */
2007 rc = emulate_grp1a(ctxt, ops);
2008 if (rc != 0)
2009 goto done;
2010 break;
2011 case 0x90: /* nop / xchg r8,rax */
2012 if (!(c->rex_prefix & 1)) { /* nop */
2013 c->dst.type = OP_NONE;
2014 break;
2015 }
2016 case 0x91 ... 0x97: /* xchg reg,rax */
2017 c->src.type = c->dst.type = OP_REG;
2018 c->src.bytes = c->dst.bytes = c->op_bytes;
2019 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2020 c->src.val = *(c->src.ptr);
2021 goto xchg;
2022 case 0x9c: /* pushf */
2023 c->src.val = (unsigned long) ctxt->eflags;
2024 emulate_push(ctxt);
2025 break;
2026 case 0x9d: /* popf */
2027 c->dst.type = OP_REG;
2028 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2029 c->dst.bytes = c->op_bytes;
2030 goto pop_instruction;
2031 case 0xa0 ... 0xa1: /* mov */
2032 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2033 c->dst.val = c->src.val;
2034 break;
2035 case 0xa2 ... 0xa3: /* mov */
2036 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
2037 break;
2038 case 0xa4 ... 0xa5: /* movs */
2039 c->dst.type = OP_MEM;
2040 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2041 c->dst.ptr = (unsigned long *)register_address(c,
2042 es_base(ctxt),
2043 c->regs[VCPU_REGS_RDI]);
2044 rc = ops->read_emulated(register_address(c,
2045 seg_override_base(ctxt, c),
2046 c->regs[VCPU_REGS_RSI]),
2047 &c->dst.val,
2048 c->dst.bytes, ctxt->vcpu);
2049 if (rc != X86EMUL_CONTINUE)
2050 goto done;
2051 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
2052 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2053 : c->dst.bytes);
2054 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
2055 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2056 : c->dst.bytes);
2057 break;
2058 case 0xa6 ... 0xa7: /* cmps */
2059 c->src.type = OP_NONE; /* Disable writeback. */
2060 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2061 c->src.ptr = (unsigned long *)register_address(c,
2062 seg_override_base(ctxt, c),
2063 c->regs[VCPU_REGS_RSI]);
2064 rc = ops->read_emulated((unsigned long)c->src.ptr,
2065 &c->src.val,
2066 c->src.bytes,
2067 ctxt->vcpu);
2068 if (rc != X86EMUL_CONTINUE)
2069 goto done;
2070
2071 c->dst.type = OP_NONE; /* Disable writeback. */
2072 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2073 c->dst.ptr = (unsigned long *)register_address(c,
2074 es_base(ctxt),
2075 c->regs[VCPU_REGS_RDI]);
2076 rc = ops->read_emulated((unsigned long)c->dst.ptr,
2077 &c->dst.val,
2078 c->dst.bytes,
2079 ctxt->vcpu);
2080 if (rc != X86EMUL_CONTINUE)
2081 goto done;
2082
2083 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
2084
2085 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2086
2087 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
2088 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
2089 : c->src.bytes);
2090 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
2091 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2092 : c->dst.bytes);
2093
2094 break;
2095 case 0xaa ... 0xab: /* stos */
2096 c->dst.type = OP_MEM;
2097 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2098 c->dst.ptr = (unsigned long *)register_address(c,
2099 es_base(ctxt),
2100 c->regs[VCPU_REGS_RDI]);
2101 c->dst.val = c->regs[VCPU_REGS_RAX];
2102 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
2103 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2104 : c->dst.bytes);
2105 break;
2106 case 0xac ... 0xad: /* lods */
2107 c->dst.type = OP_REG;
2108 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2109 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2110 rc = ops->read_emulated(register_address(c,
2111 seg_override_base(ctxt, c),
2112 c->regs[VCPU_REGS_RSI]),
2113 &c->dst.val,
2114 c->dst.bytes,
2115 ctxt->vcpu);
2116 if (rc != X86EMUL_CONTINUE)
2117 goto done;
2118 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
2119 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2120 : c->dst.bytes);
2121 break;
2122 case 0xae ... 0xaf: /* scas */
2123 DPRINTF("Urk! I don't handle SCAS.\n");
2124 goto cannot_emulate;
2125 case 0xb0 ... 0xbf: /* mov r, imm */
2126 goto mov;
2127 case 0xc0 ... 0xc1:
2128 emulate_grp2(ctxt);
2129 break;
2130 case 0xc3: /* ret */
2131 c->dst.type = OP_REG;
2132 c->dst.ptr = &c->eip;
2133 c->dst.bytes = c->op_bytes;
2134 goto pop_instruction;
2135 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2136 mov:
2137 c->dst.val = c->src.val;
2138 break;
2139 case 0xcb: /* ret far */
2140 rc = emulate_ret_far(ctxt, ops);
2141 if (rc)
2142 goto done;
2143 break;
2144 case 0xd0 ... 0xd1: /* Grp2 */
2145 c->src.val = 1;
2146 emulate_grp2(ctxt);
2147 break;
2148 case 0xd2 ... 0xd3: /* Grp2 */
2149 c->src.val = c->regs[VCPU_REGS_RCX];
2150 emulate_grp2(ctxt);
2151 break;
2152 case 0xe4: /* inb */
2153 case 0xe5: /* in */
2154 port = c->src.val;
2155 io_dir_in = 1;
2156 goto do_io;
2157 case 0xe6: /* outb */
2158 case 0xe7: /* out */
2159 port = c->src.val;
2160 io_dir_in = 0;
2161 goto do_io;
2162 case 0xe8: /* call (near) */ {
2163 long int rel = c->src.val;
2164 c->src.val = (unsigned long) c->eip;
2165 jmp_rel(c, rel);
2166 emulate_push(ctxt);
2167 break;
2168 }
2169 case 0xe9: /* jmp rel */
2170 goto jmp;
2171 case 0xea: /* jmp far */
2172 if (kvm_load_segment_descriptor(ctxt->vcpu, c->src2.val, 9,
2173 VCPU_SREG_CS) < 0) {
2174 DPRINTF("jmp far: Failed to load CS descriptor\n");
2175 goto cannot_emulate;
2176 }
2177
2178 c->eip = c->src.val;
2179 break;
2180 case 0xeb:
2181 jmp: /* jmp rel short */
2182 jmp_rel(c, c->src.val);
2183 c->dst.type = OP_NONE; /* Disable writeback. */
2184 break;
2185 case 0xec: /* in al,dx */
2186 case 0xed: /* in (e/r)ax,dx */
2187 port = c->regs[VCPU_REGS_RDX];
2188 io_dir_in = 1;
2189 goto do_io;
2190 case 0xee: /* out al,dx */
2191 case 0xef: /* out (e/r)ax,dx */
2192 port = c->regs[VCPU_REGS_RDX];
2193 io_dir_in = 0;
2194 do_io: if (kvm_emulate_pio(ctxt->vcpu, io_dir_in,
2195 (c->d & ByteOp) ? 1 : c->op_bytes,
2196 port) != 0) {
2197 c->eip = saved_eip;
2198 goto cannot_emulate;
2199 }
2200 break;
2201 case 0xf4: /* hlt */
2202 ctxt->vcpu->arch.halt_request = 1;
2203 break;
2204 case 0xf5: /* cmc */
2205 /* complement carry flag from eflags reg */
2206 ctxt->eflags ^= EFLG_CF;
2207 c->dst.type = OP_NONE; /* Disable writeback. */
2208 break;
2209 case 0xf6 ... 0xf7: /* Grp3 */
2210 rc = emulate_grp3(ctxt, ops);
2211 if (rc != 0)
2212 goto done;
2213 break;
2214 case 0xf8: /* clc */
2215 ctxt->eflags &= ~EFLG_CF;
2216 c->dst.type = OP_NONE; /* Disable writeback. */
2217 break;
2218 case 0xfa: /* cli */
2219 ctxt->eflags &= ~X86_EFLAGS_IF;
2220 c->dst.type = OP_NONE; /* Disable writeback. */
2221 break;
2222 case 0xfb: /* sti */
2223 toggle_interruptibility(ctxt, X86_SHADOW_INT_STI);
2224 ctxt->eflags |= X86_EFLAGS_IF;
2225 c->dst.type = OP_NONE; /* Disable writeback. */
2226 break;
2227 case 0xfc: /* cld */
2228 ctxt->eflags &= ~EFLG_DF;
2229 c->dst.type = OP_NONE; /* Disable writeback. */
2230 break;
2231 case 0xfd: /* std */
2232 ctxt->eflags |= EFLG_DF;
2233 c->dst.type = OP_NONE; /* Disable writeback. */
2234 break;
2235 case 0xfe ... 0xff: /* Grp4/Grp5 */
2236 rc = emulate_grp45(ctxt, ops);
2237 if (rc != 0)
2238 goto done;
2239 break;
2240 }
2241
2242 writeback:
2243 rc = writeback(ctxt, ops);
2244 if (rc != 0)
2245 goto done;
2246
2247 /* Commit shadow register state. */
2248 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
2249 kvm_rip_write(ctxt->vcpu, c->eip);
2250
2251 done:
2252 if (rc == X86EMUL_UNHANDLEABLE) {
2253 c->eip = saved_eip;
2254 return -1;
2255 }
2256 return 0;
2257
2258 twobyte_insn:
2259 switch (c->b) {
2260 case 0x01: /* lgdt, lidt, lmsw */
2261 switch (c->modrm_reg) {
2262 u16 size;
2263 unsigned long address;
2264
2265 case 0: /* vmcall */
2266 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2267 goto cannot_emulate;
2268
2269 rc = kvm_fix_hypercall(ctxt->vcpu);
2270 if (rc)
2271 goto done;
2272
2273 /* Let the processor re-execute the fixed hypercall */
2274 c->eip = kvm_rip_read(ctxt->vcpu);
2275 /* Disable writeback. */
2276 c->dst.type = OP_NONE;
2277 break;
2278 case 2: /* lgdt */
2279 rc = read_descriptor(ctxt, ops, c->src.ptr,
2280 &size, &address, c->op_bytes);
2281 if (rc)
2282 goto done;
2283 realmode_lgdt(ctxt->vcpu, size, address);
2284 /* Disable writeback. */
2285 c->dst.type = OP_NONE;
2286 break;
2287 case 3: /* lidt/vmmcall */
2288 if (c->modrm_mod == 3) {
2289 switch (c->modrm_rm) {
2290 case 1:
2291 rc = kvm_fix_hypercall(ctxt->vcpu);
2292 if (rc)
2293 goto done;
2294 break;
2295 default:
2296 goto cannot_emulate;
2297 }
2298 } else {
2299 rc = read_descriptor(ctxt, ops, c->src.ptr,
2300 &size, &address,
2301 c->op_bytes);
2302 if (rc)
2303 goto done;
2304 realmode_lidt(ctxt->vcpu, size, address);
2305 }
2306 /* Disable writeback. */
2307 c->dst.type = OP_NONE;
2308 break;
2309 case 4: /* smsw */
2310 c->dst.bytes = 2;
2311 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
2312 break;
2313 case 6: /* lmsw */
2314 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
2315 &ctxt->eflags);
2316 c->dst.type = OP_NONE;
2317 break;
2318 case 7: /* invlpg*/
2319 emulate_invlpg(ctxt->vcpu, memop);
2320 /* Disable writeback. */
2321 c->dst.type = OP_NONE;
2322 break;
2323 default:
2324 goto cannot_emulate;
2325 }
2326 break;
2327 case 0x05: /* syscall */
2328 if (emulate_syscall(ctxt) == -1)
2329 goto cannot_emulate;
2330 else
2331 goto writeback;
2332 break;
2333 case 0x06:
2334 emulate_clts(ctxt->vcpu);
2335 c->dst.type = OP_NONE;
2336 break;
2337 case 0x08: /* invd */
2338 case 0x09: /* wbinvd */
2339 case 0x0d: /* GrpP (prefetch) */
2340 case 0x18: /* Grp16 (prefetch/nop) */
2341 c->dst.type = OP_NONE;
2342 break;
2343 case 0x20: /* mov cr, reg */
2344 if (c->modrm_mod != 3)
2345 goto cannot_emulate;
2346 c->regs[c->modrm_rm] =
2347 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
2348 c->dst.type = OP_NONE; /* no writeback */
2349 break;
2350 case 0x21: /* mov from dr to reg */
2351 if (c->modrm_mod != 3)
2352 goto cannot_emulate;
2353 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
2354 if (rc)
2355 goto cannot_emulate;
2356 c->dst.type = OP_NONE; /* no writeback */
2357 break;
2358 case 0x22: /* mov reg, cr */
2359 if (c->modrm_mod != 3)
2360 goto cannot_emulate;
2361 realmode_set_cr(ctxt->vcpu,
2362 c->modrm_reg, c->modrm_val, &ctxt->eflags);
2363 c->dst.type = OP_NONE;
2364 break;
2365 case 0x23: /* mov from reg to dr */
2366 if (c->modrm_mod != 3)
2367 goto cannot_emulate;
2368 rc = emulator_set_dr(ctxt, c->modrm_reg,
2369 c->regs[c->modrm_rm]);
2370 if (rc)
2371 goto cannot_emulate;
2372 c->dst.type = OP_NONE; /* no writeback */
2373 break;
2374 case 0x30:
2375 /* wrmsr */
2376 msr_data = (u32)c->regs[VCPU_REGS_RAX]
2377 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
2378 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
2379 if (rc) {
2380 kvm_inject_gp(ctxt->vcpu, 0);
2381 c->eip = kvm_rip_read(ctxt->vcpu);
2382 }
2383 rc = X86EMUL_CONTINUE;
2384 c->dst.type = OP_NONE;
2385 break;
2386 case 0x32:
2387 /* rdmsr */
2388 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2389 if (rc) {
2390 kvm_inject_gp(ctxt->vcpu, 0);
2391 c->eip = kvm_rip_read(ctxt->vcpu);
2392 } else {
2393 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2394 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2395 }
2396 rc = X86EMUL_CONTINUE;
2397 c->dst.type = OP_NONE;
2398 break;
2399 case 0x34: /* sysenter */
2400 if (emulate_sysenter(ctxt) == -1)
2401 goto cannot_emulate;
2402 else
2403 goto writeback;
2404 break;
2405 case 0x35: /* sysexit */
2406 if (emulate_sysexit(ctxt) == -1)
2407 goto cannot_emulate;
2408 else
2409 goto writeback;
2410 break;
2411 case 0x40 ... 0x4f: /* cmov */
2412 c->dst.val = c->dst.orig_val = c->src.val;
2413 if (!test_cc(c->b, ctxt->eflags))
2414 c->dst.type = OP_NONE; /* no writeback */
2415 break;
2416 case 0x80 ... 0x8f: /* jnz rel, etc*/
2417 if (test_cc(c->b, ctxt->eflags))
2418 jmp_rel(c, c->src.val);
2419 c->dst.type = OP_NONE;
2420 break;
2421 case 0xa0: /* push fs */
2422 emulate_push_sreg(ctxt, VCPU_SREG_FS);
2423 break;
2424 case 0xa1: /* pop fs */
2425 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
2426 if (rc != 0)
2427 goto done;
2428 break;
2429 case 0xa3:
2430 bt: /* bt */
2431 c->dst.type = OP_NONE;
2432 /* only subword offset */
2433 c->src.val &= (c->dst.bytes << 3) - 1;
2434 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
2435 break;
2436 case 0xa4: /* shld imm8, r, r/m */
2437 case 0xa5: /* shld cl, r, r/m */
2438 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2439 break;
2440 case 0xa8: /* push gs */
2441 emulate_push_sreg(ctxt, VCPU_SREG_GS);
2442 break;
2443 case 0xa9: /* pop gs */
2444 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
2445 if (rc != 0)
2446 goto done;
2447 break;
2448 case 0xab:
2449 bts: /* bts */
2450 /* only subword offset */
2451 c->src.val &= (c->dst.bytes << 3) - 1;
2452 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
2453 break;
2454 case 0xac: /* shrd imm8, r, r/m */
2455 case 0xad: /* shrd cl, r, r/m */
2456 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2457 break;
2458 case 0xae: /* clflush */
2459 break;
2460 case 0xb0 ... 0xb1: /* cmpxchg */
2461 /*
2462 * Save real source value, then compare EAX against
2463 * destination.
2464 */
2465 c->src.orig_val = c->src.val;
2466 c->src.val = c->regs[VCPU_REGS_RAX];
2467 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2468 if (ctxt->eflags & EFLG_ZF) {
2469 /* Success: write back to memory. */
2470 c->dst.val = c->src.orig_val;
2471 } else {
2472 /* Failure: write the value we saw to EAX. */
2473 c->dst.type = OP_REG;
2474 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2475 }
2476 break;
2477 case 0xb3:
2478 btr: /* btr */
2479 /* only subword offset */
2480 c->src.val &= (c->dst.bytes << 3) - 1;
2481 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
2482 break;
2483 case 0xb6 ... 0xb7: /* movzx */
2484 c->dst.bytes = c->op_bytes;
2485 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2486 : (u16) c->src.val;
2487 break;
2488 case 0xba: /* Grp8 */
2489 switch (c->modrm_reg & 3) {
2490 case 0:
2491 goto bt;
2492 case 1:
2493 goto bts;
2494 case 2:
2495 goto btr;
2496 case 3:
2497 goto btc;
2498 }
2499 break;
2500 case 0xbb:
2501 btc: /* btc */
2502 /* only subword offset */
2503 c->src.val &= (c->dst.bytes << 3) - 1;
2504 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
2505 break;
2506 case 0xbe ... 0xbf: /* movsx */
2507 c->dst.bytes = c->op_bytes;
2508 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2509 (s16) c->src.val;
2510 break;
2511 case 0xc3: /* movnti */
2512 c->dst.bytes = c->op_bytes;
2513 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2514 (u64) c->src.val;
2515 break;
2516 case 0xc7: /* Grp9 (cmpxchg8b) */
2517 rc = emulate_grp9(ctxt, ops, memop);
2518 if (rc != 0)
2519 goto done;
2520 c->dst.type = OP_NONE;
2521 break;
2522 }
2523 goto writeback;
2524
2525 cannot_emulate:
2526 DPRINTF("Cannot emulate %02x\n", c->b);
2527 c->eip = saved_eip;
2528 return -1;
2529 }
Linux kernel - Deliverables
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