1 /******************************************************************************
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
6 * Copyright (c) 2005 Keir Fraser
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
26 #include <public/xen.h>
27 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
29 #include <linux/kvm_host.h>
30 #include "kvm_cache_regs.h"
31 #define DPRINTF(x...) do {} while (0)
33 #include <linux/module.h>
34 #include <asm/kvm_emulate.h>
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
48 /* Operand sizes: 8-bit operands or specified/overridden size. */
49 #define ByteOp (1<<0) /* 8-bit operands. */
50 /* Destination operand type. */
51 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
52 #define DstReg (2<<1) /* Register operand. */
53 #define DstMem (3<<1) /* Memory operand. */
54 #define DstAcc (4<<1) /* Destination Accumulator */
55 #define DstDI (5<<1) /* Destination is in ES:(E)DI */
56 #define DstMem64 (6<<1) /* 64bit memory operand */
57 #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
58 #define DstMask (7<<1)
59 /* Source operand type. */
60 #define SrcNone (0<<4) /* No source operand. */
61 #define SrcReg (1<<4) /* Register operand. */
62 #define SrcMem (2<<4) /* Memory operand. */
63 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65 #define SrcImm (5<<4) /* Immediate operand. */
66 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
67 #define SrcOne (7<<4) /* Implied '1' */
68 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
69 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
70 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */
71 #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72 #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
73 #define SrcAcc (0xd<<4) /* Source Accumulator */
74 #define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
75 #define SrcMask (0xf<<4)
76 /* Generic ModRM decode. */
78 /* Destination is only written; never read. */
81 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
82 #define String (1<<12) /* String instruction (rep capable) */
83 #define Stack (1<<13) /* Stack instruction (push/pop) */
84 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
85 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
87 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
88 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
89 #define Undefined (1<<25) /* No Such Instruction */
90 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
91 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
93 /* Source 2 operand type */
94 #define Src2None (0<<29)
95 #define Src2CL (1<<29)
96 #define Src2ImmByte (2<<29)
97 #define Src2One (3<<29)
98 #define Src2Imm (4<<29)
99 #define Src2Mask (7<<29)
101 #define X2(x...) x, x
102 #define X3(x...) X2(x), x
103 #define X4(x...) X2(x), X2(x)
104 #define X5(x...) X4(x), x
105 #define X6(x...) X4(x), X2(x)
106 #define X7(x...) X4(x), X3(x)
107 #define X8(x...) X4(x), X4(x)
108 #define X16(x...) X8(x), X8(x)
113 int (*execute
)(struct x86_emulate_ctxt
*ctxt
);
114 struct opcode
*group
;
115 struct group_dual
*gdual
;
120 struct opcode mod012
[8];
121 struct opcode mod3
[8];
124 /* EFLAGS bit definitions. */
125 #define EFLG_ID (1<<21)
126 #define EFLG_VIP (1<<20)
127 #define EFLG_VIF (1<<19)
128 #define EFLG_AC (1<<18)
129 #define EFLG_VM (1<<17)
130 #define EFLG_RF (1<<16)
131 #define EFLG_IOPL (3<<12)
132 #define EFLG_NT (1<<14)
133 #define EFLG_OF (1<<11)
134 #define EFLG_DF (1<<10)
135 #define EFLG_IF (1<<9)
136 #define EFLG_TF (1<<8)
137 #define EFLG_SF (1<<7)
138 #define EFLG_ZF (1<<6)
139 #define EFLG_AF (1<<4)
140 #define EFLG_PF (1<<2)
141 #define EFLG_CF (1<<0)
143 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
144 #define EFLG_RESERVED_ONE_MASK 2
147 * Instruction emulation:
148 * Most instructions are emulated directly via a fragment of inline assembly
149 * code. This allows us to save/restore EFLAGS and thus very easily pick up
150 * any modified flags.
153 #if defined(CONFIG_X86_64)
154 #define _LO32 "k" /* force 32-bit operand */
155 #define _STK "%%rsp" /* stack pointer */
156 #elif defined(__i386__)
157 #define _LO32 "" /* force 32-bit operand */
158 #define _STK "%%esp" /* stack pointer */
162 * These EFLAGS bits are restored from saved value during emulation, and
163 * any changes are written back to the saved value after emulation.
165 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
167 /* Before executing instruction: restore necessary bits in EFLAGS. */
168 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
169 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
170 "movl %"_sav",%"_LO32 _tmp"; " \
173 "movl %"_msk",%"_LO32 _tmp"; " \
174 "andl %"_LO32 _tmp",("_STK"); " \
176 "notl %"_LO32 _tmp"; " \
177 "andl %"_LO32 _tmp",("_STK"); " \
178 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
180 "orl %"_LO32 _tmp",("_STK"); " \
184 /* After executing instruction: write-back necessary bits in EFLAGS. */
185 #define _POST_EFLAGS(_sav, _msk, _tmp) \
186 /* _sav |= EFLAGS & _msk; */ \
189 "andl %"_msk",%"_LO32 _tmp"; " \
190 "orl %"_LO32 _tmp",%"_sav"; "
198 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
200 __asm__ __volatile__ ( \
201 _PRE_EFLAGS("0", "4", "2") \
202 _op _suffix " %"_x"3,%1; " \
203 _POST_EFLAGS("0", "4", "2") \
204 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
206 : _y ((_src).val), "i" (EFLAGS_MASK)); \
210 /* Raw emulation: instruction has two explicit operands. */
211 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
213 unsigned long _tmp; \
215 switch ((_dst).bytes) { \
217 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
220 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
223 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
228 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
230 unsigned long _tmp; \
231 switch ((_dst).bytes) { \
233 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
236 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
237 _wx, _wy, _lx, _ly, _qx, _qy); \
242 /* Source operand is byte-sized and may be restricted to just %cl. */
243 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
244 __emulate_2op(_op, _src, _dst, _eflags, \
245 "b", "c", "b", "c", "b", "c", "b", "c")
247 /* Source operand is byte, word, long or quad sized. */
248 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
249 __emulate_2op(_op, _src, _dst, _eflags, \
250 "b", "q", "w", "r", _LO32, "r", "", "r")
252 /* Source operand is word, long or quad sized. */
253 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
254 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
255 "w", "r", _LO32, "r", "", "r")
257 /* Instruction has three operands and one operand is stored in ECX register */
258 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
260 unsigned long _tmp; \
261 _type _clv = (_cl).val; \
262 _type _srcv = (_src).val; \
263 _type _dstv = (_dst).val; \
265 __asm__ __volatile__ ( \
266 _PRE_EFLAGS("0", "5", "2") \
267 _op _suffix " %4,%1 \n" \
268 _POST_EFLAGS("0", "5", "2") \
269 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
270 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
273 (_cl).val = (unsigned long) _clv; \
274 (_src).val = (unsigned long) _srcv; \
275 (_dst).val = (unsigned long) _dstv; \
278 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
280 switch ((_dst).bytes) { \
282 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
283 "w", unsigned short); \
286 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
287 "l", unsigned int); \
290 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
291 "q", unsigned long)); \
296 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
298 unsigned long _tmp; \
300 __asm__ __volatile__ ( \
301 _PRE_EFLAGS("0", "3", "2") \
302 _op _suffix " %1; " \
303 _POST_EFLAGS("0", "3", "2") \
304 : "=m" (_eflags), "+m" ((_dst).val), \
306 : "i" (EFLAGS_MASK)); \
309 /* Instruction has only one explicit operand (no source operand). */
310 #define emulate_1op(_op, _dst, _eflags) \
312 switch ((_dst).bytes) { \
313 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
314 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
315 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
316 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
320 #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
322 unsigned long _tmp; \
324 __asm__ __volatile__ ( \
325 _PRE_EFLAGS("0", "4", "1") \
326 _op _suffix " %5; " \
327 _POST_EFLAGS("0", "4", "1") \
328 : "=m" (_eflags), "=&r" (_tmp), \
329 "+a" (_rax), "+d" (_rdx) \
330 : "i" (EFLAGS_MASK), "m" ((_src).val), \
331 "a" (_rax), "d" (_rdx)); \
334 #define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
336 unsigned long _tmp; \
338 __asm__ __volatile__ ( \
339 _PRE_EFLAGS("0", "5", "1") \
341 _op _suffix " %6; " \
343 _POST_EFLAGS("0", "5", "1") \
344 ".pushsection .fixup,\"ax\" \n\t" \
345 "3: movb $1, %4 \n\t" \
348 _ASM_EXTABLE(1b, 3b) \
349 : "=m" (_eflags), "=&r" (_tmp), \
350 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
351 : "i" (EFLAGS_MASK), "m" ((_src).val), \
352 "a" (_rax), "d" (_rdx)); \
355 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
356 #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
358 switch((_src).bytes) { \
359 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
360 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
361 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
362 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
366 #define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
368 switch((_src).bytes) { \
370 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
371 _eflags, "b", _ex); \
374 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
375 _eflags, "w", _ex); \
378 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
379 _eflags, "l", _ex); \
382 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
383 _eflags, "q", _ex)); \
388 /* Fetch next part of the instruction being emulated. */
389 #define insn_fetch(_type, _size, _eip) \
390 ({ unsigned long _x; \
391 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
392 if (rc != X86EMUL_CONTINUE) \
398 #define insn_fetch_arr(_arr, _size, _eip) \
399 ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
400 if (rc != X86EMUL_CONTINUE) \
405 static inline unsigned long ad_mask(struct decode_cache
*c
)
407 return (1UL << (c
->ad_bytes
<< 3)) - 1;
410 /* Access/update address held in a register, based on addressing mode. */
411 static inline unsigned long
412 address_mask(struct decode_cache
*c
, unsigned long reg
)
414 if (c
->ad_bytes
== sizeof(unsigned long))
417 return reg
& ad_mask(c
);
420 static inline unsigned long
421 register_address(struct decode_cache
*c
, unsigned long base
, unsigned long reg
)
423 return base
+ address_mask(c
, reg
);
427 register_address_increment(struct decode_cache
*c
, unsigned long *reg
, int inc
)
429 if (c
->ad_bytes
== sizeof(unsigned long))
432 *reg
= (*reg
& ~ad_mask(c
)) | ((*reg
+ inc
) & ad_mask(c
));
435 static inline void jmp_rel(struct decode_cache
*c
, int rel
)
437 register_address_increment(c
, &c
->eip
, rel
);
440 static void set_seg_override(struct decode_cache
*c
, int seg
)
442 c
->has_seg_override
= true;
443 c
->seg_override
= seg
;
446 static unsigned long seg_base(struct x86_emulate_ctxt
*ctxt
,
447 struct x86_emulate_ops
*ops
, int seg
)
449 if (ctxt
->mode
== X86EMUL_MODE_PROT64
&& seg
< VCPU_SREG_FS
)
452 return ops
->get_cached_segment_base(seg
, ctxt
->vcpu
);
455 static unsigned long seg_override_base(struct x86_emulate_ctxt
*ctxt
,
456 struct x86_emulate_ops
*ops
,
457 struct decode_cache
*c
)
459 if (!c
->has_seg_override
)
462 return seg_base(ctxt
, ops
, c
->seg_override
);
465 static unsigned long es_base(struct x86_emulate_ctxt
*ctxt
,
466 struct x86_emulate_ops
*ops
)
468 return seg_base(ctxt
, ops
, VCPU_SREG_ES
);
471 static unsigned long ss_base(struct x86_emulate_ctxt
*ctxt
,
472 struct x86_emulate_ops
*ops
)
474 return seg_base(ctxt
, ops
, VCPU_SREG_SS
);
477 static void emulate_exception(struct x86_emulate_ctxt
*ctxt
, int vec
,
478 u32 error
, bool valid
)
480 ctxt
->exception
= vec
;
481 ctxt
->error_code
= error
;
482 ctxt
->error_code_valid
= valid
;
485 static void emulate_gp(struct x86_emulate_ctxt
*ctxt
, int err
)
487 emulate_exception(ctxt
, GP_VECTOR
, err
, true);
490 static void emulate_pf(struct x86_emulate_ctxt
*ctxt
, unsigned long addr
,
494 emulate_exception(ctxt
, PF_VECTOR
, err
, true);
497 static void emulate_ud(struct x86_emulate_ctxt
*ctxt
)
499 emulate_exception(ctxt
, UD_VECTOR
, 0, false);
502 static void emulate_ts(struct x86_emulate_ctxt
*ctxt
, int err
)
504 emulate_exception(ctxt
, TS_VECTOR
, err
, true);
507 static int emulate_de(struct x86_emulate_ctxt
*ctxt
)
509 emulate_exception(ctxt
, DE_VECTOR
, 0, false);
510 return X86EMUL_PROPAGATE_FAULT
;
513 static int do_fetch_insn_byte(struct x86_emulate_ctxt
*ctxt
,
514 struct x86_emulate_ops
*ops
,
515 unsigned long eip
, u8
*dest
)
517 struct fetch_cache
*fc
= &ctxt
->decode
.fetch
;
521 if (eip
== fc
->end
) {
522 cur_size
= fc
->end
- fc
->start
;
523 size
= min(15UL - cur_size
, PAGE_SIZE
- offset_in_page(eip
));
524 rc
= ops
->fetch(ctxt
->cs_base
+ eip
, fc
->data
+ cur_size
,
525 size
, ctxt
->vcpu
, NULL
);
526 if (rc
!= X86EMUL_CONTINUE
)
530 *dest
= fc
->data
[eip
- fc
->start
];
531 return X86EMUL_CONTINUE
;
534 static int do_insn_fetch(struct x86_emulate_ctxt
*ctxt
,
535 struct x86_emulate_ops
*ops
,
536 unsigned long eip
, void *dest
, unsigned size
)
540 /* x86 instructions are limited to 15 bytes. */
541 if (eip
+ size
- ctxt
->eip
> 15)
542 return X86EMUL_UNHANDLEABLE
;
544 rc
= do_fetch_insn_byte(ctxt
, ops
, eip
++, dest
++);
545 if (rc
!= X86EMUL_CONTINUE
)
548 return X86EMUL_CONTINUE
;
552 * Given the 'reg' portion of a ModRM byte, and a register block, return a
553 * pointer into the block that addresses the relevant register.
554 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
556 static void *decode_register(u8 modrm_reg
, unsigned long *regs
,
561 p
= ®s
[modrm_reg
];
562 if (highbyte_regs
&& modrm_reg
>= 4 && modrm_reg
< 8)
563 p
= (unsigned char *)®s
[modrm_reg
& 3] + 1;
567 static int read_descriptor(struct x86_emulate_ctxt
*ctxt
,
568 struct x86_emulate_ops
*ops
,
570 u16
*size
, unsigned long *address
, int op_bytes
)
577 rc
= ops
->read_std(addr
, (unsigned long *)size
, 2, ctxt
->vcpu
, NULL
);
578 if (rc
!= X86EMUL_CONTINUE
)
580 rc
= ops
->read_std(addr
+ 2, address
, op_bytes
, ctxt
->vcpu
, NULL
);
584 static int test_cc(unsigned int condition
, unsigned int flags
)
588 switch ((condition
& 15) >> 1) {
590 rc
|= (flags
& EFLG_OF
);
592 case 1: /* b/c/nae */
593 rc
|= (flags
& EFLG_CF
);
596 rc
|= (flags
& EFLG_ZF
);
599 rc
|= (flags
& (EFLG_CF
|EFLG_ZF
));
602 rc
|= (flags
& EFLG_SF
);
605 rc
|= (flags
& EFLG_PF
);
608 rc
|= (flags
& EFLG_ZF
);
611 rc
|= (!(flags
& EFLG_SF
) != !(flags
& EFLG_OF
));
615 /* Odd condition identifiers (lsb == 1) have inverted sense. */
616 return (!!rc
^ (condition
& 1));
619 static void fetch_register_operand(struct operand
*op
)
623 op
->val
= *(u8
*)op
->addr
.reg
;
626 op
->val
= *(u16
*)op
->addr
.reg
;
629 op
->val
= *(u32
*)op
->addr
.reg
;
632 op
->val
= *(u64
*)op
->addr
.reg
;
637 static void decode_register_operand(struct operand
*op
,
638 struct decode_cache
*c
,
641 unsigned reg
= c
->modrm_reg
;
642 int highbyte_regs
= c
->rex_prefix
== 0;
645 reg
= (c
->b
& 7) | ((c
->rex_prefix
& 1) << 3);
647 if ((c
->d
& ByteOp
) && !inhibit_bytereg
) {
648 op
->addr
.reg
= decode_register(reg
, c
->regs
, highbyte_regs
);
651 op
->addr
.reg
= decode_register(reg
, c
->regs
, 0);
652 op
->bytes
= c
->op_bytes
;
654 fetch_register_operand(op
);
655 op
->orig_val
= op
->val
;
658 static int decode_modrm(struct x86_emulate_ctxt
*ctxt
,
659 struct x86_emulate_ops
*ops
,
662 struct decode_cache
*c
= &ctxt
->decode
;
664 int index_reg
= 0, base_reg
= 0, scale
;
665 int rc
= X86EMUL_CONTINUE
;
669 c
->modrm_reg
= (c
->rex_prefix
& 4) << 1; /* REX.R */
670 index_reg
= (c
->rex_prefix
& 2) << 2; /* REX.X */
671 c
->modrm_rm
= base_reg
= (c
->rex_prefix
& 1) << 3; /* REG.B */
674 c
->modrm
= insn_fetch(u8
, 1, c
->eip
);
675 c
->modrm_mod
|= (c
->modrm
& 0xc0) >> 6;
676 c
->modrm_reg
|= (c
->modrm
& 0x38) >> 3;
677 c
->modrm_rm
|= (c
->modrm
& 0x07);
678 c
->modrm_seg
= VCPU_SREG_DS
;
680 if (c
->modrm_mod
== 3) {
682 op
->bytes
= (c
->d
& ByteOp
) ? 1 : c
->op_bytes
;
683 op
->addr
.reg
= decode_register(c
->modrm_rm
,
684 c
->regs
, c
->d
& ByteOp
);
685 fetch_register_operand(op
);
691 if (c
->ad_bytes
== 2) {
692 unsigned bx
= c
->regs
[VCPU_REGS_RBX
];
693 unsigned bp
= c
->regs
[VCPU_REGS_RBP
];
694 unsigned si
= c
->regs
[VCPU_REGS_RSI
];
695 unsigned di
= c
->regs
[VCPU_REGS_RDI
];
697 /* 16-bit ModR/M decode. */
698 switch (c
->modrm_mod
) {
700 if (c
->modrm_rm
== 6)
701 modrm_ea
+= insn_fetch(u16
, 2, c
->eip
);
704 modrm_ea
+= insn_fetch(s8
, 1, c
->eip
);
707 modrm_ea
+= insn_fetch(u16
, 2, c
->eip
);
710 switch (c
->modrm_rm
) {
730 if (c
->modrm_mod
!= 0)
737 if (c
->modrm_rm
== 2 || c
->modrm_rm
== 3 ||
738 (c
->modrm_rm
== 6 && c
->modrm_mod
!= 0))
739 c
->modrm_seg
= VCPU_SREG_SS
;
740 modrm_ea
= (u16
)modrm_ea
;
742 /* 32/64-bit ModR/M decode. */
743 if ((c
->modrm_rm
& 7) == 4) {
744 sib
= insn_fetch(u8
, 1, c
->eip
);
745 index_reg
|= (sib
>> 3) & 7;
749 if ((base_reg
& 7) == 5 && c
->modrm_mod
== 0)
750 modrm_ea
+= insn_fetch(s32
, 4, c
->eip
);
752 modrm_ea
+= c
->regs
[base_reg
];
754 modrm_ea
+= c
->regs
[index_reg
] << scale
;
755 } else if ((c
->modrm_rm
& 7) == 5 && c
->modrm_mod
== 0) {
756 if (ctxt
->mode
== X86EMUL_MODE_PROT64
)
759 modrm_ea
+= c
->regs
[c
->modrm_rm
];
760 switch (c
->modrm_mod
) {
762 if (c
->modrm_rm
== 5)
763 modrm_ea
+= insn_fetch(s32
, 4, c
->eip
);
766 modrm_ea
+= insn_fetch(s8
, 1, c
->eip
);
769 modrm_ea
+= insn_fetch(s32
, 4, c
->eip
);
773 op
->addr
.mem
= modrm_ea
;
778 static int decode_abs(struct x86_emulate_ctxt
*ctxt
,
779 struct x86_emulate_ops
*ops
,
782 struct decode_cache
*c
= &ctxt
->decode
;
783 int rc
= X86EMUL_CONTINUE
;
786 switch (c
->ad_bytes
) {
788 op
->addr
.mem
= insn_fetch(u16
, 2, c
->eip
);
791 op
->addr
.mem
= insn_fetch(u32
, 4, c
->eip
);
794 op
->addr
.mem
= insn_fetch(u64
, 8, c
->eip
);
801 static void fetch_bit_operand(struct decode_cache
*c
)
805 if (c
->dst
.type
== OP_MEM
&& c
->src
.type
== OP_REG
) {
806 mask
= ~(c
->dst
.bytes
* 8 - 1);
808 if (c
->src
.bytes
== 2)
809 sv
= (s16
)c
->src
.val
& (s16
)mask
;
810 else if (c
->src
.bytes
== 4)
811 sv
= (s32
)c
->src
.val
& (s32
)mask
;
813 c
->dst
.addr
.mem
+= (sv
>> 3);
816 /* only subword offset */
817 c
->src
.val
&= (c
->dst
.bytes
<< 3) - 1;
820 static int read_emulated(struct x86_emulate_ctxt
*ctxt
,
821 struct x86_emulate_ops
*ops
,
822 unsigned long addr
, void *dest
, unsigned size
)
825 struct read_cache
*mc
= &ctxt
->decode
.mem_read
;
829 int n
= min(size
, 8u);
831 if (mc
->pos
< mc
->end
)
834 rc
= ops
->read_emulated(addr
, mc
->data
+ mc
->end
, n
, &err
,
836 if (rc
== X86EMUL_PROPAGATE_FAULT
)
837 emulate_pf(ctxt
, addr
, err
);
838 if (rc
!= X86EMUL_CONTINUE
)
843 memcpy(dest
, mc
->data
+ mc
->pos
, n
);
848 return X86EMUL_CONTINUE
;
851 static int pio_in_emulated(struct x86_emulate_ctxt
*ctxt
,
852 struct x86_emulate_ops
*ops
,
853 unsigned int size
, unsigned short port
,
856 struct read_cache
*rc
= &ctxt
->decode
.io_read
;
858 if (rc
->pos
== rc
->end
) { /* refill pio read ahead */
859 struct decode_cache
*c
= &ctxt
->decode
;
860 unsigned int in_page
, n
;
861 unsigned int count
= c
->rep_prefix
?
862 address_mask(c
, c
->regs
[VCPU_REGS_RCX
]) : 1;
863 in_page
= (ctxt
->eflags
& EFLG_DF
) ?
864 offset_in_page(c
->regs
[VCPU_REGS_RDI
]) :
865 PAGE_SIZE
- offset_in_page(c
->regs
[VCPU_REGS_RDI
]);
866 n
= min(min(in_page
, (unsigned int)sizeof(rc
->data
)) / size
,
870 rc
->pos
= rc
->end
= 0;
871 if (!ops
->pio_in_emulated(size
, port
, rc
->data
, n
, ctxt
->vcpu
))
876 memcpy(dest
, rc
->data
+ rc
->pos
, size
);
881 static u32
desc_limit_scaled(struct desc_struct
*desc
)
883 u32 limit
= get_desc_limit(desc
);
885 return desc
->g
? (limit
<< 12) | 0xfff : limit
;
888 static void get_descriptor_table_ptr(struct x86_emulate_ctxt
*ctxt
,
889 struct x86_emulate_ops
*ops
,
890 u16 selector
, struct desc_ptr
*dt
)
892 if (selector
& 1 << 2) {
893 struct desc_struct desc
;
894 memset (dt
, 0, sizeof *dt
);
895 if (!ops
->get_cached_descriptor(&desc
, VCPU_SREG_LDTR
, ctxt
->vcpu
))
898 dt
->size
= desc_limit_scaled(&desc
); /* what if limit > 65535? */
899 dt
->address
= get_desc_base(&desc
);
901 ops
->get_gdt(dt
, ctxt
->vcpu
);
904 /* allowed just for 8 bytes segments */
905 static int read_segment_descriptor(struct x86_emulate_ctxt
*ctxt
,
906 struct x86_emulate_ops
*ops
,
907 u16 selector
, struct desc_struct
*desc
)
910 u16 index
= selector
>> 3;
915 get_descriptor_table_ptr(ctxt
, ops
, selector
, &dt
);
917 if (dt
.size
< index
* 8 + 7) {
918 emulate_gp(ctxt
, selector
& 0xfffc);
919 return X86EMUL_PROPAGATE_FAULT
;
921 addr
= dt
.address
+ index
* 8;
922 ret
= ops
->read_std(addr
, desc
, sizeof *desc
, ctxt
->vcpu
, &err
);
923 if (ret
== X86EMUL_PROPAGATE_FAULT
)
924 emulate_pf(ctxt
, addr
, err
);
929 /* allowed just for 8 bytes segments */
930 static int write_segment_descriptor(struct x86_emulate_ctxt
*ctxt
,
931 struct x86_emulate_ops
*ops
,
932 u16 selector
, struct desc_struct
*desc
)
935 u16 index
= selector
>> 3;
940 get_descriptor_table_ptr(ctxt
, ops
, selector
, &dt
);
942 if (dt
.size
< index
* 8 + 7) {
943 emulate_gp(ctxt
, selector
& 0xfffc);
944 return X86EMUL_PROPAGATE_FAULT
;
947 addr
= dt
.address
+ index
* 8;
948 ret
= ops
->write_std(addr
, desc
, sizeof *desc
, ctxt
->vcpu
, &err
);
949 if (ret
== X86EMUL_PROPAGATE_FAULT
)
950 emulate_pf(ctxt
, addr
, err
);
955 static int load_segment_descriptor(struct x86_emulate_ctxt
*ctxt
,
956 struct x86_emulate_ops
*ops
,
957 u16 selector
, int seg
)
959 struct desc_struct seg_desc
;
961 unsigned err_vec
= GP_VECTOR
;
963 bool null_selector
= !(selector
& ~0x3); /* 0000-0003 are null */
966 memset(&seg_desc
, 0, sizeof seg_desc
);
968 if ((seg
<= VCPU_SREG_GS
&& ctxt
->mode
== X86EMUL_MODE_VM86
)
969 || ctxt
->mode
== X86EMUL_MODE_REAL
) {
970 /* set real mode segment descriptor */
971 set_desc_base(&seg_desc
, selector
<< 4);
972 set_desc_limit(&seg_desc
, 0xffff);
979 /* NULL selector is not valid for TR, CS and SS */
980 if ((seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
|| seg
== VCPU_SREG_TR
)
984 /* TR should be in GDT only */
985 if (seg
== VCPU_SREG_TR
&& (selector
& (1 << 2)))
988 if (null_selector
) /* for NULL selector skip all following checks */
991 ret
= read_segment_descriptor(ctxt
, ops
, selector
, &seg_desc
);
992 if (ret
!= X86EMUL_CONTINUE
)
995 err_code
= selector
& 0xfffc;
998 /* can't load system descriptor into segment selecor */
999 if (seg
<= VCPU_SREG_GS
&& !seg_desc
.s
)
1003 err_vec
= (seg
== VCPU_SREG_SS
) ? SS_VECTOR
: NP_VECTOR
;
1009 cpl
= ops
->cpl(ctxt
->vcpu
);
1014 * segment is not a writable data segment or segment
1015 * selector's RPL != CPL or segment selector's RPL != CPL
1017 if (rpl
!= cpl
|| (seg_desc
.type
& 0xa) != 0x2 || dpl
!= cpl
)
1021 if (!(seg_desc
.type
& 8))
1024 if (seg_desc
.type
& 4) {
1030 if (rpl
> cpl
|| dpl
!= cpl
)
1033 /* CS(RPL) <- CPL */
1034 selector
= (selector
& 0xfffc) | cpl
;
1037 if (seg_desc
.s
|| (seg_desc
.type
!= 1 && seg_desc
.type
!= 9))
1040 case VCPU_SREG_LDTR
:
1041 if (seg_desc
.s
|| seg_desc
.type
!= 2)
1044 default: /* DS, ES, FS, or GS */
1046 * segment is not a data or readable code segment or
1047 * ((segment is a data or nonconforming code segment)
1048 * and (both RPL and CPL > DPL))
1050 if ((seg_desc
.type
& 0xa) == 0x8 ||
1051 (((seg_desc
.type
& 0xc) != 0xc) &&
1052 (rpl
> dpl
&& cpl
> dpl
)))
1058 /* mark segment as accessed */
1060 ret
= write_segment_descriptor(ctxt
, ops
, selector
, &seg_desc
);
1061 if (ret
!= X86EMUL_CONTINUE
)
1065 ops
->set_segment_selector(selector
, seg
, ctxt
->vcpu
);
1066 ops
->set_cached_descriptor(&seg_desc
, seg
, ctxt
->vcpu
);
1067 return X86EMUL_CONTINUE
;
1069 emulate_exception(ctxt
, err_vec
, err_code
, true);
1070 return X86EMUL_PROPAGATE_FAULT
;
1073 static void write_register_operand(struct operand
*op
)
1075 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1076 switch (op
->bytes
) {
1078 *(u8
*)op
->addr
.reg
= (u8
)op
->val
;
1081 *(u16
*)op
->addr
.reg
= (u16
)op
->val
;
1084 *op
->addr
.reg
= (u32
)op
->val
;
1085 break; /* 64b: zero-extend */
1087 *op
->addr
.reg
= op
->val
;
1092 static inline int writeback(struct x86_emulate_ctxt
*ctxt
,
1093 struct x86_emulate_ops
*ops
)
1096 struct decode_cache
*c
= &ctxt
->decode
;
1099 switch (c
->dst
.type
) {
1101 write_register_operand(&c
->dst
);
1105 rc
= ops
->cmpxchg_emulated(
1113 rc
= ops
->write_emulated(
1119 if (rc
== X86EMUL_PROPAGATE_FAULT
)
1120 emulate_pf(ctxt
, c
->dst
.addr
.mem
, err
);
1121 if (rc
!= X86EMUL_CONTINUE
)
1130 return X86EMUL_CONTINUE
;
1133 static inline void emulate_push(struct x86_emulate_ctxt
*ctxt
,
1134 struct x86_emulate_ops
*ops
)
1136 struct decode_cache
*c
= &ctxt
->decode
;
1138 c
->dst
.type
= OP_MEM
;
1139 c
->dst
.bytes
= c
->op_bytes
;
1140 c
->dst
.val
= c
->src
.val
;
1141 register_address_increment(c
, &c
->regs
[VCPU_REGS_RSP
], -c
->op_bytes
);
1142 c
->dst
.addr
.mem
= register_address(c
, ss_base(ctxt
, ops
),
1143 c
->regs
[VCPU_REGS_RSP
]);
1146 static int emulate_pop(struct x86_emulate_ctxt
*ctxt
,
1147 struct x86_emulate_ops
*ops
,
1148 void *dest
, int len
)
1150 struct decode_cache
*c
= &ctxt
->decode
;
1153 rc
= read_emulated(ctxt
, ops
, register_address(c
, ss_base(ctxt
, ops
),
1154 c
->regs
[VCPU_REGS_RSP
]),
1156 if (rc
!= X86EMUL_CONTINUE
)
1159 register_address_increment(c
, &c
->regs
[VCPU_REGS_RSP
], len
);
1163 static int emulate_popf(struct x86_emulate_ctxt
*ctxt
,
1164 struct x86_emulate_ops
*ops
,
1165 void *dest
, int len
)
1168 unsigned long val
, change_mask
;
1169 int iopl
= (ctxt
->eflags
& X86_EFLAGS_IOPL
) >> IOPL_SHIFT
;
1170 int cpl
= ops
->cpl(ctxt
->vcpu
);
1172 rc
= emulate_pop(ctxt
, ops
, &val
, len
);
1173 if (rc
!= X86EMUL_CONTINUE
)
1176 change_mask
= EFLG_CF
| EFLG_PF
| EFLG_AF
| EFLG_ZF
| EFLG_SF
| EFLG_OF
1177 | EFLG_TF
| EFLG_DF
| EFLG_NT
| EFLG_RF
| EFLG_AC
| EFLG_ID
;
1179 switch(ctxt
->mode
) {
1180 case X86EMUL_MODE_PROT64
:
1181 case X86EMUL_MODE_PROT32
:
1182 case X86EMUL_MODE_PROT16
:
1184 change_mask
|= EFLG_IOPL
;
1186 change_mask
|= EFLG_IF
;
1188 case X86EMUL_MODE_VM86
:
1190 emulate_gp(ctxt
, 0);
1191 return X86EMUL_PROPAGATE_FAULT
;
1193 change_mask
|= EFLG_IF
;
1195 default: /* real mode */
1196 change_mask
|= (EFLG_IOPL
| EFLG_IF
);
1200 *(unsigned long *)dest
=
1201 (ctxt
->eflags
& ~change_mask
) | (val
& change_mask
);
1206 static void emulate_push_sreg(struct x86_emulate_ctxt
*ctxt
,
1207 struct x86_emulate_ops
*ops
, int seg
)
1209 struct decode_cache
*c
= &ctxt
->decode
;
1211 c
->src
.val
= ops
->get_segment_selector(seg
, ctxt
->vcpu
);
1213 emulate_push(ctxt
, ops
);
1216 static int emulate_pop_sreg(struct x86_emulate_ctxt
*ctxt
,
1217 struct x86_emulate_ops
*ops
, int seg
)
1219 struct decode_cache
*c
= &ctxt
->decode
;
1220 unsigned long selector
;
1223 rc
= emulate_pop(ctxt
, ops
, &selector
, c
->op_bytes
);
1224 if (rc
!= X86EMUL_CONTINUE
)
1227 rc
= load_segment_descriptor(ctxt
, ops
, (u16
)selector
, seg
);
1231 static int emulate_pusha(struct x86_emulate_ctxt
*ctxt
,
1232 struct x86_emulate_ops
*ops
)
1234 struct decode_cache
*c
= &ctxt
->decode
;
1235 unsigned long old_esp
= c
->regs
[VCPU_REGS_RSP
];
1236 int rc
= X86EMUL_CONTINUE
;
1237 int reg
= VCPU_REGS_RAX
;
1239 while (reg
<= VCPU_REGS_RDI
) {
1240 (reg
== VCPU_REGS_RSP
) ?
1241 (c
->src
.val
= old_esp
) : (c
->src
.val
= c
->regs
[reg
]);
1243 emulate_push(ctxt
, ops
);
1245 rc
= writeback(ctxt
, ops
);
1246 if (rc
!= X86EMUL_CONTINUE
)
1252 /* Disable writeback. */
1253 c
->dst
.type
= OP_NONE
;
1258 static int emulate_popa(struct x86_emulate_ctxt
*ctxt
,
1259 struct x86_emulate_ops
*ops
)
1261 struct decode_cache
*c
= &ctxt
->decode
;
1262 int rc
= X86EMUL_CONTINUE
;
1263 int reg
= VCPU_REGS_RDI
;
1265 while (reg
>= VCPU_REGS_RAX
) {
1266 if (reg
== VCPU_REGS_RSP
) {
1267 register_address_increment(c
, &c
->regs
[VCPU_REGS_RSP
],
1272 rc
= emulate_pop(ctxt
, ops
, &c
->regs
[reg
], c
->op_bytes
);
1273 if (rc
!= X86EMUL_CONTINUE
)
1280 int emulate_int_real(struct x86_emulate_ctxt
*ctxt
,
1281 struct x86_emulate_ops
*ops
, int irq
)
1283 struct decode_cache
*c
= &ctxt
->decode
;
1291 /* TODO: Add limit checks */
1292 c
->src
.val
= ctxt
->eflags
;
1293 emulate_push(ctxt
, ops
);
1294 rc
= writeback(ctxt
, ops
);
1295 if (rc
!= X86EMUL_CONTINUE
)
1298 ctxt
->eflags
&= ~(EFLG_IF
| EFLG_TF
| EFLG_AC
);
1300 c
->src
.val
= ops
->get_segment_selector(VCPU_SREG_CS
, ctxt
->vcpu
);
1301 emulate_push(ctxt
, ops
);
1302 rc
= writeback(ctxt
, ops
);
1303 if (rc
!= X86EMUL_CONTINUE
)
1306 c
->src
.val
= c
->eip
;
1307 emulate_push(ctxt
, ops
);
1308 rc
= writeback(ctxt
, ops
);
1309 if (rc
!= X86EMUL_CONTINUE
)
1312 c
->dst
.type
= OP_NONE
;
1314 ops
->get_idt(&dt
, ctxt
->vcpu
);
1316 eip_addr
= dt
.address
+ (irq
<< 2);
1317 cs_addr
= dt
.address
+ (irq
<< 2) + 2;
1319 rc
= ops
->read_std(cs_addr
, &cs
, 2, ctxt
->vcpu
, &err
);
1320 if (rc
!= X86EMUL_CONTINUE
)
1323 rc
= ops
->read_std(eip_addr
, &eip
, 2, ctxt
->vcpu
, &err
);
1324 if (rc
!= X86EMUL_CONTINUE
)
1327 rc
= load_segment_descriptor(ctxt
, ops
, cs
, VCPU_SREG_CS
);
1328 if (rc
!= X86EMUL_CONTINUE
)
1336 static int emulate_int(struct x86_emulate_ctxt
*ctxt
,
1337 struct x86_emulate_ops
*ops
, int irq
)
1339 switch(ctxt
->mode
) {
1340 case X86EMUL_MODE_REAL
:
1341 return emulate_int_real(ctxt
, ops
, irq
);
1342 case X86EMUL_MODE_VM86
:
1343 case X86EMUL_MODE_PROT16
:
1344 case X86EMUL_MODE_PROT32
:
1345 case X86EMUL_MODE_PROT64
:
1347 /* Protected mode interrupts unimplemented yet */
1348 return X86EMUL_UNHANDLEABLE
;
1352 static int emulate_iret_real(struct x86_emulate_ctxt
*ctxt
,
1353 struct x86_emulate_ops
*ops
)
1355 struct decode_cache
*c
= &ctxt
->decode
;
1356 int rc
= X86EMUL_CONTINUE
;
1357 unsigned long temp_eip
= 0;
1358 unsigned long temp_eflags
= 0;
1359 unsigned long cs
= 0;
1360 unsigned long mask
= EFLG_CF
| EFLG_PF
| EFLG_AF
| EFLG_ZF
| EFLG_SF
| EFLG_TF
|
1361 EFLG_IF
| EFLG_DF
| EFLG_OF
| EFLG_IOPL
| EFLG_NT
| EFLG_RF
|
1362 EFLG_AC
| EFLG_ID
| (1 << 1); /* Last one is the reserved bit */
1363 unsigned long vm86_mask
= EFLG_VM
| EFLG_VIF
| EFLG_VIP
;
1365 /* TODO: Add stack limit check */
1367 rc
= emulate_pop(ctxt
, ops
, &temp_eip
, c
->op_bytes
);
1369 if (rc
!= X86EMUL_CONTINUE
)
1372 if (temp_eip
& ~0xffff) {
1373 emulate_gp(ctxt
, 0);
1374 return X86EMUL_PROPAGATE_FAULT
;
1377 rc
= emulate_pop(ctxt
, ops
, &cs
, c
->op_bytes
);
1379 if (rc
!= X86EMUL_CONTINUE
)
1382 rc
= emulate_pop(ctxt
, ops
, &temp_eflags
, c
->op_bytes
);
1384 if (rc
!= X86EMUL_CONTINUE
)
1387 rc
= load_segment_descriptor(ctxt
, ops
, (u16
)cs
, VCPU_SREG_CS
);
1389 if (rc
!= X86EMUL_CONTINUE
)
1395 if (c
->op_bytes
== 4)
1396 ctxt
->eflags
= ((temp_eflags
& mask
) | (ctxt
->eflags
& vm86_mask
));
1397 else if (c
->op_bytes
== 2) {
1398 ctxt
->eflags
&= ~0xffff;
1399 ctxt
->eflags
|= temp_eflags
;
1402 ctxt
->eflags
&= ~EFLG_RESERVED_ZEROS_MASK
; /* Clear reserved zeros */
1403 ctxt
->eflags
|= EFLG_RESERVED_ONE_MASK
;
1408 static inline int emulate_iret(struct x86_emulate_ctxt
*ctxt
,
1409 struct x86_emulate_ops
* ops
)
1411 switch(ctxt
->mode
) {
1412 case X86EMUL_MODE_REAL
:
1413 return emulate_iret_real(ctxt
, ops
);
1414 case X86EMUL_MODE_VM86
:
1415 case X86EMUL_MODE_PROT16
:
1416 case X86EMUL_MODE_PROT32
:
1417 case X86EMUL_MODE_PROT64
:
1419 /* iret from protected mode unimplemented yet */
1420 return X86EMUL_UNHANDLEABLE
;
1424 static inline int emulate_grp1a(struct x86_emulate_ctxt
*ctxt
,
1425 struct x86_emulate_ops
*ops
)
1427 struct decode_cache
*c
= &ctxt
->decode
;
1429 return emulate_pop(ctxt
, ops
, &c
->dst
.val
, c
->dst
.bytes
);
1432 static inline void emulate_grp2(struct x86_emulate_ctxt
*ctxt
)
1434 struct decode_cache
*c
= &ctxt
->decode
;
1435 switch (c
->modrm_reg
) {
1437 emulate_2op_SrcB("rol", c
->src
, c
->dst
, ctxt
->eflags
);
1440 emulate_2op_SrcB("ror", c
->src
, c
->dst
, ctxt
->eflags
);
1443 emulate_2op_SrcB("rcl", c
->src
, c
->dst
, ctxt
->eflags
);
1446 emulate_2op_SrcB("rcr", c
->src
, c
->dst
, ctxt
->eflags
);
1448 case 4: /* sal/shl */
1449 case 6: /* sal/shl */
1450 emulate_2op_SrcB("sal", c
->src
, c
->dst
, ctxt
->eflags
);
1453 emulate_2op_SrcB("shr", c
->src
, c
->dst
, ctxt
->eflags
);
1456 emulate_2op_SrcB("sar", c
->src
, c
->dst
, ctxt
->eflags
);
1461 static inline int emulate_grp3(struct x86_emulate_ctxt
*ctxt
,
1462 struct x86_emulate_ops
*ops
)
1464 struct decode_cache
*c
= &ctxt
->decode
;
1465 unsigned long *rax
= &c
->regs
[VCPU_REGS_RAX
];
1466 unsigned long *rdx
= &c
->regs
[VCPU_REGS_RDX
];
1469 switch (c
->modrm_reg
) {
1470 case 0 ... 1: /* test */
1471 emulate_2op_SrcV("test", c
->src
, c
->dst
, ctxt
->eflags
);
1474 c
->dst
.val
= ~c
->dst
.val
;
1477 emulate_1op("neg", c
->dst
, ctxt
->eflags
);
1480 emulate_1op_rax_rdx("mul", c
->src
, *rax
, *rdx
, ctxt
->eflags
);
1483 emulate_1op_rax_rdx("imul", c
->src
, *rax
, *rdx
, ctxt
->eflags
);
1486 emulate_1op_rax_rdx_ex("div", c
->src
, *rax
, *rdx
,
1490 emulate_1op_rax_rdx_ex("idiv", c
->src
, *rax
, *rdx
,
1494 return X86EMUL_UNHANDLEABLE
;
1497 return emulate_de(ctxt
);
1498 return X86EMUL_CONTINUE
;
1501 static inline int emulate_grp45(struct x86_emulate_ctxt
*ctxt
,
1502 struct x86_emulate_ops
*ops
)
1504 struct decode_cache
*c
= &ctxt
->decode
;
1506 switch (c
->modrm_reg
) {
1508 emulate_1op("inc", c
->dst
, ctxt
->eflags
);
1511 emulate_1op("dec", c
->dst
, ctxt
->eflags
);
1513 case 2: /* call near abs */ {
1516 c
->eip
= c
->src
.val
;
1517 c
->src
.val
= old_eip
;
1518 emulate_push(ctxt
, ops
);
1521 case 4: /* jmp abs */
1522 c
->eip
= c
->src
.val
;
1525 emulate_push(ctxt
, ops
);
1528 return X86EMUL_CONTINUE
;
1531 static inline int emulate_grp9(struct x86_emulate_ctxt
*ctxt
,
1532 struct x86_emulate_ops
*ops
)
1534 struct decode_cache
*c
= &ctxt
->decode
;
1535 u64 old
= c
->dst
.orig_val64
;
1537 if (((u32
) (old
>> 0) != (u32
) c
->regs
[VCPU_REGS_RAX
]) ||
1538 ((u32
) (old
>> 32) != (u32
) c
->regs
[VCPU_REGS_RDX
])) {
1539 c
->regs
[VCPU_REGS_RAX
] = (u32
) (old
>> 0);
1540 c
->regs
[VCPU_REGS_RDX
] = (u32
) (old
>> 32);
1541 ctxt
->eflags
&= ~EFLG_ZF
;
1543 c
->dst
.val64
= ((u64
)c
->regs
[VCPU_REGS_RCX
] << 32) |
1544 (u32
) c
->regs
[VCPU_REGS_RBX
];
1546 ctxt
->eflags
|= EFLG_ZF
;
1548 return X86EMUL_CONTINUE
;
1551 static int emulate_ret_far(struct x86_emulate_ctxt
*ctxt
,
1552 struct x86_emulate_ops
*ops
)
1554 struct decode_cache
*c
= &ctxt
->decode
;
1558 rc
= emulate_pop(ctxt
, ops
, &c
->eip
, c
->op_bytes
);
1559 if (rc
!= X86EMUL_CONTINUE
)
1561 if (c
->op_bytes
== 4)
1562 c
->eip
= (u32
)c
->eip
;
1563 rc
= emulate_pop(ctxt
, ops
, &cs
, c
->op_bytes
);
1564 if (rc
!= X86EMUL_CONTINUE
)
1566 rc
= load_segment_descriptor(ctxt
, ops
, (u16
)cs
, VCPU_SREG_CS
);
1570 static int emulate_load_segment(struct x86_emulate_ctxt
*ctxt
,
1571 struct x86_emulate_ops
*ops
, int seg
)
1573 struct decode_cache
*c
= &ctxt
->decode
;
1577 memcpy(&sel
, c
->src
.valptr
+ c
->op_bytes
, 2);
1579 rc
= load_segment_descriptor(ctxt
, ops
, sel
, seg
);
1580 if (rc
!= X86EMUL_CONTINUE
)
1583 c
->dst
.val
= c
->src
.val
;
1588 setup_syscalls_segments(struct x86_emulate_ctxt
*ctxt
,
1589 struct x86_emulate_ops
*ops
, struct desc_struct
*cs
,
1590 struct desc_struct
*ss
)
1592 memset(cs
, 0, sizeof(struct desc_struct
));
1593 ops
->get_cached_descriptor(cs
, VCPU_SREG_CS
, ctxt
->vcpu
);
1594 memset(ss
, 0, sizeof(struct desc_struct
));
1596 cs
->l
= 0; /* will be adjusted later */
1597 set_desc_base(cs
, 0); /* flat segment */
1598 cs
->g
= 1; /* 4kb granularity */
1599 set_desc_limit(cs
, 0xfffff); /* 4GB limit */
1600 cs
->type
= 0x0b; /* Read, Execute, Accessed */
1602 cs
->dpl
= 0; /* will be adjusted later */
1606 set_desc_base(ss
, 0); /* flat segment */
1607 set_desc_limit(ss
, 0xfffff); /* 4GB limit */
1608 ss
->g
= 1; /* 4kb granularity */
1610 ss
->type
= 0x03; /* Read/Write, Accessed */
1611 ss
->d
= 1; /* 32bit stack segment */
1617 emulate_syscall(struct x86_emulate_ctxt
*ctxt
, struct x86_emulate_ops
*ops
)
1619 struct decode_cache
*c
= &ctxt
->decode
;
1620 struct desc_struct cs
, ss
;
1624 /* syscall is not available in real mode */
1625 if (ctxt
->mode
== X86EMUL_MODE_REAL
||
1626 ctxt
->mode
== X86EMUL_MODE_VM86
) {
1628 return X86EMUL_PROPAGATE_FAULT
;
1631 setup_syscalls_segments(ctxt
, ops
, &cs
, &ss
);
1633 ops
->get_msr(ctxt
->vcpu
, MSR_STAR
, &msr_data
);
1635 cs_sel
= (u16
)(msr_data
& 0xfffc);
1636 ss_sel
= (u16
)(msr_data
+ 8);
1638 if (is_long_mode(ctxt
->vcpu
)) {
1642 ops
->set_cached_descriptor(&cs
, VCPU_SREG_CS
, ctxt
->vcpu
);
1643 ops
->set_segment_selector(cs_sel
, VCPU_SREG_CS
, ctxt
->vcpu
);
1644 ops
->set_cached_descriptor(&ss
, VCPU_SREG_SS
, ctxt
->vcpu
);
1645 ops
->set_segment_selector(ss_sel
, VCPU_SREG_SS
, ctxt
->vcpu
);
1647 c
->regs
[VCPU_REGS_RCX
] = c
->eip
;
1648 if (is_long_mode(ctxt
->vcpu
)) {
1649 #ifdef CONFIG_X86_64
1650 c
->regs
[VCPU_REGS_R11
] = ctxt
->eflags
& ~EFLG_RF
;
1652 ops
->get_msr(ctxt
->vcpu
,
1653 ctxt
->mode
== X86EMUL_MODE_PROT64
?
1654 MSR_LSTAR
: MSR_CSTAR
, &msr_data
);
1657 ops
->get_msr(ctxt
->vcpu
, MSR_SYSCALL_MASK
, &msr_data
);
1658 ctxt
->eflags
&= ~(msr_data
| EFLG_RF
);
1662 ops
->get_msr(ctxt
->vcpu
, MSR_STAR
, &msr_data
);
1663 c
->eip
= (u32
)msr_data
;
1665 ctxt
->eflags
&= ~(EFLG_VM
| EFLG_IF
| EFLG_RF
);
1668 return X86EMUL_CONTINUE
;
1672 emulate_sysenter(struct x86_emulate_ctxt
*ctxt
, struct x86_emulate_ops
*ops
)
1674 struct decode_cache
*c
= &ctxt
->decode
;
1675 struct desc_struct cs
, ss
;
1679 /* inject #GP if in real mode */
1680 if (ctxt
->mode
== X86EMUL_MODE_REAL
) {
1681 emulate_gp(ctxt
, 0);
1682 return X86EMUL_PROPAGATE_FAULT
;
1685 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1686 * Therefore, we inject an #UD.
1688 if (ctxt
->mode
== X86EMUL_MODE_PROT64
) {
1690 return X86EMUL_PROPAGATE_FAULT
;
1693 setup_syscalls_segments(ctxt
, ops
, &cs
, &ss
);
1695 ops
->get_msr(ctxt
->vcpu
, MSR_IA32_SYSENTER_CS
, &msr_data
);
1696 switch (ctxt
->mode
) {
1697 case X86EMUL_MODE_PROT32
:
1698 if ((msr_data
& 0xfffc) == 0x0) {
1699 emulate_gp(ctxt
, 0);
1700 return X86EMUL_PROPAGATE_FAULT
;
1703 case X86EMUL_MODE_PROT64
:
1704 if (msr_data
== 0x0) {
1705 emulate_gp(ctxt
, 0);
1706 return X86EMUL_PROPAGATE_FAULT
;
1711 ctxt
->eflags
&= ~(EFLG_VM
| EFLG_IF
| EFLG_RF
);
1712 cs_sel
= (u16
)msr_data
;
1713 cs_sel
&= ~SELECTOR_RPL_MASK
;
1714 ss_sel
= cs_sel
+ 8;
1715 ss_sel
&= ~SELECTOR_RPL_MASK
;
1716 if (ctxt
->mode
== X86EMUL_MODE_PROT64
1717 || is_long_mode(ctxt
->vcpu
)) {
1722 ops
->set_cached_descriptor(&cs
, VCPU_SREG_CS
, ctxt
->vcpu
);
1723 ops
->set_segment_selector(cs_sel
, VCPU_SREG_CS
, ctxt
->vcpu
);
1724 ops
->set_cached_descriptor(&ss
, VCPU_SREG_SS
, ctxt
->vcpu
);
1725 ops
->set_segment_selector(ss_sel
, VCPU_SREG_SS
, ctxt
->vcpu
);
1727 ops
->get_msr(ctxt
->vcpu
, MSR_IA32_SYSENTER_EIP
, &msr_data
);
1730 ops
->get_msr(ctxt
->vcpu
, MSR_IA32_SYSENTER_ESP
, &msr_data
);
1731 c
->regs
[VCPU_REGS_RSP
] = msr_data
;
1733 return X86EMUL_CONTINUE
;
1737 emulate_sysexit(struct x86_emulate_ctxt
*ctxt
, struct x86_emulate_ops
*ops
)
1739 struct decode_cache
*c
= &ctxt
->decode
;
1740 struct desc_struct cs
, ss
;
1745 /* inject #GP if in real mode or Virtual 8086 mode */
1746 if (ctxt
->mode
== X86EMUL_MODE_REAL
||
1747 ctxt
->mode
== X86EMUL_MODE_VM86
) {
1748 emulate_gp(ctxt
, 0);
1749 return X86EMUL_PROPAGATE_FAULT
;
1752 setup_syscalls_segments(ctxt
, ops
, &cs
, &ss
);
1754 if ((c
->rex_prefix
& 0x8) != 0x0)
1755 usermode
= X86EMUL_MODE_PROT64
;
1757 usermode
= X86EMUL_MODE_PROT32
;
1761 ops
->get_msr(ctxt
->vcpu
, MSR_IA32_SYSENTER_CS
, &msr_data
);
1763 case X86EMUL_MODE_PROT32
:
1764 cs_sel
= (u16
)(msr_data
+ 16);
1765 if ((msr_data
& 0xfffc) == 0x0) {
1766 emulate_gp(ctxt
, 0);
1767 return X86EMUL_PROPAGATE_FAULT
;
1769 ss_sel
= (u16
)(msr_data
+ 24);
1771 case X86EMUL_MODE_PROT64
:
1772 cs_sel
= (u16
)(msr_data
+ 32);
1773 if (msr_data
== 0x0) {
1774 emulate_gp(ctxt
, 0);
1775 return X86EMUL_PROPAGATE_FAULT
;
1777 ss_sel
= cs_sel
+ 8;
1782 cs_sel
|= SELECTOR_RPL_MASK
;
1783 ss_sel
|= SELECTOR_RPL_MASK
;
1785 ops
->set_cached_descriptor(&cs
, VCPU_SREG_CS
, ctxt
->vcpu
);
1786 ops
->set_segment_selector(cs_sel
, VCPU_SREG_CS
, ctxt
->vcpu
);
1787 ops
->set_cached_descriptor(&ss
, VCPU_SREG_SS
, ctxt
->vcpu
);
1788 ops
->set_segment_selector(ss_sel
, VCPU_SREG_SS
, ctxt
->vcpu
);
1790 c
->eip
= c
->regs
[VCPU_REGS_RDX
];
1791 c
->regs
[VCPU_REGS_RSP
] = c
->regs
[VCPU_REGS_RCX
];
1793 return X86EMUL_CONTINUE
;
1796 static bool emulator_bad_iopl(struct x86_emulate_ctxt
*ctxt
,
1797 struct x86_emulate_ops
*ops
)
1800 if (ctxt
->mode
== X86EMUL_MODE_REAL
)
1802 if (ctxt
->mode
== X86EMUL_MODE_VM86
)
1804 iopl
= (ctxt
->eflags
& X86_EFLAGS_IOPL
) >> IOPL_SHIFT
;
1805 return ops
->cpl(ctxt
->vcpu
) > iopl
;
1808 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt
*ctxt
,
1809 struct x86_emulate_ops
*ops
,
1812 struct desc_struct tr_seg
;
1815 u8 perm
, bit_idx
= port
& 0x7;
1816 unsigned mask
= (1 << len
) - 1;
1818 ops
->get_cached_descriptor(&tr_seg
, VCPU_SREG_TR
, ctxt
->vcpu
);
1821 if (desc_limit_scaled(&tr_seg
) < 103)
1823 r
= ops
->read_std(get_desc_base(&tr_seg
) + 102, &io_bitmap_ptr
, 2,
1825 if (r
!= X86EMUL_CONTINUE
)
1827 if (io_bitmap_ptr
+ port
/8 > desc_limit_scaled(&tr_seg
))
1829 r
= ops
->read_std(get_desc_base(&tr_seg
) + io_bitmap_ptr
+ port
/8,
1830 &perm
, 1, ctxt
->vcpu
, NULL
);
1831 if (r
!= X86EMUL_CONTINUE
)
1833 if ((perm
>> bit_idx
) & mask
)
1838 static bool emulator_io_permited(struct x86_emulate_ctxt
*ctxt
,
1839 struct x86_emulate_ops
*ops
,
1845 if (emulator_bad_iopl(ctxt
, ops
))
1846 if (!emulator_io_port_access_allowed(ctxt
, ops
, port
, len
))
1849 ctxt
->perm_ok
= true;
1854 static void save_state_to_tss16(struct x86_emulate_ctxt
*ctxt
,
1855 struct x86_emulate_ops
*ops
,
1856 struct tss_segment_16
*tss
)
1858 struct decode_cache
*c
= &ctxt
->decode
;
1861 tss
->flag
= ctxt
->eflags
;
1862 tss
->ax
= c
->regs
[VCPU_REGS_RAX
];
1863 tss
->cx
= c
->regs
[VCPU_REGS_RCX
];
1864 tss
->dx
= c
->regs
[VCPU_REGS_RDX
];
1865 tss
->bx
= c
->regs
[VCPU_REGS_RBX
];
1866 tss
->sp
= c
->regs
[VCPU_REGS_RSP
];
1867 tss
->bp
= c
->regs
[VCPU_REGS_RBP
];
1868 tss
->si
= c
->regs
[VCPU_REGS_RSI
];
1869 tss
->di
= c
->regs
[VCPU_REGS_RDI
];
1871 tss
->es
= ops
->get_segment_selector(VCPU_SREG_ES
, ctxt
->vcpu
);
1872 tss
->cs
= ops
->get_segment_selector(VCPU_SREG_CS
, ctxt
->vcpu
);
1873 tss
->ss
= ops
->get_segment_selector(VCPU_SREG_SS
, ctxt
->vcpu
);
1874 tss
->ds
= ops
->get_segment_selector(VCPU_SREG_DS
, ctxt
->vcpu
);
1875 tss
->ldt
= ops
->get_segment_selector(VCPU_SREG_LDTR
, ctxt
->vcpu
);
1878 static int load_state_from_tss16(struct x86_emulate_ctxt
*ctxt
,
1879 struct x86_emulate_ops
*ops
,
1880 struct tss_segment_16
*tss
)
1882 struct decode_cache
*c
= &ctxt
->decode
;
1886 ctxt
->eflags
= tss
->flag
| 2;
1887 c
->regs
[VCPU_REGS_RAX
] = tss
->ax
;
1888 c
->regs
[VCPU_REGS_RCX
] = tss
->cx
;
1889 c
->regs
[VCPU_REGS_RDX
] = tss
->dx
;
1890 c
->regs
[VCPU_REGS_RBX
] = tss
->bx
;
1891 c
->regs
[VCPU_REGS_RSP
] = tss
->sp
;
1892 c
->regs
[VCPU_REGS_RBP
] = tss
->bp
;
1893 c
->regs
[VCPU_REGS_RSI
] = tss
->si
;
1894 c
->regs
[VCPU_REGS_RDI
] = tss
->di
;
1897 * SDM says that segment selectors are loaded before segment
1900 ops
->set_segment_selector(tss
->ldt
, VCPU_SREG_LDTR
, ctxt
->vcpu
);
1901 ops
->set_segment_selector(tss
->es
, VCPU_SREG_ES
, ctxt
->vcpu
);
1902 ops
->set_segment_selector(tss
->cs
, VCPU_SREG_CS
, ctxt
->vcpu
);
1903 ops
->set_segment_selector(tss
->ss
, VCPU_SREG_SS
, ctxt
->vcpu
);
1904 ops
->set_segment_selector(tss
->ds
, VCPU_SREG_DS
, ctxt
->vcpu
);
1907 * Now load segment descriptors. If fault happenes at this stage
1908 * it is handled in a context of new task
1910 ret
= load_segment_descriptor(ctxt
, ops
, tss
->ldt
, VCPU_SREG_LDTR
);
1911 if (ret
!= X86EMUL_CONTINUE
)
1913 ret
= load_segment_descriptor(ctxt
, ops
, tss
->es
, VCPU_SREG_ES
);
1914 if (ret
!= X86EMUL_CONTINUE
)
1916 ret
= load_segment_descriptor(ctxt
, ops
, tss
->cs
, VCPU_SREG_CS
);
1917 if (ret
!= X86EMUL_CONTINUE
)
1919 ret
= load_segment_descriptor(ctxt
, ops
, tss
->ss
, VCPU_SREG_SS
);
1920 if (ret
!= X86EMUL_CONTINUE
)
1922 ret
= load_segment_descriptor(ctxt
, ops
, tss
->ds
, VCPU_SREG_DS
);
1923 if (ret
!= X86EMUL_CONTINUE
)
1926 return X86EMUL_CONTINUE
;
1929 static int task_switch_16(struct x86_emulate_ctxt
*ctxt
,
1930 struct x86_emulate_ops
*ops
,
1931 u16 tss_selector
, u16 old_tss_sel
,
1932 ulong old_tss_base
, struct desc_struct
*new_desc
)
1934 struct tss_segment_16 tss_seg
;
1936 u32 err
, new_tss_base
= get_desc_base(new_desc
);
1938 ret
= ops
->read_std(old_tss_base
, &tss_seg
, sizeof tss_seg
, ctxt
->vcpu
,
1940 if (ret
== X86EMUL_PROPAGATE_FAULT
) {
1941 /* FIXME: need to provide precise fault address */
1942 emulate_pf(ctxt
, old_tss_base
, err
);
1946 save_state_to_tss16(ctxt
, ops
, &tss_seg
);
1948 ret
= ops
->write_std(old_tss_base
, &tss_seg
, sizeof tss_seg
, ctxt
->vcpu
,
1950 if (ret
== X86EMUL_PROPAGATE_FAULT
) {
1951 /* FIXME: need to provide precise fault address */
1952 emulate_pf(ctxt
, old_tss_base
, err
);
1956 ret
= ops
->read_std(new_tss_base
, &tss_seg
, sizeof tss_seg
, ctxt
->vcpu
,
1958 if (ret
== X86EMUL_PROPAGATE_FAULT
) {
1959 /* FIXME: need to provide precise fault address */
1960 emulate_pf(ctxt
, new_tss_base
, err
);
1964 if (old_tss_sel
!= 0xffff) {
1965 tss_seg
.prev_task_link
= old_tss_sel
;
1967 ret
= ops
->write_std(new_tss_base
,
1968 &tss_seg
.prev_task_link
,
1969 sizeof tss_seg
.prev_task_link
,
1971 if (ret
== X86EMUL_PROPAGATE_FAULT
) {
1972 /* FIXME: need to provide precise fault address */
1973 emulate_pf(ctxt
, new_tss_base
, err
);
1978 return load_state_from_tss16(ctxt
, ops
, &tss_seg
);
1981 static void save_state_to_tss32(struct x86_emulate_ctxt
*ctxt
,
1982 struct x86_emulate_ops
*ops
,
1983 struct tss_segment_32
*tss
)
1985 struct decode_cache
*c
= &ctxt
->decode
;
1987 tss
->cr3
= ops
->get_cr(3, ctxt
->vcpu
);
1989 tss
->eflags
= ctxt
->eflags
;
1990 tss
->eax
= c
->regs
[VCPU_REGS_RAX
];
1991 tss
->ecx
= c
->regs
[VCPU_REGS_RCX
];
1992 tss
->edx
= c
->regs
[VCPU_REGS_RDX
];
1993 tss
->ebx
= c
->regs
[VCPU_REGS_RBX
];
1994 tss
->esp
= c
->regs
[VCPU_REGS_RSP
];
1995 tss
->ebp
= c
->regs
[VCPU_REGS_RBP
];
1996 tss
->esi
= c
->regs
[VCPU_REGS_RSI
];
1997 tss
->edi
= c
->regs
[VCPU_REGS_RDI
];
1999 tss
->es
= ops
->get_segment_selector(VCPU_SREG_ES
, ctxt
->vcpu
);
2000 tss
->cs
= ops
->get_segment_selector(VCPU_SREG_CS
, ctxt
->vcpu
);
2001 tss
->ss
= ops
->get_segment_selector(VCPU_SREG_SS
, ctxt
->vcpu
);
2002 tss
->ds
= ops
->get_segment_selector(VCPU_SREG_DS
, ctxt
->vcpu
);
2003 tss
->fs
= ops
->get_segment_selector(VCPU_SREG_FS
, ctxt
->vcpu
);
2004 tss
->gs
= ops
->get_segment_selector(VCPU_SREG_GS
, ctxt
->vcpu
);
2005 tss
->ldt_selector
= ops
->get_segment_selector(VCPU_SREG_LDTR
, ctxt
->vcpu
);
2008 static int load_state_from_tss32(struct x86_emulate_ctxt
*ctxt
,
2009 struct x86_emulate_ops
*ops
,
2010 struct tss_segment_32
*tss
)
2012 struct decode_cache
*c
= &ctxt
->decode
;
2015 if (ops
->set_cr(3, tss
->cr3
, ctxt
->vcpu
)) {
2016 emulate_gp(ctxt
, 0);
2017 return X86EMUL_PROPAGATE_FAULT
;
2020 ctxt
->eflags
= tss
->eflags
| 2;
2021 c
->regs
[VCPU_REGS_RAX
] = tss
->eax
;
2022 c
->regs
[VCPU_REGS_RCX
] = tss
->ecx
;
2023 c
->regs
[VCPU_REGS_RDX
] = tss
->edx
;
2024 c
->regs
[VCPU_REGS_RBX
] = tss
->ebx
;
2025 c
->regs
[VCPU_REGS_RSP
] = tss
->esp
;
2026 c
->regs
[VCPU_REGS_RBP
] = tss
->ebp
;
2027 c
->regs
[VCPU_REGS_RSI
] = tss
->esi
;
2028 c
->regs
[VCPU_REGS_RDI
] = tss
->edi
;
2031 * SDM says that segment selectors are loaded before segment
2034 ops
->set_segment_selector(tss
->ldt_selector
, VCPU_SREG_LDTR
, ctxt
->vcpu
);
2035 ops
->set_segment_selector(tss
->es
, VCPU_SREG_ES
, ctxt
->vcpu
);
2036 ops
->set_segment_selector(tss
->cs
, VCPU_SREG_CS
, ctxt
->vcpu
);
2037 ops
->set_segment_selector(tss
->ss
, VCPU_SREG_SS
, ctxt
->vcpu
);
2038 ops
->set_segment_selector(tss
->ds
, VCPU_SREG_DS
, ctxt
->vcpu
);
2039 ops
->set_segment_selector(tss
->fs
, VCPU_SREG_FS
, ctxt
->vcpu
);
2040 ops
->set_segment_selector(tss
->gs
, VCPU_SREG_GS
, ctxt
->vcpu
);
2043 * Now load segment descriptors. If fault happenes at this stage
2044 * it is handled in a context of new task
2046 ret
= load_segment_descriptor(ctxt
, ops
, tss
->ldt_selector
, VCPU_SREG_LDTR
);
2047 if (ret
!= X86EMUL_CONTINUE
)
2049 ret
= load_segment_descriptor(ctxt
, ops
, tss
->es
, VCPU_SREG_ES
);
2050 if (ret
!= X86EMUL_CONTINUE
)
2052 ret
= load_segment_descriptor(ctxt
, ops
, tss
->cs
, VCPU_SREG_CS
);
2053 if (ret
!= X86EMUL_CONTINUE
)
2055 ret
= load_segment_descriptor(ctxt
, ops
, tss
->ss
, VCPU_SREG_SS
);
2056 if (ret
!= X86EMUL_CONTINUE
)
2058 ret
= load_segment_descriptor(ctxt
, ops
, tss
->ds
, VCPU_SREG_DS
);
2059 if (ret
!= X86EMUL_CONTINUE
)
2061 ret
= load_segment_descriptor(ctxt
, ops
, tss
->fs
, VCPU_SREG_FS
);
2062 if (ret
!= X86EMUL_CONTINUE
)
2064 ret
= load_segment_descriptor(ctxt
, ops
, tss
->gs
, VCPU_SREG_GS
);
2065 if (ret
!= X86EMUL_CONTINUE
)
2068 return X86EMUL_CONTINUE
;
2071 static int task_switch_32(struct x86_emulate_ctxt
*ctxt
,
2072 struct x86_emulate_ops
*ops
,
2073 u16 tss_selector
, u16 old_tss_sel
,
2074 ulong old_tss_base
, struct desc_struct
*new_desc
)
2076 struct tss_segment_32 tss_seg
;
2078 u32 err
, new_tss_base
= get_desc_base(new_desc
);
2080 ret
= ops
->read_std(old_tss_base
, &tss_seg
, sizeof tss_seg
, ctxt
->vcpu
,
2082 if (ret
== X86EMUL_PROPAGATE_FAULT
) {
2083 /* FIXME: need to provide precise fault address */
2084 emulate_pf(ctxt
, old_tss_base
, err
);
2088 save_state_to_tss32(ctxt
, ops
, &tss_seg
);
2090 ret
= ops
->write_std(old_tss_base
, &tss_seg
, sizeof tss_seg
, ctxt
->vcpu
,
2092 if (ret
== X86EMUL_PROPAGATE_FAULT
) {
2093 /* FIXME: need to provide precise fault address */
2094 emulate_pf(ctxt
, old_tss_base
, err
);
2098 ret
= ops
->read_std(new_tss_base
, &tss_seg
, sizeof tss_seg
, ctxt
->vcpu
,
2100 if (ret
== X86EMUL_PROPAGATE_FAULT
) {
2101 /* FIXME: need to provide precise fault address */
2102 emulate_pf(ctxt
, new_tss_base
, err
);
2106 if (old_tss_sel
!= 0xffff) {
2107 tss_seg
.prev_task_link
= old_tss_sel
;
2109 ret
= ops
->write_std(new_tss_base
,
2110 &tss_seg
.prev_task_link
,
2111 sizeof tss_seg
.prev_task_link
,
2113 if (ret
== X86EMUL_PROPAGATE_FAULT
) {
2114 /* FIXME: need to provide precise fault address */
2115 emulate_pf(ctxt
, new_tss_base
, err
);
2120 return load_state_from_tss32(ctxt
, ops
, &tss_seg
);
2123 static int emulator_do_task_switch(struct x86_emulate_ctxt
*ctxt
,
2124 struct x86_emulate_ops
*ops
,
2125 u16 tss_selector
, int reason
,
2126 bool has_error_code
, u32 error_code
)
2128 struct desc_struct curr_tss_desc
, next_tss_desc
;
2130 u16 old_tss_sel
= ops
->get_segment_selector(VCPU_SREG_TR
, ctxt
->vcpu
);
2131 ulong old_tss_base
=
2132 ops
->get_cached_segment_base(VCPU_SREG_TR
, ctxt
->vcpu
);
2135 /* FIXME: old_tss_base == ~0 ? */
2137 ret
= read_segment_descriptor(ctxt
, ops
, tss_selector
, &next_tss_desc
);
2138 if (ret
!= X86EMUL_CONTINUE
)
2140 ret
= read_segment_descriptor(ctxt
, ops
, old_tss_sel
, &curr_tss_desc
);
2141 if (ret
!= X86EMUL_CONTINUE
)
2144 /* FIXME: check that next_tss_desc is tss */
2146 if (reason
!= TASK_SWITCH_IRET
) {
2147 if ((tss_selector
& 3) > next_tss_desc
.dpl
||
2148 ops
->cpl(ctxt
->vcpu
) > next_tss_desc
.dpl
) {
2149 emulate_gp(ctxt
, 0);
2150 return X86EMUL_PROPAGATE_FAULT
;
2154 desc_limit
= desc_limit_scaled(&next_tss_desc
);
2155 if (!next_tss_desc
.p
||
2156 ((desc_limit
< 0x67 && (next_tss_desc
.type
& 8)) ||
2157 desc_limit
< 0x2b)) {
2158 emulate_ts(ctxt
, tss_selector
& 0xfffc);
2159 return X86EMUL_PROPAGATE_FAULT
;
2162 if (reason
== TASK_SWITCH_IRET
|| reason
== TASK_SWITCH_JMP
) {
2163 curr_tss_desc
.type
&= ~(1 << 1); /* clear busy flag */
2164 write_segment_descriptor(ctxt
, ops
, old_tss_sel
,
2168 if (reason
== TASK_SWITCH_IRET
)
2169 ctxt
->eflags
= ctxt
->eflags
& ~X86_EFLAGS_NT
;
2171 /* set back link to prev task only if NT bit is set in eflags
2172 note that old_tss_sel is not used afetr this point */
2173 if (reason
!= TASK_SWITCH_CALL
&& reason
!= TASK_SWITCH_GATE
)
2174 old_tss_sel
= 0xffff;
2176 if (next_tss_desc
.type
& 8)
2177 ret
= task_switch_32(ctxt
, ops
, tss_selector
, old_tss_sel
,
2178 old_tss_base
, &next_tss_desc
);
2180 ret
= task_switch_16(ctxt
, ops
, tss_selector
, old_tss_sel
,
2181 old_tss_base
, &next_tss_desc
);
2182 if (ret
!= X86EMUL_CONTINUE
)
2185 if (reason
== TASK_SWITCH_CALL
|| reason
== TASK_SWITCH_GATE
)
2186 ctxt
->eflags
= ctxt
->eflags
| X86_EFLAGS_NT
;
2188 if (reason
!= TASK_SWITCH_IRET
) {
2189 next_tss_desc
.type
|= (1 << 1); /* set busy flag */
2190 write_segment_descriptor(ctxt
, ops
, tss_selector
,
2194 ops
->set_cr(0, ops
->get_cr(0, ctxt
->vcpu
) | X86_CR0_TS
, ctxt
->vcpu
);
2195 ops
->set_cached_descriptor(&next_tss_desc
, VCPU_SREG_TR
, ctxt
->vcpu
);
2196 ops
->set_segment_selector(tss_selector
, VCPU_SREG_TR
, ctxt
->vcpu
);
2198 if (has_error_code
) {
2199 struct decode_cache
*c
= &ctxt
->decode
;
2201 c
->op_bytes
= c
->ad_bytes
= (next_tss_desc
.type
& 8) ? 4 : 2;
2203 c
->src
.val
= (unsigned long) error_code
;
2204 emulate_push(ctxt
, ops
);
2210 int emulator_task_switch(struct x86_emulate_ctxt
*ctxt
,
2211 u16 tss_selector
, int reason
,
2212 bool has_error_code
, u32 error_code
)
2214 struct x86_emulate_ops
*ops
= ctxt
->ops
;
2215 struct decode_cache
*c
= &ctxt
->decode
;
2219 c
->dst
.type
= OP_NONE
;
2221 rc
= emulator_do_task_switch(ctxt
, ops
, tss_selector
, reason
,
2222 has_error_code
, error_code
);
2224 if (rc
== X86EMUL_CONTINUE
) {
2225 rc
= writeback(ctxt
, ops
);
2226 if (rc
== X86EMUL_CONTINUE
)
2230 return (rc
== X86EMUL_UNHANDLEABLE
) ? -1 : 0;
2233 static void string_addr_inc(struct x86_emulate_ctxt
*ctxt
, unsigned long base
,
2234 int reg
, struct operand
*op
)
2236 struct decode_cache
*c
= &ctxt
->decode
;
2237 int df
= (ctxt
->eflags
& EFLG_DF
) ? -1 : 1;
2239 register_address_increment(c
, &c
->regs
[reg
], df
* op
->bytes
);
2240 op
->addr
.mem
= register_address(c
, base
, c
->regs
[reg
]);
2243 static int em_push(struct x86_emulate_ctxt
*ctxt
)
2245 emulate_push(ctxt
, ctxt
->ops
);
2246 return X86EMUL_CONTINUE
;
2249 static int em_das(struct x86_emulate_ctxt
*ctxt
)
2251 struct decode_cache
*c
= &ctxt
->decode
;
2253 bool af
, cf
, old_cf
;
2255 cf
= ctxt
->eflags
& X86_EFLAGS_CF
;
2261 af
= ctxt
->eflags
& X86_EFLAGS_AF
;
2262 if ((al
& 0x0f) > 9 || af
) {
2264 cf
= old_cf
| (al
>= 250);
2269 if (old_al
> 0x99 || old_cf
) {
2275 /* Set PF, ZF, SF */
2276 c
->src
.type
= OP_IMM
;
2279 emulate_2op_SrcV("or", c
->src
, c
->dst
, ctxt
->eflags
);
2280 ctxt
->eflags
&= ~(X86_EFLAGS_AF
| X86_EFLAGS_CF
);
2282 ctxt
->eflags
|= X86_EFLAGS_CF
;
2284 ctxt
->eflags
|= X86_EFLAGS_AF
;
2285 return X86EMUL_CONTINUE
;
2288 static int em_call_far(struct x86_emulate_ctxt
*ctxt
)
2290 struct decode_cache
*c
= &ctxt
->decode
;
2295 old_cs
= ctxt
->ops
->get_segment_selector(VCPU_SREG_CS
, ctxt
->vcpu
);
2298 memcpy(&sel
, c
->src
.valptr
+ c
->op_bytes
, 2);
2299 if (load_segment_descriptor(ctxt
, ctxt
->ops
, sel
, VCPU_SREG_CS
))
2300 return X86EMUL_CONTINUE
;
2303 memcpy(&c
->eip
, c
->src
.valptr
, c
->op_bytes
);
2305 c
->src
.val
= old_cs
;
2306 emulate_push(ctxt
, ctxt
->ops
);
2307 rc
= writeback(ctxt
, ctxt
->ops
);
2308 if (rc
!= X86EMUL_CONTINUE
)
2311 c
->src
.val
= old_eip
;
2312 emulate_push(ctxt
, ctxt
->ops
);
2313 rc
= writeback(ctxt
, ctxt
->ops
);
2314 if (rc
!= X86EMUL_CONTINUE
)
2317 c
->dst
.type
= OP_NONE
;
2319 return X86EMUL_CONTINUE
;
2322 static int em_ret_near_imm(struct x86_emulate_ctxt
*ctxt
)
2324 struct decode_cache
*c
= &ctxt
->decode
;
2327 c
->dst
.type
= OP_REG
;
2328 c
->dst
.addr
.reg
= &c
->eip
;
2329 c
->dst
.bytes
= c
->op_bytes
;
2330 rc
= emulate_pop(ctxt
, ctxt
->ops
, &c
->dst
.val
, c
->op_bytes
);
2331 if (rc
!= X86EMUL_CONTINUE
)
2333 register_address_increment(c
, &c
->regs
[VCPU_REGS_RSP
], c
->src
.val
);
2334 return X86EMUL_CONTINUE
;
2337 static int em_imul(struct x86_emulate_ctxt
*ctxt
)
2339 struct decode_cache
*c
= &ctxt
->decode
;
2341 emulate_2op_SrcV_nobyte("imul", c
->src
, c
->dst
, ctxt
->eflags
);
2342 return X86EMUL_CONTINUE
;
2345 static int em_imul_3op(struct x86_emulate_ctxt
*ctxt
)
2347 struct decode_cache
*c
= &ctxt
->decode
;
2349 c
->dst
.val
= c
->src2
.val
;
2350 return em_imul(ctxt
);
2353 static int em_cwd(struct x86_emulate_ctxt
*ctxt
)
2355 struct decode_cache
*c
= &ctxt
->decode
;
2357 c
->dst
.type
= OP_REG
;
2358 c
->dst
.bytes
= c
->src
.bytes
;
2359 c
->dst
.addr
.reg
= &c
->regs
[VCPU_REGS_RDX
];
2360 c
->dst
.val
= ~((c
->src
.val
>> (c
->src
.bytes
* 8 - 1)) - 1);
2362 return X86EMUL_CONTINUE
;
2365 static int em_rdtsc(struct x86_emulate_ctxt
*ctxt
)
2367 unsigned cpl
= ctxt
->ops
->cpl(ctxt
->vcpu
);
2368 struct decode_cache
*c
= &ctxt
->decode
;
2371 if (cpl
> 0 && (ctxt
->ops
->get_cr(4, ctxt
->vcpu
) & X86_CR4_TSD
)) {
2372 emulate_gp(ctxt
, 0);
2373 return X86EMUL_PROPAGATE_FAULT
;
2375 ctxt
->ops
->get_msr(ctxt
->vcpu
, MSR_IA32_TSC
, &tsc
);
2376 c
->regs
[VCPU_REGS_RAX
] = (u32
)tsc
;
2377 c
->regs
[VCPU_REGS_RDX
] = tsc
>> 32;
2378 return X86EMUL_CONTINUE
;
2381 #define D(_y) { .flags = (_y) }
2383 #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2384 #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2385 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2387 #define D2bv(_f) D((_f) | ByteOp), D(_f)
2388 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2390 static struct opcode group1
[] = {
2394 static struct opcode group1A
[] = {
2395 D(DstMem
| SrcNone
| ModRM
| Mov
| Stack
), N
, N
, N
, N
, N
, N
, N
,
2398 static struct opcode group3
[] = {
2399 D(DstMem
| SrcImm
| ModRM
), D(DstMem
| SrcImm
| ModRM
),
2400 D(DstMem
| SrcNone
| ModRM
| Lock
), D(DstMem
| SrcNone
| ModRM
| Lock
),
2401 X4(D(SrcMem
| ModRM
)),
2404 static struct opcode group4
[] = {
2405 D(ByteOp
| DstMem
| SrcNone
| ModRM
| Lock
), D(ByteOp
| DstMem
| SrcNone
| ModRM
| Lock
),
2409 static struct opcode group5
[] = {
2410 D(DstMem
| SrcNone
| ModRM
| Lock
), D(DstMem
| SrcNone
| ModRM
| Lock
),
2411 D(SrcMem
| ModRM
| Stack
),
2412 I(SrcMemFAddr
| ModRM
| ImplicitOps
| Stack
, em_call_far
),
2413 D(SrcMem
| ModRM
| Stack
), D(SrcMemFAddr
| ModRM
| ImplicitOps
),
2414 D(SrcMem
| ModRM
| Stack
), N
,
2417 static struct group_dual group7
= { {
2418 N
, N
, D(ModRM
| SrcMem
| Priv
), D(ModRM
| SrcMem
| Priv
),
2419 D(SrcNone
| ModRM
| DstMem
| Mov
), N
,
2420 D(SrcMem16
| ModRM
| Mov
| Priv
),
2421 D(SrcMem
| ModRM
| ByteOp
| Priv
| NoAccess
),
2423 D(SrcNone
| ModRM
| Priv
), N
, N
, D(SrcNone
| ModRM
| Priv
),
2424 D(SrcNone
| ModRM
| DstMem
| Mov
), N
,
2425 D(SrcMem16
| ModRM
| Mov
| Priv
), N
,
2428 static struct opcode group8
[] = {
2430 D(DstMem
| SrcImmByte
| ModRM
), D(DstMem
| SrcImmByte
| ModRM
| Lock
),
2431 D(DstMem
| SrcImmByte
| ModRM
| Lock
), D(DstMem
| SrcImmByte
| ModRM
| Lock
),
2434 static struct group_dual group9
= { {
2435 N
, D(DstMem64
| ModRM
| Lock
), N
, N
, N
, N
, N
, N
,
2437 N
, N
, N
, N
, N
, N
, N
, N
,
2440 static struct opcode opcode_table
[256] = {
2442 D2bv(DstMem
| SrcReg
| ModRM
| Lock
), D2bv(DstReg
| SrcMem
| ModRM
),
2443 D2bv(DstAcc
| SrcImm
),
2444 D(ImplicitOps
| Stack
| No64
), D(ImplicitOps
| Stack
| No64
),
2446 D2bv(DstMem
| SrcReg
| ModRM
| Lock
), D2bv(DstReg
| SrcMem
| ModRM
),
2447 D2bv(DstAcc
| SrcImm
),
2448 D(ImplicitOps
| Stack
| No64
), N
,
2450 D2bv(DstMem
| SrcReg
| ModRM
| Lock
), D2bv(DstReg
| SrcMem
| ModRM
),
2451 D2bv(DstAcc
| SrcImm
),
2452 D(ImplicitOps
| Stack
| No64
), D(ImplicitOps
| Stack
| No64
),
2454 D2bv(DstMem
| SrcReg
| ModRM
| Lock
), D2bv(DstReg
| SrcMem
| ModRM
),
2455 D2bv(DstAcc
| SrcImm
),
2456 D(ImplicitOps
| Stack
| No64
), D(ImplicitOps
| Stack
| No64
),
2458 D2bv(DstMem
| SrcReg
| ModRM
| Lock
), D2bv(DstReg
| SrcMem
| ModRM
),
2459 D2bv(DstAcc
| SrcImm
), N
, N
,
2461 D2bv(DstMem
| SrcReg
| ModRM
| Lock
), D2bv(DstReg
| SrcMem
| ModRM
),
2462 D2bv(DstAcc
| SrcImm
),
2463 N
, I(ByteOp
| DstAcc
| No64
, em_das
),
2465 D2bv(DstMem
| SrcReg
| ModRM
| Lock
), D2bv(DstReg
| SrcMem
| ModRM
),
2466 D2bv(DstAcc
| SrcImm
), N
, N
,
2468 D2bv(DstMem
| SrcReg
| ModRM
), D2bv(DstReg
| SrcMem
| ModRM
),
2469 D2bv(DstAcc
| SrcImm
),
2474 X8(I(SrcReg
| Stack
, em_push
)),
2476 X8(D(DstReg
| Stack
)),
2478 D(ImplicitOps
| Stack
| No64
), D(ImplicitOps
| Stack
| No64
),
2479 N
, D(DstReg
| SrcMem32
| ModRM
| Mov
) /* movsxd (x86/64) */ ,
2482 I(SrcImm
| Mov
| Stack
, em_push
),
2483 I(DstReg
| SrcMem
| ModRM
| Src2Imm
, em_imul_3op
),
2484 I(SrcImmByte
| Mov
| Stack
, em_push
),
2485 I(DstReg
| SrcMem
| ModRM
| Src2ImmByte
, em_imul_3op
),
2486 D2bv(DstDI
| Mov
| String
), /* insb, insw/insd */
2487 D2bv(SrcSI
| ImplicitOps
| String
), /* outsb, outsw/outsd */
2491 G(ByteOp
| DstMem
| SrcImm
| ModRM
| Group
, group1
),
2492 G(DstMem
| SrcImm
| ModRM
| Group
, group1
),
2493 G(ByteOp
| DstMem
| SrcImm
| ModRM
| No64
| Group
, group1
),
2494 G(DstMem
| SrcImmByte
| ModRM
| Group
, group1
),
2495 D2bv(DstMem
| SrcReg
| ModRM
), D2bv(DstMem
| SrcReg
| ModRM
| Lock
),
2497 D2bv(DstMem
| SrcReg
| ModRM
| Mov
),
2498 D2bv(DstReg
| SrcMem
| ModRM
| Mov
),
2499 D(DstMem
| SrcNone
| ModRM
| Mov
), D(ModRM
| SrcMem
| NoAccess
| DstReg
),
2500 D(ImplicitOps
| SrcMem16
| ModRM
), G(0, group1A
),
2502 X8(D(SrcAcc
| DstReg
)),
2504 D(DstAcc
| SrcNone
), I(ImplicitOps
| SrcAcc
, em_cwd
),
2505 I(SrcImmFAddr
| No64
, em_call_far
), N
,
2506 D(ImplicitOps
| Stack
), D(ImplicitOps
| Stack
), N
, N
,
2508 D2bv(DstAcc
| SrcMem
| Mov
| MemAbs
),
2509 D2bv(DstMem
| SrcAcc
| Mov
| MemAbs
),
2510 D2bv(SrcSI
| DstDI
| Mov
| String
), D2bv(SrcSI
| DstDI
| String
),
2512 D2bv(DstAcc
| SrcImm
),
2513 D2bv(SrcAcc
| DstDI
| Mov
| String
),
2514 D2bv(SrcSI
| DstAcc
| Mov
| String
),
2515 D2bv(SrcAcc
| DstDI
| String
),
2517 X8(D(ByteOp
| DstReg
| SrcImm
| Mov
)),
2519 X8(D(DstReg
| SrcImm
| Mov
)),
2521 D2bv(DstMem
| SrcImmByte
| ModRM
),
2522 I(ImplicitOps
| Stack
| SrcImmU16
, em_ret_near_imm
),
2523 D(ImplicitOps
| Stack
),
2524 D(DstReg
| SrcMemFAddr
| ModRM
| No64
), D(DstReg
| SrcMemFAddr
| ModRM
| No64
),
2525 D2bv(DstMem
| SrcImm
| ModRM
| Mov
),
2527 N
, N
, N
, D(ImplicitOps
| Stack
),
2528 D(ImplicitOps
), D(SrcImmByte
), D(ImplicitOps
| No64
), D(ImplicitOps
),
2530 D2bv(DstMem
| SrcOne
| ModRM
), D2bv(DstMem
| ModRM
),
2533 N
, N
, N
, N
, N
, N
, N
, N
,
2536 D2bv(SrcImmUByte
| DstAcc
), D2bv(SrcAcc
| DstImmUByte
),
2538 D(SrcImm
| Stack
), D(SrcImm
| ImplicitOps
),
2539 D(SrcImmFAddr
| No64
), D(SrcImmByte
| ImplicitOps
),
2540 D2bv(SrcNone
| DstAcc
), D2bv(SrcAcc
| ImplicitOps
),
2543 D(ImplicitOps
| Priv
), D(ImplicitOps
), G(ByteOp
, group3
), G(0, group3
),
2545 D(ImplicitOps
), D(ImplicitOps
), D(ImplicitOps
), D(ImplicitOps
),
2546 D(ImplicitOps
), D(ImplicitOps
), G(0, group4
), G(0, group5
),
2549 static struct opcode twobyte_table
[256] = {
2551 N
, GD(0, &group7
), N
, N
,
2552 N
, D(ImplicitOps
), D(ImplicitOps
| Priv
), N
,
2553 D(ImplicitOps
| Priv
), D(ImplicitOps
| Priv
), N
, N
,
2554 N
, D(ImplicitOps
| ModRM
), N
, N
,
2556 N
, N
, N
, N
, N
, N
, N
, N
, D(ImplicitOps
| ModRM
), N
, N
, N
, N
, N
, N
, N
,
2558 D(ModRM
| DstMem
| Priv
| Op3264
), D(ModRM
| DstMem
| Priv
| Op3264
),
2559 D(ModRM
| SrcMem
| Priv
| Op3264
), D(ModRM
| SrcMem
| Priv
| Op3264
),
2561 N
, N
, N
, N
, N
, N
, N
, N
,
2563 D(ImplicitOps
| Priv
), I(ImplicitOps
, em_rdtsc
),
2564 D(ImplicitOps
| Priv
), N
,
2565 D(ImplicitOps
), D(ImplicitOps
| Priv
), N
, N
,
2566 N
, N
, N
, N
, N
, N
, N
, N
,
2568 X16(D(DstReg
| SrcMem
| ModRM
| Mov
)),
2570 N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
,
2572 N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
,
2574 N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
,
2578 X16(D(ByteOp
| DstMem
| SrcNone
| ModRM
| Mov
)),
2580 D(ImplicitOps
| Stack
), D(ImplicitOps
| Stack
),
2581 N
, D(DstMem
| SrcReg
| ModRM
| BitOp
),
2582 D(DstMem
| SrcReg
| Src2ImmByte
| ModRM
),
2583 D(DstMem
| SrcReg
| Src2CL
| ModRM
), N
, N
,
2585 D(ImplicitOps
| Stack
), D(ImplicitOps
| Stack
),
2586 N
, D(DstMem
| SrcReg
| ModRM
| BitOp
| Lock
),
2587 D(DstMem
| SrcReg
| Src2ImmByte
| ModRM
),
2588 D(DstMem
| SrcReg
| Src2CL
| ModRM
),
2589 D(ModRM
), I(DstReg
| SrcMem
| ModRM
, em_imul
),
2591 D2bv(DstMem
| SrcReg
| ModRM
| Lock
),
2592 D(DstReg
| SrcMemFAddr
| ModRM
), D(DstMem
| SrcReg
| ModRM
| BitOp
| Lock
),
2593 D(DstReg
| SrcMemFAddr
| ModRM
), D(DstReg
| SrcMemFAddr
| ModRM
),
2594 D(ByteOp
| DstReg
| SrcMem
| ModRM
| Mov
), D(DstReg
| SrcMem16
| ModRM
| Mov
),
2597 G(BitOp
, group8
), D(DstMem
| SrcReg
| ModRM
| BitOp
| Lock
),
2598 D(DstReg
| SrcMem
| ModRM
), D(DstReg
| SrcMem
| ModRM
),
2599 D(ByteOp
| DstReg
| SrcMem
| ModRM
| Mov
), D(DstReg
| SrcMem16
| ModRM
| Mov
),
2601 D2bv(DstMem
| SrcReg
| ModRM
| Lock
),
2602 N
, D(DstMem
| SrcReg
| ModRM
| Mov
),
2603 N
, N
, N
, GD(0, &group9
),
2604 N
, N
, N
, N
, N
, N
, N
, N
,
2606 N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
,
2608 N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
,
2610 N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
2622 static unsigned imm_size(struct decode_cache
*c
)
2626 size
= (c
->d
& ByteOp
) ? 1 : c
->op_bytes
;
2632 static int decode_imm(struct x86_emulate_ctxt
*ctxt
, struct operand
*op
,
2633 unsigned size
, bool sign_extension
)
2635 struct decode_cache
*c
= &ctxt
->decode
;
2636 struct x86_emulate_ops
*ops
= ctxt
->ops
;
2637 int rc
= X86EMUL_CONTINUE
;
2641 op
->addr
.mem
= c
->eip
;
2642 /* NB. Immediates are sign-extended as necessary. */
2643 switch (op
->bytes
) {
2645 op
->val
= insn_fetch(s8
, 1, c
->eip
);
2648 op
->val
= insn_fetch(s16
, 2, c
->eip
);
2651 op
->val
= insn_fetch(s32
, 4, c
->eip
);
2654 if (!sign_extension
) {
2655 switch (op
->bytes
) {
2663 op
->val
&= 0xffffffff;
2672 x86_decode_insn(struct x86_emulate_ctxt
*ctxt
)
2674 struct x86_emulate_ops
*ops
= ctxt
->ops
;
2675 struct decode_cache
*c
= &ctxt
->decode
;
2676 int rc
= X86EMUL_CONTINUE
;
2677 int mode
= ctxt
->mode
;
2678 int def_op_bytes
, def_ad_bytes
, dual
, goffset
;
2679 struct opcode opcode
, *g_mod012
, *g_mod3
;
2680 struct operand memop
= { .type
= OP_NONE
};
2683 c
->fetch
.start
= c
->fetch
.end
= c
->eip
;
2684 ctxt
->cs_base
= seg_base(ctxt
, ops
, VCPU_SREG_CS
);
2687 case X86EMUL_MODE_REAL
:
2688 case X86EMUL_MODE_VM86
:
2689 case X86EMUL_MODE_PROT16
:
2690 def_op_bytes
= def_ad_bytes
= 2;
2692 case X86EMUL_MODE_PROT32
:
2693 def_op_bytes
= def_ad_bytes
= 4;
2695 #ifdef CONFIG_X86_64
2696 case X86EMUL_MODE_PROT64
:
2705 c
->op_bytes
= def_op_bytes
;
2706 c
->ad_bytes
= def_ad_bytes
;
2708 /* Legacy prefixes. */
2710 switch (c
->b
= insn_fetch(u8
, 1, c
->eip
)) {
2711 case 0x66: /* operand-size override */
2712 /* switch between 2/4 bytes */
2713 c
->op_bytes
= def_op_bytes
^ 6;
2715 case 0x67: /* address-size override */
2716 if (mode
== X86EMUL_MODE_PROT64
)
2717 /* switch between 4/8 bytes */
2718 c
->ad_bytes
= def_ad_bytes
^ 12;
2720 /* switch between 2/4 bytes */
2721 c
->ad_bytes
= def_ad_bytes
^ 6;
2723 case 0x26: /* ES override */
2724 case 0x2e: /* CS override */
2725 case 0x36: /* SS override */
2726 case 0x3e: /* DS override */
2727 set_seg_override(c
, (c
->b
>> 3) & 3);
2729 case 0x64: /* FS override */
2730 case 0x65: /* GS override */
2731 set_seg_override(c
, c
->b
& 7);
2733 case 0x40 ... 0x4f: /* REX */
2734 if (mode
!= X86EMUL_MODE_PROT64
)
2736 c
->rex_prefix
= c
->b
;
2738 case 0xf0: /* LOCK */
2741 case 0xf2: /* REPNE/REPNZ */
2742 c
->rep_prefix
= REPNE_PREFIX
;
2744 case 0xf3: /* REP/REPE/REPZ */
2745 c
->rep_prefix
= REPE_PREFIX
;
2751 /* Any legacy prefix after a REX prefix nullifies its effect. */
2759 if (c
->rex_prefix
& 8)
2760 c
->op_bytes
= 8; /* REX.W */
2762 /* Opcode byte(s). */
2763 opcode
= opcode_table
[c
->b
];
2764 /* Two-byte opcode? */
2767 c
->b
= insn_fetch(u8
, 1, c
->eip
);
2768 opcode
= twobyte_table
[c
->b
];
2770 c
->d
= opcode
.flags
;
2773 dual
= c
->d
& GroupDual
;
2774 c
->modrm
= insn_fetch(u8
, 1, c
->eip
);
2777 if (c
->d
& GroupDual
) {
2778 g_mod012
= opcode
.u
.gdual
->mod012
;
2779 g_mod3
= opcode
.u
.gdual
->mod3
;
2781 g_mod012
= g_mod3
= opcode
.u
.group
;
2783 c
->d
&= ~(Group
| GroupDual
);
2785 goffset
= (c
->modrm
>> 3) & 7;
2787 if ((c
->modrm
>> 6) == 3)
2788 opcode
= g_mod3
[goffset
];
2790 opcode
= g_mod012
[goffset
];
2791 c
->d
|= opcode
.flags
;
2794 c
->execute
= opcode
.u
.execute
;
2797 if (c
->d
== 0 || (c
->d
& Undefined
)) {
2798 DPRINTF("Cannot emulate %02x\n", c
->b
);
2802 if (mode
== X86EMUL_MODE_PROT64
&& (c
->d
& Stack
))
2805 if (c
->d
& Op3264
) {
2806 if (mode
== X86EMUL_MODE_PROT64
)
2812 /* ModRM and SIB bytes. */
2814 rc
= decode_modrm(ctxt
, ops
, &memop
);
2815 if (!c
->has_seg_override
)
2816 set_seg_override(c
, c
->modrm_seg
);
2817 } else if (c
->d
& MemAbs
)
2818 rc
= decode_abs(ctxt
, ops
, &memop
);
2819 if (rc
!= X86EMUL_CONTINUE
)
2822 if (!c
->has_seg_override
)
2823 set_seg_override(c
, VCPU_SREG_DS
);
2825 if (memop
.type
== OP_MEM
&& !(!c
->twobyte
&& c
->b
== 0x8d))
2826 memop
.addr
.mem
+= seg_override_base(ctxt
, ops
, c
);
2828 if (memop
.type
== OP_MEM
&& c
->ad_bytes
!= 8)
2829 memop
.addr
.mem
= (u32
)memop
.addr
.mem
;
2831 if (memop
.type
== OP_MEM
&& c
->rip_relative
)
2832 memop
.addr
.mem
+= c
->eip
;
2835 * Decode and fetch the source operand: register, memory
2838 switch (c
->d
& SrcMask
) {
2842 decode_register_operand(&c
->src
, c
, 0);
2851 memop
.bytes
= (c
->d
& ByteOp
) ? 1 :
2857 rc
= decode_imm(ctxt
, &c
->src
, 2, false);
2860 rc
= decode_imm(ctxt
, &c
->src
, imm_size(c
), true);
2863 rc
= decode_imm(ctxt
, &c
->src
, imm_size(c
), false);
2866 rc
= decode_imm(ctxt
, &c
->src
, 1, true);
2869 rc
= decode_imm(ctxt
, &c
->src
, 1, false);
2872 c
->src
.type
= OP_REG
;
2873 c
->src
.bytes
= (c
->d
& ByteOp
) ? 1 : c
->op_bytes
;
2874 c
->src
.addr
.reg
= &c
->regs
[VCPU_REGS_RAX
];
2875 fetch_register_operand(&c
->src
);
2882 c
->src
.type
= OP_MEM
;
2883 c
->src
.bytes
= (c
->d
& ByteOp
) ? 1 : c
->op_bytes
;
2885 register_address(c
, seg_override_base(ctxt
, ops
, c
),
2886 c
->regs
[VCPU_REGS_RSI
]);
2890 c
->src
.type
= OP_IMM
;
2891 c
->src
.addr
.mem
= c
->eip
;
2892 c
->src
.bytes
= c
->op_bytes
+ 2;
2893 insn_fetch_arr(c
->src
.valptr
, c
->src
.bytes
, c
->eip
);
2896 memop
.bytes
= c
->op_bytes
+ 2;
2901 if (rc
!= X86EMUL_CONTINUE
)
2905 * Decode and fetch the second source operand: register, memory
2908 switch (c
->d
& Src2Mask
) {
2913 c
->src2
.val
= c
->regs
[VCPU_REGS_RCX
] & 0x8;
2916 rc
= decode_imm(ctxt
, &c
->src2
, 1, true);
2923 rc
= decode_imm(ctxt
, &c
->src2
, imm_size(c
), true);
2927 if (rc
!= X86EMUL_CONTINUE
)
2930 /* Decode and fetch the destination operand: register or memory. */
2931 switch (c
->d
& DstMask
) {
2933 decode_register_operand(&c
->dst
, c
,
2934 c
->twobyte
&& (c
->b
== 0xb6 || c
->b
== 0xb7));
2937 c
->dst
.type
= OP_IMM
;
2938 c
->dst
.addr
.mem
= c
->eip
;
2940 c
->dst
.val
= insn_fetch(u8
, 1, c
->eip
);
2945 if ((c
->d
& DstMask
) == DstMem64
)
2948 c
->dst
.bytes
= (c
->d
& ByteOp
) ? 1 : c
->op_bytes
;
2950 fetch_bit_operand(c
);
2951 c
->dst
.orig_val
= c
->dst
.val
;
2954 c
->dst
.type
= OP_REG
;
2955 c
->dst
.bytes
= (c
->d
& ByteOp
) ? 1 : c
->op_bytes
;
2956 c
->dst
.addr
.reg
= &c
->regs
[VCPU_REGS_RAX
];
2957 fetch_register_operand(&c
->dst
);
2958 c
->dst
.orig_val
= c
->dst
.val
;
2961 c
->dst
.type
= OP_MEM
;
2962 c
->dst
.bytes
= (c
->d
& ByteOp
) ? 1 : c
->op_bytes
;
2964 register_address(c
, es_base(ctxt
, ops
),
2965 c
->regs
[VCPU_REGS_RDI
]);
2969 /* Special instructions do their own operand decoding. */
2971 c
->dst
.type
= OP_NONE
; /* Disable writeback. */
2976 return (rc
== X86EMUL_UNHANDLEABLE
) ? -1 : 0;
2979 static bool string_insn_completed(struct x86_emulate_ctxt
*ctxt
)
2981 struct decode_cache
*c
= &ctxt
->decode
;
2983 /* The second termination condition only applies for REPE
2984 * and REPNE. Test if the repeat string operation prefix is
2985 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2986 * corresponding termination condition according to:
2987 * - if REPE/REPZ and ZF = 0 then done
2988 * - if REPNE/REPNZ and ZF = 1 then done
2990 if (((c
->b
== 0xa6) || (c
->b
== 0xa7) ||
2991 (c
->b
== 0xae) || (c
->b
== 0xaf))
2992 && (((c
->rep_prefix
== REPE_PREFIX
) &&
2993 ((ctxt
->eflags
& EFLG_ZF
) == 0))
2994 || ((c
->rep_prefix
== REPNE_PREFIX
) &&
2995 ((ctxt
->eflags
& EFLG_ZF
) == EFLG_ZF
))))
3002 x86_emulate_insn(struct x86_emulate_ctxt
*ctxt
)
3004 struct x86_emulate_ops
*ops
= ctxt
->ops
;
3006 struct decode_cache
*c
= &ctxt
->decode
;
3007 int rc
= X86EMUL_CONTINUE
;
3008 int saved_dst_type
= c
->dst
.type
;
3009 int irq
; /* Used for int 3, int, and into */
3011 ctxt
->decode
.mem_read
.pos
= 0;
3013 if (ctxt
->mode
== X86EMUL_MODE_PROT64
&& (c
->d
& No64
)) {
3018 /* LOCK prefix is allowed only with some instructions */
3019 if (c
->lock_prefix
&& (!(c
->d
& Lock
) || c
->dst
.type
!= OP_MEM
)) {
3024 if ((c
->d
& SrcMask
) == SrcMemFAddr
&& c
->src
.type
!= OP_MEM
) {
3029 /* Privileged instruction can be executed only in CPL=0 */
3030 if ((c
->d
& Priv
) && ops
->cpl(ctxt
->vcpu
)) {
3031 emulate_gp(ctxt
, 0);
3035 if (c
->rep_prefix
&& (c
->d
& String
)) {
3036 /* All REP prefixes have the same first termination condition */
3037 if (address_mask(c
, c
->regs
[VCPU_REGS_RCX
]) == 0) {
3043 if ((c
->src
.type
== OP_MEM
) && !(c
->d
& NoAccess
)) {
3044 rc
= read_emulated(ctxt
, ops
, c
->src
.addr
.mem
,
3045 c
->src
.valptr
, c
->src
.bytes
);
3046 if (rc
!= X86EMUL_CONTINUE
)
3048 c
->src
.orig_val64
= c
->src
.val64
;
3051 if (c
->src2
.type
== OP_MEM
) {
3052 rc
= read_emulated(ctxt
, ops
, c
->src2
.addr
.mem
,
3053 &c
->src2
.val
, c
->src2
.bytes
);
3054 if (rc
!= X86EMUL_CONTINUE
)
3058 if ((c
->d
& DstMask
) == ImplicitOps
)
3062 if ((c
->dst
.type
== OP_MEM
) && !(c
->d
& Mov
)) {
3063 /* optimisation - avoid slow emulated read if Mov */
3064 rc
= read_emulated(ctxt
, ops
, c
->dst
.addr
.mem
,
3065 &c
->dst
.val
, c
->dst
.bytes
);
3066 if (rc
!= X86EMUL_CONTINUE
)
3069 c
->dst
.orig_val
= c
->dst
.val
;
3074 rc
= c
->execute(ctxt
);
3075 if (rc
!= X86EMUL_CONTINUE
)
3086 emulate_2op_SrcV("add", c
->src
, c
->dst
, ctxt
->eflags
);
3088 case 0x06: /* push es */
3089 emulate_push_sreg(ctxt
, ops
, VCPU_SREG_ES
);
3091 case 0x07: /* pop es */
3092 rc
= emulate_pop_sreg(ctxt
, ops
, VCPU_SREG_ES
);
3093 if (rc
!= X86EMUL_CONTINUE
)
3098 emulate_2op_SrcV("or", c
->src
, c
->dst
, ctxt
->eflags
);
3100 case 0x0e: /* push cs */
3101 emulate_push_sreg(ctxt
, ops
, VCPU_SREG_CS
);
3105 emulate_2op_SrcV("adc", c
->src
, c
->dst
, ctxt
->eflags
);
3107 case 0x16: /* push ss */
3108 emulate_push_sreg(ctxt
, ops
, VCPU_SREG_SS
);
3110 case 0x17: /* pop ss */
3111 rc
= emulate_pop_sreg(ctxt
, ops
, VCPU_SREG_SS
);
3112 if (rc
!= X86EMUL_CONTINUE
)
3117 emulate_2op_SrcV("sbb", c
->src
, c
->dst
, ctxt
->eflags
);
3119 case 0x1e: /* push ds */
3120 emulate_push_sreg(ctxt
, ops
, VCPU_SREG_DS
);
3122 case 0x1f: /* pop ds */
3123 rc
= emulate_pop_sreg(ctxt
, ops
, VCPU_SREG_DS
);
3124 if (rc
!= X86EMUL_CONTINUE
)
3129 emulate_2op_SrcV("and", c
->src
, c
->dst
, ctxt
->eflags
);
3133 emulate_2op_SrcV("sub", c
->src
, c
->dst
, ctxt
->eflags
);
3137 emulate_2op_SrcV("xor", c
->src
, c
->dst
, ctxt
->eflags
);
3141 emulate_2op_SrcV("cmp", c
->src
, c
->dst
, ctxt
->eflags
);
3143 case 0x40 ... 0x47: /* inc r16/r32 */
3144 emulate_1op("inc", c
->dst
, ctxt
->eflags
);
3146 case 0x48 ... 0x4f: /* dec r16/r32 */
3147 emulate_1op("dec", c
->dst
, ctxt
->eflags
);
3149 case 0x58 ... 0x5f: /* pop reg */
3151 rc
= emulate_pop(ctxt
, ops
, &c
->dst
.val
, c
->op_bytes
);
3152 if (rc
!= X86EMUL_CONTINUE
)
3155 case 0x60: /* pusha */
3156 rc
= emulate_pusha(ctxt
, ops
);
3157 if (rc
!= X86EMUL_CONTINUE
)
3160 case 0x61: /* popa */
3161 rc
= emulate_popa(ctxt
, ops
);
3162 if (rc
!= X86EMUL_CONTINUE
)
3165 case 0x63: /* movsxd */
3166 if (ctxt
->mode
!= X86EMUL_MODE_PROT64
)
3167 goto cannot_emulate
;
3168 c
->dst
.val
= (s32
) c
->src
.val
;
3170 case 0x6c: /* insb */
3171 case 0x6d: /* insw/insd */
3172 c
->src
.val
= c
->regs
[VCPU_REGS_RDX
];
3174 case 0x6e: /* outsb */
3175 case 0x6f: /* outsw/outsd */
3176 c
->dst
.val
= c
->regs
[VCPU_REGS_RDX
];
3179 case 0x70 ... 0x7f: /* jcc (short) */
3180 if (test_cc(c
->b
, ctxt
->eflags
))
3181 jmp_rel(c
, c
->src
.val
);
3183 case 0x80 ... 0x83: /* Grp1 */
3184 switch (c
->modrm_reg
) {
3205 emulate_2op_SrcV("test", c
->src
, c
->dst
, ctxt
->eflags
);
3207 case 0x86 ... 0x87: /* xchg */
3209 /* Write back the register source. */
3210 c
->src
.val
= c
->dst
.val
;
3211 write_register_operand(&c
->src
);
3213 * Write back the memory destination with implicit LOCK
3216 c
->dst
.val
= c
->src
.orig_val
;
3219 case 0x88 ... 0x8b: /* mov */
3221 case 0x8c: /* mov r/m, sreg */
3222 if (c
->modrm_reg
> VCPU_SREG_GS
) {
3226 c
->dst
.val
= ops
->get_segment_selector(c
->modrm_reg
, ctxt
->vcpu
);
3228 case 0x8d: /* lea r16/r32, m */
3229 c
->dst
.val
= c
->src
.addr
.mem
;
3231 case 0x8e: { /* mov seg, r/m16 */
3236 if (c
->modrm_reg
== VCPU_SREG_CS
||
3237 c
->modrm_reg
> VCPU_SREG_GS
) {
3242 if (c
->modrm_reg
== VCPU_SREG_SS
)
3243 ctxt
->interruptibility
= KVM_X86_SHADOW_INT_MOV_SS
;
3245 rc
= load_segment_descriptor(ctxt
, ops
, sel
, c
->modrm_reg
);
3247 c
->dst
.type
= OP_NONE
; /* Disable writeback. */
3250 case 0x8f: /* pop (sole member of Grp1a) */
3251 rc
= emulate_grp1a(ctxt
, ops
);
3252 if (rc
!= X86EMUL_CONTINUE
)
3255 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3256 if (c
->dst
.addr
.reg
== &c
->regs
[VCPU_REGS_RAX
])
3259 case 0x98: /* cbw/cwde/cdqe */
3260 switch (c
->op_bytes
) {
3261 case 2: c
->dst
.val
= (s8
)c
->dst
.val
; break;
3262 case 4: c
->dst
.val
= (s16
)c
->dst
.val
; break;
3263 case 8: c
->dst
.val
= (s32
)c
->dst
.val
; break;
3266 case 0x9c: /* pushf */
3267 c
->src
.val
= (unsigned long) ctxt
->eflags
;
3268 emulate_push(ctxt
, ops
);
3270 case 0x9d: /* popf */
3271 c
->dst
.type
= OP_REG
;
3272 c
->dst
.addr
.reg
= &ctxt
->eflags
;
3273 c
->dst
.bytes
= c
->op_bytes
;
3274 rc
= emulate_popf(ctxt
, ops
, &c
->dst
.val
, c
->op_bytes
);
3275 if (rc
!= X86EMUL_CONTINUE
)
3278 case 0xa0 ... 0xa3: /* mov */
3279 case 0xa4 ... 0xa5: /* movs */
3281 case 0xa6 ... 0xa7: /* cmps */
3282 c
->dst
.type
= OP_NONE
; /* Disable writeback. */
3283 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c
->src
.addr
.mem
, c
->dst
.addr
.mem
);
3285 case 0xa8 ... 0xa9: /* test ax, imm */
3287 case 0xaa ... 0xab: /* stos */
3288 case 0xac ... 0xad: /* lods */
3290 case 0xae ... 0xaf: /* scas */
3292 case 0xb0 ... 0xbf: /* mov r, imm */
3297 case 0xc3: /* ret */
3298 c
->dst
.type
= OP_REG
;
3299 c
->dst
.addr
.reg
= &c
->eip
;
3300 c
->dst
.bytes
= c
->op_bytes
;
3301 goto pop_instruction
;
3302 case 0xc4: /* les */
3303 rc
= emulate_load_segment(ctxt
, ops
, VCPU_SREG_ES
);
3304 if (rc
!= X86EMUL_CONTINUE
)
3307 case 0xc5: /* lds */
3308 rc
= emulate_load_segment(ctxt
, ops
, VCPU_SREG_DS
);
3309 if (rc
!= X86EMUL_CONTINUE
)
3312 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
3314 c
->dst
.val
= c
->src
.val
;
3316 case 0xcb: /* ret far */
3317 rc
= emulate_ret_far(ctxt
, ops
);
3318 if (rc
!= X86EMUL_CONTINUE
)
3321 case 0xcc: /* int3 */
3324 case 0xcd: /* int n */
3327 rc
= emulate_int(ctxt
, ops
, irq
);
3328 if (rc
!= X86EMUL_CONTINUE
)
3331 case 0xce: /* into */
3332 if (ctxt
->eflags
& EFLG_OF
) {
3337 case 0xcf: /* iret */
3338 rc
= emulate_iret(ctxt
, ops
);
3340 if (rc
!= X86EMUL_CONTINUE
)
3343 case 0xd0 ... 0xd1: /* Grp2 */
3346 case 0xd2 ... 0xd3: /* Grp2 */
3347 c
->src
.val
= c
->regs
[VCPU_REGS_RCX
];
3350 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3351 register_address_increment(c
, &c
->regs
[VCPU_REGS_RCX
], -1);
3352 if (address_mask(c
, c
->regs
[VCPU_REGS_RCX
]) != 0 &&
3353 (c
->b
== 0xe2 || test_cc(c
->b
^ 0x5, ctxt
->eflags
)))
3354 jmp_rel(c
, c
->src
.val
);
3356 case 0xe3: /* jcxz/jecxz/jrcxz */
3357 if (address_mask(c
, c
->regs
[VCPU_REGS_RCX
]) == 0)
3358 jmp_rel(c
, c
->src
.val
);
3360 case 0xe4: /* inb */
3363 case 0xe6: /* outb */
3364 case 0xe7: /* out */
3366 case 0xe8: /* call (near) */ {
3367 long int rel
= c
->src
.val
;
3368 c
->src
.val
= (unsigned long) c
->eip
;
3370 emulate_push(ctxt
, ops
);
3373 case 0xe9: /* jmp rel */
3375 case 0xea: { /* jmp far */
3378 memcpy(&sel
, c
->src
.valptr
+ c
->op_bytes
, 2);
3380 if (load_segment_descriptor(ctxt
, ops
, sel
, VCPU_SREG_CS
))
3384 memcpy(&c
->eip
, c
->src
.valptr
, c
->op_bytes
);
3388 jmp
: /* jmp rel short */
3389 jmp_rel(c
, c
->src
.val
);
3390 c
->dst
.type
= OP_NONE
; /* Disable writeback. */
3392 case 0xec: /* in al,dx */
3393 case 0xed: /* in (e/r)ax,dx */
3394 c
->src
.val
= c
->regs
[VCPU_REGS_RDX
];
3396 c
->dst
.bytes
= min(c
->dst
.bytes
, 4u);
3397 if (!emulator_io_permited(ctxt
, ops
, c
->src
.val
, c
->dst
.bytes
)) {
3398 emulate_gp(ctxt
, 0);
3401 if (!pio_in_emulated(ctxt
, ops
, c
->dst
.bytes
, c
->src
.val
,
3403 goto done
; /* IO is needed */
3405 case 0xee: /* out dx,al */
3406 case 0xef: /* out dx,(e/r)ax */
3407 c
->dst
.val
= c
->regs
[VCPU_REGS_RDX
];
3409 c
->src
.bytes
= min(c
->src
.bytes
, 4u);
3410 if (!emulator_io_permited(ctxt
, ops
, c
->dst
.val
,
3412 emulate_gp(ctxt
, 0);
3415 ops
->pio_out_emulated(c
->src
.bytes
, c
->dst
.val
,
3416 &c
->src
.val
, 1, ctxt
->vcpu
);
3417 c
->dst
.type
= OP_NONE
; /* Disable writeback. */
3419 case 0xf4: /* hlt */
3420 ctxt
->vcpu
->arch
.halt_request
= 1;
3422 case 0xf5: /* cmc */
3423 /* complement carry flag from eflags reg */
3424 ctxt
->eflags
^= EFLG_CF
;
3426 case 0xf6 ... 0xf7: /* Grp3 */
3427 rc
= emulate_grp3(ctxt
, ops
);
3428 if (rc
!= X86EMUL_CONTINUE
)
3431 case 0xf8: /* clc */
3432 ctxt
->eflags
&= ~EFLG_CF
;
3434 case 0xf9: /* stc */
3435 ctxt
->eflags
|= EFLG_CF
;
3437 case 0xfa: /* cli */
3438 if (emulator_bad_iopl(ctxt
, ops
)) {
3439 emulate_gp(ctxt
, 0);
3442 ctxt
->eflags
&= ~X86_EFLAGS_IF
;
3444 case 0xfb: /* sti */
3445 if (emulator_bad_iopl(ctxt
, ops
)) {
3446 emulate_gp(ctxt
, 0);
3449 ctxt
->interruptibility
= KVM_X86_SHADOW_INT_STI
;
3450 ctxt
->eflags
|= X86_EFLAGS_IF
;
3453 case 0xfc: /* cld */
3454 ctxt
->eflags
&= ~EFLG_DF
;
3456 case 0xfd: /* std */
3457 ctxt
->eflags
|= EFLG_DF
;
3459 case 0xfe: /* Grp4 */
3461 rc
= emulate_grp45(ctxt
, ops
);
3462 if (rc
!= X86EMUL_CONTINUE
)
3465 case 0xff: /* Grp5 */
3466 if (c
->modrm_reg
== 5)
3470 goto cannot_emulate
;
3474 rc
= writeback(ctxt
, ops
);
3475 if (rc
!= X86EMUL_CONTINUE
)
3479 * restore dst type in case the decoding will be reused
3480 * (happens for string instruction )
3482 c
->dst
.type
= saved_dst_type
;
3484 if ((c
->d
& SrcMask
) == SrcSI
)
3485 string_addr_inc(ctxt
, seg_override_base(ctxt
, ops
, c
),
3486 VCPU_REGS_RSI
, &c
->src
);
3488 if ((c
->d
& DstMask
) == DstDI
)
3489 string_addr_inc(ctxt
, es_base(ctxt
, ops
), VCPU_REGS_RDI
,
3492 if (c
->rep_prefix
&& (c
->d
& String
)) {
3493 struct read_cache
*r
= &ctxt
->decode
.io_read
;
3494 register_address_increment(c
, &c
->regs
[VCPU_REGS_RCX
], -1);
3496 if (!string_insn_completed(ctxt
)) {
3498 * Re-enter guest when pio read ahead buffer is empty
3499 * or, if it is not used, after each 1024 iteration.
3501 if ((r
->end
!= 0 || c
->regs
[VCPU_REGS_RCX
] & 0x3ff) &&
3502 (r
->end
== 0 || r
->end
!= r
->pos
)) {
3504 * Reset read cache. Usually happens before
3505 * decode, but since instruction is restarted
3506 * we have to do it here.
3508 ctxt
->decode
.mem_read
.end
= 0;
3509 return EMULATION_RESTART
;
3511 goto done
; /* skip rip writeback */
3518 return (rc
== X86EMUL_UNHANDLEABLE
) ? EMULATION_FAILED
: EMULATION_OK
;
3522 case 0x01: /* lgdt, lidt, lmsw */
3523 switch (c
->modrm_reg
) {
3525 unsigned long address
;
3527 case 0: /* vmcall */
3528 if (c
->modrm_mod
!= 3 || c
->modrm_rm
!= 1)
3529 goto cannot_emulate
;
3531 rc
= kvm_fix_hypercall(ctxt
->vcpu
);
3532 if (rc
!= X86EMUL_CONTINUE
)
3535 /* Let the processor re-execute the fixed hypercall */
3537 /* Disable writeback. */
3538 c
->dst
.type
= OP_NONE
;
3541 rc
= read_descriptor(ctxt
, ops
, c
->src
.addr
.mem
,
3542 &size
, &address
, c
->op_bytes
);
3543 if (rc
!= X86EMUL_CONTINUE
)
3545 realmode_lgdt(ctxt
->vcpu
, size
, address
);
3546 /* Disable writeback. */
3547 c
->dst
.type
= OP_NONE
;
3549 case 3: /* lidt/vmmcall */
3550 if (c
->modrm_mod
== 3) {
3551 switch (c
->modrm_rm
) {
3553 rc
= kvm_fix_hypercall(ctxt
->vcpu
);
3554 if (rc
!= X86EMUL_CONTINUE
)
3558 goto cannot_emulate
;
3561 rc
= read_descriptor(ctxt
, ops
, c
->src
.addr
.mem
,
3564 if (rc
!= X86EMUL_CONTINUE
)
3566 realmode_lidt(ctxt
->vcpu
, size
, address
);
3568 /* Disable writeback. */
3569 c
->dst
.type
= OP_NONE
;
3573 c
->dst
.val
= ops
->get_cr(0, ctxt
->vcpu
);
3576 ops
->set_cr(0, (ops
->get_cr(0, ctxt
->vcpu
) & ~0x0eul
) |
3577 (c
->src
.val
& 0x0f), ctxt
->vcpu
);
3578 c
->dst
.type
= OP_NONE
;
3580 case 5: /* not defined */
3584 emulate_invlpg(ctxt
->vcpu
, c
->src
.addr
.mem
);
3585 /* Disable writeback. */
3586 c
->dst
.type
= OP_NONE
;
3589 goto cannot_emulate
;
3592 case 0x05: /* syscall */
3593 rc
= emulate_syscall(ctxt
, ops
);
3594 if (rc
!= X86EMUL_CONTINUE
)
3600 emulate_clts(ctxt
->vcpu
);
3602 case 0x09: /* wbinvd */
3603 kvm_emulate_wbinvd(ctxt
->vcpu
);
3605 case 0x08: /* invd */
3606 case 0x0d: /* GrpP (prefetch) */
3607 case 0x18: /* Grp16 (prefetch/nop) */
3609 case 0x20: /* mov cr, reg */
3610 switch (c
->modrm_reg
) {
3617 c
->dst
.val
= ops
->get_cr(c
->modrm_reg
, ctxt
->vcpu
);
3619 case 0x21: /* mov from dr to reg */
3620 if ((ops
->get_cr(4, ctxt
->vcpu
) & X86_CR4_DE
) &&
3621 (c
->modrm_reg
== 4 || c
->modrm_reg
== 5)) {
3625 ops
->get_dr(c
->modrm_reg
, &c
->dst
.val
, ctxt
->vcpu
);
3627 case 0x22: /* mov reg, cr */
3628 if (ops
->set_cr(c
->modrm_reg
, c
->src
.val
, ctxt
->vcpu
)) {
3629 emulate_gp(ctxt
, 0);
3632 c
->dst
.type
= OP_NONE
;
3634 case 0x23: /* mov from reg to dr */
3635 if ((ops
->get_cr(4, ctxt
->vcpu
) & X86_CR4_DE
) &&
3636 (c
->modrm_reg
== 4 || c
->modrm_reg
== 5)) {
3641 if (ops
->set_dr(c
->modrm_reg
, c
->src
.val
&
3642 ((ctxt
->mode
== X86EMUL_MODE_PROT64
) ?
3643 ~0ULL : ~0U), ctxt
->vcpu
) < 0) {
3644 /* #UD condition is already handled by the code above */
3645 emulate_gp(ctxt
, 0);
3649 c
->dst
.type
= OP_NONE
; /* no writeback */
3653 msr_data
= (u32
)c
->regs
[VCPU_REGS_RAX
]
3654 | ((u64
)c
->regs
[VCPU_REGS_RDX
] << 32);
3655 if (ops
->set_msr(ctxt
->vcpu
, c
->regs
[VCPU_REGS_RCX
], msr_data
)) {
3656 emulate_gp(ctxt
, 0);
3659 rc
= X86EMUL_CONTINUE
;
3663 if (ops
->get_msr(ctxt
->vcpu
, c
->regs
[VCPU_REGS_RCX
], &msr_data
)) {
3664 emulate_gp(ctxt
, 0);
3667 c
->regs
[VCPU_REGS_RAX
] = (u32
)msr_data
;
3668 c
->regs
[VCPU_REGS_RDX
] = msr_data
>> 32;
3670 rc
= X86EMUL_CONTINUE
;
3672 case 0x34: /* sysenter */
3673 rc
= emulate_sysenter(ctxt
, ops
);
3674 if (rc
!= X86EMUL_CONTINUE
)
3679 case 0x35: /* sysexit */
3680 rc
= emulate_sysexit(ctxt
, ops
);
3681 if (rc
!= X86EMUL_CONTINUE
)
3686 case 0x40 ... 0x4f: /* cmov */
3687 c
->dst
.val
= c
->dst
.orig_val
= c
->src
.val
;
3688 if (!test_cc(c
->b
, ctxt
->eflags
))
3689 c
->dst
.type
= OP_NONE
; /* no writeback */
3691 case 0x80 ... 0x8f: /* jnz rel, etc*/
3692 if (test_cc(c
->b
, ctxt
->eflags
))
3693 jmp_rel(c
, c
->src
.val
);
3695 case 0x90 ... 0x9f: /* setcc r/m8 */
3696 c
->dst
.val
= test_cc(c
->b
, ctxt
->eflags
);
3698 case 0xa0: /* push fs */
3699 emulate_push_sreg(ctxt
, ops
, VCPU_SREG_FS
);
3701 case 0xa1: /* pop fs */
3702 rc
= emulate_pop_sreg(ctxt
, ops
, VCPU_SREG_FS
);
3703 if (rc
!= X86EMUL_CONTINUE
)
3708 c
->dst
.type
= OP_NONE
;
3709 /* only subword offset */
3710 c
->src
.val
&= (c
->dst
.bytes
<< 3) - 1;
3711 emulate_2op_SrcV_nobyte("bt", c
->src
, c
->dst
, ctxt
->eflags
);
3713 case 0xa4: /* shld imm8, r, r/m */
3714 case 0xa5: /* shld cl, r, r/m */
3715 emulate_2op_cl("shld", c
->src2
, c
->src
, c
->dst
, ctxt
->eflags
);
3717 case 0xa8: /* push gs */
3718 emulate_push_sreg(ctxt
, ops
, VCPU_SREG_GS
);
3720 case 0xa9: /* pop gs */
3721 rc
= emulate_pop_sreg(ctxt
, ops
, VCPU_SREG_GS
);
3722 if (rc
!= X86EMUL_CONTINUE
)
3727 emulate_2op_SrcV_nobyte("bts", c
->src
, c
->dst
, ctxt
->eflags
);
3729 case 0xac: /* shrd imm8, r, r/m */
3730 case 0xad: /* shrd cl, r, r/m */
3731 emulate_2op_cl("shrd", c
->src2
, c
->src
, c
->dst
, ctxt
->eflags
);
3733 case 0xae: /* clflush */
3735 case 0xb0 ... 0xb1: /* cmpxchg */
3737 * Save real source value, then compare EAX against
3740 c
->src
.orig_val
= c
->src
.val
;
3741 c
->src
.val
= c
->regs
[VCPU_REGS_RAX
];
3742 emulate_2op_SrcV("cmp", c
->src
, c
->dst
, ctxt
->eflags
);
3743 if (ctxt
->eflags
& EFLG_ZF
) {
3744 /* Success: write back to memory. */
3745 c
->dst
.val
= c
->src
.orig_val
;
3747 /* Failure: write the value we saw to EAX. */
3748 c
->dst
.type
= OP_REG
;
3749 c
->dst
.addr
.reg
= (unsigned long *)&c
->regs
[VCPU_REGS_RAX
];
3752 case 0xb2: /* lss */
3753 rc
= emulate_load_segment(ctxt
, ops
, VCPU_SREG_SS
);
3754 if (rc
!= X86EMUL_CONTINUE
)
3759 emulate_2op_SrcV_nobyte("btr", c
->src
, c
->dst
, ctxt
->eflags
);
3761 case 0xb4: /* lfs */
3762 rc
= emulate_load_segment(ctxt
, ops
, VCPU_SREG_FS
);
3763 if (rc
!= X86EMUL_CONTINUE
)
3766 case 0xb5: /* lgs */
3767 rc
= emulate_load_segment(ctxt
, ops
, VCPU_SREG_GS
);
3768 if (rc
!= X86EMUL_CONTINUE
)
3771 case 0xb6 ... 0xb7: /* movzx */
3772 c
->dst
.bytes
= c
->op_bytes
;
3773 c
->dst
.val
= (c
->d
& ByteOp
) ? (u8
) c
->src
.val
3776 case 0xba: /* Grp8 */
3777 switch (c
->modrm_reg
& 3) {
3790 emulate_2op_SrcV_nobyte("btc", c
->src
, c
->dst
, ctxt
->eflags
);
3792 case 0xbc: { /* bsf */
3794 __asm__ ("bsf %2, %0; setz %1"
3795 : "=r"(c
->dst
.val
), "=q"(zf
)
3797 ctxt
->eflags
&= ~X86_EFLAGS_ZF
;
3799 ctxt
->eflags
|= X86_EFLAGS_ZF
;
3800 c
->dst
.type
= OP_NONE
; /* Disable writeback. */
3804 case 0xbd: { /* bsr */
3806 __asm__ ("bsr %2, %0; setz %1"
3807 : "=r"(c
->dst
.val
), "=q"(zf
)
3809 ctxt
->eflags
&= ~X86_EFLAGS_ZF
;
3811 ctxt
->eflags
|= X86_EFLAGS_ZF
;
3812 c
->dst
.type
= OP_NONE
; /* Disable writeback. */
3816 case 0xbe ... 0xbf: /* movsx */
3817 c
->dst
.bytes
= c
->op_bytes
;
3818 c
->dst
.val
= (c
->d
& ByteOp
) ? (s8
) c
->src
.val
:
3821 case 0xc0 ... 0xc1: /* xadd */
3822 emulate_2op_SrcV("add", c
->src
, c
->dst
, ctxt
->eflags
);
3823 /* Write back the register source. */
3824 c
->src
.val
= c
->dst
.orig_val
;
3825 write_register_operand(&c
->src
);
3827 case 0xc3: /* movnti */
3828 c
->dst
.bytes
= c
->op_bytes
;
3829 c
->dst
.val
= (c
->op_bytes
== 4) ? (u32
) c
->src
.val
:
3832 case 0xc7: /* Grp9 (cmpxchg8b) */
3833 rc
= emulate_grp9(ctxt
, ops
);
3834 if (rc
!= X86EMUL_CONTINUE
)
3838 goto cannot_emulate
;
3843 DPRINTF("Cannot emulate %02x\n", c
->b
);