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KVM: x86 emulator: add decoding of CMPXCHG8B dst operand
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22 #ifndef __KERNEL__
23 #include <stdio.h>
24 #include <stdint.h>
25 #include <public/xen.h>
26 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
27 #else
28 #include <linux/kvm_host.h>
29 #include "kvm_cache_regs.h"
30 #define DPRINTF(x...) do {} while (0)
31 #endif
32 #include <linux/module.h>
33 #include <asm/kvm_emulate.h>
34
35 #include "x86.h"
36 #include "tss.h"
37
38 /*
39 * Opcode effective-address decode tables.
40 * Note that we only emulate instructions that have at least one memory
41 * operand (excluding implicit stack references). We assume that stack
42 * references and instruction fetches will never occur in special memory
43 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
44 * not be handled.
45 */
46
47 /* Operand sizes: 8-bit operands or specified/overridden size. */
48 #define ByteOp (1<<0) /* 8-bit operands. */
49 /* Destination operand type. */
50 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
51 #define DstReg (2<<1) /* Register operand. */
52 #define DstMem (3<<1) /* Memory operand. */
53 #define DstAcc (4<<1) /* Destination Accumulator */
54 #define DstDI (5<<1) /* Destination is in ES:(E)DI */
55 #define DstMem64 (6<<1) /* 64bit memory operand */
56 #define DstMask (7<<1)
57 /* Source operand type. */
58 #define SrcNone (0<<4) /* No source operand. */
59 #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
60 #define SrcReg (1<<4) /* Register operand. */
61 #define SrcMem (2<<4) /* Memory operand. */
62 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
63 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
64 #define SrcImm (5<<4) /* Immediate operand. */
65 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
66 #define SrcOne (7<<4) /* Implied '1' */
67 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
68 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
69 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */
70 #define SrcMask (0xf<<4)
71 /* Generic ModRM decode. */
72 #define ModRM (1<<8)
73 /* Destination is only written; never read. */
74 #define Mov (1<<9)
75 #define BitOp (1<<10)
76 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
77 #define String (1<<12) /* String instruction (rep capable) */
78 #define Stack (1<<13) /* Stack instruction (push/pop) */
79 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
80 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
81 #define GroupMask 0xff /* Group number stored in bits 0:7 */
82 /* Misc flags */
83 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
84 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
85 #define No64 (1<<28)
86 /* Source 2 operand type */
87 #define Src2None (0<<29)
88 #define Src2CL (1<<29)
89 #define Src2ImmByte (2<<29)
90 #define Src2One (3<<29)
91 #define Src2Imm16 (4<<29)
92 #define Src2Mem16 (5<<29) /* Used for Ep encoding. First argument has to be
93 in memory and second argument is located
94 immediately after the first one in memory. */
95 #define Src2Mask (7<<29)
96
97 enum {
98 Group1_80, Group1_81, Group1_82, Group1_83,
99 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
100 Group8, Group9,
101 };
102
103 static u32 opcode_table[256] = {
104 /* 0x00 - 0x07 */
105 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
106 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
107 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
108 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
109 /* 0x08 - 0x0F */
110 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
111 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
112 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
113 ImplicitOps | Stack | No64, 0,
114 /* 0x10 - 0x17 */
115 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
116 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
117 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
118 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
119 /* 0x18 - 0x1F */
120 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
121 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
122 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
123 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
124 /* 0x20 - 0x27 */
125 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
126 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
127 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
128 /* 0x28 - 0x2F */
129 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
130 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
131 0, 0, 0, 0,
132 /* 0x30 - 0x37 */
133 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
134 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
135 0, 0, 0, 0,
136 /* 0x38 - 0x3F */
137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
138 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
139 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
140 0, 0,
141 /* 0x40 - 0x47 */
142 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
143 /* 0x48 - 0x4F */
144 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
145 /* 0x50 - 0x57 */
146 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
147 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
148 /* 0x58 - 0x5F */
149 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
150 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
151 /* 0x60 - 0x67 */
152 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
153 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
154 0, 0, 0, 0,
155 /* 0x68 - 0x6F */
156 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
157 DstDI | ByteOp | Mov | String, DstDI | Mov | String, /* insb, insw/insd */
158 SrcSI | ByteOp | ImplicitOps | String, SrcSI | ImplicitOps | String, /* outsb, outsw/outsd */
159 /* 0x70 - 0x77 */
160 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
161 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
162 /* 0x78 - 0x7F */
163 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
164 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
165 /* 0x80 - 0x87 */
166 Group | Group1_80, Group | Group1_81,
167 Group | Group1_82, Group | Group1_83,
168 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
169 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
170 /* 0x88 - 0x8F */
171 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
172 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
173 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
174 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
175 /* 0x90 - 0x97 */
176 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
177 /* 0x98 - 0x9F */
178 0, 0, SrcImm | Src2Imm16 | No64, 0,
179 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
180 /* 0xA0 - 0xA7 */
181 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
182 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
183 ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String,
184 ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String,
185 /* 0xA8 - 0xAF */
186 0, 0, ByteOp | DstDI | Mov | String, DstDI | Mov | String,
187 ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String,
188 ByteOp | DstDI | String, DstDI | String,
189 /* 0xB0 - 0xB7 */
190 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
191 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
192 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
193 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
194 /* 0xB8 - 0xBF */
195 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
196 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
197 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
198 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
199 /* 0xC0 - 0xC7 */
200 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
201 0, ImplicitOps | Stack, 0, 0,
202 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
203 /* 0xC8 - 0xCF */
204 0, 0, 0, ImplicitOps | Stack,
205 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
206 /* 0xD0 - 0xD7 */
207 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
208 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
209 0, 0, 0, 0,
210 /* 0xD8 - 0xDF */
211 0, 0, 0, 0, 0, 0, 0, 0,
212 /* 0xE0 - 0xE7 */
213 0, 0, 0, 0,
214 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
215 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
216 /* 0xE8 - 0xEF */
217 SrcImm | Stack, SrcImm | ImplicitOps,
218 SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps,
219 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
220 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
221 /* 0xF0 - 0xF7 */
222 0, 0, 0, 0,
223 ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3,
224 /* 0xF8 - 0xFF */
225 ImplicitOps, 0, ImplicitOps, ImplicitOps,
226 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
227 };
228
229 static u32 twobyte_table[256] = {
230 /* 0x00 - 0x0F */
231 0, Group | GroupDual | Group7, 0, 0,
232 0, ImplicitOps, ImplicitOps | Priv, 0,
233 ImplicitOps | Priv, ImplicitOps | Priv, 0, 0,
234 0, ImplicitOps | ModRM, 0, 0,
235 /* 0x10 - 0x1F */
236 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
237 /* 0x20 - 0x2F */
238 ModRM | ImplicitOps | Priv, ModRM | Priv,
239 ModRM | ImplicitOps | Priv, ModRM | Priv,
240 0, 0, 0, 0,
241 0, 0, 0, 0, 0, 0, 0, 0,
242 /* 0x30 - 0x3F */
243 ImplicitOps | Priv, 0, ImplicitOps | Priv, 0,
244 ImplicitOps, ImplicitOps | Priv, 0, 0,
245 0, 0, 0, 0, 0, 0, 0, 0,
246 /* 0x40 - 0x47 */
247 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
248 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
249 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
250 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
251 /* 0x48 - 0x4F */
252 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
253 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
254 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
255 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
256 /* 0x50 - 0x5F */
257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
258 /* 0x60 - 0x6F */
259 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
260 /* 0x70 - 0x7F */
261 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
262 /* 0x80 - 0x8F */
263 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
264 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
265 /* 0x90 - 0x9F */
266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
267 /* 0xA0 - 0xA7 */
268 ImplicitOps | Stack, ImplicitOps | Stack,
269 0, DstMem | SrcReg | ModRM | BitOp,
270 DstMem | SrcReg | Src2ImmByte | ModRM,
271 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
272 /* 0xA8 - 0xAF */
273 ImplicitOps | Stack, ImplicitOps | Stack,
274 0, DstMem | SrcReg | ModRM | BitOp | Lock,
275 DstMem | SrcReg | Src2ImmByte | ModRM,
276 DstMem | SrcReg | Src2CL | ModRM,
277 ModRM, 0,
278 /* 0xB0 - 0xB7 */
279 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
280 0, DstMem | SrcReg | ModRM | BitOp | Lock,
281 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
282 DstReg | SrcMem16 | ModRM | Mov,
283 /* 0xB8 - 0xBF */
284 0, 0,
285 Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock,
286 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
287 DstReg | SrcMem16 | ModRM | Mov,
288 /* 0xC0 - 0xCF */
289 0, 0, 0, DstMem | SrcReg | ModRM | Mov,
290 0, 0, 0, Group | GroupDual | Group9,
291 0, 0, 0, 0, 0, 0, 0, 0,
292 /* 0xD0 - 0xDF */
293 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
294 /* 0xE0 - 0xEF */
295 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
296 /* 0xF0 - 0xFF */
297 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
298 };
299
300 static u32 group_table[] = {
301 [Group1_80*8] =
302 ByteOp | DstMem | SrcImm | ModRM | Lock,
303 ByteOp | DstMem | SrcImm | ModRM | Lock,
304 ByteOp | DstMem | SrcImm | ModRM | Lock,
305 ByteOp | DstMem | SrcImm | ModRM | Lock,
306 ByteOp | DstMem | SrcImm | ModRM | Lock,
307 ByteOp | DstMem | SrcImm | ModRM | Lock,
308 ByteOp | DstMem | SrcImm | ModRM | Lock,
309 ByteOp | DstMem | SrcImm | ModRM,
310 [Group1_81*8] =
311 DstMem | SrcImm | ModRM | Lock,
312 DstMem | SrcImm | ModRM | Lock,
313 DstMem | SrcImm | ModRM | Lock,
314 DstMem | SrcImm | ModRM | Lock,
315 DstMem | SrcImm | ModRM | Lock,
316 DstMem | SrcImm | ModRM | Lock,
317 DstMem | SrcImm | ModRM | Lock,
318 DstMem | SrcImm | ModRM,
319 [Group1_82*8] =
320 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
321 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
322 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
323 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
324 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
325 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
326 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
327 ByteOp | DstMem | SrcImm | ModRM | No64,
328 [Group1_83*8] =
329 DstMem | SrcImmByte | ModRM | Lock,
330 DstMem | SrcImmByte | ModRM | Lock,
331 DstMem | SrcImmByte | ModRM | Lock,
332 DstMem | SrcImmByte | ModRM | Lock,
333 DstMem | SrcImmByte | ModRM | Lock,
334 DstMem | SrcImmByte | ModRM | Lock,
335 DstMem | SrcImmByte | ModRM | Lock,
336 DstMem | SrcImmByte | ModRM,
337 [Group1A*8] =
338 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
339 [Group3_Byte*8] =
340 ByteOp | SrcImm | DstMem | ModRM, 0,
341 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
342 0, 0, 0, 0,
343 [Group3*8] =
344 DstMem | SrcImm | ModRM, 0,
345 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
346 0, 0, 0, 0,
347 [Group4*8] =
348 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
349 0, 0, 0, 0, 0, 0,
350 [Group5*8] =
351 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
352 SrcMem | ModRM | Stack, 0,
353 SrcMem | ModRM | Stack, SrcMem | ModRM | Src2Mem16 | ImplicitOps,
354 SrcMem | ModRM | Stack, 0,
355 [Group7*8] =
356 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv,
357 SrcNone | ModRM | DstMem | Mov, 0,
358 SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv,
359 [Group8*8] =
360 0, 0, 0, 0,
361 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock,
362 DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock,
363 [Group9*8] =
364 0, DstMem64 | ModRM | Lock, 0, 0, 0, 0, 0, 0,
365 };
366
367 static u32 group2_table[] = {
368 [Group7*8] =
369 SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv,
370 SrcNone | ModRM | DstMem | Mov, 0,
371 SrcMem16 | ModRM | Mov | Priv, 0,
372 [Group9*8] =
373 0, 0, 0, 0, 0, 0, 0, 0,
374 };
375
376 /* EFLAGS bit definitions. */
377 #define EFLG_ID (1<<21)
378 #define EFLG_VIP (1<<20)
379 #define EFLG_VIF (1<<19)
380 #define EFLG_AC (1<<18)
381 #define EFLG_VM (1<<17)
382 #define EFLG_RF (1<<16)
383 #define EFLG_IOPL (3<<12)
384 #define EFLG_NT (1<<14)
385 #define EFLG_OF (1<<11)
386 #define EFLG_DF (1<<10)
387 #define EFLG_IF (1<<9)
388 #define EFLG_TF (1<<8)
389 #define EFLG_SF (1<<7)
390 #define EFLG_ZF (1<<6)
391 #define EFLG_AF (1<<4)
392 #define EFLG_PF (1<<2)
393 #define EFLG_CF (1<<0)
394
395 /*
396 * Instruction emulation:
397 * Most instructions are emulated directly via a fragment of inline assembly
398 * code. This allows us to save/restore EFLAGS and thus very easily pick up
399 * any modified flags.
400 */
401
402 #if defined(CONFIG_X86_64)
403 #define _LO32 "k" /* force 32-bit operand */
404 #define _STK "%%rsp" /* stack pointer */
405 #elif defined(__i386__)
406 #define _LO32 "" /* force 32-bit operand */
407 #define _STK "%%esp" /* stack pointer */
408 #endif
409
410 /*
411 * These EFLAGS bits are restored from saved value during emulation, and
412 * any changes are written back to the saved value after emulation.
413 */
414 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
415
416 /* Before executing instruction: restore necessary bits in EFLAGS. */
417 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
418 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
419 "movl %"_sav",%"_LO32 _tmp"; " \
420 "push %"_tmp"; " \
421 "push %"_tmp"; " \
422 "movl %"_msk",%"_LO32 _tmp"; " \
423 "andl %"_LO32 _tmp",("_STK"); " \
424 "pushf; " \
425 "notl %"_LO32 _tmp"; " \
426 "andl %"_LO32 _tmp",("_STK"); " \
427 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
428 "pop %"_tmp"; " \
429 "orl %"_LO32 _tmp",("_STK"); " \
430 "popf; " \
431 "pop %"_sav"; "
432
433 /* After executing instruction: write-back necessary bits in EFLAGS. */
434 #define _POST_EFLAGS(_sav, _msk, _tmp) \
435 /* _sav |= EFLAGS & _msk; */ \
436 "pushf; " \
437 "pop %"_tmp"; " \
438 "andl %"_msk",%"_LO32 _tmp"; " \
439 "orl %"_LO32 _tmp",%"_sav"; "
440
441 #ifdef CONFIG_X86_64
442 #define ON64(x) x
443 #else
444 #define ON64(x)
445 #endif
446
447 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
448 do { \
449 __asm__ __volatile__ ( \
450 _PRE_EFLAGS("0", "4", "2") \
451 _op _suffix " %"_x"3,%1; " \
452 _POST_EFLAGS("0", "4", "2") \
453 : "=m" (_eflags), "=m" ((_dst).val), \
454 "=&r" (_tmp) \
455 : _y ((_src).val), "i" (EFLAGS_MASK)); \
456 } while (0)
457
458
459 /* Raw emulation: instruction has two explicit operands. */
460 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
461 do { \
462 unsigned long _tmp; \
463 \
464 switch ((_dst).bytes) { \
465 case 2: \
466 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
467 break; \
468 case 4: \
469 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
470 break; \
471 case 8: \
472 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
473 break; \
474 } \
475 } while (0)
476
477 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
478 do { \
479 unsigned long _tmp; \
480 switch ((_dst).bytes) { \
481 case 1: \
482 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
483 break; \
484 default: \
485 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
486 _wx, _wy, _lx, _ly, _qx, _qy); \
487 break; \
488 } \
489 } while (0)
490
491 /* Source operand is byte-sized and may be restricted to just %cl. */
492 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
493 __emulate_2op(_op, _src, _dst, _eflags, \
494 "b", "c", "b", "c", "b", "c", "b", "c")
495
496 /* Source operand is byte, word, long or quad sized. */
497 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
498 __emulate_2op(_op, _src, _dst, _eflags, \
499 "b", "q", "w", "r", _LO32, "r", "", "r")
500
501 /* Source operand is word, long or quad sized. */
502 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
503 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
504 "w", "r", _LO32, "r", "", "r")
505
506 /* Instruction has three operands and one operand is stored in ECX register */
507 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
508 do { \
509 unsigned long _tmp; \
510 _type _clv = (_cl).val; \
511 _type _srcv = (_src).val; \
512 _type _dstv = (_dst).val; \
513 \
514 __asm__ __volatile__ ( \
515 _PRE_EFLAGS("0", "5", "2") \
516 _op _suffix " %4,%1 \n" \
517 _POST_EFLAGS("0", "5", "2") \
518 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
519 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
520 ); \
521 \
522 (_cl).val = (unsigned long) _clv; \
523 (_src).val = (unsigned long) _srcv; \
524 (_dst).val = (unsigned long) _dstv; \
525 } while (0)
526
527 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
528 do { \
529 switch ((_dst).bytes) { \
530 case 2: \
531 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
532 "w", unsigned short); \
533 break; \
534 case 4: \
535 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
536 "l", unsigned int); \
537 break; \
538 case 8: \
539 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
540 "q", unsigned long)); \
541 break; \
542 } \
543 } while (0)
544
545 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
546 do { \
547 unsigned long _tmp; \
548 \
549 __asm__ __volatile__ ( \
550 _PRE_EFLAGS("0", "3", "2") \
551 _op _suffix " %1; " \
552 _POST_EFLAGS("0", "3", "2") \
553 : "=m" (_eflags), "+m" ((_dst).val), \
554 "=&r" (_tmp) \
555 : "i" (EFLAGS_MASK)); \
556 } while (0)
557
558 /* Instruction has only one explicit operand (no source operand). */
559 #define emulate_1op(_op, _dst, _eflags) \
560 do { \
561 switch ((_dst).bytes) { \
562 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
563 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
564 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
565 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
566 } \
567 } while (0)
568
569 /* Fetch next part of the instruction being emulated. */
570 #define insn_fetch(_type, _size, _eip) \
571 ({ unsigned long _x; \
572 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
573 if (rc != X86EMUL_CONTINUE) \
574 goto done; \
575 (_eip) += (_size); \
576 (_type)_x; \
577 })
578
579 static inline unsigned long ad_mask(struct decode_cache *c)
580 {
581 return (1UL << (c->ad_bytes << 3)) - 1;
582 }
583
584 /* Access/update address held in a register, based on addressing mode. */
585 static inline unsigned long
586 address_mask(struct decode_cache *c, unsigned long reg)
587 {
588 if (c->ad_bytes == sizeof(unsigned long))
589 return reg;
590 else
591 return reg & ad_mask(c);
592 }
593
594 static inline unsigned long
595 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
596 {
597 return base + address_mask(c, reg);
598 }
599
600 static inline void
601 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
602 {
603 if (c->ad_bytes == sizeof(unsigned long))
604 *reg += inc;
605 else
606 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
607 }
608
609 static inline void jmp_rel(struct decode_cache *c, int rel)
610 {
611 register_address_increment(c, &c->eip, rel);
612 }
613
614 static void set_seg_override(struct decode_cache *c, int seg)
615 {
616 c->has_seg_override = true;
617 c->seg_override = seg;
618 }
619
620 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
621 {
622 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
623 return 0;
624
625 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
626 }
627
628 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
629 struct decode_cache *c)
630 {
631 if (!c->has_seg_override)
632 return 0;
633
634 return seg_base(ctxt, c->seg_override);
635 }
636
637 static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
638 {
639 return seg_base(ctxt, VCPU_SREG_ES);
640 }
641
642 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
643 {
644 return seg_base(ctxt, VCPU_SREG_SS);
645 }
646
647 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
648 struct x86_emulate_ops *ops,
649 unsigned long linear, u8 *dest)
650 {
651 struct fetch_cache *fc = &ctxt->decode.fetch;
652 int rc;
653 int size;
654
655 if (linear < fc->start || linear >= fc->end) {
656 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
657 rc = ops->fetch(linear, fc->data, size, ctxt->vcpu, NULL);
658 if (rc != X86EMUL_CONTINUE)
659 return rc;
660 fc->start = linear;
661 fc->end = linear + size;
662 }
663 *dest = fc->data[linear - fc->start];
664 return X86EMUL_CONTINUE;
665 }
666
667 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
668 struct x86_emulate_ops *ops,
669 unsigned long eip, void *dest, unsigned size)
670 {
671 int rc;
672
673 /* x86 instructions are limited to 15 bytes. */
674 if (eip + size - ctxt->eip > 15)
675 return X86EMUL_UNHANDLEABLE;
676 eip += ctxt->cs_base;
677 while (size--) {
678 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
679 if (rc != X86EMUL_CONTINUE)
680 return rc;
681 }
682 return X86EMUL_CONTINUE;
683 }
684
685 /*
686 * Given the 'reg' portion of a ModRM byte, and a register block, return a
687 * pointer into the block that addresses the relevant register.
688 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
689 */
690 static void *decode_register(u8 modrm_reg, unsigned long *regs,
691 int highbyte_regs)
692 {
693 void *p;
694
695 p = &regs[modrm_reg];
696 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
697 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
698 return p;
699 }
700
701 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
702 struct x86_emulate_ops *ops,
703 void *ptr,
704 u16 *size, unsigned long *address, int op_bytes)
705 {
706 int rc;
707
708 if (op_bytes == 2)
709 op_bytes = 3;
710 *address = 0;
711 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
712 ctxt->vcpu, NULL);
713 if (rc != X86EMUL_CONTINUE)
714 return rc;
715 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
716 ctxt->vcpu, NULL);
717 return rc;
718 }
719
720 static int test_cc(unsigned int condition, unsigned int flags)
721 {
722 int rc = 0;
723
724 switch ((condition & 15) >> 1) {
725 case 0: /* o */
726 rc |= (flags & EFLG_OF);
727 break;
728 case 1: /* b/c/nae */
729 rc |= (flags & EFLG_CF);
730 break;
731 case 2: /* z/e */
732 rc |= (flags & EFLG_ZF);
733 break;
734 case 3: /* be/na */
735 rc |= (flags & (EFLG_CF|EFLG_ZF));
736 break;
737 case 4: /* s */
738 rc |= (flags & EFLG_SF);
739 break;
740 case 5: /* p/pe */
741 rc |= (flags & EFLG_PF);
742 break;
743 case 7: /* le/ng */
744 rc |= (flags & EFLG_ZF);
745 /* fall through */
746 case 6: /* l/nge */
747 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
748 break;
749 }
750
751 /* Odd condition identifiers (lsb == 1) have inverted sense. */
752 return (!!rc ^ (condition & 1));
753 }
754
755 static void decode_register_operand(struct operand *op,
756 struct decode_cache *c,
757 int inhibit_bytereg)
758 {
759 unsigned reg = c->modrm_reg;
760 int highbyte_regs = c->rex_prefix == 0;
761
762 if (!(c->d & ModRM))
763 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
764 op->type = OP_REG;
765 if ((c->d & ByteOp) && !inhibit_bytereg) {
766 op->ptr = decode_register(reg, c->regs, highbyte_regs);
767 op->val = *(u8 *)op->ptr;
768 op->bytes = 1;
769 } else {
770 op->ptr = decode_register(reg, c->regs, 0);
771 op->bytes = c->op_bytes;
772 switch (op->bytes) {
773 case 2:
774 op->val = *(u16 *)op->ptr;
775 break;
776 case 4:
777 op->val = *(u32 *)op->ptr;
778 break;
779 case 8:
780 op->val = *(u64 *) op->ptr;
781 break;
782 }
783 }
784 op->orig_val = op->val;
785 }
786
787 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
788 struct x86_emulate_ops *ops)
789 {
790 struct decode_cache *c = &ctxt->decode;
791 u8 sib;
792 int index_reg = 0, base_reg = 0, scale;
793 int rc = X86EMUL_CONTINUE;
794
795 if (c->rex_prefix) {
796 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
797 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
798 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
799 }
800
801 c->modrm = insn_fetch(u8, 1, c->eip);
802 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
803 c->modrm_reg |= (c->modrm & 0x38) >> 3;
804 c->modrm_rm |= (c->modrm & 0x07);
805 c->modrm_ea = 0;
806 c->use_modrm_ea = 1;
807
808 if (c->modrm_mod == 3) {
809 c->modrm_ptr = decode_register(c->modrm_rm,
810 c->regs, c->d & ByteOp);
811 c->modrm_val = *(unsigned long *)c->modrm_ptr;
812 return rc;
813 }
814
815 if (c->ad_bytes == 2) {
816 unsigned bx = c->regs[VCPU_REGS_RBX];
817 unsigned bp = c->regs[VCPU_REGS_RBP];
818 unsigned si = c->regs[VCPU_REGS_RSI];
819 unsigned di = c->regs[VCPU_REGS_RDI];
820
821 /* 16-bit ModR/M decode. */
822 switch (c->modrm_mod) {
823 case 0:
824 if (c->modrm_rm == 6)
825 c->modrm_ea += insn_fetch(u16, 2, c->eip);
826 break;
827 case 1:
828 c->modrm_ea += insn_fetch(s8, 1, c->eip);
829 break;
830 case 2:
831 c->modrm_ea += insn_fetch(u16, 2, c->eip);
832 break;
833 }
834 switch (c->modrm_rm) {
835 case 0:
836 c->modrm_ea += bx + si;
837 break;
838 case 1:
839 c->modrm_ea += bx + di;
840 break;
841 case 2:
842 c->modrm_ea += bp + si;
843 break;
844 case 3:
845 c->modrm_ea += bp + di;
846 break;
847 case 4:
848 c->modrm_ea += si;
849 break;
850 case 5:
851 c->modrm_ea += di;
852 break;
853 case 6:
854 if (c->modrm_mod != 0)
855 c->modrm_ea += bp;
856 break;
857 case 7:
858 c->modrm_ea += bx;
859 break;
860 }
861 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
862 (c->modrm_rm == 6 && c->modrm_mod != 0))
863 if (!c->has_seg_override)
864 set_seg_override(c, VCPU_SREG_SS);
865 c->modrm_ea = (u16)c->modrm_ea;
866 } else {
867 /* 32/64-bit ModR/M decode. */
868 if ((c->modrm_rm & 7) == 4) {
869 sib = insn_fetch(u8, 1, c->eip);
870 index_reg |= (sib >> 3) & 7;
871 base_reg |= sib & 7;
872 scale = sib >> 6;
873
874 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
875 c->modrm_ea += insn_fetch(s32, 4, c->eip);
876 else
877 c->modrm_ea += c->regs[base_reg];
878 if (index_reg != 4)
879 c->modrm_ea += c->regs[index_reg] << scale;
880 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
881 if (ctxt->mode == X86EMUL_MODE_PROT64)
882 c->rip_relative = 1;
883 } else
884 c->modrm_ea += c->regs[c->modrm_rm];
885 switch (c->modrm_mod) {
886 case 0:
887 if (c->modrm_rm == 5)
888 c->modrm_ea += insn_fetch(s32, 4, c->eip);
889 break;
890 case 1:
891 c->modrm_ea += insn_fetch(s8, 1, c->eip);
892 break;
893 case 2:
894 c->modrm_ea += insn_fetch(s32, 4, c->eip);
895 break;
896 }
897 }
898 done:
899 return rc;
900 }
901
902 static int decode_abs(struct x86_emulate_ctxt *ctxt,
903 struct x86_emulate_ops *ops)
904 {
905 struct decode_cache *c = &ctxt->decode;
906 int rc = X86EMUL_CONTINUE;
907
908 switch (c->ad_bytes) {
909 case 2:
910 c->modrm_ea = insn_fetch(u16, 2, c->eip);
911 break;
912 case 4:
913 c->modrm_ea = insn_fetch(u32, 4, c->eip);
914 break;
915 case 8:
916 c->modrm_ea = insn_fetch(u64, 8, c->eip);
917 break;
918 }
919 done:
920 return rc;
921 }
922
923 int
924 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
925 {
926 struct decode_cache *c = &ctxt->decode;
927 int rc = X86EMUL_CONTINUE;
928 int mode = ctxt->mode;
929 int def_op_bytes, def_ad_bytes, group;
930
931
932 /* we cannot decode insn before we complete previous rep insn */
933 WARN_ON(ctxt->restart);
934
935 /* Shadow copy of register state. Committed on successful emulation. */
936 memset(c, 0, sizeof(struct decode_cache));
937 c->eip = ctxt->eip;
938 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
939 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
940
941 switch (mode) {
942 case X86EMUL_MODE_REAL:
943 case X86EMUL_MODE_VM86:
944 case X86EMUL_MODE_PROT16:
945 def_op_bytes = def_ad_bytes = 2;
946 break;
947 case X86EMUL_MODE_PROT32:
948 def_op_bytes = def_ad_bytes = 4;
949 break;
950 #ifdef CONFIG_X86_64
951 case X86EMUL_MODE_PROT64:
952 def_op_bytes = 4;
953 def_ad_bytes = 8;
954 break;
955 #endif
956 default:
957 return -1;
958 }
959
960 c->op_bytes = def_op_bytes;
961 c->ad_bytes = def_ad_bytes;
962
963 /* Legacy prefixes. */
964 for (;;) {
965 switch (c->b = insn_fetch(u8, 1, c->eip)) {
966 case 0x66: /* operand-size override */
967 /* switch between 2/4 bytes */
968 c->op_bytes = def_op_bytes ^ 6;
969 break;
970 case 0x67: /* address-size override */
971 if (mode == X86EMUL_MODE_PROT64)
972 /* switch between 4/8 bytes */
973 c->ad_bytes = def_ad_bytes ^ 12;
974 else
975 /* switch between 2/4 bytes */
976 c->ad_bytes = def_ad_bytes ^ 6;
977 break;
978 case 0x26: /* ES override */
979 case 0x2e: /* CS override */
980 case 0x36: /* SS override */
981 case 0x3e: /* DS override */
982 set_seg_override(c, (c->b >> 3) & 3);
983 break;
984 case 0x64: /* FS override */
985 case 0x65: /* GS override */
986 set_seg_override(c, c->b & 7);
987 break;
988 case 0x40 ... 0x4f: /* REX */
989 if (mode != X86EMUL_MODE_PROT64)
990 goto done_prefixes;
991 c->rex_prefix = c->b;
992 continue;
993 case 0xf0: /* LOCK */
994 c->lock_prefix = 1;
995 break;
996 case 0xf2: /* REPNE/REPNZ */
997 c->rep_prefix = REPNE_PREFIX;
998 break;
999 case 0xf3: /* REP/REPE/REPZ */
1000 c->rep_prefix = REPE_PREFIX;
1001 break;
1002 default:
1003 goto done_prefixes;
1004 }
1005
1006 /* Any legacy prefix after a REX prefix nullifies its effect. */
1007
1008 c->rex_prefix = 0;
1009 }
1010
1011 done_prefixes:
1012
1013 /* REX prefix. */
1014 if (c->rex_prefix)
1015 if (c->rex_prefix & 8)
1016 c->op_bytes = 8; /* REX.W */
1017
1018 /* Opcode byte(s). */
1019 c->d = opcode_table[c->b];
1020 if (c->d == 0) {
1021 /* Two-byte opcode? */
1022 if (c->b == 0x0f) {
1023 c->twobyte = 1;
1024 c->b = insn_fetch(u8, 1, c->eip);
1025 c->d = twobyte_table[c->b];
1026 }
1027 }
1028
1029 if (c->d & Group) {
1030 group = c->d & GroupMask;
1031 c->modrm = insn_fetch(u8, 1, c->eip);
1032 --c->eip;
1033
1034 group = (group << 3) + ((c->modrm >> 3) & 7);
1035 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
1036 c->d = group2_table[group];
1037 else
1038 c->d = group_table[group];
1039 }
1040
1041 /* Unrecognised? */
1042 if (c->d == 0) {
1043 DPRINTF("Cannot emulate %02x\n", c->b);
1044 return -1;
1045 }
1046
1047 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1048 c->op_bytes = 8;
1049
1050 /* ModRM and SIB bytes. */
1051 if (c->d & ModRM)
1052 rc = decode_modrm(ctxt, ops);
1053 else if (c->d & MemAbs)
1054 rc = decode_abs(ctxt, ops);
1055 if (rc != X86EMUL_CONTINUE)
1056 goto done;
1057
1058 if (!c->has_seg_override)
1059 set_seg_override(c, VCPU_SREG_DS);
1060
1061 if (!(!c->twobyte && c->b == 0x8d))
1062 c->modrm_ea += seg_override_base(ctxt, c);
1063
1064 if (c->ad_bytes != 8)
1065 c->modrm_ea = (u32)c->modrm_ea;
1066
1067 if (c->rip_relative)
1068 c->modrm_ea += c->eip;
1069
1070 /*
1071 * Decode and fetch the source operand: register, memory
1072 * or immediate.
1073 */
1074 switch (c->d & SrcMask) {
1075 case SrcNone:
1076 break;
1077 case SrcReg:
1078 decode_register_operand(&c->src, c, 0);
1079 break;
1080 case SrcMem16:
1081 c->src.bytes = 2;
1082 goto srcmem_common;
1083 case SrcMem32:
1084 c->src.bytes = 4;
1085 goto srcmem_common;
1086 case SrcMem:
1087 c->src.bytes = (c->d & ByteOp) ? 1 :
1088 c->op_bytes;
1089 /* Don't fetch the address for invlpg: it could be unmapped. */
1090 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
1091 break;
1092 srcmem_common:
1093 /*
1094 * For instructions with a ModR/M byte, switch to register
1095 * access if Mod = 3.
1096 */
1097 if ((c->d & ModRM) && c->modrm_mod == 3) {
1098 c->src.type = OP_REG;
1099 c->src.val = c->modrm_val;
1100 c->src.ptr = c->modrm_ptr;
1101 break;
1102 }
1103 c->src.type = OP_MEM;
1104 c->src.ptr = (unsigned long *)c->modrm_ea;
1105 c->src.val = 0;
1106 break;
1107 case SrcImm:
1108 case SrcImmU:
1109 c->src.type = OP_IMM;
1110 c->src.ptr = (unsigned long *)c->eip;
1111 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1112 if (c->src.bytes == 8)
1113 c->src.bytes = 4;
1114 /* NB. Immediates are sign-extended as necessary. */
1115 switch (c->src.bytes) {
1116 case 1:
1117 c->src.val = insn_fetch(s8, 1, c->eip);
1118 break;
1119 case 2:
1120 c->src.val = insn_fetch(s16, 2, c->eip);
1121 break;
1122 case 4:
1123 c->src.val = insn_fetch(s32, 4, c->eip);
1124 break;
1125 }
1126 if ((c->d & SrcMask) == SrcImmU) {
1127 switch (c->src.bytes) {
1128 case 1:
1129 c->src.val &= 0xff;
1130 break;
1131 case 2:
1132 c->src.val &= 0xffff;
1133 break;
1134 case 4:
1135 c->src.val &= 0xffffffff;
1136 break;
1137 }
1138 }
1139 break;
1140 case SrcImmByte:
1141 case SrcImmUByte:
1142 c->src.type = OP_IMM;
1143 c->src.ptr = (unsigned long *)c->eip;
1144 c->src.bytes = 1;
1145 if ((c->d & SrcMask) == SrcImmByte)
1146 c->src.val = insn_fetch(s8, 1, c->eip);
1147 else
1148 c->src.val = insn_fetch(u8, 1, c->eip);
1149 break;
1150 case SrcOne:
1151 c->src.bytes = 1;
1152 c->src.val = 1;
1153 break;
1154 case SrcSI:
1155 c->src.type = OP_MEM;
1156 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1157 c->src.ptr = (unsigned long *)
1158 register_address(c, seg_override_base(ctxt, c),
1159 c->regs[VCPU_REGS_RSI]);
1160 c->src.val = 0;
1161 break;
1162 }
1163
1164 /*
1165 * Decode and fetch the second source operand: register, memory
1166 * or immediate.
1167 */
1168 switch (c->d & Src2Mask) {
1169 case Src2None:
1170 break;
1171 case Src2CL:
1172 c->src2.bytes = 1;
1173 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1174 break;
1175 case Src2ImmByte:
1176 c->src2.type = OP_IMM;
1177 c->src2.ptr = (unsigned long *)c->eip;
1178 c->src2.bytes = 1;
1179 c->src2.val = insn_fetch(u8, 1, c->eip);
1180 break;
1181 case Src2Imm16:
1182 c->src2.type = OP_IMM;
1183 c->src2.ptr = (unsigned long *)c->eip;
1184 c->src2.bytes = 2;
1185 c->src2.val = insn_fetch(u16, 2, c->eip);
1186 break;
1187 case Src2One:
1188 c->src2.bytes = 1;
1189 c->src2.val = 1;
1190 break;
1191 case Src2Mem16:
1192 c->src2.type = OP_MEM;
1193 c->src2.bytes = 2;
1194 c->src2.ptr = (unsigned long *)(c->modrm_ea + c->src.bytes);
1195 c->src2.val = 0;
1196 break;
1197 }
1198
1199 /* Decode and fetch the destination operand: register or memory. */
1200 switch (c->d & DstMask) {
1201 case ImplicitOps:
1202 /* Special instructions do their own operand decoding. */
1203 return 0;
1204 case DstReg:
1205 decode_register_operand(&c->dst, c,
1206 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
1207 break;
1208 case DstMem:
1209 case DstMem64:
1210 if ((c->d & ModRM) && c->modrm_mod == 3) {
1211 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1212 c->dst.type = OP_REG;
1213 c->dst.val = c->dst.orig_val = c->modrm_val;
1214 c->dst.ptr = c->modrm_ptr;
1215 break;
1216 }
1217 c->dst.type = OP_MEM;
1218 c->dst.ptr = (unsigned long *)c->modrm_ea;
1219 if ((c->d & DstMask) == DstMem64)
1220 c->dst.bytes = 8;
1221 else
1222 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1223 c->dst.val = 0;
1224 if (c->d & BitOp) {
1225 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1226
1227 c->dst.ptr = (void *)c->dst.ptr +
1228 (c->src.val & mask) / 8;
1229 }
1230 break;
1231 case DstAcc:
1232 c->dst.type = OP_REG;
1233 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1234 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1235 switch (c->dst.bytes) {
1236 case 1:
1237 c->dst.val = *(u8 *)c->dst.ptr;
1238 break;
1239 case 2:
1240 c->dst.val = *(u16 *)c->dst.ptr;
1241 break;
1242 case 4:
1243 c->dst.val = *(u32 *)c->dst.ptr;
1244 break;
1245 case 8:
1246 c->dst.val = *(u64 *)c->dst.ptr;
1247 break;
1248 }
1249 c->dst.orig_val = c->dst.val;
1250 break;
1251 case DstDI:
1252 c->dst.type = OP_MEM;
1253 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1254 c->dst.ptr = (unsigned long *)
1255 register_address(c, es_base(ctxt),
1256 c->regs[VCPU_REGS_RDI]);
1257 c->dst.val = 0;
1258 break;
1259 }
1260
1261 done:
1262 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1263 }
1264
1265 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1266 struct x86_emulate_ops *ops,
1267 unsigned int size, unsigned short port,
1268 void *dest)
1269 {
1270 struct read_cache *rc = &ctxt->decode.io_read;
1271
1272 if (rc->pos == rc->end) { /* refill pio read ahead */
1273 struct decode_cache *c = &ctxt->decode;
1274 unsigned int in_page, n;
1275 unsigned int count = c->rep_prefix ?
1276 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1277 in_page = (ctxt->eflags & EFLG_DF) ?
1278 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1279 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1280 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1281 count);
1282 if (n == 0)
1283 n = 1;
1284 rc->pos = rc->end = 0;
1285 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1286 return 0;
1287 rc->end = n * size;
1288 }
1289
1290 memcpy(dest, rc->data + rc->pos, size);
1291 rc->pos += size;
1292 return 1;
1293 }
1294
1295 static u32 desc_limit_scaled(struct desc_struct *desc)
1296 {
1297 u32 limit = get_desc_limit(desc);
1298
1299 return desc->g ? (limit << 12) | 0xfff : limit;
1300 }
1301
1302 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1303 struct x86_emulate_ops *ops,
1304 u16 selector, struct desc_ptr *dt)
1305 {
1306 if (selector & 1 << 2) {
1307 struct desc_struct desc;
1308 memset (dt, 0, sizeof *dt);
1309 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1310 return;
1311
1312 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1313 dt->address = get_desc_base(&desc);
1314 } else
1315 ops->get_gdt(dt, ctxt->vcpu);
1316 }
1317
1318 /* allowed just for 8 bytes segments */
1319 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1320 struct x86_emulate_ops *ops,
1321 u16 selector, struct desc_struct *desc)
1322 {
1323 struct desc_ptr dt;
1324 u16 index = selector >> 3;
1325 int ret;
1326 u32 err;
1327 ulong addr;
1328
1329 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1330
1331 if (dt.size < index * 8 + 7) {
1332 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
1333 return X86EMUL_PROPAGATE_FAULT;
1334 }
1335 addr = dt.address + index * 8;
1336 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1337 if (ret == X86EMUL_PROPAGATE_FAULT)
1338 kvm_inject_page_fault(ctxt->vcpu, addr, err);
1339
1340 return ret;
1341 }
1342
1343 /* allowed just for 8 bytes segments */
1344 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1345 struct x86_emulate_ops *ops,
1346 u16 selector, struct desc_struct *desc)
1347 {
1348 struct desc_ptr dt;
1349 u16 index = selector >> 3;
1350 u32 err;
1351 ulong addr;
1352 int ret;
1353
1354 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1355
1356 if (dt.size < index * 8 + 7) {
1357 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
1358 return X86EMUL_PROPAGATE_FAULT;
1359 }
1360
1361 addr = dt.address + index * 8;
1362 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1363 if (ret == X86EMUL_PROPAGATE_FAULT)
1364 kvm_inject_page_fault(ctxt->vcpu, addr, err);
1365
1366 return ret;
1367 }
1368
1369 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1370 struct x86_emulate_ops *ops,
1371 u16 selector, int seg)
1372 {
1373 struct desc_struct seg_desc;
1374 u8 dpl, rpl, cpl;
1375 unsigned err_vec = GP_VECTOR;
1376 u32 err_code = 0;
1377 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1378 int ret;
1379
1380 memset(&seg_desc, 0, sizeof seg_desc);
1381
1382 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1383 || ctxt->mode == X86EMUL_MODE_REAL) {
1384 /* set real mode segment descriptor */
1385 set_desc_base(&seg_desc, selector << 4);
1386 set_desc_limit(&seg_desc, 0xffff);
1387 seg_desc.type = 3;
1388 seg_desc.p = 1;
1389 seg_desc.s = 1;
1390 goto load;
1391 }
1392
1393 /* NULL selector is not valid for TR, CS and SS */
1394 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1395 && null_selector)
1396 goto exception;
1397
1398 /* TR should be in GDT only */
1399 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1400 goto exception;
1401
1402 if (null_selector) /* for NULL selector skip all following checks */
1403 goto load;
1404
1405 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1406 if (ret != X86EMUL_CONTINUE)
1407 return ret;
1408
1409 err_code = selector & 0xfffc;
1410 err_vec = GP_VECTOR;
1411
1412 /* can't load system descriptor into segment selecor */
1413 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1414 goto exception;
1415
1416 if (!seg_desc.p) {
1417 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1418 goto exception;
1419 }
1420
1421 rpl = selector & 3;
1422 dpl = seg_desc.dpl;
1423 cpl = ops->cpl(ctxt->vcpu);
1424
1425 switch (seg) {
1426 case VCPU_SREG_SS:
1427 /*
1428 * segment is not a writable data segment or segment
1429 * selector's RPL != CPL or segment selector's RPL != CPL
1430 */
1431 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1432 goto exception;
1433 break;
1434 case VCPU_SREG_CS:
1435 if (!(seg_desc.type & 8))
1436 goto exception;
1437
1438 if (seg_desc.type & 4) {
1439 /* conforming */
1440 if (dpl > cpl)
1441 goto exception;
1442 } else {
1443 /* nonconforming */
1444 if (rpl > cpl || dpl != cpl)
1445 goto exception;
1446 }
1447 /* CS(RPL) <- CPL */
1448 selector = (selector & 0xfffc) | cpl;
1449 break;
1450 case VCPU_SREG_TR:
1451 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1452 goto exception;
1453 break;
1454 case VCPU_SREG_LDTR:
1455 if (seg_desc.s || seg_desc.type != 2)
1456 goto exception;
1457 break;
1458 default: /* DS, ES, FS, or GS */
1459 /*
1460 * segment is not a data or readable code segment or
1461 * ((segment is a data or nonconforming code segment)
1462 * and (both RPL and CPL > DPL))
1463 */
1464 if ((seg_desc.type & 0xa) == 0x8 ||
1465 (((seg_desc.type & 0xc) != 0xc) &&
1466 (rpl > dpl && cpl > dpl)))
1467 goto exception;
1468 break;
1469 }
1470
1471 if (seg_desc.s) {
1472 /* mark segment as accessed */
1473 seg_desc.type |= 1;
1474 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1475 if (ret != X86EMUL_CONTINUE)
1476 return ret;
1477 }
1478 load:
1479 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1480 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1481 return X86EMUL_CONTINUE;
1482 exception:
1483 kvm_queue_exception_e(ctxt->vcpu, err_vec, err_code);
1484 return X86EMUL_PROPAGATE_FAULT;
1485 }
1486
1487 static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1488 {
1489 struct decode_cache *c = &ctxt->decode;
1490
1491 c->dst.type = OP_MEM;
1492 c->dst.bytes = c->op_bytes;
1493 c->dst.val = c->src.val;
1494 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1495 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
1496 c->regs[VCPU_REGS_RSP]);
1497 }
1498
1499 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1500 struct x86_emulate_ops *ops,
1501 void *dest, int len)
1502 {
1503 struct decode_cache *c = &ctxt->decode;
1504 int rc;
1505
1506 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1507 c->regs[VCPU_REGS_RSP]),
1508 dest, len, ctxt->vcpu);
1509 if (rc != X86EMUL_CONTINUE)
1510 return rc;
1511
1512 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1513 return rc;
1514 }
1515
1516 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1517 struct x86_emulate_ops *ops,
1518 void *dest, int len)
1519 {
1520 int rc;
1521 unsigned long val, change_mask;
1522 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1523 int cpl = ops->cpl(ctxt->vcpu);
1524
1525 rc = emulate_pop(ctxt, ops, &val, len);
1526 if (rc != X86EMUL_CONTINUE)
1527 return rc;
1528
1529 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1530 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1531
1532 switch(ctxt->mode) {
1533 case X86EMUL_MODE_PROT64:
1534 case X86EMUL_MODE_PROT32:
1535 case X86EMUL_MODE_PROT16:
1536 if (cpl == 0)
1537 change_mask |= EFLG_IOPL;
1538 if (cpl <= iopl)
1539 change_mask |= EFLG_IF;
1540 break;
1541 case X86EMUL_MODE_VM86:
1542 if (iopl < 3) {
1543 kvm_inject_gp(ctxt->vcpu, 0);
1544 return X86EMUL_PROPAGATE_FAULT;
1545 }
1546 change_mask |= EFLG_IF;
1547 break;
1548 default: /* real mode */
1549 change_mask |= (EFLG_IOPL | EFLG_IF);
1550 break;
1551 }
1552
1553 *(unsigned long *)dest =
1554 (ctxt->eflags & ~change_mask) | (val & change_mask);
1555
1556 return rc;
1557 }
1558
1559 static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1560 {
1561 struct decode_cache *c = &ctxt->decode;
1562 struct kvm_segment segment;
1563
1564 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
1565
1566 c->src.val = segment.selector;
1567 emulate_push(ctxt);
1568 }
1569
1570 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1571 struct x86_emulate_ops *ops, int seg)
1572 {
1573 struct decode_cache *c = &ctxt->decode;
1574 unsigned long selector;
1575 int rc;
1576
1577 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1578 if (rc != X86EMUL_CONTINUE)
1579 return rc;
1580
1581 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1582 return rc;
1583 }
1584
1585 static void emulate_pusha(struct x86_emulate_ctxt *ctxt)
1586 {
1587 struct decode_cache *c = &ctxt->decode;
1588 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1589 int reg = VCPU_REGS_RAX;
1590
1591 while (reg <= VCPU_REGS_RDI) {
1592 (reg == VCPU_REGS_RSP) ?
1593 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1594
1595 emulate_push(ctxt);
1596 ++reg;
1597 }
1598 }
1599
1600 static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1601 struct x86_emulate_ops *ops)
1602 {
1603 struct decode_cache *c = &ctxt->decode;
1604 int rc = X86EMUL_CONTINUE;
1605 int reg = VCPU_REGS_RDI;
1606
1607 while (reg >= VCPU_REGS_RAX) {
1608 if (reg == VCPU_REGS_RSP) {
1609 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1610 c->op_bytes);
1611 --reg;
1612 }
1613
1614 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1615 if (rc != X86EMUL_CONTINUE)
1616 break;
1617 --reg;
1618 }
1619 return rc;
1620 }
1621
1622 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1623 struct x86_emulate_ops *ops)
1624 {
1625 struct decode_cache *c = &ctxt->decode;
1626
1627 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1628 }
1629
1630 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1631 {
1632 struct decode_cache *c = &ctxt->decode;
1633 switch (c->modrm_reg) {
1634 case 0: /* rol */
1635 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1636 break;
1637 case 1: /* ror */
1638 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1639 break;
1640 case 2: /* rcl */
1641 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1642 break;
1643 case 3: /* rcr */
1644 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1645 break;
1646 case 4: /* sal/shl */
1647 case 6: /* sal/shl */
1648 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1649 break;
1650 case 5: /* shr */
1651 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1652 break;
1653 case 7: /* sar */
1654 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1655 break;
1656 }
1657 }
1658
1659 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1660 struct x86_emulate_ops *ops)
1661 {
1662 struct decode_cache *c = &ctxt->decode;
1663
1664 switch (c->modrm_reg) {
1665 case 0 ... 1: /* test */
1666 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1667 break;
1668 case 2: /* not */
1669 c->dst.val = ~c->dst.val;
1670 break;
1671 case 3: /* neg */
1672 emulate_1op("neg", c->dst, ctxt->eflags);
1673 break;
1674 default:
1675 return 0;
1676 }
1677 return 1;
1678 }
1679
1680 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1681 struct x86_emulate_ops *ops)
1682 {
1683 struct decode_cache *c = &ctxt->decode;
1684
1685 switch (c->modrm_reg) {
1686 case 0: /* inc */
1687 emulate_1op("inc", c->dst, ctxt->eflags);
1688 break;
1689 case 1: /* dec */
1690 emulate_1op("dec", c->dst, ctxt->eflags);
1691 break;
1692 case 2: /* call near abs */ {
1693 long int old_eip;
1694 old_eip = c->eip;
1695 c->eip = c->src.val;
1696 c->src.val = old_eip;
1697 emulate_push(ctxt);
1698 break;
1699 }
1700 case 4: /* jmp abs */
1701 c->eip = c->src.val;
1702 break;
1703 case 6: /* push */
1704 emulate_push(ctxt);
1705 break;
1706 }
1707 return X86EMUL_CONTINUE;
1708 }
1709
1710 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1711 struct x86_emulate_ops *ops)
1712 {
1713 struct decode_cache *c = &ctxt->decode;
1714 u64 old = c->dst.orig_val;
1715
1716 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1717 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1718
1719 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1720 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1721 ctxt->eflags &= ~EFLG_ZF;
1722 } else {
1723 c->dst.val = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1724 (u32) c->regs[VCPU_REGS_RBX];
1725
1726 ctxt->eflags |= EFLG_ZF;
1727 c->lock_prefix = 1;
1728 }
1729 return X86EMUL_CONTINUE;
1730 }
1731
1732 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1733 struct x86_emulate_ops *ops)
1734 {
1735 struct decode_cache *c = &ctxt->decode;
1736 int rc;
1737 unsigned long cs;
1738
1739 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1740 if (rc != X86EMUL_CONTINUE)
1741 return rc;
1742 if (c->op_bytes == 4)
1743 c->eip = (u32)c->eip;
1744 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1745 if (rc != X86EMUL_CONTINUE)
1746 return rc;
1747 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1748 return rc;
1749 }
1750
1751 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1752 struct x86_emulate_ops *ops)
1753 {
1754 int rc;
1755 struct decode_cache *c = &ctxt->decode;
1756
1757 switch (c->dst.type) {
1758 case OP_REG:
1759 /* The 4-byte case *is* correct:
1760 * in 64-bit mode we zero-extend.
1761 */
1762 switch (c->dst.bytes) {
1763 case 1:
1764 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1765 break;
1766 case 2:
1767 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1768 break;
1769 case 4:
1770 *c->dst.ptr = (u32)c->dst.val;
1771 break; /* 64b: zero-ext */
1772 case 8:
1773 *c->dst.ptr = c->dst.val;
1774 break;
1775 }
1776 break;
1777 case OP_MEM:
1778 if (c->lock_prefix)
1779 rc = ops->cmpxchg_emulated(
1780 (unsigned long)c->dst.ptr,
1781 &c->dst.orig_val,
1782 &c->dst.val,
1783 c->dst.bytes,
1784 ctxt->vcpu);
1785 else
1786 rc = ops->write_emulated(
1787 (unsigned long)c->dst.ptr,
1788 &c->dst.val,
1789 c->dst.bytes,
1790 ctxt->vcpu);
1791 if (rc != X86EMUL_CONTINUE)
1792 return rc;
1793 break;
1794 case OP_NONE:
1795 /* no writeback */
1796 break;
1797 default:
1798 break;
1799 }
1800 return X86EMUL_CONTINUE;
1801 }
1802
1803 static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
1804 {
1805 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1806 /*
1807 * an sti; sti; sequence only disable interrupts for the first
1808 * instruction. So, if the last instruction, be it emulated or
1809 * not, left the system with the INT_STI flag enabled, it
1810 * means that the last instruction is an sti. We should not
1811 * leave the flag on in this case. The same goes for mov ss
1812 */
1813 if (!(int_shadow & mask))
1814 ctxt->interruptibility = mask;
1815 }
1816
1817 static inline void
1818 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1819 struct kvm_segment *cs, struct kvm_segment *ss)
1820 {
1821 memset(cs, 0, sizeof(struct kvm_segment));
1822 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
1823 memset(ss, 0, sizeof(struct kvm_segment));
1824
1825 cs->l = 0; /* will be adjusted later */
1826 cs->base = 0; /* flat segment */
1827 cs->g = 1; /* 4kb granularity */
1828 cs->limit = 0xffffffff; /* 4GB limit */
1829 cs->type = 0x0b; /* Read, Execute, Accessed */
1830 cs->s = 1;
1831 cs->dpl = 0; /* will be adjusted later */
1832 cs->present = 1;
1833 cs->db = 1;
1834
1835 ss->unusable = 0;
1836 ss->base = 0; /* flat segment */
1837 ss->limit = 0xffffffff; /* 4GB limit */
1838 ss->g = 1; /* 4kb granularity */
1839 ss->s = 1;
1840 ss->type = 0x03; /* Read/Write, Accessed */
1841 ss->db = 1; /* 32bit stack segment */
1842 ss->dpl = 0;
1843 ss->present = 1;
1844 }
1845
1846 static int
1847 emulate_syscall(struct x86_emulate_ctxt *ctxt)
1848 {
1849 struct decode_cache *c = &ctxt->decode;
1850 struct kvm_segment cs, ss;
1851 u64 msr_data;
1852
1853 /* syscall is not available in real mode */
1854 if (ctxt->mode == X86EMUL_MODE_REAL ||
1855 ctxt->mode == X86EMUL_MODE_VM86) {
1856 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1857 return X86EMUL_PROPAGATE_FAULT;
1858 }
1859
1860 setup_syscalls_segments(ctxt, &cs, &ss);
1861
1862 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1863 msr_data >>= 32;
1864 cs.selector = (u16)(msr_data & 0xfffc);
1865 ss.selector = (u16)(msr_data + 8);
1866
1867 if (is_long_mode(ctxt->vcpu)) {
1868 cs.db = 0;
1869 cs.l = 1;
1870 }
1871 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1872 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1873
1874 c->regs[VCPU_REGS_RCX] = c->eip;
1875 if (is_long_mode(ctxt->vcpu)) {
1876 #ifdef CONFIG_X86_64
1877 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1878
1879 kvm_x86_ops->get_msr(ctxt->vcpu,
1880 ctxt->mode == X86EMUL_MODE_PROT64 ?
1881 MSR_LSTAR : MSR_CSTAR, &msr_data);
1882 c->eip = msr_data;
1883
1884 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1885 ctxt->eflags &= ~(msr_data | EFLG_RF);
1886 #endif
1887 } else {
1888 /* legacy mode */
1889 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1890 c->eip = (u32)msr_data;
1891
1892 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1893 }
1894
1895 return X86EMUL_CONTINUE;
1896 }
1897
1898 static int
1899 emulate_sysenter(struct x86_emulate_ctxt *ctxt)
1900 {
1901 struct decode_cache *c = &ctxt->decode;
1902 struct kvm_segment cs, ss;
1903 u64 msr_data;
1904
1905 /* inject #GP if in real mode */
1906 if (ctxt->mode == X86EMUL_MODE_REAL) {
1907 kvm_inject_gp(ctxt->vcpu, 0);
1908 return X86EMUL_PROPAGATE_FAULT;
1909 }
1910
1911 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1912 * Therefore, we inject an #UD.
1913 */
1914 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1915 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1916 return X86EMUL_PROPAGATE_FAULT;
1917 }
1918
1919 setup_syscalls_segments(ctxt, &cs, &ss);
1920
1921 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1922 switch (ctxt->mode) {
1923 case X86EMUL_MODE_PROT32:
1924 if ((msr_data & 0xfffc) == 0x0) {
1925 kvm_inject_gp(ctxt->vcpu, 0);
1926 return X86EMUL_PROPAGATE_FAULT;
1927 }
1928 break;
1929 case X86EMUL_MODE_PROT64:
1930 if (msr_data == 0x0) {
1931 kvm_inject_gp(ctxt->vcpu, 0);
1932 return X86EMUL_PROPAGATE_FAULT;
1933 }
1934 break;
1935 }
1936
1937 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1938 cs.selector = (u16)msr_data;
1939 cs.selector &= ~SELECTOR_RPL_MASK;
1940 ss.selector = cs.selector + 8;
1941 ss.selector &= ~SELECTOR_RPL_MASK;
1942 if (ctxt->mode == X86EMUL_MODE_PROT64
1943 || is_long_mode(ctxt->vcpu)) {
1944 cs.db = 0;
1945 cs.l = 1;
1946 }
1947
1948 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1949 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1950
1951 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1952 c->eip = msr_data;
1953
1954 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1955 c->regs[VCPU_REGS_RSP] = msr_data;
1956
1957 return X86EMUL_CONTINUE;
1958 }
1959
1960 static int
1961 emulate_sysexit(struct x86_emulate_ctxt *ctxt)
1962 {
1963 struct decode_cache *c = &ctxt->decode;
1964 struct kvm_segment cs, ss;
1965 u64 msr_data;
1966 int usermode;
1967
1968 /* inject #GP if in real mode or Virtual 8086 mode */
1969 if (ctxt->mode == X86EMUL_MODE_REAL ||
1970 ctxt->mode == X86EMUL_MODE_VM86) {
1971 kvm_inject_gp(ctxt->vcpu, 0);
1972 return X86EMUL_PROPAGATE_FAULT;
1973 }
1974
1975 setup_syscalls_segments(ctxt, &cs, &ss);
1976
1977 if ((c->rex_prefix & 0x8) != 0x0)
1978 usermode = X86EMUL_MODE_PROT64;
1979 else
1980 usermode = X86EMUL_MODE_PROT32;
1981
1982 cs.dpl = 3;
1983 ss.dpl = 3;
1984 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1985 switch (usermode) {
1986 case X86EMUL_MODE_PROT32:
1987 cs.selector = (u16)(msr_data + 16);
1988 if ((msr_data & 0xfffc) == 0x0) {
1989 kvm_inject_gp(ctxt->vcpu, 0);
1990 return X86EMUL_PROPAGATE_FAULT;
1991 }
1992 ss.selector = (u16)(msr_data + 24);
1993 break;
1994 case X86EMUL_MODE_PROT64:
1995 cs.selector = (u16)(msr_data + 32);
1996 if (msr_data == 0x0) {
1997 kvm_inject_gp(ctxt->vcpu, 0);
1998 return X86EMUL_PROPAGATE_FAULT;
1999 }
2000 ss.selector = cs.selector + 8;
2001 cs.db = 0;
2002 cs.l = 1;
2003 break;
2004 }
2005 cs.selector |= SELECTOR_RPL_MASK;
2006 ss.selector |= SELECTOR_RPL_MASK;
2007
2008 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
2009 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
2010
2011 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
2012 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
2013
2014 return X86EMUL_CONTINUE;
2015 }
2016
2017 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2018 struct x86_emulate_ops *ops)
2019 {
2020 int iopl;
2021 if (ctxt->mode == X86EMUL_MODE_REAL)
2022 return false;
2023 if (ctxt->mode == X86EMUL_MODE_VM86)
2024 return true;
2025 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2026 return ops->cpl(ctxt->vcpu) > iopl;
2027 }
2028
2029 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2030 struct x86_emulate_ops *ops,
2031 u16 port, u16 len)
2032 {
2033 struct kvm_segment tr_seg;
2034 int r;
2035 u16 io_bitmap_ptr;
2036 u8 perm, bit_idx = port & 0x7;
2037 unsigned mask = (1 << len) - 1;
2038
2039 kvm_get_segment(ctxt->vcpu, &tr_seg, VCPU_SREG_TR);
2040 if (tr_seg.unusable)
2041 return false;
2042 if (tr_seg.limit < 103)
2043 return false;
2044 r = ops->read_std(tr_seg.base + 102, &io_bitmap_ptr, 2, ctxt->vcpu,
2045 NULL);
2046 if (r != X86EMUL_CONTINUE)
2047 return false;
2048 if (io_bitmap_ptr + port/8 > tr_seg.limit)
2049 return false;
2050 r = ops->read_std(tr_seg.base + io_bitmap_ptr + port/8, &perm, 1,
2051 ctxt->vcpu, NULL);
2052 if (r != X86EMUL_CONTINUE)
2053 return false;
2054 if ((perm >> bit_idx) & mask)
2055 return false;
2056 return true;
2057 }
2058
2059 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2060 struct x86_emulate_ops *ops,
2061 u16 port, u16 len)
2062 {
2063 if (emulator_bad_iopl(ctxt, ops))
2064 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2065 return false;
2066 return true;
2067 }
2068
2069 static u32 get_cached_descriptor_base(struct x86_emulate_ctxt *ctxt,
2070 struct x86_emulate_ops *ops,
2071 int seg)
2072 {
2073 struct desc_struct desc;
2074 if (ops->get_cached_descriptor(&desc, seg, ctxt->vcpu))
2075 return get_desc_base(&desc);
2076 else
2077 return ~0;
2078 }
2079
2080 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2081 struct x86_emulate_ops *ops,
2082 struct tss_segment_16 *tss)
2083 {
2084 struct decode_cache *c = &ctxt->decode;
2085
2086 tss->ip = c->eip;
2087 tss->flag = ctxt->eflags;
2088 tss->ax = c->regs[VCPU_REGS_RAX];
2089 tss->cx = c->regs[VCPU_REGS_RCX];
2090 tss->dx = c->regs[VCPU_REGS_RDX];
2091 tss->bx = c->regs[VCPU_REGS_RBX];
2092 tss->sp = c->regs[VCPU_REGS_RSP];
2093 tss->bp = c->regs[VCPU_REGS_RBP];
2094 tss->si = c->regs[VCPU_REGS_RSI];
2095 tss->di = c->regs[VCPU_REGS_RDI];
2096
2097 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2098 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2099 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2100 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2101 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2102 }
2103
2104 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2105 struct x86_emulate_ops *ops,
2106 struct tss_segment_16 *tss)
2107 {
2108 struct decode_cache *c = &ctxt->decode;
2109 int ret;
2110
2111 c->eip = tss->ip;
2112 ctxt->eflags = tss->flag | 2;
2113 c->regs[VCPU_REGS_RAX] = tss->ax;
2114 c->regs[VCPU_REGS_RCX] = tss->cx;
2115 c->regs[VCPU_REGS_RDX] = tss->dx;
2116 c->regs[VCPU_REGS_RBX] = tss->bx;
2117 c->regs[VCPU_REGS_RSP] = tss->sp;
2118 c->regs[VCPU_REGS_RBP] = tss->bp;
2119 c->regs[VCPU_REGS_RSI] = tss->si;
2120 c->regs[VCPU_REGS_RDI] = tss->di;
2121
2122 /*
2123 * SDM says that segment selectors are loaded before segment
2124 * descriptors
2125 */
2126 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2127 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2128 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2129 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2130 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2131
2132 /*
2133 * Now load segment descriptors. If fault happenes at this stage
2134 * it is handled in a context of new task
2135 */
2136 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2137 if (ret != X86EMUL_CONTINUE)
2138 return ret;
2139 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2140 if (ret != X86EMUL_CONTINUE)
2141 return ret;
2142 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2143 if (ret != X86EMUL_CONTINUE)
2144 return ret;
2145 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2146 if (ret != X86EMUL_CONTINUE)
2147 return ret;
2148 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2149 if (ret != X86EMUL_CONTINUE)
2150 return ret;
2151
2152 return X86EMUL_CONTINUE;
2153 }
2154
2155 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2156 struct x86_emulate_ops *ops,
2157 u16 tss_selector, u16 old_tss_sel,
2158 ulong old_tss_base, struct desc_struct *new_desc)
2159 {
2160 struct tss_segment_16 tss_seg;
2161 int ret;
2162 u32 err, new_tss_base = get_desc_base(new_desc);
2163
2164 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2165 &err);
2166 if (ret == X86EMUL_PROPAGATE_FAULT) {
2167 /* FIXME: need to provide precise fault address */
2168 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2169 return ret;
2170 }
2171
2172 save_state_to_tss16(ctxt, ops, &tss_seg);
2173
2174 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2175 &err);
2176 if (ret == X86EMUL_PROPAGATE_FAULT) {
2177 /* FIXME: need to provide precise fault address */
2178 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2179 return ret;
2180 }
2181
2182 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2183 &err);
2184 if (ret == X86EMUL_PROPAGATE_FAULT) {
2185 /* FIXME: need to provide precise fault address */
2186 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2187 return ret;
2188 }
2189
2190 if (old_tss_sel != 0xffff) {
2191 tss_seg.prev_task_link = old_tss_sel;
2192
2193 ret = ops->write_std(new_tss_base,
2194 &tss_seg.prev_task_link,
2195 sizeof tss_seg.prev_task_link,
2196 ctxt->vcpu, &err);
2197 if (ret == X86EMUL_PROPAGATE_FAULT) {
2198 /* FIXME: need to provide precise fault address */
2199 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2200 return ret;
2201 }
2202 }
2203
2204 return load_state_from_tss16(ctxt, ops, &tss_seg);
2205 }
2206
2207 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2208 struct x86_emulate_ops *ops,
2209 struct tss_segment_32 *tss)
2210 {
2211 struct decode_cache *c = &ctxt->decode;
2212
2213 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2214 tss->eip = c->eip;
2215 tss->eflags = ctxt->eflags;
2216 tss->eax = c->regs[VCPU_REGS_RAX];
2217 tss->ecx = c->regs[VCPU_REGS_RCX];
2218 tss->edx = c->regs[VCPU_REGS_RDX];
2219 tss->ebx = c->regs[VCPU_REGS_RBX];
2220 tss->esp = c->regs[VCPU_REGS_RSP];
2221 tss->ebp = c->regs[VCPU_REGS_RBP];
2222 tss->esi = c->regs[VCPU_REGS_RSI];
2223 tss->edi = c->regs[VCPU_REGS_RDI];
2224
2225 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2226 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2227 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2228 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2229 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2230 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2231 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2232 }
2233
2234 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2235 struct x86_emulate_ops *ops,
2236 struct tss_segment_32 *tss)
2237 {
2238 struct decode_cache *c = &ctxt->decode;
2239 int ret;
2240
2241 ops->set_cr(3, tss->cr3, ctxt->vcpu);
2242 c->eip = tss->eip;
2243 ctxt->eflags = tss->eflags | 2;
2244 c->regs[VCPU_REGS_RAX] = tss->eax;
2245 c->regs[VCPU_REGS_RCX] = tss->ecx;
2246 c->regs[VCPU_REGS_RDX] = tss->edx;
2247 c->regs[VCPU_REGS_RBX] = tss->ebx;
2248 c->regs[VCPU_REGS_RSP] = tss->esp;
2249 c->regs[VCPU_REGS_RBP] = tss->ebp;
2250 c->regs[VCPU_REGS_RSI] = tss->esi;
2251 c->regs[VCPU_REGS_RDI] = tss->edi;
2252
2253 /*
2254 * SDM says that segment selectors are loaded before segment
2255 * descriptors
2256 */
2257 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2258 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2259 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2260 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2261 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2262 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2263 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2264
2265 /*
2266 * Now load segment descriptors. If fault happenes at this stage
2267 * it is handled in a context of new task
2268 */
2269 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2270 if (ret != X86EMUL_CONTINUE)
2271 return ret;
2272 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2273 if (ret != X86EMUL_CONTINUE)
2274 return ret;
2275 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2276 if (ret != X86EMUL_CONTINUE)
2277 return ret;
2278 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2279 if (ret != X86EMUL_CONTINUE)
2280 return ret;
2281 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2282 if (ret != X86EMUL_CONTINUE)
2283 return ret;
2284 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2285 if (ret != X86EMUL_CONTINUE)
2286 return ret;
2287 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2288 if (ret != X86EMUL_CONTINUE)
2289 return ret;
2290
2291 return X86EMUL_CONTINUE;
2292 }
2293
2294 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2295 struct x86_emulate_ops *ops,
2296 u16 tss_selector, u16 old_tss_sel,
2297 ulong old_tss_base, struct desc_struct *new_desc)
2298 {
2299 struct tss_segment_32 tss_seg;
2300 int ret;
2301 u32 err, new_tss_base = get_desc_base(new_desc);
2302
2303 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2304 &err);
2305 if (ret == X86EMUL_PROPAGATE_FAULT) {
2306 /* FIXME: need to provide precise fault address */
2307 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2308 return ret;
2309 }
2310
2311 save_state_to_tss32(ctxt, ops, &tss_seg);
2312
2313 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2314 &err);
2315 if (ret == X86EMUL_PROPAGATE_FAULT) {
2316 /* FIXME: need to provide precise fault address */
2317 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2318 return ret;
2319 }
2320
2321 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2322 &err);
2323 if (ret == X86EMUL_PROPAGATE_FAULT) {
2324 /* FIXME: need to provide precise fault address */
2325 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2326 return ret;
2327 }
2328
2329 if (old_tss_sel != 0xffff) {
2330 tss_seg.prev_task_link = old_tss_sel;
2331
2332 ret = ops->write_std(new_tss_base,
2333 &tss_seg.prev_task_link,
2334 sizeof tss_seg.prev_task_link,
2335 ctxt->vcpu, &err);
2336 if (ret == X86EMUL_PROPAGATE_FAULT) {
2337 /* FIXME: need to provide precise fault address */
2338 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2339 return ret;
2340 }
2341 }
2342
2343 return load_state_from_tss32(ctxt, ops, &tss_seg);
2344 }
2345
2346 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2347 struct x86_emulate_ops *ops,
2348 u16 tss_selector, int reason)
2349 {
2350 struct desc_struct curr_tss_desc, next_tss_desc;
2351 int ret;
2352 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2353 ulong old_tss_base =
2354 get_cached_descriptor_base(ctxt, ops, VCPU_SREG_TR);
2355 u32 desc_limit;
2356
2357 /* FIXME: old_tss_base == ~0 ? */
2358
2359 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2360 if (ret != X86EMUL_CONTINUE)
2361 return ret;
2362 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2363 if (ret != X86EMUL_CONTINUE)
2364 return ret;
2365
2366 /* FIXME: check that next_tss_desc is tss */
2367
2368 if (reason != TASK_SWITCH_IRET) {
2369 if ((tss_selector & 3) > next_tss_desc.dpl ||
2370 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
2371 kvm_inject_gp(ctxt->vcpu, 0);
2372 return X86EMUL_PROPAGATE_FAULT;
2373 }
2374 }
2375
2376 desc_limit = desc_limit_scaled(&next_tss_desc);
2377 if (!next_tss_desc.p ||
2378 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2379 desc_limit < 0x2b)) {
2380 kvm_queue_exception_e(ctxt->vcpu, TS_VECTOR,
2381 tss_selector & 0xfffc);
2382 return X86EMUL_PROPAGATE_FAULT;
2383 }
2384
2385 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2386 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2387 write_segment_descriptor(ctxt, ops, old_tss_sel,
2388 &curr_tss_desc);
2389 }
2390
2391 if (reason == TASK_SWITCH_IRET)
2392 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2393
2394 /* set back link to prev task only if NT bit is set in eflags
2395 note that old_tss_sel is not used afetr this point */
2396 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2397 old_tss_sel = 0xffff;
2398
2399 if (next_tss_desc.type & 8)
2400 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2401 old_tss_base, &next_tss_desc);
2402 else
2403 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2404 old_tss_base, &next_tss_desc);
2405
2406 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2407 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2408
2409 if (reason != TASK_SWITCH_IRET) {
2410 next_tss_desc.type |= (1 << 1); /* set busy flag */
2411 write_segment_descriptor(ctxt, ops, tss_selector,
2412 &next_tss_desc);
2413 }
2414
2415 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2416 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2417 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2418
2419 return ret;
2420 }
2421
2422 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2423 struct x86_emulate_ops *ops,
2424 u16 tss_selector, int reason)
2425 {
2426 struct decode_cache *c = &ctxt->decode;
2427 int rc;
2428
2429 memset(c, 0, sizeof(struct decode_cache));
2430 c->eip = ctxt->eip;
2431 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
2432
2433 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason);
2434
2435 if (rc == X86EMUL_CONTINUE) {
2436 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
2437 kvm_rip_write(ctxt->vcpu, c->eip);
2438 }
2439
2440 return rc;
2441 }
2442
2443 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
2444 int reg, struct operand *op)
2445 {
2446 struct decode_cache *c = &ctxt->decode;
2447 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2448
2449 register_address_increment(c, &c->regs[reg], df * op->bytes);
2450 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
2451 }
2452
2453 int
2454 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
2455 {
2456 u64 msr_data;
2457 struct decode_cache *c = &ctxt->decode;
2458 int rc = X86EMUL_CONTINUE;
2459 int saved_dst_type = c->dst.type;
2460
2461 ctxt->interruptibility = 0;
2462
2463 /* Shadow copy of register state. Committed on successful emulation.
2464 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
2465 * modify them.
2466 */
2467
2468 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
2469
2470 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
2471 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2472 goto done;
2473 }
2474
2475 /* LOCK prefix is allowed only with some instructions */
2476 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
2477 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2478 goto done;
2479 }
2480
2481 /* Privileged instruction can be executed only in CPL=0 */
2482 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
2483 kvm_inject_gp(ctxt->vcpu, 0);
2484 goto done;
2485 }
2486
2487 if (c->rep_prefix && (c->d & String)) {
2488 ctxt->restart = true;
2489 /* All REP prefixes have the same first termination condition */
2490 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
2491 string_done:
2492 ctxt->restart = false;
2493 kvm_rip_write(ctxt->vcpu, c->eip);
2494 goto done;
2495 }
2496 /* The second termination condition only applies for REPE
2497 * and REPNE. Test if the repeat string operation prefix is
2498 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2499 * corresponding termination condition according to:
2500 * - if REPE/REPZ and ZF = 0 then done
2501 * - if REPNE/REPNZ and ZF = 1 then done
2502 */
2503 if ((c->b == 0xa6) || (c->b == 0xa7) ||
2504 (c->b == 0xae) || (c->b == 0xaf)) {
2505 if ((c->rep_prefix == REPE_PREFIX) &&
2506 ((ctxt->eflags & EFLG_ZF) == 0))
2507 goto string_done;
2508 if ((c->rep_prefix == REPNE_PREFIX) &&
2509 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2510 goto string_done;
2511 }
2512 c->eip = ctxt->eip;
2513 }
2514
2515 if (c->src.type == OP_MEM) {
2516 rc = ops->read_emulated((unsigned long)c->src.ptr,
2517 &c->src.val,
2518 c->src.bytes,
2519 ctxt->vcpu);
2520 if (rc != X86EMUL_CONTINUE)
2521 goto done;
2522 c->src.orig_val = c->src.val;
2523 }
2524
2525 if (c->src2.type == OP_MEM) {
2526 rc = ops->read_emulated((unsigned long)c->src2.ptr,
2527 &c->src2.val,
2528 c->src2.bytes,
2529 ctxt->vcpu);
2530 if (rc != X86EMUL_CONTINUE)
2531 goto done;
2532 }
2533
2534 if ((c->d & DstMask) == ImplicitOps)
2535 goto special_insn;
2536
2537
2538 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2539 /* optimisation - avoid slow emulated read if Mov */
2540 rc = ops->read_emulated((unsigned long)c->dst.ptr, &c->dst.val,
2541 c->dst.bytes, ctxt->vcpu);
2542 if (rc != X86EMUL_CONTINUE)
2543 goto done;
2544 }
2545 c->dst.orig_val = c->dst.val;
2546
2547 special_insn:
2548
2549 if (c->twobyte)
2550 goto twobyte_insn;
2551
2552 switch (c->b) {
2553 case 0x00 ... 0x05:
2554 add: /* add */
2555 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2556 break;
2557 case 0x06: /* push es */
2558 emulate_push_sreg(ctxt, VCPU_SREG_ES);
2559 break;
2560 case 0x07: /* pop es */
2561 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
2562 if (rc != X86EMUL_CONTINUE)
2563 goto done;
2564 break;
2565 case 0x08 ... 0x0d:
2566 or: /* or */
2567 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2568 break;
2569 case 0x0e: /* push cs */
2570 emulate_push_sreg(ctxt, VCPU_SREG_CS);
2571 break;
2572 case 0x10 ... 0x15:
2573 adc: /* adc */
2574 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2575 break;
2576 case 0x16: /* push ss */
2577 emulate_push_sreg(ctxt, VCPU_SREG_SS);
2578 break;
2579 case 0x17: /* pop ss */
2580 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
2581 if (rc != X86EMUL_CONTINUE)
2582 goto done;
2583 break;
2584 case 0x18 ... 0x1d:
2585 sbb: /* sbb */
2586 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2587 break;
2588 case 0x1e: /* push ds */
2589 emulate_push_sreg(ctxt, VCPU_SREG_DS);
2590 break;
2591 case 0x1f: /* pop ds */
2592 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
2593 if (rc != X86EMUL_CONTINUE)
2594 goto done;
2595 break;
2596 case 0x20 ... 0x25:
2597 and: /* and */
2598 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2599 break;
2600 case 0x28 ... 0x2d:
2601 sub: /* sub */
2602 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2603 break;
2604 case 0x30 ... 0x35:
2605 xor: /* xor */
2606 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2607 break;
2608 case 0x38 ... 0x3d:
2609 cmp: /* cmp */
2610 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2611 break;
2612 case 0x40 ... 0x47: /* inc r16/r32 */
2613 emulate_1op("inc", c->dst, ctxt->eflags);
2614 break;
2615 case 0x48 ... 0x4f: /* dec r16/r32 */
2616 emulate_1op("dec", c->dst, ctxt->eflags);
2617 break;
2618 case 0x50 ... 0x57: /* push reg */
2619 emulate_push(ctxt);
2620 break;
2621 case 0x58 ... 0x5f: /* pop reg */
2622 pop_instruction:
2623 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
2624 if (rc != X86EMUL_CONTINUE)
2625 goto done;
2626 break;
2627 case 0x60: /* pusha */
2628 emulate_pusha(ctxt);
2629 break;
2630 case 0x61: /* popa */
2631 rc = emulate_popa(ctxt, ops);
2632 if (rc != X86EMUL_CONTINUE)
2633 goto done;
2634 break;
2635 case 0x63: /* movsxd */
2636 if (ctxt->mode != X86EMUL_MODE_PROT64)
2637 goto cannot_emulate;
2638 c->dst.val = (s32) c->src.val;
2639 break;
2640 case 0x68: /* push imm */
2641 case 0x6a: /* push imm8 */
2642 emulate_push(ctxt);
2643 break;
2644 case 0x6c: /* insb */
2645 case 0x6d: /* insw/insd */
2646 c->dst.bytes = min(c->dst.bytes, 4u);
2647 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2648 c->dst.bytes)) {
2649 kvm_inject_gp(ctxt->vcpu, 0);
2650 goto done;
2651 }
2652 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2653 c->regs[VCPU_REGS_RDX], &c->dst.val))
2654 goto done; /* IO is needed, skip writeback */
2655 break;
2656 case 0x6e: /* outsb */
2657 case 0x6f: /* outsw/outsd */
2658 c->src.bytes = min(c->src.bytes, 4u);
2659 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2660 c->src.bytes)) {
2661 kvm_inject_gp(ctxt->vcpu, 0);
2662 goto done;
2663 }
2664 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2665 &c->src.val, 1, ctxt->vcpu);
2666
2667 c->dst.type = OP_NONE; /* nothing to writeback */
2668 break;
2669 case 0x70 ... 0x7f: /* jcc (short) */
2670 if (test_cc(c->b, ctxt->eflags))
2671 jmp_rel(c, c->src.val);
2672 break;
2673 case 0x80 ... 0x83: /* Grp1 */
2674 switch (c->modrm_reg) {
2675 case 0:
2676 goto add;
2677 case 1:
2678 goto or;
2679 case 2:
2680 goto adc;
2681 case 3:
2682 goto sbb;
2683 case 4:
2684 goto and;
2685 case 5:
2686 goto sub;
2687 case 6:
2688 goto xor;
2689 case 7:
2690 goto cmp;
2691 }
2692 break;
2693 case 0x84 ... 0x85:
2694 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
2695 break;
2696 case 0x86 ... 0x87: /* xchg */
2697 xchg:
2698 /* Write back the register source. */
2699 switch (c->dst.bytes) {
2700 case 1:
2701 *(u8 *) c->src.ptr = (u8) c->dst.val;
2702 break;
2703 case 2:
2704 *(u16 *) c->src.ptr = (u16) c->dst.val;
2705 break;
2706 case 4:
2707 *c->src.ptr = (u32) c->dst.val;
2708 break; /* 64b reg: zero-extend */
2709 case 8:
2710 *c->src.ptr = c->dst.val;
2711 break;
2712 }
2713 /*
2714 * Write back the memory destination with implicit LOCK
2715 * prefix.
2716 */
2717 c->dst.val = c->src.val;
2718 c->lock_prefix = 1;
2719 break;
2720 case 0x88 ... 0x8b: /* mov */
2721 goto mov;
2722 case 0x8c: { /* mov r/m, sreg */
2723 struct kvm_segment segreg;
2724
2725 if (c->modrm_reg <= VCPU_SREG_GS)
2726 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
2727 else {
2728 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2729 goto done;
2730 }
2731 c->dst.val = segreg.selector;
2732 break;
2733 }
2734 case 0x8d: /* lea r16/r32, m */
2735 c->dst.val = c->modrm_ea;
2736 break;
2737 case 0x8e: { /* mov seg, r/m16 */
2738 uint16_t sel;
2739
2740 sel = c->src.val;
2741
2742 if (c->modrm_reg == VCPU_SREG_CS ||
2743 c->modrm_reg > VCPU_SREG_GS) {
2744 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2745 goto done;
2746 }
2747
2748 if (c->modrm_reg == VCPU_SREG_SS)
2749 toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_MOV_SS);
2750
2751 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
2752
2753 c->dst.type = OP_NONE; /* Disable writeback. */
2754 break;
2755 }
2756 case 0x8f: /* pop (sole member of Grp1a) */
2757 rc = emulate_grp1a(ctxt, ops);
2758 if (rc != X86EMUL_CONTINUE)
2759 goto done;
2760 break;
2761 case 0x90: /* nop / xchg r8,rax */
2762 if (!(c->rex_prefix & 1)) { /* nop */
2763 c->dst.type = OP_NONE;
2764 break;
2765 }
2766 case 0x91 ... 0x97: /* xchg reg,rax */
2767 c->src.type = c->dst.type = OP_REG;
2768 c->src.bytes = c->dst.bytes = c->op_bytes;
2769 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2770 c->src.val = *(c->src.ptr);
2771 goto xchg;
2772 case 0x9c: /* pushf */
2773 c->src.val = (unsigned long) ctxt->eflags;
2774 emulate_push(ctxt);
2775 break;
2776 case 0x9d: /* popf */
2777 c->dst.type = OP_REG;
2778 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2779 c->dst.bytes = c->op_bytes;
2780 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2781 if (rc != X86EMUL_CONTINUE)
2782 goto done;
2783 break;
2784 case 0xa0 ... 0xa1: /* mov */
2785 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2786 c->dst.val = c->src.val;
2787 break;
2788 case 0xa2 ... 0xa3: /* mov */
2789 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
2790 break;
2791 case 0xa4 ... 0xa5: /* movs */
2792 goto mov;
2793 case 0xa6 ... 0xa7: /* cmps */
2794 c->dst.type = OP_NONE; /* Disable writeback. */
2795 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
2796 goto cmp;
2797 case 0xaa ... 0xab: /* stos */
2798 c->dst.val = c->regs[VCPU_REGS_RAX];
2799 break;
2800 case 0xac ... 0xad: /* lods */
2801 goto mov;
2802 case 0xae ... 0xaf: /* scas */
2803 DPRINTF("Urk! I don't handle SCAS.\n");
2804 goto cannot_emulate;
2805 case 0xb0 ... 0xbf: /* mov r, imm */
2806 goto mov;
2807 case 0xc0 ... 0xc1:
2808 emulate_grp2(ctxt);
2809 break;
2810 case 0xc3: /* ret */
2811 c->dst.type = OP_REG;
2812 c->dst.ptr = &c->eip;
2813 c->dst.bytes = c->op_bytes;
2814 goto pop_instruction;
2815 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2816 mov:
2817 c->dst.val = c->src.val;
2818 break;
2819 case 0xcb: /* ret far */
2820 rc = emulate_ret_far(ctxt, ops);
2821 if (rc != X86EMUL_CONTINUE)
2822 goto done;
2823 break;
2824 case 0xd0 ... 0xd1: /* Grp2 */
2825 c->src.val = 1;
2826 emulate_grp2(ctxt);
2827 break;
2828 case 0xd2 ... 0xd3: /* Grp2 */
2829 c->src.val = c->regs[VCPU_REGS_RCX];
2830 emulate_grp2(ctxt);
2831 break;
2832 case 0xe4: /* inb */
2833 case 0xe5: /* in */
2834 goto do_io_in;
2835 case 0xe6: /* outb */
2836 case 0xe7: /* out */
2837 goto do_io_out;
2838 case 0xe8: /* call (near) */ {
2839 long int rel = c->src.val;
2840 c->src.val = (unsigned long) c->eip;
2841 jmp_rel(c, rel);
2842 emulate_push(ctxt);
2843 break;
2844 }
2845 case 0xe9: /* jmp rel */
2846 goto jmp;
2847 case 0xea: /* jmp far */
2848 jump_far:
2849 if (load_segment_descriptor(ctxt, ops, c->src2.val,
2850 VCPU_SREG_CS))
2851 goto done;
2852
2853 c->eip = c->src.val;
2854 break;
2855 case 0xeb:
2856 jmp: /* jmp rel short */
2857 jmp_rel(c, c->src.val);
2858 c->dst.type = OP_NONE; /* Disable writeback. */
2859 break;
2860 case 0xec: /* in al,dx */
2861 case 0xed: /* in (e/r)ax,dx */
2862 c->src.val = c->regs[VCPU_REGS_RDX];
2863 do_io_in:
2864 c->dst.bytes = min(c->dst.bytes, 4u);
2865 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
2866 kvm_inject_gp(ctxt->vcpu, 0);
2867 goto done;
2868 }
2869 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
2870 &c->dst.val))
2871 goto done; /* IO is needed */
2872 break;
2873 case 0xee: /* out al,dx */
2874 case 0xef: /* out (e/r)ax,dx */
2875 c->src.val = c->regs[VCPU_REGS_RDX];
2876 do_io_out:
2877 c->dst.bytes = min(c->dst.bytes, 4u);
2878 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
2879 kvm_inject_gp(ctxt->vcpu, 0);
2880 goto done;
2881 }
2882 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
2883 ctxt->vcpu);
2884 c->dst.type = OP_NONE; /* Disable writeback. */
2885 break;
2886 case 0xf4: /* hlt */
2887 ctxt->vcpu->arch.halt_request = 1;
2888 break;
2889 case 0xf5: /* cmc */
2890 /* complement carry flag from eflags reg */
2891 ctxt->eflags ^= EFLG_CF;
2892 c->dst.type = OP_NONE; /* Disable writeback. */
2893 break;
2894 case 0xf6 ... 0xf7: /* Grp3 */
2895 if (!emulate_grp3(ctxt, ops))
2896 goto cannot_emulate;
2897 break;
2898 case 0xf8: /* clc */
2899 ctxt->eflags &= ~EFLG_CF;
2900 c->dst.type = OP_NONE; /* Disable writeback. */
2901 break;
2902 case 0xfa: /* cli */
2903 if (emulator_bad_iopl(ctxt, ops))
2904 kvm_inject_gp(ctxt->vcpu, 0);
2905 else {
2906 ctxt->eflags &= ~X86_EFLAGS_IF;
2907 c->dst.type = OP_NONE; /* Disable writeback. */
2908 }
2909 break;
2910 case 0xfb: /* sti */
2911 if (emulator_bad_iopl(ctxt, ops))
2912 kvm_inject_gp(ctxt->vcpu, 0);
2913 else {
2914 toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_STI);
2915 ctxt->eflags |= X86_EFLAGS_IF;
2916 c->dst.type = OP_NONE; /* Disable writeback. */
2917 }
2918 break;
2919 case 0xfc: /* cld */
2920 ctxt->eflags &= ~EFLG_DF;
2921 c->dst.type = OP_NONE; /* Disable writeback. */
2922 break;
2923 case 0xfd: /* std */
2924 ctxt->eflags |= EFLG_DF;
2925 c->dst.type = OP_NONE; /* Disable writeback. */
2926 break;
2927 case 0xfe: /* Grp4 */
2928 grp45:
2929 rc = emulate_grp45(ctxt, ops);
2930 if (rc != X86EMUL_CONTINUE)
2931 goto done;
2932 break;
2933 case 0xff: /* Grp5 */
2934 if (c->modrm_reg == 5)
2935 goto jump_far;
2936 goto grp45;
2937 }
2938
2939 writeback:
2940 rc = writeback(ctxt, ops);
2941 if (rc != X86EMUL_CONTINUE)
2942 goto done;
2943
2944 /*
2945 * restore dst type in case the decoding will be reused
2946 * (happens for string instruction )
2947 */
2948 c->dst.type = saved_dst_type;
2949
2950 if ((c->d & SrcMask) == SrcSI)
2951 string_addr_inc(ctxt, seg_override_base(ctxt, c), VCPU_REGS_RSI,
2952 &c->src);
2953
2954 if ((c->d & DstMask) == DstDI)
2955 string_addr_inc(ctxt, es_base(ctxt), VCPU_REGS_RDI, &c->dst);
2956
2957 if (c->rep_prefix && (c->d & String)) {
2958 struct read_cache *rc = &ctxt->decode.io_read;
2959 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
2960 /*
2961 * Re-enter guest when pio read ahead buffer is empty or,
2962 * if it is not used, after each 1024 iteration.
2963 */
2964 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
2965 (rc->end != 0 && rc->end == rc->pos))
2966 ctxt->restart = false;
2967 }
2968
2969 /* Commit shadow register state. */
2970 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
2971 kvm_rip_write(ctxt->vcpu, c->eip);
2972 ops->set_rflags(ctxt->vcpu, ctxt->eflags);
2973
2974 done:
2975 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2976
2977 twobyte_insn:
2978 switch (c->b) {
2979 case 0x01: /* lgdt, lidt, lmsw */
2980 switch (c->modrm_reg) {
2981 u16 size;
2982 unsigned long address;
2983
2984 case 0: /* vmcall */
2985 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2986 goto cannot_emulate;
2987
2988 rc = kvm_fix_hypercall(ctxt->vcpu);
2989 if (rc != X86EMUL_CONTINUE)
2990 goto done;
2991
2992 /* Let the processor re-execute the fixed hypercall */
2993 c->eip = ctxt->eip;
2994 /* Disable writeback. */
2995 c->dst.type = OP_NONE;
2996 break;
2997 case 2: /* lgdt */
2998 rc = read_descriptor(ctxt, ops, c->src.ptr,
2999 &size, &address, c->op_bytes);
3000 if (rc != X86EMUL_CONTINUE)
3001 goto done;
3002 realmode_lgdt(ctxt->vcpu, size, address);
3003 /* Disable writeback. */
3004 c->dst.type = OP_NONE;
3005 break;
3006 case 3: /* lidt/vmmcall */
3007 if (c->modrm_mod == 3) {
3008 switch (c->modrm_rm) {
3009 case 1:
3010 rc = kvm_fix_hypercall(ctxt->vcpu);
3011 if (rc != X86EMUL_CONTINUE)
3012 goto done;
3013 break;
3014 default:
3015 goto cannot_emulate;
3016 }
3017 } else {
3018 rc = read_descriptor(ctxt, ops, c->src.ptr,
3019 &size, &address,
3020 c->op_bytes);
3021 if (rc != X86EMUL_CONTINUE)
3022 goto done;
3023 realmode_lidt(ctxt->vcpu, size, address);
3024 }
3025 /* Disable writeback. */
3026 c->dst.type = OP_NONE;
3027 break;
3028 case 4: /* smsw */
3029 c->dst.bytes = 2;
3030 c->dst.val = ops->get_cr(0, ctxt->vcpu);
3031 break;
3032 case 6: /* lmsw */
3033 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3034 (c->src.val & 0x0f), ctxt->vcpu);
3035 c->dst.type = OP_NONE;
3036 break;
3037 case 5: /* not defined */
3038 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3039 goto done;
3040 case 7: /* invlpg*/
3041 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
3042 /* Disable writeback. */
3043 c->dst.type = OP_NONE;
3044 break;
3045 default:
3046 goto cannot_emulate;
3047 }
3048 break;
3049 case 0x05: /* syscall */
3050 rc = emulate_syscall(ctxt);
3051 if (rc != X86EMUL_CONTINUE)
3052 goto done;
3053 else
3054 goto writeback;
3055 break;
3056 case 0x06:
3057 emulate_clts(ctxt->vcpu);
3058 c->dst.type = OP_NONE;
3059 break;
3060 case 0x08: /* invd */
3061 case 0x09: /* wbinvd */
3062 case 0x0d: /* GrpP (prefetch) */
3063 case 0x18: /* Grp16 (prefetch/nop) */
3064 c->dst.type = OP_NONE;
3065 break;
3066 case 0x20: /* mov cr, reg */
3067 switch (c->modrm_reg) {
3068 case 1:
3069 case 5 ... 7:
3070 case 9 ... 15:
3071 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3072 goto done;
3073 }
3074 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
3075 c->dst.type = OP_NONE; /* no writeback */
3076 break;
3077 case 0x21: /* mov from dr to reg */
3078 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3079 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3080 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3081 goto done;
3082 }
3083 emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
3084 c->dst.type = OP_NONE; /* no writeback */
3085 break;
3086 case 0x22: /* mov reg, cr */
3087 ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu);
3088 c->dst.type = OP_NONE;
3089 break;
3090 case 0x23: /* mov from reg to dr */
3091 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3092 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3093 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3094 goto done;
3095 }
3096 emulator_set_dr(ctxt, c->modrm_reg, c->regs[c->modrm_rm]);
3097 c->dst.type = OP_NONE; /* no writeback */
3098 break;
3099 case 0x30:
3100 /* wrmsr */
3101 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3102 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3103 if (kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
3104 kvm_inject_gp(ctxt->vcpu, 0);
3105 goto done;
3106 }
3107 rc = X86EMUL_CONTINUE;
3108 c->dst.type = OP_NONE;
3109 break;
3110 case 0x32:
3111 /* rdmsr */
3112 if (kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
3113 kvm_inject_gp(ctxt->vcpu, 0);
3114 goto done;
3115 } else {
3116 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3117 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3118 }
3119 rc = X86EMUL_CONTINUE;
3120 c->dst.type = OP_NONE;
3121 break;
3122 case 0x34: /* sysenter */
3123 rc = emulate_sysenter(ctxt);
3124 if (rc != X86EMUL_CONTINUE)
3125 goto done;
3126 else
3127 goto writeback;
3128 break;
3129 case 0x35: /* sysexit */
3130 rc = emulate_sysexit(ctxt);
3131 if (rc != X86EMUL_CONTINUE)
3132 goto done;
3133 else
3134 goto writeback;
3135 break;
3136 case 0x40 ... 0x4f: /* cmov */
3137 c->dst.val = c->dst.orig_val = c->src.val;
3138 if (!test_cc(c->b, ctxt->eflags))
3139 c->dst.type = OP_NONE; /* no writeback */
3140 break;
3141 case 0x80 ... 0x8f: /* jnz rel, etc*/
3142 if (test_cc(c->b, ctxt->eflags))
3143 jmp_rel(c, c->src.val);
3144 c->dst.type = OP_NONE;
3145 break;
3146 case 0xa0: /* push fs */
3147 emulate_push_sreg(ctxt, VCPU_SREG_FS);
3148 break;
3149 case 0xa1: /* pop fs */
3150 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
3151 if (rc != X86EMUL_CONTINUE)
3152 goto done;
3153 break;
3154 case 0xa3:
3155 bt: /* bt */
3156 c->dst.type = OP_NONE;
3157 /* only subword offset */
3158 c->src.val &= (c->dst.bytes << 3) - 1;
3159 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
3160 break;
3161 case 0xa4: /* shld imm8, r, r/m */
3162 case 0xa5: /* shld cl, r, r/m */
3163 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3164 break;
3165 case 0xa8: /* push gs */
3166 emulate_push_sreg(ctxt, VCPU_SREG_GS);
3167 break;
3168 case 0xa9: /* pop gs */
3169 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
3170 if (rc != X86EMUL_CONTINUE)
3171 goto done;
3172 break;
3173 case 0xab:
3174 bts: /* bts */
3175 /* only subword offset */
3176 c->src.val &= (c->dst.bytes << 3) - 1;
3177 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
3178 break;
3179 case 0xac: /* shrd imm8, r, r/m */
3180 case 0xad: /* shrd cl, r, r/m */
3181 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3182 break;
3183 case 0xae: /* clflush */
3184 break;
3185 case 0xb0 ... 0xb1: /* cmpxchg */
3186 /*
3187 * Save real source value, then compare EAX against
3188 * destination.
3189 */
3190 c->src.orig_val = c->src.val;
3191 c->src.val = c->regs[VCPU_REGS_RAX];
3192 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3193 if (ctxt->eflags & EFLG_ZF) {
3194 /* Success: write back to memory. */
3195 c->dst.val = c->src.orig_val;
3196 } else {
3197 /* Failure: write the value we saw to EAX. */
3198 c->dst.type = OP_REG;
3199 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
3200 }
3201 break;
3202 case 0xb3:
3203 btr: /* btr */
3204 /* only subword offset */
3205 c->src.val &= (c->dst.bytes << 3) - 1;
3206 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
3207 break;
3208 case 0xb6 ... 0xb7: /* movzx */
3209 c->dst.bytes = c->op_bytes;
3210 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3211 : (u16) c->src.val;
3212 break;
3213 case 0xba: /* Grp8 */
3214 switch (c->modrm_reg & 3) {
3215 case 0:
3216 goto bt;
3217 case 1:
3218 goto bts;
3219 case 2:
3220 goto btr;
3221 case 3:
3222 goto btc;
3223 }
3224 break;
3225 case 0xbb:
3226 btc: /* btc */
3227 /* only subword offset */
3228 c->src.val &= (c->dst.bytes << 3) - 1;
3229 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
3230 break;
3231 case 0xbe ... 0xbf: /* movsx */
3232 c->dst.bytes = c->op_bytes;
3233 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3234 (s16) c->src.val;
3235 break;
3236 case 0xc3: /* movnti */
3237 c->dst.bytes = c->op_bytes;
3238 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3239 (u64) c->src.val;
3240 break;
3241 case 0xc7: /* Grp9 (cmpxchg8b) */
3242 rc = emulate_grp9(ctxt, ops);
3243 if (rc != X86EMUL_CONTINUE)
3244 goto done;
3245 break;
3246 }
3247 goto writeback;
3248
3249 cannot_emulate:
3250 DPRINTF("Cannot emulate %02x\n", c->b);
3251 return -1;
3252 }
Linux kernel - Deliverables
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