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KVM: MMU: Optimize guest page table walk
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
25 #include <linux/module.h>
26 #include <asm/kvm_emulate.h>
27
28 #include "x86.h"
29 #include "tss.h"
30
31 /*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40 /* Operand sizes: 8-bit operands or specified/overridden size. */
41 #define ByteOp (1<<0) /* 8-bit operands. */
42 /* Destination operand type. */
43 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44 #define DstReg (2<<1) /* Register operand. */
45 #define DstMem (3<<1) /* Memory operand. */
46 #define DstAcc (4<<1) /* Destination Accumulator */
47 #define DstDI (5<<1) /* Destination is in ES:(E)DI */
48 #define DstMem64 (6<<1) /* 64bit memory operand */
49 #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
50 #define DstMask (7<<1)
51 /* Source operand type. */
52 #define SrcNone (0<<4) /* No source operand. */
53 #define SrcReg (1<<4) /* Register operand. */
54 #define SrcMem (2<<4) /* Memory operand. */
55 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57 #define SrcImm (5<<4) /* Immediate operand. */
58 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
59 #define SrcOne (7<<4) /* Implied '1' */
60 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
61 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
62 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */
63 #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64 #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
65 #define SrcAcc (0xd<<4) /* Source Accumulator */
66 #define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
67 #define SrcMask (0xf<<4)
68 /* Generic ModRM decode. */
69 #define ModRM (1<<8)
70 /* Destination is only written; never read. */
71 #define Mov (1<<9)
72 #define BitOp (1<<10)
73 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
74 #define String (1<<12) /* String instruction (rep capable) */
75 #define Stack (1<<13) /* Stack instruction (push/pop) */
76 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
78 #define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */
79 #define Sse (1<<17) /* SSE Vector instruction */
80 #define RMExt (1<<18) /* Opcode extension in ModRM r/m if mod == 3 */
81 /* Misc flags */
82 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
83 #define VendorSpecific (1<<22) /* Vendor specific instruction */
84 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
85 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
86 #define Undefined (1<<25) /* No Such Instruction */
87 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
88 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
89 #define No64 (1<<28)
90 /* Source 2 operand type */
91 #define Src2None (0<<29)
92 #define Src2CL (1<<29)
93 #define Src2ImmByte (2<<29)
94 #define Src2One (3<<29)
95 #define Src2Imm (4<<29)
96 #define Src2Mask (7<<29)
97
98 #define X2(x...) x, x
99 #define X3(x...) X2(x), x
100 #define X4(x...) X2(x), X2(x)
101 #define X5(x...) X4(x), x
102 #define X6(x...) X4(x), X2(x)
103 #define X7(x...) X4(x), X3(x)
104 #define X8(x...) X4(x), X4(x)
105 #define X16(x...) X8(x), X8(x)
106
107 struct opcode {
108 u32 flags;
109 u8 intercept;
110 union {
111 int (*execute)(struct x86_emulate_ctxt *ctxt);
112 struct opcode *group;
113 struct group_dual *gdual;
114 struct gprefix *gprefix;
115 } u;
116 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
117 };
118
119 struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
122 };
123
124 struct gprefix {
125 struct opcode pfx_no;
126 struct opcode pfx_66;
127 struct opcode pfx_f2;
128 struct opcode pfx_f3;
129 };
130
131 /* EFLAGS bit definitions. */
132 #define EFLG_ID (1<<21)
133 #define EFLG_VIP (1<<20)
134 #define EFLG_VIF (1<<19)
135 #define EFLG_AC (1<<18)
136 #define EFLG_VM (1<<17)
137 #define EFLG_RF (1<<16)
138 #define EFLG_IOPL (3<<12)
139 #define EFLG_NT (1<<14)
140 #define EFLG_OF (1<<11)
141 #define EFLG_DF (1<<10)
142 #define EFLG_IF (1<<9)
143 #define EFLG_TF (1<<8)
144 #define EFLG_SF (1<<7)
145 #define EFLG_ZF (1<<6)
146 #define EFLG_AF (1<<4)
147 #define EFLG_PF (1<<2)
148 #define EFLG_CF (1<<0)
149
150 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
151 #define EFLG_RESERVED_ONE_MASK 2
152
153 /*
154 * Instruction emulation:
155 * Most instructions are emulated directly via a fragment of inline assembly
156 * code. This allows us to save/restore EFLAGS and thus very easily pick up
157 * any modified flags.
158 */
159
160 #if defined(CONFIG_X86_64)
161 #define _LO32 "k" /* force 32-bit operand */
162 #define _STK "%%rsp" /* stack pointer */
163 #elif defined(__i386__)
164 #define _LO32 "" /* force 32-bit operand */
165 #define _STK "%%esp" /* stack pointer */
166 #endif
167
168 /*
169 * These EFLAGS bits are restored from saved value during emulation, and
170 * any changes are written back to the saved value after emulation.
171 */
172 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
173
174 /* Before executing instruction: restore necessary bits in EFLAGS. */
175 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
176 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
177 "movl %"_sav",%"_LO32 _tmp"; " \
178 "push %"_tmp"; " \
179 "push %"_tmp"; " \
180 "movl %"_msk",%"_LO32 _tmp"; " \
181 "andl %"_LO32 _tmp",("_STK"); " \
182 "pushf; " \
183 "notl %"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
186 "pop %"_tmp"; " \
187 "orl %"_LO32 _tmp",("_STK"); " \
188 "popf; " \
189 "pop %"_sav"; "
190
191 /* After executing instruction: write-back necessary bits in EFLAGS. */
192 #define _POST_EFLAGS(_sav, _msk, _tmp) \
193 /* _sav |= EFLAGS & _msk; */ \
194 "pushf; " \
195 "pop %"_tmp"; " \
196 "andl %"_msk",%"_LO32 _tmp"; " \
197 "orl %"_LO32 _tmp",%"_sav"; "
198
199 #ifdef CONFIG_X86_64
200 #define ON64(x) x
201 #else
202 #define ON64(x)
203 #endif
204
205 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
206 do { \
207 __asm__ __volatile__ ( \
208 _PRE_EFLAGS("0", "4", "2") \
209 _op _suffix " %"_x"3,%1; " \
210 _POST_EFLAGS("0", "4", "2") \
211 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
212 "=&r" (_tmp) \
213 : _y ((_src).val), "i" (EFLAGS_MASK)); \
214 } while (0)
215
216
217 /* Raw emulation: instruction has two explicit operands. */
218 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
219 do { \
220 unsigned long _tmp; \
221 \
222 switch ((_dst).bytes) { \
223 case 2: \
224 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
225 break; \
226 case 4: \
227 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
228 break; \
229 case 8: \
230 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
231 break; \
232 } \
233 } while (0)
234
235 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
236 do { \
237 unsigned long _tmp; \
238 switch ((_dst).bytes) { \
239 case 1: \
240 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
241 break; \
242 default: \
243 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
244 _wx, _wy, _lx, _ly, _qx, _qy); \
245 break; \
246 } \
247 } while (0)
248
249 /* Source operand is byte-sized and may be restricted to just %cl. */
250 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
251 __emulate_2op(_op, _src, _dst, _eflags, \
252 "b", "c", "b", "c", "b", "c", "b", "c")
253
254 /* Source operand is byte, word, long or quad sized. */
255 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
256 __emulate_2op(_op, _src, _dst, _eflags, \
257 "b", "q", "w", "r", _LO32, "r", "", "r")
258
259 /* Source operand is word, long or quad sized. */
260 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
261 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
262 "w", "r", _LO32, "r", "", "r")
263
264 /* Instruction has three operands and one operand is stored in ECX register */
265 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
266 do { \
267 unsigned long _tmp; \
268 _type _clv = (_cl).val; \
269 _type _srcv = (_src).val; \
270 _type _dstv = (_dst).val; \
271 \
272 __asm__ __volatile__ ( \
273 _PRE_EFLAGS("0", "5", "2") \
274 _op _suffix " %4,%1 \n" \
275 _POST_EFLAGS("0", "5", "2") \
276 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
277 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
278 ); \
279 \
280 (_cl).val = (unsigned long) _clv; \
281 (_src).val = (unsigned long) _srcv; \
282 (_dst).val = (unsigned long) _dstv; \
283 } while (0)
284
285 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
286 do { \
287 switch ((_dst).bytes) { \
288 case 2: \
289 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
290 "w", unsigned short); \
291 break; \
292 case 4: \
293 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
294 "l", unsigned int); \
295 break; \
296 case 8: \
297 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
298 "q", unsigned long)); \
299 break; \
300 } \
301 } while (0)
302
303 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
304 do { \
305 unsigned long _tmp; \
306 \
307 __asm__ __volatile__ ( \
308 _PRE_EFLAGS("0", "3", "2") \
309 _op _suffix " %1; " \
310 _POST_EFLAGS("0", "3", "2") \
311 : "=m" (_eflags), "+m" ((_dst).val), \
312 "=&r" (_tmp) \
313 : "i" (EFLAGS_MASK)); \
314 } while (0)
315
316 /* Instruction has only one explicit operand (no source operand). */
317 #define emulate_1op(_op, _dst, _eflags) \
318 do { \
319 switch ((_dst).bytes) { \
320 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
321 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
322 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
323 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
324 } \
325 } while (0)
326
327 #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
328 do { \
329 unsigned long _tmp; \
330 \
331 __asm__ __volatile__ ( \
332 _PRE_EFLAGS("0", "4", "1") \
333 _op _suffix " %5; " \
334 _POST_EFLAGS("0", "4", "1") \
335 : "=m" (_eflags), "=&r" (_tmp), \
336 "+a" (_rax), "+d" (_rdx) \
337 : "i" (EFLAGS_MASK), "m" ((_src).val), \
338 "a" (_rax), "d" (_rdx)); \
339 } while (0)
340
341 #define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
342 do { \
343 unsigned long _tmp; \
344 \
345 __asm__ __volatile__ ( \
346 _PRE_EFLAGS("0", "5", "1") \
347 "1: \n\t" \
348 _op _suffix " %6; " \
349 "2: \n\t" \
350 _POST_EFLAGS("0", "5", "1") \
351 ".pushsection .fixup,\"ax\" \n\t" \
352 "3: movb $1, %4 \n\t" \
353 "jmp 2b \n\t" \
354 ".popsection \n\t" \
355 _ASM_EXTABLE(1b, 3b) \
356 : "=m" (_eflags), "=&r" (_tmp), \
357 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
358 : "i" (EFLAGS_MASK), "m" ((_src).val), \
359 "a" (_rax), "d" (_rdx)); \
360 } while (0)
361
362 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
363 #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
364 do { \
365 switch((_src).bytes) { \
366 case 1: \
367 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
368 _eflags, "b"); \
369 break; \
370 case 2: \
371 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
372 _eflags, "w"); \
373 break; \
374 case 4: \
375 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
376 _eflags, "l"); \
377 break; \
378 case 8: \
379 ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
380 _eflags, "q")); \
381 break; \
382 } \
383 } while (0)
384
385 #define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
386 do { \
387 switch((_src).bytes) { \
388 case 1: \
389 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
390 _eflags, "b", _ex); \
391 break; \
392 case 2: \
393 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
394 _eflags, "w", _ex); \
395 break; \
396 case 4: \
397 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
398 _eflags, "l", _ex); \
399 break; \
400 case 8: ON64( \
401 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
402 _eflags, "q", _ex)); \
403 break; \
404 } \
405 } while (0)
406
407 /* Fetch next part of the instruction being emulated. */
408 #define insn_fetch(_type, _size, _eip) \
409 ({ unsigned long _x; \
410 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
411 if (rc != X86EMUL_CONTINUE) \
412 goto done; \
413 (_eip) += (_size); \
414 (_type)_x; \
415 })
416
417 #define insn_fetch_arr(_arr, _size, _eip) \
418 ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
419 if (rc != X86EMUL_CONTINUE) \
420 goto done; \
421 (_eip) += (_size); \
422 })
423
424 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
425 enum x86_intercept intercept,
426 enum x86_intercept_stage stage)
427 {
428 struct x86_instruction_info info = {
429 .intercept = intercept,
430 .rep_prefix = ctxt->decode.rep_prefix,
431 .modrm_mod = ctxt->decode.modrm_mod,
432 .modrm_reg = ctxt->decode.modrm_reg,
433 .modrm_rm = ctxt->decode.modrm_rm,
434 .src_val = ctxt->decode.src.val64,
435 .src_bytes = ctxt->decode.src.bytes,
436 .dst_bytes = ctxt->decode.dst.bytes,
437 .ad_bytes = ctxt->decode.ad_bytes,
438 .next_rip = ctxt->eip,
439 };
440
441 return ctxt->ops->intercept(ctxt, &info, stage);
442 }
443
444 static inline unsigned long ad_mask(struct decode_cache *c)
445 {
446 return (1UL << (c->ad_bytes << 3)) - 1;
447 }
448
449 /* Access/update address held in a register, based on addressing mode. */
450 static inline unsigned long
451 address_mask(struct decode_cache *c, unsigned long reg)
452 {
453 if (c->ad_bytes == sizeof(unsigned long))
454 return reg;
455 else
456 return reg & ad_mask(c);
457 }
458
459 static inline unsigned long
460 register_address(struct decode_cache *c, unsigned long reg)
461 {
462 return address_mask(c, reg);
463 }
464
465 static inline void
466 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
467 {
468 if (c->ad_bytes == sizeof(unsigned long))
469 *reg += inc;
470 else
471 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
472 }
473
474 static inline void jmp_rel(struct decode_cache *c, int rel)
475 {
476 register_address_increment(c, &c->eip, rel);
477 }
478
479 static u32 desc_limit_scaled(struct desc_struct *desc)
480 {
481 u32 limit = get_desc_limit(desc);
482
483 return desc->g ? (limit << 12) | 0xfff : limit;
484 }
485
486 static void set_seg_override(struct decode_cache *c, int seg)
487 {
488 c->has_seg_override = true;
489 c->seg_override = seg;
490 }
491
492 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
493 struct x86_emulate_ops *ops, int seg)
494 {
495 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
496 return 0;
497
498 return ops->get_cached_segment_base(ctxt, seg);
499 }
500
501 static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
502 struct x86_emulate_ops *ops,
503 struct decode_cache *c)
504 {
505 if (!c->has_seg_override)
506 return 0;
507
508 return c->seg_override;
509 }
510
511 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
512 u32 error, bool valid)
513 {
514 ctxt->exception.vector = vec;
515 ctxt->exception.error_code = error;
516 ctxt->exception.error_code_valid = valid;
517 return X86EMUL_PROPAGATE_FAULT;
518 }
519
520 static int emulate_db(struct x86_emulate_ctxt *ctxt)
521 {
522 return emulate_exception(ctxt, DB_VECTOR, 0, false);
523 }
524
525 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
526 {
527 return emulate_exception(ctxt, GP_VECTOR, err, true);
528 }
529
530 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
531 {
532 return emulate_exception(ctxt, SS_VECTOR, err, true);
533 }
534
535 static int emulate_ud(struct x86_emulate_ctxt *ctxt)
536 {
537 return emulate_exception(ctxt, UD_VECTOR, 0, false);
538 }
539
540 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
541 {
542 return emulate_exception(ctxt, TS_VECTOR, err, true);
543 }
544
545 static int emulate_de(struct x86_emulate_ctxt *ctxt)
546 {
547 return emulate_exception(ctxt, DE_VECTOR, 0, false);
548 }
549
550 static int emulate_nm(struct x86_emulate_ctxt *ctxt)
551 {
552 return emulate_exception(ctxt, NM_VECTOR, 0, false);
553 }
554
555 static int __linearize(struct x86_emulate_ctxt *ctxt,
556 struct segmented_address addr,
557 unsigned size, bool write, bool fetch,
558 ulong *linear)
559 {
560 struct decode_cache *c = &ctxt->decode;
561 struct desc_struct desc;
562 bool usable;
563 ulong la;
564 u32 lim;
565 unsigned cpl, rpl;
566
567 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
568 switch (ctxt->mode) {
569 case X86EMUL_MODE_REAL:
570 break;
571 case X86EMUL_MODE_PROT64:
572 if (((signed long)la << 16) >> 16 != la)
573 return emulate_gp(ctxt, 0);
574 break;
575 default:
576 usable = ctxt->ops->get_cached_descriptor(ctxt, &desc, NULL,
577 addr.seg);
578 if (!usable)
579 goto bad;
580 /* code segment or read-only data segment */
581 if (((desc.type & 8) || !(desc.type & 2)) && write)
582 goto bad;
583 /* unreadable code segment */
584 if (!fetch && (desc.type & 8) && !(desc.type & 2))
585 goto bad;
586 lim = desc_limit_scaled(&desc);
587 if ((desc.type & 8) || !(desc.type & 4)) {
588 /* expand-up segment */
589 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
590 goto bad;
591 } else {
592 /* exapand-down segment */
593 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
594 goto bad;
595 lim = desc.d ? 0xffffffff : 0xffff;
596 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
597 goto bad;
598 }
599 cpl = ctxt->ops->cpl(ctxt);
600 rpl = ctxt->ops->get_segment_selector(ctxt, addr.seg) & 3;
601 cpl = max(cpl, rpl);
602 if (!(desc.type & 8)) {
603 /* data segment */
604 if (cpl > desc.dpl)
605 goto bad;
606 } else if ((desc.type & 8) && !(desc.type & 4)) {
607 /* nonconforming code segment */
608 if (cpl != desc.dpl)
609 goto bad;
610 } else if ((desc.type & 8) && (desc.type & 4)) {
611 /* conforming code segment */
612 if (cpl < desc.dpl)
613 goto bad;
614 }
615 break;
616 }
617 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : c->ad_bytes != 8)
618 la &= (u32)-1;
619 *linear = la;
620 return X86EMUL_CONTINUE;
621 bad:
622 if (addr.seg == VCPU_SREG_SS)
623 return emulate_ss(ctxt, addr.seg);
624 else
625 return emulate_gp(ctxt, addr.seg);
626 }
627
628 static int linearize(struct x86_emulate_ctxt *ctxt,
629 struct segmented_address addr,
630 unsigned size, bool write,
631 ulong *linear)
632 {
633 return __linearize(ctxt, addr, size, write, false, linear);
634 }
635
636
637 static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
638 struct segmented_address addr,
639 void *data,
640 unsigned size)
641 {
642 int rc;
643 ulong linear;
644
645 rc = linearize(ctxt, addr, size, false, &linear);
646 if (rc != X86EMUL_CONTINUE)
647 return rc;
648 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
649 }
650
651 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
652 struct x86_emulate_ops *ops,
653 unsigned long eip, u8 *dest)
654 {
655 struct fetch_cache *fc = &ctxt->decode.fetch;
656 int rc;
657 int size, cur_size;
658
659 if (eip == fc->end) {
660 unsigned long linear;
661 struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
662 cur_size = fc->end - fc->start;
663 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
664 rc = __linearize(ctxt, addr, size, false, true, &linear);
665 if (rc != X86EMUL_CONTINUE)
666 return rc;
667 rc = ops->fetch(ctxt, linear, fc->data + cur_size,
668 size, &ctxt->exception);
669 if (rc != X86EMUL_CONTINUE)
670 return rc;
671 fc->end += size;
672 }
673 *dest = fc->data[eip - fc->start];
674 return X86EMUL_CONTINUE;
675 }
676
677 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
678 struct x86_emulate_ops *ops,
679 unsigned long eip, void *dest, unsigned size)
680 {
681 int rc;
682
683 /* x86 instructions are limited to 15 bytes. */
684 if (eip + size - ctxt->eip > 15)
685 return X86EMUL_UNHANDLEABLE;
686 while (size--) {
687 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
688 if (rc != X86EMUL_CONTINUE)
689 return rc;
690 }
691 return X86EMUL_CONTINUE;
692 }
693
694 /*
695 * Given the 'reg' portion of a ModRM byte, and a register block, return a
696 * pointer into the block that addresses the relevant register.
697 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
698 */
699 static void *decode_register(u8 modrm_reg, unsigned long *regs,
700 int highbyte_regs)
701 {
702 void *p;
703
704 p = &regs[modrm_reg];
705 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
706 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
707 return p;
708 }
709
710 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
711 struct x86_emulate_ops *ops,
712 struct segmented_address addr,
713 u16 *size, unsigned long *address, int op_bytes)
714 {
715 int rc;
716
717 if (op_bytes == 2)
718 op_bytes = 3;
719 *address = 0;
720 rc = segmented_read_std(ctxt, addr, size, 2);
721 if (rc != X86EMUL_CONTINUE)
722 return rc;
723 addr.ea += 2;
724 rc = segmented_read_std(ctxt, addr, address, op_bytes);
725 return rc;
726 }
727
728 static int test_cc(unsigned int condition, unsigned int flags)
729 {
730 int rc = 0;
731
732 switch ((condition & 15) >> 1) {
733 case 0: /* o */
734 rc |= (flags & EFLG_OF);
735 break;
736 case 1: /* b/c/nae */
737 rc |= (flags & EFLG_CF);
738 break;
739 case 2: /* z/e */
740 rc |= (flags & EFLG_ZF);
741 break;
742 case 3: /* be/na */
743 rc |= (flags & (EFLG_CF|EFLG_ZF));
744 break;
745 case 4: /* s */
746 rc |= (flags & EFLG_SF);
747 break;
748 case 5: /* p/pe */
749 rc |= (flags & EFLG_PF);
750 break;
751 case 7: /* le/ng */
752 rc |= (flags & EFLG_ZF);
753 /* fall through */
754 case 6: /* l/nge */
755 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
756 break;
757 }
758
759 /* Odd condition identifiers (lsb == 1) have inverted sense. */
760 return (!!rc ^ (condition & 1));
761 }
762
763 static void fetch_register_operand(struct operand *op)
764 {
765 switch (op->bytes) {
766 case 1:
767 op->val = *(u8 *)op->addr.reg;
768 break;
769 case 2:
770 op->val = *(u16 *)op->addr.reg;
771 break;
772 case 4:
773 op->val = *(u32 *)op->addr.reg;
774 break;
775 case 8:
776 op->val = *(u64 *)op->addr.reg;
777 break;
778 }
779 }
780
781 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
782 {
783 ctxt->ops->get_fpu(ctxt);
784 switch (reg) {
785 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
786 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
787 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
788 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
789 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
790 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
791 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
792 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
793 #ifdef CONFIG_X86_64
794 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
795 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
796 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
797 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
798 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
799 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
800 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
801 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
802 #endif
803 default: BUG();
804 }
805 ctxt->ops->put_fpu(ctxt);
806 }
807
808 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
809 int reg)
810 {
811 ctxt->ops->get_fpu(ctxt);
812 switch (reg) {
813 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
814 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
815 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
816 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
817 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
818 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
819 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
820 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
821 #ifdef CONFIG_X86_64
822 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
823 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
824 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
825 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
826 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
827 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
828 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
829 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
830 #endif
831 default: BUG();
832 }
833 ctxt->ops->put_fpu(ctxt);
834 }
835
836 static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
837 struct operand *op,
838 struct decode_cache *c,
839 int inhibit_bytereg)
840 {
841 unsigned reg = c->modrm_reg;
842 int highbyte_regs = c->rex_prefix == 0;
843
844 if (!(c->d & ModRM))
845 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
846
847 if (c->d & Sse) {
848 op->type = OP_XMM;
849 op->bytes = 16;
850 op->addr.xmm = reg;
851 read_sse_reg(ctxt, &op->vec_val, reg);
852 return;
853 }
854
855 op->type = OP_REG;
856 if ((c->d & ByteOp) && !inhibit_bytereg) {
857 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
858 op->bytes = 1;
859 } else {
860 op->addr.reg = decode_register(reg, c->regs, 0);
861 op->bytes = c->op_bytes;
862 }
863 fetch_register_operand(op);
864 op->orig_val = op->val;
865 }
866
867 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
868 struct x86_emulate_ops *ops,
869 struct operand *op)
870 {
871 struct decode_cache *c = &ctxt->decode;
872 u8 sib;
873 int index_reg = 0, base_reg = 0, scale;
874 int rc = X86EMUL_CONTINUE;
875 ulong modrm_ea = 0;
876
877 if (c->rex_prefix) {
878 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
879 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
880 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
881 }
882
883 c->modrm = insn_fetch(u8, 1, c->eip);
884 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
885 c->modrm_reg |= (c->modrm & 0x38) >> 3;
886 c->modrm_rm |= (c->modrm & 0x07);
887 c->modrm_seg = VCPU_SREG_DS;
888
889 if (c->modrm_mod == 3) {
890 op->type = OP_REG;
891 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
892 op->addr.reg = decode_register(c->modrm_rm,
893 c->regs, c->d & ByteOp);
894 if (c->d & Sse) {
895 op->type = OP_XMM;
896 op->bytes = 16;
897 op->addr.xmm = c->modrm_rm;
898 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
899 return rc;
900 }
901 fetch_register_operand(op);
902 return rc;
903 }
904
905 op->type = OP_MEM;
906
907 if (c->ad_bytes == 2) {
908 unsigned bx = c->regs[VCPU_REGS_RBX];
909 unsigned bp = c->regs[VCPU_REGS_RBP];
910 unsigned si = c->regs[VCPU_REGS_RSI];
911 unsigned di = c->regs[VCPU_REGS_RDI];
912
913 /* 16-bit ModR/M decode. */
914 switch (c->modrm_mod) {
915 case 0:
916 if (c->modrm_rm == 6)
917 modrm_ea += insn_fetch(u16, 2, c->eip);
918 break;
919 case 1:
920 modrm_ea += insn_fetch(s8, 1, c->eip);
921 break;
922 case 2:
923 modrm_ea += insn_fetch(u16, 2, c->eip);
924 break;
925 }
926 switch (c->modrm_rm) {
927 case 0:
928 modrm_ea += bx + si;
929 break;
930 case 1:
931 modrm_ea += bx + di;
932 break;
933 case 2:
934 modrm_ea += bp + si;
935 break;
936 case 3:
937 modrm_ea += bp + di;
938 break;
939 case 4:
940 modrm_ea += si;
941 break;
942 case 5:
943 modrm_ea += di;
944 break;
945 case 6:
946 if (c->modrm_mod != 0)
947 modrm_ea += bp;
948 break;
949 case 7:
950 modrm_ea += bx;
951 break;
952 }
953 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
954 (c->modrm_rm == 6 && c->modrm_mod != 0))
955 c->modrm_seg = VCPU_SREG_SS;
956 modrm_ea = (u16)modrm_ea;
957 } else {
958 /* 32/64-bit ModR/M decode. */
959 if ((c->modrm_rm & 7) == 4) {
960 sib = insn_fetch(u8, 1, c->eip);
961 index_reg |= (sib >> 3) & 7;
962 base_reg |= sib & 7;
963 scale = sib >> 6;
964
965 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
966 modrm_ea += insn_fetch(s32, 4, c->eip);
967 else
968 modrm_ea += c->regs[base_reg];
969 if (index_reg != 4)
970 modrm_ea += c->regs[index_reg] << scale;
971 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
972 if (ctxt->mode == X86EMUL_MODE_PROT64)
973 c->rip_relative = 1;
974 } else
975 modrm_ea += c->regs[c->modrm_rm];
976 switch (c->modrm_mod) {
977 case 0:
978 if (c->modrm_rm == 5)
979 modrm_ea += insn_fetch(s32, 4, c->eip);
980 break;
981 case 1:
982 modrm_ea += insn_fetch(s8, 1, c->eip);
983 break;
984 case 2:
985 modrm_ea += insn_fetch(s32, 4, c->eip);
986 break;
987 }
988 }
989 op->addr.mem.ea = modrm_ea;
990 done:
991 return rc;
992 }
993
994 static int decode_abs(struct x86_emulate_ctxt *ctxt,
995 struct x86_emulate_ops *ops,
996 struct operand *op)
997 {
998 struct decode_cache *c = &ctxt->decode;
999 int rc = X86EMUL_CONTINUE;
1000
1001 op->type = OP_MEM;
1002 switch (c->ad_bytes) {
1003 case 2:
1004 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1005 break;
1006 case 4:
1007 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1008 break;
1009 case 8:
1010 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1011 break;
1012 }
1013 done:
1014 return rc;
1015 }
1016
1017 static void fetch_bit_operand(struct decode_cache *c)
1018 {
1019 long sv = 0, mask;
1020
1021 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
1022 mask = ~(c->dst.bytes * 8 - 1);
1023
1024 if (c->src.bytes == 2)
1025 sv = (s16)c->src.val & (s16)mask;
1026 else if (c->src.bytes == 4)
1027 sv = (s32)c->src.val & (s32)mask;
1028
1029 c->dst.addr.mem.ea += (sv >> 3);
1030 }
1031
1032 /* only subword offset */
1033 c->src.val &= (c->dst.bytes << 3) - 1;
1034 }
1035
1036 static int read_emulated(struct x86_emulate_ctxt *ctxt,
1037 struct x86_emulate_ops *ops,
1038 unsigned long addr, void *dest, unsigned size)
1039 {
1040 int rc;
1041 struct read_cache *mc = &ctxt->decode.mem_read;
1042
1043 while (size) {
1044 int n = min(size, 8u);
1045 size -= n;
1046 if (mc->pos < mc->end)
1047 goto read_cached;
1048
1049 rc = ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1050 &ctxt->exception);
1051 if (rc != X86EMUL_CONTINUE)
1052 return rc;
1053 mc->end += n;
1054
1055 read_cached:
1056 memcpy(dest, mc->data + mc->pos, n);
1057 mc->pos += n;
1058 dest += n;
1059 addr += n;
1060 }
1061 return X86EMUL_CONTINUE;
1062 }
1063
1064 static int segmented_read(struct x86_emulate_ctxt *ctxt,
1065 struct segmented_address addr,
1066 void *data,
1067 unsigned size)
1068 {
1069 int rc;
1070 ulong linear;
1071
1072 rc = linearize(ctxt, addr, size, false, &linear);
1073 if (rc != X86EMUL_CONTINUE)
1074 return rc;
1075 return read_emulated(ctxt, ctxt->ops, linear, data, size);
1076 }
1077
1078 static int segmented_write(struct x86_emulate_ctxt *ctxt,
1079 struct segmented_address addr,
1080 const void *data,
1081 unsigned size)
1082 {
1083 int rc;
1084 ulong linear;
1085
1086 rc = linearize(ctxt, addr, size, true, &linear);
1087 if (rc != X86EMUL_CONTINUE)
1088 return rc;
1089 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1090 &ctxt->exception);
1091 }
1092
1093 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1094 struct segmented_address addr,
1095 const void *orig_data, const void *data,
1096 unsigned size)
1097 {
1098 int rc;
1099 ulong linear;
1100
1101 rc = linearize(ctxt, addr, size, true, &linear);
1102 if (rc != X86EMUL_CONTINUE)
1103 return rc;
1104 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1105 size, &ctxt->exception);
1106 }
1107
1108 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1109 struct x86_emulate_ops *ops,
1110 unsigned int size, unsigned short port,
1111 void *dest)
1112 {
1113 struct read_cache *rc = &ctxt->decode.io_read;
1114
1115 if (rc->pos == rc->end) { /* refill pio read ahead */
1116 struct decode_cache *c = &ctxt->decode;
1117 unsigned int in_page, n;
1118 unsigned int count = c->rep_prefix ?
1119 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1120 in_page = (ctxt->eflags & EFLG_DF) ?
1121 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1122 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1123 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1124 count);
1125 if (n == 0)
1126 n = 1;
1127 rc->pos = rc->end = 0;
1128 if (!ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1129 return 0;
1130 rc->end = n * size;
1131 }
1132
1133 memcpy(dest, rc->data + rc->pos, size);
1134 rc->pos += size;
1135 return 1;
1136 }
1137
1138 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1139 struct x86_emulate_ops *ops,
1140 u16 selector, struct desc_ptr *dt)
1141 {
1142 if (selector & 1 << 2) {
1143 struct desc_struct desc;
1144 memset (dt, 0, sizeof *dt);
1145 if (!ops->get_cached_descriptor(ctxt, &desc, NULL,
1146 VCPU_SREG_LDTR))
1147 return;
1148
1149 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1150 dt->address = get_desc_base(&desc);
1151 } else
1152 ops->get_gdt(ctxt, dt);
1153 }
1154
1155 /* allowed just for 8 bytes segments */
1156 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1157 struct x86_emulate_ops *ops,
1158 u16 selector, struct desc_struct *desc)
1159 {
1160 struct desc_ptr dt;
1161 u16 index = selector >> 3;
1162 int ret;
1163 ulong addr;
1164
1165 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1166
1167 if (dt.size < index * 8 + 7)
1168 return emulate_gp(ctxt, selector & 0xfffc);
1169 addr = dt.address + index * 8;
1170 ret = ops->read_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
1171
1172 return ret;
1173 }
1174
1175 /* allowed just for 8 bytes segments */
1176 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1177 struct x86_emulate_ops *ops,
1178 u16 selector, struct desc_struct *desc)
1179 {
1180 struct desc_ptr dt;
1181 u16 index = selector >> 3;
1182 ulong addr;
1183 int ret;
1184
1185 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1186
1187 if (dt.size < index * 8 + 7)
1188 return emulate_gp(ctxt, selector & 0xfffc);
1189
1190 addr = dt.address + index * 8;
1191 ret = ops->write_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
1192
1193 return ret;
1194 }
1195
1196 /* Does not support long mode */
1197 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1198 struct x86_emulate_ops *ops,
1199 u16 selector, int seg)
1200 {
1201 struct desc_struct seg_desc;
1202 u8 dpl, rpl, cpl;
1203 unsigned err_vec = GP_VECTOR;
1204 u32 err_code = 0;
1205 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1206 int ret;
1207
1208 memset(&seg_desc, 0, sizeof seg_desc);
1209
1210 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1211 || ctxt->mode == X86EMUL_MODE_REAL) {
1212 /* set real mode segment descriptor */
1213 set_desc_base(&seg_desc, selector << 4);
1214 set_desc_limit(&seg_desc, 0xffff);
1215 seg_desc.type = 3;
1216 seg_desc.p = 1;
1217 seg_desc.s = 1;
1218 goto load;
1219 }
1220
1221 /* NULL selector is not valid for TR, CS and SS */
1222 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1223 && null_selector)
1224 goto exception;
1225
1226 /* TR should be in GDT only */
1227 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1228 goto exception;
1229
1230 if (null_selector) /* for NULL selector skip all following checks */
1231 goto load;
1232
1233 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1234 if (ret != X86EMUL_CONTINUE)
1235 return ret;
1236
1237 err_code = selector & 0xfffc;
1238 err_vec = GP_VECTOR;
1239
1240 /* can't load system descriptor into segment selecor */
1241 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1242 goto exception;
1243
1244 if (!seg_desc.p) {
1245 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1246 goto exception;
1247 }
1248
1249 rpl = selector & 3;
1250 dpl = seg_desc.dpl;
1251 cpl = ops->cpl(ctxt);
1252
1253 switch (seg) {
1254 case VCPU_SREG_SS:
1255 /*
1256 * segment is not a writable data segment or segment
1257 * selector's RPL != CPL or segment selector's RPL != CPL
1258 */
1259 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1260 goto exception;
1261 break;
1262 case VCPU_SREG_CS:
1263 if (!(seg_desc.type & 8))
1264 goto exception;
1265
1266 if (seg_desc.type & 4) {
1267 /* conforming */
1268 if (dpl > cpl)
1269 goto exception;
1270 } else {
1271 /* nonconforming */
1272 if (rpl > cpl || dpl != cpl)
1273 goto exception;
1274 }
1275 /* CS(RPL) <- CPL */
1276 selector = (selector & 0xfffc) | cpl;
1277 break;
1278 case VCPU_SREG_TR:
1279 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1280 goto exception;
1281 break;
1282 case VCPU_SREG_LDTR:
1283 if (seg_desc.s || seg_desc.type != 2)
1284 goto exception;
1285 break;
1286 default: /* DS, ES, FS, or GS */
1287 /*
1288 * segment is not a data or readable code segment or
1289 * ((segment is a data or nonconforming code segment)
1290 * and (both RPL and CPL > DPL))
1291 */
1292 if ((seg_desc.type & 0xa) == 0x8 ||
1293 (((seg_desc.type & 0xc) != 0xc) &&
1294 (rpl > dpl && cpl > dpl)))
1295 goto exception;
1296 break;
1297 }
1298
1299 if (seg_desc.s) {
1300 /* mark segment as accessed */
1301 seg_desc.type |= 1;
1302 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1303 if (ret != X86EMUL_CONTINUE)
1304 return ret;
1305 }
1306 load:
1307 ops->set_segment_selector(ctxt, selector, seg);
1308 ops->set_cached_descriptor(ctxt, &seg_desc, 0, seg);
1309 return X86EMUL_CONTINUE;
1310 exception:
1311 emulate_exception(ctxt, err_vec, err_code, true);
1312 return X86EMUL_PROPAGATE_FAULT;
1313 }
1314
1315 static void write_register_operand(struct operand *op)
1316 {
1317 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1318 switch (op->bytes) {
1319 case 1:
1320 *(u8 *)op->addr.reg = (u8)op->val;
1321 break;
1322 case 2:
1323 *(u16 *)op->addr.reg = (u16)op->val;
1324 break;
1325 case 4:
1326 *op->addr.reg = (u32)op->val;
1327 break; /* 64b: zero-extend */
1328 case 8:
1329 *op->addr.reg = op->val;
1330 break;
1331 }
1332 }
1333
1334 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1335 struct x86_emulate_ops *ops)
1336 {
1337 int rc;
1338 struct decode_cache *c = &ctxt->decode;
1339
1340 switch (c->dst.type) {
1341 case OP_REG:
1342 write_register_operand(&c->dst);
1343 break;
1344 case OP_MEM:
1345 if (c->lock_prefix)
1346 rc = segmented_cmpxchg(ctxt,
1347 c->dst.addr.mem,
1348 &c->dst.orig_val,
1349 &c->dst.val,
1350 c->dst.bytes);
1351 else
1352 rc = segmented_write(ctxt,
1353 c->dst.addr.mem,
1354 &c->dst.val,
1355 c->dst.bytes);
1356 if (rc != X86EMUL_CONTINUE)
1357 return rc;
1358 break;
1359 case OP_XMM:
1360 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1361 break;
1362 case OP_NONE:
1363 /* no writeback */
1364 break;
1365 default:
1366 break;
1367 }
1368 return X86EMUL_CONTINUE;
1369 }
1370
1371 static int em_push(struct x86_emulate_ctxt *ctxt)
1372 {
1373 struct decode_cache *c = &ctxt->decode;
1374 struct segmented_address addr;
1375
1376 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1377 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1378 addr.seg = VCPU_SREG_SS;
1379
1380 /* Disable writeback. */
1381 c->dst.type = OP_NONE;
1382 return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
1383 }
1384
1385 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1386 struct x86_emulate_ops *ops,
1387 void *dest, int len)
1388 {
1389 struct decode_cache *c = &ctxt->decode;
1390 int rc;
1391 struct segmented_address addr;
1392
1393 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1394 addr.seg = VCPU_SREG_SS;
1395 rc = segmented_read(ctxt, addr, dest, len);
1396 if (rc != X86EMUL_CONTINUE)
1397 return rc;
1398
1399 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1400 return rc;
1401 }
1402
1403 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1404 struct x86_emulate_ops *ops,
1405 void *dest, int len)
1406 {
1407 int rc;
1408 unsigned long val, change_mask;
1409 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1410 int cpl = ops->cpl(ctxt);
1411
1412 rc = emulate_pop(ctxt, ops, &val, len);
1413 if (rc != X86EMUL_CONTINUE)
1414 return rc;
1415
1416 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1417 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1418
1419 switch(ctxt->mode) {
1420 case X86EMUL_MODE_PROT64:
1421 case X86EMUL_MODE_PROT32:
1422 case X86EMUL_MODE_PROT16:
1423 if (cpl == 0)
1424 change_mask |= EFLG_IOPL;
1425 if (cpl <= iopl)
1426 change_mask |= EFLG_IF;
1427 break;
1428 case X86EMUL_MODE_VM86:
1429 if (iopl < 3)
1430 return emulate_gp(ctxt, 0);
1431 change_mask |= EFLG_IF;
1432 break;
1433 default: /* real mode */
1434 change_mask |= (EFLG_IOPL | EFLG_IF);
1435 break;
1436 }
1437
1438 *(unsigned long *)dest =
1439 (ctxt->eflags & ~change_mask) | (val & change_mask);
1440
1441 return rc;
1442 }
1443
1444 static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1445 struct x86_emulate_ops *ops, int seg)
1446 {
1447 struct decode_cache *c = &ctxt->decode;
1448
1449 c->src.val = ops->get_segment_selector(ctxt, seg);
1450
1451 return em_push(ctxt);
1452 }
1453
1454 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1455 struct x86_emulate_ops *ops, int seg)
1456 {
1457 struct decode_cache *c = &ctxt->decode;
1458 unsigned long selector;
1459 int rc;
1460
1461 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1462 if (rc != X86EMUL_CONTINUE)
1463 return rc;
1464
1465 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1466 return rc;
1467 }
1468
1469 static int emulate_pusha(struct x86_emulate_ctxt *ctxt)
1470 {
1471 struct decode_cache *c = &ctxt->decode;
1472 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1473 int rc = X86EMUL_CONTINUE;
1474 int reg = VCPU_REGS_RAX;
1475
1476 while (reg <= VCPU_REGS_RDI) {
1477 (reg == VCPU_REGS_RSP) ?
1478 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1479
1480 rc = em_push(ctxt);
1481 if (rc != X86EMUL_CONTINUE)
1482 return rc;
1483
1484 ++reg;
1485 }
1486
1487 return rc;
1488 }
1489
1490 static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1491 struct x86_emulate_ops *ops)
1492 {
1493 struct decode_cache *c = &ctxt->decode;
1494 int rc = X86EMUL_CONTINUE;
1495 int reg = VCPU_REGS_RDI;
1496
1497 while (reg >= VCPU_REGS_RAX) {
1498 if (reg == VCPU_REGS_RSP) {
1499 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1500 c->op_bytes);
1501 --reg;
1502 }
1503
1504 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1505 if (rc != X86EMUL_CONTINUE)
1506 break;
1507 --reg;
1508 }
1509 return rc;
1510 }
1511
1512 int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1513 struct x86_emulate_ops *ops, int irq)
1514 {
1515 struct decode_cache *c = &ctxt->decode;
1516 int rc;
1517 struct desc_ptr dt;
1518 gva_t cs_addr;
1519 gva_t eip_addr;
1520 u16 cs, eip;
1521
1522 /* TODO: Add limit checks */
1523 c->src.val = ctxt->eflags;
1524 rc = em_push(ctxt);
1525 if (rc != X86EMUL_CONTINUE)
1526 return rc;
1527
1528 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1529
1530 c->src.val = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
1531 rc = em_push(ctxt);
1532 if (rc != X86EMUL_CONTINUE)
1533 return rc;
1534
1535 c->src.val = c->eip;
1536 rc = em_push(ctxt);
1537 if (rc != X86EMUL_CONTINUE)
1538 return rc;
1539
1540 ops->get_idt(ctxt, &dt);
1541
1542 eip_addr = dt.address + (irq << 2);
1543 cs_addr = dt.address + (irq << 2) + 2;
1544
1545 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1546 if (rc != X86EMUL_CONTINUE)
1547 return rc;
1548
1549 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1550 if (rc != X86EMUL_CONTINUE)
1551 return rc;
1552
1553 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1554 if (rc != X86EMUL_CONTINUE)
1555 return rc;
1556
1557 c->eip = eip;
1558
1559 return rc;
1560 }
1561
1562 static int emulate_int(struct x86_emulate_ctxt *ctxt,
1563 struct x86_emulate_ops *ops, int irq)
1564 {
1565 switch(ctxt->mode) {
1566 case X86EMUL_MODE_REAL:
1567 return emulate_int_real(ctxt, ops, irq);
1568 case X86EMUL_MODE_VM86:
1569 case X86EMUL_MODE_PROT16:
1570 case X86EMUL_MODE_PROT32:
1571 case X86EMUL_MODE_PROT64:
1572 default:
1573 /* Protected mode interrupts unimplemented yet */
1574 return X86EMUL_UNHANDLEABLE;
1575 }
1576 }
1577
1578 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1579 struct x86_emulate_ops *ops)
1580 {
1581 struct decode_cache *c = &ctxt->decode;
1582 int rc = X86EMUL_CONTINUE;
1583 unsigned long temp_eip = 0;
1584 unsigned long temp_eflags = 0;
1585 unsigned long cs = 0;
1586 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1587 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1588 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1589 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1590
1591 /* TODO: Add stack limit check */
1592
1593 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1594
1595 if (rc != X86EMUL_CONTINUE)
1596 return rc;
1597
1598 if (temp_eip & ~0xffff)
1599 return emulate_gp(ctxt, 0);
1600
1601 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1602
1603 if (rc != X86EMUL_CONTINUE)
1604 return rc;
1605
1606 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1607
1608 if (rc != X86EMUL_CONTINUE)
1609 return rc;
1610
1611 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1612
1613 if (rc != X86EMUL_CONTINUE)
1614 return rc;
1615
1616 c->eip = temp_eip;
1617
1618
1619 if (c->op_bytes == 4)
1620 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1621 else if (c->op_bytes == 2) {
1622 ctxt->eflags &= ~0xffff;
1623 ctxt->eflags |= temp_eflags;
1624 }
1625
1626 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1627 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1628
1629 return rc;
1630 }
1631
1632 static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1633 struct x86_emulate_ops* ops)
1634 {
1635 switch(ctxt->mode) {
1636 case X86EMUL_MODE_REAL:
1637 return emulate_iret_real(ctxt, ops);
1638 case X86EMUL_MODE_VM86:
1639 case X86EMUL_MODE_PROT16:
1640 case X86EMUL_MODE_PROT32:
1641 case X86EMUL_MODE_PROT64:
1642 default:
1643 /* iret from protected mode unimplemented yet */
1644 return X86EMUL_UNHANDLEABLE;
1645 }
1646 }
1647
1648 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1649 struct x86_emulate_ops *ops)
1650 {
1651 struct decode_cache *c = &ctxt->decode;
1652
1653 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1654 }
1655
1656 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1657 {
1658 struct decode_cache *c = &ctxt->decode;
1659 switch (c->modrm_reg) {
1660 case 0: /* rol */
1661 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1662 break;
1663 case 1: /* ror */
1664 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1665 break;
1666 case 2: /* rcl */
1667 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1668 break;
1669 case 3: /* rcr */
1670 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1671 break;
1672 case 4: /* sal/shl */
1673 case 6: /* sal/shl */
1674 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1675 break;
1676 case 5: /* shr */
1677 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1678 break;
1679 case 7: /* sar */
1680 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1681 break;
1682 }
1683 }
1684
1685 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1686 struct x86_emulate_ops *ops)
1687 {
1688 struct decode_cache *c = &ctxt->decode;
1689 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1690 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
1691 u8 de = 0;
1692
1693 switch (c->modrm_reg) {
1694 case 0 ... 1: /* test */
1695 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1696 break;
1697 case 2: /* not */
1698 c->dst.val = ~c->dst.val;
1699 break;
1700 case 3: /* neg */
1701 emulate_1op("neg", c->dst, ctxt->eflags);
1702 break;
1703 case 4: /* mul */
1704 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1705 break;
1706 case 5: /* imul */
1707 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1708 break;
1709 case 6: /* div */
1710 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1711 ctxt->eflags, de);
1712 break;
1713 case 7: /* idiv */
1714 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1715 ctxt->eflags, de);
1716 break;
1717 default:
1718 return X86EMUL_UNHANDLEABLE;
1719 }
1720 if (de)
1721 return emulate_de(ctxt);
1722 return X86EMUL_CONTINUE;
1723 }
1724
1725 static int emulate_grp45(struct x86_emulate_ctxt *ctxt)
1726 {
1727 struct decode_cache *c = &ctxt->decode;
1728 int rc = X86EMUL_CONTINUE;
1729
1730 switch (c->modrm_reg) {
1731 case 0: /* inc */
1732 emulate_1op("inc", c->dst, ctxt->eflags);
1733 break;
1734 case 1: /* dec */
1735 emulate_1op("dec", c->dst, ctxt->eflags);
1736 break;
1737 case 2: /* call near abs */ {
1738 long int old_eip;
1739 old_eip = c->eip;
1740 c->eip = c->src.val;
1741 c->src.val = old_eip;
1742 rc = em_push(ctxt);
1743 break;
1744 }
1745 case 4: /* jmp abs */
1746 c->eip = c->src.val;
1747 break;
1748 case 6: /* push */
1749 rc = em_push(ctxt);
1750 break;
1751 }
1752 return rc;
1753 }
1754
1755 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1756 struct x86_emulate_ops *ops)
1757 {
1758 struct decode_cache *c = &ctxt->decode;
1759 u64 old = c->dst.orig_val64;
1760
1761 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1762 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1763 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1764 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1765 ctxt->eflags &= ~EFLG_ZF;
1766 } else {
1767 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1768 (u32) c->regs[VCPU_REGS_RBX];
1769
1770 ctxt->eflags |= EFLG_ZF;
1771 }
1772 return X86EMUL_CONTINUE;
1773 }
1774
1775 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1776 struct x86_emulate_ops *ops)
1777 {
1778 struct decode_cache *c = &ctxt->decode;
1779 int rc;
1780 unsigned long cs;
1781
1782 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1783 if (rc != X86EMUL_CONTINUE)
1784 return rc;
1785 if (c->op_bytes == 4)
1786 c->eip = (u32)c->eip;
1787 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1788 if (rc != X86EMUL_CONTINUE)
1789 return rc;
1790 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1791 return rc;
1792 }
1793
1794 static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1795 struct x86_emulate_ops *ops, int seg)
1796 {
1797 struct decode_cache *c = &ctxt->decode;
1798 unsigned short sel;
1799 int rc;
1800
1801 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1802
1803 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1804 if (rc != X86EMUL_CONTINUE)
1805 return rc;
1806
1807 c->dst.val = c->src.val;
1808 return rc;
1809 }
1810
1811 static inline void
1812 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1813 struct x86_emulate_ops *ops, struct desc_struct *cs,
1814 struct desc_struct *ss)
1815 {
1816 memset(cs, 0, sizeof(struct desc_struct));
1817 ops->get_cached_descriptor(ctxt, cs, NULL, VCPU_SREG_CS);
1818 memset(ss, 0, sizeof(struct desc_struct));
1819
1820 cs->l = 0; /* will be adjusted later */
1821 set_desc_base(cs, 0); /* flat segment */
1822 cs->g = 1; /* 4kb granularity */
1823 set_desc_limit(cs, 0xfffff); /* 4GB limit */
1824 cs->type = 0x0b; /* Read, Execute, Accessed */
1825 cs->s = 1;
1826 cs->dpl = 0; /* will be adjusted later */
1827 cs->p = 1;
1828 cs->d = 1;
1829
1830 set_desc_base(ss, 0); /* flat segment */
1831 set_desc_limit(ss, 0xfffff); /* 4GB limit */
1832 ss->g = 1; /* 4kb granularity */
1833 ss->s = 1;
1834 ss->type = 0x03; /* Read/Write, Accessed */
1835 ss->d = 1; /* 32bit stack segment */
1836 ss->dpl = 0;
1837 ss->p = 1;
1838 }
1839
1840 static int
1841 emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1842 {
1843 struct decode_cache *c = &ctxt->decode;
1844 struct desc_struct cs, ss;
1845 u64 msr_data;
1846 u16 cs_sel, ss_sel;
1847 u64 efer = 0;
1848
1849 /* syscall is not available in real mode */
1850 if (ctxt->mode == X86EMUL_MODE_REAL ||
1851 ctxt->mode == X86EMUL_MODE_VM86)
1852 return emulate_ud(ctxt);
1853
1854 ops->get_msr(ctxt, MSR_EFER, &efer);
1855 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1856
1857 ops->get_msr(ctxt, MSR_STAR, &msr_data);
1858 msr_data >>= 32;
1859 cs_sel = (u16)(msr_data & 0xfffc);
1860 ss_sel = (u16)(msr_data + 8);
1861
1862 if (efer & EFER_LMA) {
1863 cs.d = 0;
1864 cs.l = 1;
1865 }
1866 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1867 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1868 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1869 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
1870
1871 c->regs[VCPU_REGS_RCX] = c->eip;
1872 if (efer & EFER_LMA) {
1873 #ifdef CONFIG_X86_64
1874 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1875
1876 ops->get_msr(ctxt,
1877 ctxt->mode == X86EMUL_MODE_PROT64 ?
1878 MSR_LSTAR : MSR_CSTAR, &msr_data);
1879 c->eip = msr_data;
1880
1881 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
1882 ctxt->eflags &= ~(msr_data | EFLG_RF);
1883 #endif
1884 } else {
1885 /* legacy mode */
1886 ops->get_msr(ctxt, MSR_STAR, &msr_data);
1887 c->eip = (u32)msr_data;
1888
1889 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1890 }
1891
1892 return X86EMUL_CONTINUE;
1893 }
1894
1895 static int
1896 emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1897 {
1898 struct decode_cache *c = &ctxt->decode;
1899 struct desc_struct cs, ss;
1900 u64 msr_data;
1901 u16 cs_sel, ss_sel;
1902 u64 efer = 0;
1903
1904 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1905 /* inject #GP if in real mode */
1906 if (ctxt->mode == X86EMUL_MODE_REAL)
1907 return emulate_gp(ctxt, 0);
1908
1909 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1910 * Therefore, we inject an #UD.
1911 */
1912 if (ctxt->mode == X86EMUL_MODE_PROT64)
1913 return emulate_ud(ctxt);
1914
1915 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1916
1917 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
1918 switch (ctxt->mode) {
1919 case X86EMUL_MODE_PROT32:
1920 if ((msr_data & 0xfffc) == 0x0)
1921 return emulate_gp(ctxt, 0);
1922 break;
1923 case X86EMUL_MODE_PROT64:
1924 if (msr_data == 0x0)
1925 return emulate_gp(ctxt, 0);
1926 break;
1927 }
1928
1929 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1930 cs_sel = (u16)msr_data;
1931 cs_sel &= ~SELECTOR_RPL_MASK;
1932 ss_sel = cs_sel + 8;
1933 ss_sel &= ~SELECTOR_RPL_MASK;
1934 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
1935 cs.d = 0;
1936 cs.l = 1;
1937 }
1938
1939 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1940 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1941 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1942 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
1943
1944 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
1945 c->eip = msr_data;
1946
1947 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
1948 c->regs[VCPU_REGS_RSP] = msr_data;
1949
1950 return X86EMUL_CONTINUE;
1951 }
1952
1953 static int
1954 emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1955 {
1956 struct decode_cache *c = &ctxt->decode;
1957 struct desc_struct cs, ss;
1958 u64 msr_data;
1959 int usermode;
1960 u16 cs_sel, ss_sel;
1961
1962 /* inject #GP if in real mode or Virtual 8086 mode */
1963 if (ctxt->mode == X86EMUL_MODE_REAL ||
1964 ctxt->mode == X86EMUL_MODE_VM86)
1965 return emulate_gp(ctxt, 0);
1966
1967 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1968
1969 if ((c->rex_prefix & 0x8) != 0x0)
1970 usermode = X86EMUL_MODE_PROT64;
1971 else
1972 usermode = X86EMUL_MODE_PROT32;
1973
1974 cs.dpl = 3;
1975 ss.dpl = 3;
1976 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
1977 switch (usermode) {
1978 case X86EMUL_MODE_PROT32:
1979 cs_sel = (u16)(msr_data + 16);
1980 if ((msr_data & 0xfffc) == 0x0)
1981 return emulate_gp(ctxt, 0);
1982 ss_sel = (u16)(msr_data + 24);
1983 break;
1984 case X86EMUL_MODE_PROT64:
1985 cs_sel = (u16)(msr_data + 32);
1986 if (msr_data == 0x0)
1987 return emulate_gp(ctxt, 0);
1988 ss_sel = cs_sel + 8;
1989 cs.d = 0;
1990 cs.l = 1;
1991 break;
1992 }
1993 cs_sel |= SELECTOR_RPL_MASK;
1994 ss_sel |= SELECTOR_RPL_MASK;
1995
1996 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1997 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1998 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1999 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
2000
2001 c->eip = c->regs[VCPU_REGS_RDX];
2002 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
2003
2004 return X86EMUL_CONTINUE;
2005 }
2006
2007 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2008 struct x86_emulate_ops *ops)
2009 {
2010 int iopl;
2011 if (ctxt->mode == X86EMUL_MODE_REAL)
2012 return false;
2013 if (ctxt->mode == X86EMUL_MODE_VM86)
2014 return true;
2015 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2016 return ops->cpl(ctxt) > iopl;
2017 }
2018
2019 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2020 struct x86_emulate_ops *ops,
2021 u16 port, u16 len)
2022 {
2023 struct desc_struct tr_seg;
2024 u32 base3;
2025 int r;
2026 u16 io_bitmap_ptr, perm, bit_idx = port & 0x7;
2027 unsigned mask = (1 << len) - 1;
2028 unsigned long base;
2029
2030 ops->get_cached_descriptor(ctxt, &tr_seg, &base3, VCPU_SREG_TR);
2031 if (!tr_seg.p)
2032 return false;
2033 if (desc_limit_scaled(&tr_seg) < 103)
2034 return false;
2035 base = get_desc_base(&tr_seg);
2036 #ifdef CONFIG_X86_64
2037 base |= ((u64)base3) << 32;
2038 #endif
2039 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2040 if (r != X86EMUL_CONTINUE)
2041 return false;
2042 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2043 return false;
2044 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2045 if (r != X86EMUL_CONTINUE)
2046 return false;
2047 if ((perm >> bit_idx) & mask)
2048 return false;
2049 return true;
2050 }
2051
2052 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2053 struct x86_emulate_ops *ops,
2054 u16 port, u16 len)
2055 {
2056 if (ctxt->perm_ok)
2057 return true;
2058
2059 if (emulator_bad_iopl(ctxt, ops))
2060 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2061 return false;
2062
2063 ctxt->perm_ok = true;
2064
2065 return true;
2066 }
2067
2068 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2069 struct x86_emulate_ops *ops,
2070 struct tss_segment_16 *tss)
2071 {
2072 struct decode_cache *c = &ctxt->decode;
2073
2074 tss->ip = c->eip;
2075 tss->flag = ctxt->eflags;
2076 tss->ax = c->regs[VCPU_REGS_RAX];
2077 tss->cx = c->regs[VCPU_REGS_RCX];
2078 tss->dx = c->regs[VCPU_REGS_RDX];
2079 tss->bx = c->regs[VCPU_REGS_RBX];
2080 tss->sp = c->regs[VCPU_REGS_RSP];
2081 tss->bp = c->regs[VCPU_REGS_RBP];
2082 tss->si = c->regs[VCPU_REGS_RSI];
2083 tss->di = c->regs[VCPU_REGS_RDI];
2084
2085 tss->es = ops->get_segment_selector(ctxt, VCPU_SREG_ES);
2086 tss->cs = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2087 tss->ss = ops->get_segment_selector(ctxt, VCPU_SREG_SS);
2088 tss->ds = ops->get_segment_selector(ctxt, VCPU_SREG_DS);
2089 tss->ldt = ops->get_segment_selector(ctxt, VCPU_SREG_LDTR);
2090 }
2091
2092 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2093 struct x86_emulate_ops *ops,
2094 struct tss_segment_16 *tss)
2095 {
2096 struct decode_cache *c = &ctxt->decode;
2097 int ret;
2098
2099 c->eip = tss->ip;
2100 ctxt->eflags = tss->flag | 2;
2101 c->regs[VCPU_REGS_RAX] = tss->ax;
2102 c->regs[VCPU_REGS_RCX] = tss->cx;
2103 c->regs[VCPU_REGS_RDX] = tss->dx;
2104 c->regs[VCPU_REGS_RBX] = tss->bx;
2105 c->regs[VCPU_REGS_RSP] = tss->sp;
2106 c->regs[VCPU_REGS_RBP] = tss->bp;
2107 c->regs[VCPU_REGS_RSI] = tss->si;
2108 c->regs[VCPU_REGS_RDI] = tss->di;
2109
2110 /*
2111 * SDM says that segment selectors are loaded before segment
2112 * descriptors
2113 */
2114 ops->set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2115 ops->set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2116 ops->set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2117 ops->set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2118 ops->set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2119
2120 /*
2121 * Now load segment descriptors. If fault happenes at this stage
2122 * it is handled in a context of new task
2123 */
2124 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2125 if (ret != X86EMUL_CONTINUE)
2126 return ret;
2127 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2128 if (ret != X86EMUL_CONTINUE)
2129 return ret;
2130 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2131 if (ret != X86EMUL_CONTINUE)
2132 return ret;
2133 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2134 if (ret != X86EMUL_CONTINUE)
2135 return ret;
2136 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2137 if (ret != X86EMUL_CONTINUE)
2138 return ret;
2139
2140 return X86EMUL_CONTINUE;
2141 }
2142
2143 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2144 struct x86_emulate_ops *ops,
2145 u16 tss_selector, u16 old_tss_sel,
2146 ulong old_tss_base, struct desc_struct *new_desc)
2147 {
2148 struct tss_segment_16 tss_seg;
2149 int ret;
2150 u32 new_tss_base = get_desc_base(new_desc);
2151
2152 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2153 &ctxt->exception);
2154 if (ret != X86EMUL_CONTINUE)
2155 /* FIXME: need to provide precise fault address */
2156 return ret;
2157
2158 save_state_to_tss16(ctxt, ops, &tss_seg);
2159
2160 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2161 &ctxt->exception);
2162 if (ret != X86EMUL_CONTINUE)
2163 /* FIXME: need to provide precise fault address */
2164 return ret;
2165
2166 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2167 &ctxt->exception);
2168 if (ret != X86EMUL_CONTINUE)
2169 /* FIXME: need to provide precise fault address */
2170 return ret;
2171
2172 if (old_tss_sel != 0xffff) {
2173 tss_seg.prev_task_link = old_tss_sel;
2174
2175 ret = ops->write_std(ctxt, new_tss_base,
2176 &tss_seg.prev_task_link,
2177 sizeof tss_seg.prev_task_link,
2178 &ctxt->exception);
2179 if (ret != X86EMUL_CONTINUE)
2180 /* FIXME: need to provide precise fault address */
2181 return ret;
2182 }
2183
2184 return load_state_from_tss16(ctxt, ops, &tss_seg);
2185 }
2186
2187 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2188 struct x86_emulate_ops *ops,
2189 struct tss_segment_32 *tss)
2190 {
2191 struct decode_cache *c = &ctxt->decode;
2192
2193 tss->cr3 = ops->get_cr(ctxt, 3);
2194 tss->eip = c->eip;
2195 tss->eflags = ctxt->eflags;
2196 tss->eax = c->regs[VCPU_REGS_RAX];
2197 tss->ecx = c->regs[VCPU_REGS_RCX];
2198 tss->edx = c->regs[VCPU_REGS_RDX];
2199 tss->ebx = c->regs[VCPU_REGS_RBX];
2200 tss->esp = c->regs[VCPU_REGS_RSP];
2201 tss->ebp = c->regs[VCPU_REGS_RBP];
2202 tss->esi = c->regs[VCPU_REGS_RSI];
2203 tss->edi = c->regs[VCPU_REGS_RDI];
2204
2205 tss->es = ops->get_segment_selector(ctxt, VCPU_SREG_ES);
2206 tss->cs = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2207 tss->ss = ops->get_segment_selector(ctxt, VCPU_SREG_SS);
2208 tss->ds = ops->get_segment_selector(ctxt, VCPU_SREG_DS);
2209 tss->fs = ops->get_segment_selector(ctxt, VCPU_SREG_FS);
2210 tss->gs = ops->get_segment_selector(ctxt, VCPU_SREG_GS);
2211 tss->ldt_selector = ops->get_segment_selector(ctxt, VCPU_SREG_LDTR);
2212 }
2213
2214 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2215 struct x86_emulate_ops *ops,
2216 struct tss_segment_32 *tss)
2217 {
2218 struct decode_cache *c = &ctxt->decode;
2219 int ret;
2220
2221 if (ops->set_cr(ctxt, 3, tss->cr3))
2222 return emulate_gp(ctxt, 0);
2223 c->eip = tss->eip;
2224 ctxt->eflags = tss->eflags | 2;
2225 c->regs[VCPU_REGS_RAX] = tss->eax;
2226 c->regs[VCPU_REGS_RCX] = tss->ecx;
2227 c->regs[VCPU_REGS_RDX] = tss->edx;
2228 c->regs[VCPU_REGS_RBX] = tss->ebx;
2229 c->regs[VCPU_REGS_RSP] = tss->esp;
2230 c->regs[VCPU_REGS_RBP] = tss->ebp;
2231 c->regs[VCPU_REGS_RSI] = tss->esi;
2232 c->regs[VCPU_REGS_RDI] = tss->edi;
2233
2234 /*
2235 * SDM says that segment selectors are loaded before segment
2236 * descriptors
2237 */
2238 ops->set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2239 ops->set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2240 ops->set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2241 ops->set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2242 ops->set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2243 ops->set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2244 ops->set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2245
2246 /*
2247 * Now load segment descriptors. If fault happenes at this stage
2248 * it is handled in a context of new task
2249 */
2250 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2251 if (ret != X86EMUL_CONTINUE)
2252 return ret;
2253 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2254 if (ret != X86EMUL_CONTINUE)
2255 return ret;
2256 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2257 if (ret != X86EMUL_CONTINUE)
2258 return ret;
2259 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2260 if (ret != X86EMUL_CONTINUE)
2261 return ret;
2262 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2263 if (ret != X86EMUL_CONTINUE)
2264 return ret;
2265 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2266 if (ret != X86EMUL_CONTINUE)
2267 return ret;
2268 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2269 if (ret != X86EMUL_CONTINUE)
2270 return ret;
2271
2272 return X86EMUL_CONTINUE;
2273 }
2274
2275 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2276 struct x86_emulate_ops *ops,
2277 u16 tss_selector, u16 old_tss_sel,
2278 ulong old_tss_base, struct desc_struct *new_desc)
2279 {
2280 struct tss_segment_32 tss_seg;
2281 int ret;
2282 u32 new_tss_base = get_desc_base(new_desc);
2283
2284 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2285 &ctxt->exception);
2286 if (ret != X86EMUL_CONTINUE)
2287 /* FIXME: need to provide precise fault address */
2288 return ret;
2289
2290 save_state_to_tss32(ctxt, ops, &tss_seg);
2291
2292 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2293 &ctxt->exception);
2294 if (ret != X86EMUL_CONTINUE)
2295 /* FIXME: need to provide precise fault address */
2296 return ret;
2297
2298 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2299 &ctxt->exception);
2300 if (ret != X86EMUL_CONTINUE)
2301 /* FIXME: need to provide precise fault address */
2302 return ret;
2303
2304 if (old_tss_sel != 0xffff) {
2305 tss_seg.prev_task_link = old_tss_sel;
2306
2307 ret = ops->write_std(ctxt, new_tss_base,
2308 &tss_seg.prev_task_link,
2309 sizeof tss_seg.prev_task_link,
2310 &ctxt->exception);
2311 if (ret != X86EMUL_CONTINUE)
2312 /* FIXME: need to provide precise fault address */
2313 return ret;
2314 }
2315
2316 return load_state_from_tss32(ctxt, ops, &tss_seg);
2317 }
2318
2319 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2320 struct x86_emulate_ops *ops,
2321 u16 tss_selector, int reason,
2322 bool has_error_code, u32 error_code)
2323 {
2324 struct desc_struct curr_tss_desc, next_tss_desc;
2325 int ret;
2326 u16 old_tss_sel = ops->get_segment_selector(ctxt, VCPU_SREG_TR);
2327 ulong old_tss_base =
2328 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2329 u32 desc_limit;
2330
2331 /* FIXME: old_tss_base == ~0 ? */
2332
2333 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2334 if (ret != X86EMUL_CONTINUE)
2335 return ret;
2336 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2337 if (ret != X86EMUL_CONTINUE)
2338 return ret;
2339
2340 /* FIXME: check that next_tss_desc is tss */
2341
2342 if (reason != TASK_SWITCH_IRET) {
2343 if ((tss_selector & 3) > next_tss_desc.dpl ||
2344 ops->cpl(ctxt) > next_tss_desc.dpl)
2345 return emulate_gp(ctxt, 0);
2346 }
2347
2348 desc_limit = desc_limit_scaled(&next_tss_desc);
2349 if (!next_tss_desc.p ||
2350 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2351 desc_limit < 0x2b)) {
2352 emulate_ts(ctxt, tss_selector & 0xfffc);
2353 return X86EMUL_PROPAGATE_FAULT;
2354 }
2355
2356 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2357 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2358 write_segment_descriptor(ctxt, ops, old_tss_sel,
2359 &curr_tss_desc);
2360 }
2361
2362 if (reason == TASK_SWITCH_IRET)
2363 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2364
2365 /* set back link to prev task only if NT bit is set in eflags
2366 note that old_tss_sel is not used afetr this point */
2367 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2368 old_tss_sel = 0xffff;
2369
2370 if (next_tss_desc.type & 8)
2371 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2372 old_tss_base, &next_tss_desc);
2373 else
2374 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2375 old_tss_base, &next_tss_desc);
2376 if (ret != X86EMUL_CONTINUE)
2377 return ret;
2378
2379 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2380 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2381
2382 if (reason != TASK_SWITCH_IRET) {
2383 next_tss_desc.type |= (1 << 1); /* set busy flag */
2384 write_segment_descriptor(ctxt, ops, tss_selector,
2385 &next_tss_desc);
2386 }
2387
2388 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
2389 ops->set_cached_descriptor(ctxt, &next_tss_desc, 0, VCPU_SREG_TR);
2390 ops->set_segment_selector(ctxt, tss_selector, VCPU_SREG_TR);
2391
2392 if (has_error_code) {
2393 struct decode_cache *c = &ctxt->decode;
2394
2395 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2396 c->lock_prefix = 0;
2397 c->src.val = (unsigned long) error_code;
2398 ret = em_push(ctxt);
2399 }
2400
2401 return ret;
2402 }
2403
2404 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2405 u16 tss_selector, int reason,
2406 bool has_error_code, u32 error_code)
2407 {
2408 struct x86_emulate_ops *ops = ctxt->ops;
2409 struct decode_cache *c = &ctxt->decode;
2410 int rc;
2411
2412 c->eip = ctxt->eip;
2413 c->dst.type = OP_NONE;
2414
2415 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2416 has_error_code, error_code);
2417
2418 if (rc == X86EMUL_CONTINUE)
2419 ctxt->eip = c->eip;
2420
2421 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2422 }
2423
2424 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
2425 int reg, struct operand *op)
2426 {
2427 struct decode_cache *c = &ctxt->decode;
2428 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2429
2430 register_address_increment(c, &c->regs[reg], df * op->bytes);
2431 op->addr.mem.ea = register_address(c, c->regs[reg]);
2432 op->addr.mem.seg = seg;
2433 }
2434
2435 static int em_das(struct x86_emulate_ctxt *ctxt)
2436 {
2437 struct decode_cache *c = &ctxt->decode;
2438 u8 al, old_al;
2439 bool af, cf, old_cf;
2440
2441 cf = ctxt->eflags & X86_EFLAGS_CF;
2442 al = c->dst.val;
2443
2444 old_al = al;
2445 old_cf = cf;
2446 cf = false;
2447 af = ctxt->eflags & X86_EFLAGS_AF;
2448 if ((al & 0x0f) > 9 || af) {
2449 al -= 6;
2450 cf = old_cf | (al >= 250);
2451 af = true;
2452 } else {
2453 af = false;
2454 }
2455 if (old_al > 0x99 || old_cf) {
2456 al -= 0x60;
2457 cf = true;
2458 }
2459
2460 c->dst.val = al;
2461 /* Set PF, ZF, SF */
2462 c->src.type = OP_IMM;
2463 c->src.val = 0;
2464 c->src.bytes = 1;
2465 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2466 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2467 if (cf)
2468 ctxt->eflags |= X86_EFLAGS_CF;
2469 if (af)
2470 ctxt->eflags |= X86_EFLAGS_AF;
2471 return X86EMUL_CONTINUE;
2472 }
2473
2474 static int em_call_far(struct x86_emulate_ctxt *ctxt)
2475 {
2476 struct decode_cache *c = &ctxt->decode;
2477 u16 sel, old_cs;
2478 ulong old_eip;
2479 int rc;
2480
2481 old_cs = ctxt->ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2482 old_eip = c->eip;
2483
2484 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2485 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2486 return X86EMUL_CONTINUE;
2487
2488 c->eip = 0;
2489 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2490
2491 c->src.val = old_cs;
2492 rc = em_push(ctxt);
2493 if (rc != X86EMUL_CONTINUE)
2494 return rc;
2495
2496 c->src.val = old_eip;
2497 return em_push(ctxt);
2498 }
2499
2500 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2501 {
2502 struct decode_cache *c = &ctxt->decode;
2503 int rc;
2504
2505 c->dst.type = OP_REG;
2506 c->dst.addr.reg = &c->eip;
2507 c->dst.bytes = c->op_bytes;
2508 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2509 if (rc != X86EMUL_CONTINUE)
2510 return rc;
2511 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2512 return X86EMUL_CONTINUE;
2513 }
2514
2515 static int em_imul(struct x86_emulate_ctxt *ctxt)
2516 {
2517 struct decode_cache *c = &ctxt->decode;
2518
2519 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2520 return X86EMUL_CONTINUE;
2521 }
2522
2523 static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2524 {
2525 struct decode_cache *c = &ctxt->decode;
2526
2527 c->dst.val = c->src2.val;
2528 return em_imul(ctxt);
2529 }
2530
2531 static int em_cwd(struct x86_emulate_ctxt *ctxt)
2532 {
2533 struct decode_cache *c = &ctxt->decode;
2534
2535 c->dst.type = OP_REG;
2536 c->dst.bytes = c->src.bytes;
2537 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2538 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2539
2540 return X86EMUL_CONTINUE;
2541 }
2542
2543 static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2544 {
2545 struct decode_cache *c = &ctxt->decode;
2546 u64 tsc = 0;
2547
2548 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
2549 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2550 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2551 return X86EMUL_CONTINUE;
2552 }
2553
2554 static int em_mov(struct x86_emulate_ctxt *ctxt)
2555 {
2556 struct decode_cache *c = &ctxt->decode;
2557 c->dst.val = c->src.val;
2558 return X86EMUL_CONTINUE;
2559 }
2560
2561 static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2562 {
2563 struct decode_cache *c = &ctxt->decode;
2564 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2565 return X86EMUL_CONTINUE;
2566 }
2567
2568 static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2569 {
2570 struct decode_cache *c = &ctxt->decode;
2571 int rc;
2572 ulong linear;
2573
2574 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
2575 if (rc == X86EMUL_CONTINUE)
2576 ctxt->ops->invlpg(ctxt, linear);
2577 /* Disable writeback. */
2578 c->dst.type = OP_NONE;
2579 return X86EMUL_CONTINUE;
2580 }
2581
2582 static int em_clts(struct x86_emulate_ctxt *ctxt)
2583 {
2584 ulong cr0;
2585
2586 cr0 = ctxt->ops->get_cr(ctxt, 0);
2587 cr0 &= ~X86_CR0_TS;
2588 ctxt->ops->set_cr(ctxt, 0, cr0);
2589 return X86EMUL_CONTINUE;
2590 }
2591
2592 static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2593 {
2594 struct decode_cache *c = &ctxt->decode;
2595 int rc;
2596
2597 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2598 return X86EMUL_UNHANDLEABLE;
2599
2600 rc = ctxt->ops->fix_hypercall(ctxt);
2601 if (rc != X86EMUL_CONTINUE)
2602 return rc;
2603
2604 /* Let the processor re-execute the fixed hypercall */
2605 c->eip = ctxt->eip;
2606 /* Disable writeback. */
2607 c->dst.type = OP_NONE;
2608 return X86EMUL_CONTINUE;
2609 }
2610
2611 static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2612 {
2613 struct decode_cache *c = &ctxt->decode;
2614 struct desc_ptr desc_ptr;
2615 int rc;
2616
2617 rc = read_descriptor(ctxt, ctxt->ops, c->src.addr.mem,
2618 &desc_ptr.size, &desc_ptr.address,
2619 c->op_bytes);
2620 if (rc != X86EMUL_CONTINUE)
2621 return rc;
2622 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2623 /* Disable writeback. */
2624 c->dst.type = OP_NONE;
2625 return X86EMUL_CONTINUE;
2626 }
2627
2628 static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
2629 {
2630 struct decode_cache *c = &ctxt->decode;
2631 int rc;
2632
2633 rc = ctxt->ops->fix_hypercall(ctxt);
2634
2635 /* Disable writeback. */
2636 c->dst.type = OP_NONE;
2637 return rc;
2638 }
2639
2640 static int em_lidt(struct x86_emulate_ctxt *ctxt)
2641 {
2642 struct decode_cache *c = &ctxt->decode;
2643 struct desc_ptr desc_ptr;
2644 int rc;
2645
2646 rc = read_descriptor(ctxt, ctxt->ops, c->src.addr.mem,
2647 &desc_ptr.size,
2648 &desc_ptr.address,
2649 c->op_bytes);
2650 if (rc != X86EMUL_CONTINUE)
2651 return rc;
2652 ctxt->ops->set_idt(ctxt, &desc_ptr);
2653 /* Disable writeback. */
2654 c->dst.type = OP_NONE;
2655 return X86EMUL_CONTINUE;
2656 }
2657
2658 static int em_smsw(struct x86_emulate_ctxt *ctxt)
2659 {
2660 struct decode_cache *c = &ctxt->decode;
2661
2662 c->dst.bytes = 2;
2663 c->dst.val = ctxt->ops->get_cr(ctxt, 0);
2664 return X86EMUL_CONTINUE;
2665 }
2666
2667 static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2668 {
2669 struct decode_cache *c = &ctxt->decode;
2670 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
2671 | (c->src.val & 0x0f));
2672 c->dst.type = OP_NONE;
2673 return X86EMUL_CONTINUE;
2674 }
2675
2676 static bool valid_cr(int nr)
2677 {
2678 switch (nr) {
2679 case 0:
2680 case 2 ... 4:
2681 case 8:
2682 return true;
2683 default:
2684 return false;
2685 }
2686 }
2687
2688 static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2689 {
2690 struct decode_cache *c = &ctxt->decode;
2691
2692 if (!valid_cr(c->modrm_reg))
2693 return emulate_ud(ctxt);
2694
2695 return X86EMUL_CONTINUE;
2696 }
2697
2698 static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2699 {
2700 struct decode_cache *c = &ctxt->decode;
2701 u64 new_val = c->src.val64;
2702 int cr = c->modrm_reg;
2703 u64 efer = 0;
2704
2705 static u64 cr_reserved_bits[] = {
2706 0xffffffff00000000ULL,
2707 0, 0, 0, /* CR3 checked later */
2708 CR4_RESERVED_BITS,
2709 0, 0, 0,
2710 CR8_RESERVED_BITS,
2711 };
2712
2713 if (!valid_cr(cr))
2714 return emulate_ud(ctxt);
2715
2716 if (new_val & cr_reserved_bits[cr])
2717 return emulate_gp(ctxt, 0);
2718
2719 switch (cr) {
2720 case 0: {
2721 u64 cr4;
2722 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2723 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2724 return emulate_gp(ctxt, 0);
2725
2726 cr4 = ctxt->ops->get_cr(ctxt, 4);
2727 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2728
2729 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2730 !(cr4 & X86_CR4_PAE))
2731 return emulate_gp(ctxt, 0);
2732
2733 break;
2734 }
2735 case 3: {
2736 u64 rsvd = 0;
2737
2738 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2739 if (efer & EFER_LMA)
2740 rsvd = CR3_L_MODE_RESERVED_BITS;
2741 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
2742 rsvd = CR3_PAE_RESERVED_BITS;
2743 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
2744 rsvd = CR3_NONPAE_RESERVED_BITS;
2745
2746 if (new_val & rsvd)
2747 return emulate_gp(ctxt, 0);
2748
2749 break;
2750 }
2751 case 4: {
2752 u64 cr4;
2753
2754 cr4 = ctxt->ops->get_cr(ctxt, 4);
2755 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2756
2757 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2758 return emulate_gp(ctxt, 0);
2759
2760 break;
2761 }
2762 }
2763
2764 return X86EMUL_CONTINUE;
2765 }
2766
2767 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2768 {
2769 unsigned long dr7;
2770
2771 ctxt->ops->get_dr(ctxt, 7, &dr7);
2772
2773 /* Check if DR7.Global_Enable is set */
2774 return dr7 & (1 << 13);
2775 }
2776
2777 static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2778 {
2779 struct decode_cache *c = &ctxt->decode;
2780 int dr = c->modrm_reg;
2781 u64 cr4;
2782
2783 if (dr > 7)
2784 return emulate_ud(ctxt);
2785
2786 cr4 = ctxt->ops->get_cr(ctxt, 4);
2787 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2788 return emulate_ud(ctxt);
2789
2790 if (check_dr7_gd(ctxt))
2791 return emulate_db(ctxt);
2792
2793 return X86EMUL_CONTINUE;
2794 }
2795
2796 static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2797 {
2798 struct decode_cache *c = &ctxt->decode;
2799 u64 new_val = c->src.val64;
2800 int dr = c->modrm_reg;
2801
2802 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2803 return emulate_gp(ctxt, 0);
2804
2805 return check_dr_read(ctxt);
2806 }
2807
2808 static int check_svme(struct x86_emulate_ctxt *ctxt)
2809 {
2810 u64 efer;
2811
2812 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2813
2814 if (!(efer & EFER_SVME))
2815 return emulate_ud(ctxt);
2816
2817 return X86EMUL_CONTINUE;
2818 }
2819
2820 static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2821 {
2822 u64 rax = ctxt->decode.regs[VCPU_REGS_RAX];
2823
2824 /* Valid physical address? */
2825 if (rax & 0xffff000000000000ULL)
2826 return emulate_gp(ctxt, 0);
2827
2828 return check_svme(ctxt);
2829 }
2830
2831 static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2832 {
2833 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2834
2835 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
2836 return emulate_ud(ctxt);
2837
2838 return X86EMUL_CONTINUE;
2839 }
2840
2841 static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2842 {
2843 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2844 u64 rcx = ctxt->decode.regs[VCPU_REGS_RCX];
2845
2846 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
2847 (rcx > 3))
2848 return emulate_gp(ctxt, 0);
2849
2850 return X86EMUL_CONTINUE;
2851 }
2852
2853 static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2854 {
2855 struct decode_cache *c = &ctxt->decode;
2856
2857 c->dst.bytes = min(c->dst.bytes, 4u);
2858 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2859 return emulate_gp(ctxt, 0);
2860
2861 return X86EMUL_CONTINUE;
2862 }
2863
2864 static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2865 {
2866 struct decode_cache *c = &ctxt->decode;
2867
2868 c->src.bytes = min(c->src.bytes, 4u);
2869 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2870 return emulate_gp(ctxt, 0);
2871
2872 return X86EMUL_CONTINUE;
2873 }
2874
2875 #define D(_y) { .flags = (_y) }
2876 #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
2877 #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2878 .check_perm = (_p) }
2879 #define N D(0)
2880 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
2881 #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2882 #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2883 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2884 #define II(_f, _e, _i) \
2885 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
2886 #define IIP(_f, _e, _i, _p) \
2887 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2888 .check_perm = (_p) }
2889 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
2890
2891 #define D2bv(_f) D((_f) | ByteOp), D(_f)
2892 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
2893 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2894
2895 #define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2896 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2897 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2898
2899 static struct opcode group7_rm1[] = {
2900 DI(SrcNone | ModRM | Priv, monitor),
2901 DI(SrcNone | ModRM | Priv, mwait),
2902 N, N, N, N, N, N,
2903 };
2904
2905 static struct opcode group7_rm3[] = {
2906 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
2907 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
2908 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
2909 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
2910 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
2911 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
2912 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
2913 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
2914 };
2915
2916 static struct opcode group7_rm7[] = {
2917 N,
2918 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
2919 N, N, N, N, N, N,
2920 };
2921 static struct opcode group1[] = {
2922 X7(D(Lock)), N
2923 };
2924
2925 static struct opcode group1A[] = {
2926 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2927 };
2928
2929 static struct opcode group3[] = {
2930 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2931 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2932 X4(D(SrcMem | ModRM)),
2933 };
2934
2935 static struct opcode group4[] = {
2936 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2937 N, N, N, N, N, N,
2938 };
2939
2940 static struct opcode group5[] = {
2941 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2942 D(SrcMem | ModRM | Stack),
2943 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
2944 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2945 D(SrcMem | ModRM | Stack), N,
2946 };
2947
2948 static struct opcode group6[] = {
2949 DI(ModRM | Prot, sldt),
2950 DI(ModRM | Prot, str),
2951 DI(ModRM | Prot | Priv, lldt),
2952 DI(ModRM | Prot | Priv, ltr),
2953 N, N, N, N,
2954 };
2955
2956 static struct group_dual group7 = { {
2957 DI(ModRM | Mov | DstMem | Priv, sgdt),
2958 DI(ModRM | Mov | DstMem | Priv, sidt),
2959 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
2960 II(ModRM | SrcMem | Priv, em_lidt, lidt),
2961 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
2962 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
2963 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
2964 }, {
2965 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
2966 EXT(0, group7_rm1),
2967 N, EXT(0, group7_rm3),
2968 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
2969 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
2970 } };
2971
2972 static struct opcode group8[] = {
2973 N, N, N, N,
2974 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2975 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2976 };
2977
2978 static struct group_dual group9 = { {
2979 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2980 }, {
2981 N, N, N, N, N, N, N, N,
2982 } };
2983
2984 static struct opcode group11[] = {
2985 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2986 };
2987
2988 static struct gprefix pfx_0f_6f_0f_7f = {
2989 N, N, N, I(Sse, em_movdqu),
2990 };
2991
2992 static struct opcode opcode_table[256] = {
2993 /* 0x00 - 0x07 */
2994 D6ALU(Lock),
2995 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2996 /* 0x08 - 0x0F */
2997 D6ALU(Lock),
2998 D(ImplicitOps | Stack | No64), N,
2999 /* 0x10 - 0x17 */
3000 D6ALU(Lock),
3001 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3002 /* 0x18 - 0x1F */
3003 D6ALU(Lock),
3004 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3005 /* 0x20 - 0x27 */
3006 D6ALU(Lock), N, N,
3007 /* 0x28 - 0x2F */
3008 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
3009 /* 0x30 - 0x37 */
3010 D6ALU(Lock), N, N,
3011 /* 0x38 - 0x3F */
3012 D6ALU(0), N, N,
3013 /* 0x40 - 0x4F */
3014 X16(D(DstReg)),
3015 /* 0x50 - 0x57 */
3016 X8(I(SrcReg | Stack, em_push)),
3017 /* 0x58 - 0x5F */
3018 X8(D(DstReg | Stack)),
3019 /* 0x60 - 0x67 */
3020 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3021 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3022 N, N, N, N,
3023 /* 0x68 - 0x6F */
3024 I(SrcImm | Mov | Stack, em_push),
3025 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3026 I(SrcImmByte | Mov | Stack, em_push),
3027 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3028 D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3029 D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
3030 /* 0x70 - 0x7F */
3031 X16(D(SrcImmByte)),
3032 /* 0x80 - 0x87 */
3033 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3034 G(DstMem | SrcImm | ModRM | Group, group1),
3035 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3036 G(DstMem | SrcImmByte | ModRM | Group, group1),
3037 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
3038 /* 0x88 - 0x8F */
3039 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3040 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3041 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
3042 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
3043 /* 0x90 - 0x97 */
3044 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3045 /* 0x98 - 0x9F */
3046 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3047 I(SrcImmFAddr | No64, em_call_far), N,
3048 DI(ImplicitOps | Stack, pushf), DI(ImplicitOps | Stack, popf), N, N,
3049 /* 0xA0 - 0xA7 */
3050 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3051 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3052 I2bv(SrcSI | DstDI | Mov | String, em_mov),
3053 D2bv(SrcSI | DstDI | String),
3054 /* 0xA8 - 0xAF */
3055 D2bv(DstAcc | SrcImm),
3056 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3057 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3058 D2bv(SrcAcc | DstDI | String),
3059 /* 0xB0 - 0xB7 */
3060 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3061 /* 0xB8 - 0xBF */
3062 X8(I(DstReg | SrcImm | Mov, em_mov)),
3063 /* 0xC0 - 0xC7 */
3064 D2bv(DstMem | SrcImmByte | ModRM),
3065 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3066 D(ImplicitOps | Stack),
3067 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
3068 G(ByteOp, group11), G(0, group11),
3069 /* 0xC8 - 0xCF */
3070 N, N, N, D(ImplicitOps | Stack),
3071 D(ImplicitOps), DI(SrcImmByte, intn),
3072 D(ImplicitOps | No64), DI(ImplicitOps, iret),
3073 /* 0xD0 - 0xD7 */
3074 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
3075 N, N, N, N,
3076 /* 0xD8 - 0xDF */
3077 N, N, N, N, N, N, N, N,
3078 /* 0xE0 - 0xE7 */
3079 X4(D(SrcImmByte)),
3080 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3081 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
3082 /* 0xE8 - 0xEF */
3083 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
3084 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
3085 D2bvIP(SrcNone | DstAcc, in, check_perm_in),
3086 D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
3087 /* 0xF0 - 0xF7 */
3088 N, DI(ImplicitOps, icebp), N, N,
3089 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3090 G(ByteOp, group3), G(0, group3),
3091 /* 0xF8 - 0xFF */
3092 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
3093 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3094 };
3095
3096 static struct opcode twobyte_table[256] = {
3097 /* 0x00 - 0x0F */
3098 G(0, group6), GD(0, &group7), N, N,
3099 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
3100 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3101 N, D(ImplicitOps | ModRM), N, N,
3102 /* 0x10 - 0x1F */
3103 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3104 /* 0x20 - 0x2F */
3105 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3106 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
3107 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3108 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
3109 N, N, N, N,
3110 N, N, N, N, N, N, N, N,
3111 /* 0x30 - 0x3F */
3112 DI(ImplicitOps | Priv, wrmsr),
3113 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3114 DI(ImplicitOps | Priv, rdmsr),
3115 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
3116 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
3117 N, N,
3118 N, N, N, N, N, N, N, N,
3119 /* 0x40 - 0x4F */
3120 X16(D(DstReg | SrcMem | ModRM | Mov)),
3121 /* 0x50 - 0x5F */
3122 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3123 /* 0x60 - 0x6F */
3124 N, N, N, N,
3125 N, N, N, N,
3126 N, N, N, N,
3127 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
3128 /* 0x70 - 0x7F */
3129 N, N, N, N,
3130 N, N, N, N,
3131 N, N, N, N,
3132 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
3133 /* 0x80 - 0x8F */
3134 X16(D(SrcImm)),
3135 /* 0x90 - 0x9F */
3136 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
3137 /* 0xA0 - 0xA7 */
3138 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3139 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
3140 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3141 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3142 /* 0xA8 - 0xAF */
3143 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3144 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3145 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3146 D(DstMem | SrcReg | Src2CL | ModRM),
3147 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
3148 /* 0xB0 - 0xB7 */
3149 D2bv(DstMem | SrcReg | ModRM | Lock),
3150 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3151 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3152 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3153 /* 0xB8 - 0xBF */
3154 N, N,
3155 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3156 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3157 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3158 /* 0xC0 - 0xCF */
3159 D2bv(DstMem | SrcReg | ModRM | Lock),
3160 N, D(DstMem | SrcReg | ModRM | Mov),
3161 N, N, N, GD(0, &group9),
3162 N, N, N, N, N, N, N, N,
3163 /* 0xD0 - 0xDF */
3164 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3165 /* 0xE0 - 0xEF */
3166 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3167 /* 0xF0 - 0xFF */
3168 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3169 };
3170
3171 #undef D
3172 #undef N
3173 #undef G
3174 #undef GD
3175 #undef I
3176 #undef GP
3177 #undef EXT
3178
3179 #undef D2bv
3180 #undef D2bvIP
3181 #undef I2bv
3182 #undef D6ALU
3183
3184 static unsigned imm_size(struct decode_cache *c)
3185 {
3186 unsigned size;
3187
3188 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3189 if (size == 8)
3190 size = 4;
3191 return size;
3192 }
3193
3194 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3195 unsigned size, bool sign_extension)
3196 {
3197 struct decode_cache *c = &ctxt->decode;
3198 struct x86_emulate_ops *ops = ctxt->ops;
3199 int rc = X86EMUL_CONTINUE;
3200
3201 op->type = OP_IMM;
3202 op->bytes = size;
3203 op->addr.mem.ea = c->eip;
3204 /* NB. Immediates are sign-extended as necessary. */
3205 switch (op->bytes) {
3206 case 1:
3207 op->val = insn_fetch(s8, 1, c->eip);
3208 break;
3209 case 2:
3210 op->val = insn_fetch(s16, 2, c->eip);
3211 break;
3212 case 4:
3213 op->val = insn_fetch(s32, 4, c->eip);
3214 break;
3215 }
3216 if (!sign_extension) {
3217 switch (op->bytes) {
3218 case 1:
3219 op->val &= 0xff;
3220 break;
3221 case 2:
3222 op->val &= 0xffff;
3223 break;
3224 case 4:
3225 op->val &= 0xffffffff;
3226 break;
3227 }
3228 }
3229 done:
3230 return rc;
3231 }
3232
3233 int
3234 x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
3235 {
3236 struct x86_emulate_ops *ops = ctxt->ops;
3237 struct decode_cache *c = &ctxt->decode;
3238 int rc = X86EMUL_CONTINUE;
3239 int mode = ctxt->mode;
3240 int def_op_bytes, def_ad_bytes, dual, goffset, simd_prefix;
3241 bool op_prefix = false;
3242 struct opcode opcode, *g_mod012, *g_mod3;
3243 struct operand memop = { .type = OP_NONE };
3244
3245 c->eip = ctxt->eip;
3246 c->fetch.start = c->eip;
3247 c->fetch.end = c->fetch.start + insn_len;
3248 if (insn_len > 0)
3249 memcpy(c->fetch.data, insn, insn_len);
3250
3251 switch (mode) {
3252 case X86EMUL_MODE_REAL:
3253 case X86EMUL_MODE_VM86:
3254 case X86EMUL_MODE_PROT16:
3255 def_op_bytes = def_ad_bytes = 2;
3256 break;
3257 case X86EMUL_MODE_PROT32:
3258 def_op_bytes = def_ad_bytes = 4;
3259 break;
3260 #ifdef CONFIG_X86_64
3261 case X86EMUL_MODE_PROT64:
3262 def_op_bytes = 4;
3263 def_ad_bytes = 8;
3264 break;
3265 #endif
3266 default:
3267 return -1;
3268 }
3269
3270 c->op_bytes = def_op_bytes;
3271 c->ad_bytes = def_ad_bytes;
3272
3273 /* Legacy prefixes. */
3274 for (;;) {
3275 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3276 case 0x66: /* operand-size override */
3277 op_prefix = true;
3278 /* switch between 2/4 bytes */
3279 c->op_bytes = def_op_bytes ^ 6;
3280 break;
3281 case 0x67: /* address-size override */
3282 if (mode == X86EMUL_MODE_PROT64)
3283 /* switch between 4/8 bytes */
3284 c->ad_bytes = def_ad_bytes ^ 12;
3285 else
3286 /* switch between 2/4 bytes */
3287 c->ad_bytes = def_ad_bytes ^ 6;
3288 break;
3289 case 0x26: /* ES override */
3290 case 0x2e: /* CS override */
3291 case 0x36: /* SS override */
3292 case 0x3e: /* DS override */
3293 set_seg_override(c, (c->b >> 3) & 3);
3294 break;
3295 case 0x64: /* FS override */
3296 case 0x65: /* GS override */
3297 set_seg_override(c, c->b & 7);
3298 break;
3299 case 0x40 ... 0x4f: /* REX */
3300 if (mode != X86EMUL_MODE_PROT64)
3301 goto done_prefixes;
3302 c->rex_prefix = c->b;
3303 continue;
3304 case 0xf0: /* LOCK */
3305 c->lock_prefix = 1;
3306 break;
3307 case 0xf2: /* REPNE/REPNZ */
3308 case 0xf3: /* REP/REPE/REPZ */
3309 c->rep_prefix = c->b;
3310 break;
3311 default:
3312 goto done_prefixes;
3313 }
3314
3315 /* Any legacy prefix after a REX prefix nullifies its effect. */
3316
3317 c->rex_prefix = 0;
3318 }
3319
3320 done_prefixes:
3321
3322 /* REX prefix. */
3323 if (c->rex_prefix & 8)
3324 c->op_bytes = 8; /* REX.W */
3325
3326 /* Opcode byte(s). */
3327 opcode = opcode_table[c->b];
3328 /* Two-byte opcode? */
3329 if (c->b == 0x0f) {
3330 c->twobyte = 1;
3331 c->b = insn_fetch(u8, 1, c->eip);
3332 opcode = twobyte_table[c->b];
3333 }
3334 c->d = opcode.flags;
3335
3336 if (c->d & Group) {
3337 dual = c->d & GroupDual;
3338 c->modrm = insn_fetch(u8, 1, c->eip);
3339 --c->eip;
3340
3341 if (c->d & GroupDual) {
3342 g_mod012 = opcode.u.gdual->mod012;
3343 g_mod3 = opcode.u.gdual->mod3;
3344 } else
3345 g_mod012 = g_mod3 = opcode.u.group;
3346
3347 c->d &= ~(Group | GroupDual);
3348
3349 goffset = (c->modrm >> 3) & 7;
3350
3351 if ((c->modrm >> 6) == 3)
3352 opcode = g_mod3[goffset];
3353 else
3354 opcode = g_mod012[goffset];
3355
3356 if (opcode.flags & RMExt) {
3357 goffset = c->modrm & 7;
3358 opcode = opcode.u.group[goffset];
3359 }
3360
3361 c->d |= opcode.flags;
3362 }
3363
3364 if (c->d & Prefix) {
3365 if (c->rep_prefix && op_prefix)
3366 return X86EMUL_UNHANDLEABLE;
3367 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3368 switch (simd_prefix) {
3369 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3370 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3371 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3372 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3373 }
3374 c->d |= opcode.flags;
3375 }
3376
3377 c->execute = opcode.u.execute;
3378 c->check_perm = opcode.check_perm;
3379 c->intercept = opcode.intercept;
3380
3381 /* Unrecognised? */
3382 if (c->d == 0 || (c->d & Undefined))
3383 return -1;
3384
3385 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3386 return -1;
3387
3388 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3389 c->op_bytes = 8;
3390
3391 if (c->d & Op3264) {
3392 if (mode == X86EMUL_MODE_PROT64)
3393 c->op_bytes = 8;
3394 else
3395 c->op_bytes = 4;
3396 }
3397
3398 if (c->d & Sse)
3399 c->op_bytes = 16;
3400
3401 /* ModRM and SIB bytes. */
3402 if (c->d & ModRM) {
3403 rc = decode_modrm(ctxt, ops, &memop);
3404 if (!c->has_seg_override)
3405 set_seg_override(c, c->modrm_seg);
3406 } else if (c->d & MemAbs)
3407 rc = decode_abs(ctxt, ops, &memop);
3408 if (rc != X86EMUL_CONTINUE)
3409 goto done;
3410
3411 if (!c->has_seg_override)
3412 set_seg_override(c, VCPU_SREG_DS);
3413
3414 memop.addr.mem.seg = seg_override(ctxt, ops, c);
3415
3416 if (memop.type == OP_MEM && c->ad_bytes != 8)
3417 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
3418
3419 if (memop.type == OP_MEM && c->rip_relative)
3420 memop.addr.mem.ea += c->eip;
3421
3422 /*
3423 * Decode and fetch the source operand: register, memory
3424 * or immediate.
3425 */
3426 switch (c->d & SrcMask) {
3427 case SrcNone:
3428 break;
3429 case SrcReg:
3430 decode_register_operand(ctxt, &c->src, c, 0);
3431 break;
3432 case SrcMem16:
3433 memop.bytes = 2;
3434 goto srcmem_common;
3435 case SrcMem32:
3436 memop.bytes = 4;
3437 goto srcmem_common;
3438 case SrcMem:
3439 memop.bytes = (c->d & ByteOp) ? 1 :
3440 c->op_bytes;
3441 srcmem_common:
3442 c->src = memop;
3443 break;
3444 case SrcImmU16:
3445 rc = decode_imm(ctxt, &c->src, 2, false);
3446 break;
3447 case SrcImm:
3448 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3449 break;
3450 case SrcImmU:
3451 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
3452 break;
3453 case SrcImmByte:
3454 rc = decode_imm(ctxt, &c->src, 1, true);
3455 break;
3456 case SrcImmUByte:
3457 rc = decode_imm(ctxt, &c->src, 1, false);
3458 break;
3459 case SrcAcc:
3460 c->src.type = OP_REG;
3461 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3462 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
3463 fetch_register_operand(&c->src);
3464 break;
3465 case SrcOne:
3466 c->src.bytes = 1;
3467 c->src.val = 1;
3468 break;
3469 case SrcSI:
3470 c->src.type = OP_MEM;
3471 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3472 c->src.addr.mem.ea =
3473 register_address(c, c->regs[VCPU_REGS_RSI]);
3474 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
3475 c->src.val = 0;
3476 break;
3477 case SrcImmFAddr:
3478 c->src.type = OP_IMM;
3479 c->src.addr.mem.ea = c->eip;
3480 c->src.bytes = c->op_bytes + 2;
3481 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3482 break;
3483 case SrcMemFAddr:
3484 memop.bytes = c->op_bytes + 2;
3485 goto srcmem_common;
3486 break;
3487 }
3488
3489 if (rc != X86EMUL_CONTINUE)
3490 goto done;
3491
3492 /*
3493 * Decode and fetch the second source operand: register, memory
3494 * or immediate.
3495 */
3496 switch (c->d & Src2Mask) {
3497 case Src2None:
3498 break;
3499 case Src2CL:
3500 c->src2.bytes = 1;
3501 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3502 break;
3503 case Src2ImmByte:
3504 rc = decode_imm(ctxt, &c->src2, 1, true);
3505 break;
3506 case Src2One:
3507 c->src2.bytes = 1;
3508 c->src2.val = 1;
3509 break;
3510 case Src2Imm:
3511 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3512 break;
3513 }
3514
3515 if (rc != X86EMUL_CONTINUE)
3516 goto done;
3517
3518 /* Decode and fetch the destination operand: register or memory. */
3519 switch (c->d & DstMask) {
3520 case DstReg:
3521 decode_register_operand(ctxt, &c->dst, c,
3522 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3523 break;
3524 case DstImmUByte:
3525 c->dst.type = OP_IMM;
3526 c->dst.addr.mem.ea = c->eip;
3527 c->dst.bytes = 1;
3528 c->dst.val = insn_fetch(u8, 1, c->eip);
3529 break;
3530 case DstMem:
3531 case DstMem64:
3532 c->dst = memop;
3533 if ((c->d & DstMask) == DstMem64)
3534 c->dst.bytes = 8;
3535 else
3536 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3537 if (c->d & BitOp)
3538 fetch_bit_operand(c);
3539 c->dst.orig_val = c->dst.val;
3540 break;
3541 case DstAcc:
3542 c->dst.type = OP_REG;
3543 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3544 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
3545 fetch_register_operand(&c->dst);
3546 c->dst.orig_val = c->dst.val;
3547 break;
3548 case DstDI:
3549 c->dst.type = OP_MEM;
3550 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3551 c->dst.addr.mem.ea =
3552 register_address(c, c->regs[VCPU_REGS_RDI]);
3553 c->dst.addr.mem.seg = VCPU_SREG_ES;
3554 c->dst.val = 0;
3555 break;
3556 case ImplicitOps:
3557 /* Special instructions do their own operand decoding. */
3558 default:
3559 c->dst.type = OP_NONE; /* Disable writeback. */
3560 return 0;
3561 }
3562
3563 done:
3564 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3565 }
3566
3567 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3568 {
3569 struct decode_cache *c = &ctxt->decode;
3570
3571 /* The second termination condition only applies for REPE
3572 * and REPNE. Test if the repeat string operation prefix is
3573 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3574 * corresponding termination condition according to:
3575 * - if REPE/REPZ and ZF = 0 then done
3576 * - if REPNE/REPNZ and ZF = 1 then done
3577 */
3578 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3579 (c->b == 0xae) || (c->b == 0xaf))
3580 && (((c->rep_prefix == REPE_PREFIX) &&
3581 ((ctxt->eflags & EFLG_ZF) == 0))
3582 || ((c->rep_prefix == REPNE_PREFIX) &&
3583 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3584 return true;
3585
3586 return false;
3587 }
3588
3589 int
3590 x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
3591 {
3592 struct x86_emulate_ops *ops = ctxt->ops;
3593 u64 msr_data;
3594 struct decode_cache *c = &ctxt->decode;
3595 int rc = X86EMUL_CONTINUE;
3596 int saved_dst_type = c->dst.type;
3597 int irq; /* Used for int 3, int, and into */
3598
3599 ctxt->decode.mem_read.pos = 0;
3600
3601 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
3602 rc = emulate_ud(ctxt);
3603 goto done;
3604 }
3605
3606 /* LOCK prefix is allowed only with some instructions */
3607 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
3608 rc = emulate_ud(ctxt);
3609 goto done;
3610 }
3611
3612 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
3613 rc = emulate_ud(ctxt);
3614 goto done;
3615 }
3616
3617 if ((c->d & Sse)
3618 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3619 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
3620 rc = emulate_ud(ctxt);
3621 goto done;
3622 }
3623
3624 if ((c->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
3625 rc = emulate_nm(ctxt);
3626 goto done;
3627 }
3628
3629 if (unlikely(ctxt->guest_mode) && c->intercept) {
3630 rc = emulator_check_intercept(ctxt, c->intercept,
3631 X86_ICPT_PRE_EXCEPT);
3632 if (rc != X86EMUL_CONTINUE)
3633 goto done;
3634 }
3635
3636 /* Privileged instruction can be executed only in CPL=0 */
3637 if ((c->d & Priv) && ops->cpl(ctxt)) {
3638 rc = emulate_gp(ctxt, 0);
3639 goto done;
3640 }
3641
3642 /* Instruction can only be executed in protected mode */
3643 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3644 rc = emulate_ud(ctxt);
3645 goto done;
3646 }
3647
3648 /* Do instruction specific permission checks */
3649 if (c->check_perm) {
3650 rc = c->check_perm(ctxt);
3651 if (rc != X86EMUL_CONTINUE)
3652 goto done;
3653 }
3654
3655 if (unlikely(ctxt->guest_mode) && c->intercept) {
3656 rc = emulator_check_intercept(ctxt, c->intercept,
3657 X86_ICPT_POST_EXCEPT);
3658 if (rc != X86EMUL_CONTINUE)
3659 goto done;
3660 }
3661
3662 if (c->rep_prefix && (c->d & String)) {
3663 /* All REP prefixes have the same first termination condition */
3664 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
3665 ctxt->eip = c->eip;
3666 goto done;
3667 }
3668 }
3669
3670 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3671 rc = segmented_read(ctxt, c->src.addr.mem,
3672 c->src.valptr, c->src.bytes);
3673 if (rc != X86EMUL_CONTINUE)
3674 goto done;
3675 c->src.orig_val64 = c->src.val64;
3676 }
3677
3678 if (c->src2.type == OP_MEM) {
3679 rc = segmented_read(ctxt, c->src2.addr.mem,
3680 &c->src2.val, c->src2.bytes);
3681 if (rc != X86EMUL_CONTINUE)
3682 goto done;
3683 }
3684
3685 if ((c->d & DstMask) == ImplicitOps)
3686 goto special_insn;
3687
3688
3689 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3690 /* optimisation - avoid slow emulated read if Mov */
3691 rc = segmented_read(ctxt, c->dst.addr.mem,
3692 &c->dst.val, c->dst.bytes);
3693 if (rc != X86EMUL_CONTINUE)
3694 goto done;
3695 }
3696 c->dst.orig_val = c->dst.val;
3697
3698 special_insn:
3699
3700 if (unlikely(ctxt->guest_mode) && c->intercept) {
3701 rc = emulator_check_intercept(ctxt, c->intercept,
3702 X86_ICPT_POST_MEMACCESS);
3703 if (rc != X86EMUL_CONTINUE)
3704 goto done;
3705 }
3706
3707 if (c->execute) {
3708 rc = c->execute(ctxt);
3709 if (rc != X86EMUL_CONTINUE)
3710 goto done;
3711 goto writeback;
3712 }
3713
3714 if (c->twobyte)
3715 goto twobyte_insn;
3716
3717 switch (c->b) {
3718 case 0x00 ... 0x05:
3719 add: /* add */
3720 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3721 break;
3722 case 0x06: /* push es */
3723 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
3724 break;
3725 case 0x07: /* pop es */
3726 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
3727 break;
3728 case 0x08 ... 0x0d:
3729 or: /* or */
3730 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
3731 break;
3732 case 0x0e: /* push cs */
3733 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
3734 break;
3735 case 0x10 ... 0x15:
3736 adc: /* adc */
3737 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
3738 break;
3739 case 0x16: /* push ss */
3740 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
3741 break;
3742 case 0x17: /* pop ss */
3743 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
3744 break;
3745 case 0x18 ... 0x1d:
3746 sbb: /* sbb */
3747 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
3748 break;
3749 case 0x1e: /* push ds */
3750 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
3751 break;
3752 case 0x1f: /* pop ds */
3753 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
3754 break;
3755 case 0x20 ... 0x25:
3756 and: /* and */
3757 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
3758 break;
3759 case 0x28 ... 0x2d:
3760 sub: /* sub */
3761 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
3762 break;
3763 case 0x30 ... 0x35:
3764 xor: /* xor */
3765 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
3766 break;
3767 case 0x38 ... 0x3d:
3768 cmp: /* cmp */
3769 c->dst.type = OP_NONE; /* Disable writeback. */
3770 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3771 break;
3772 case 0x40 ... 0x47: /* inc r16/r32 */
3773 emulate_1op("inc", c->dst, ctxt->eflags);
3774 break;
3775 case 0x48 ... 0x4f: /* dec r16/r32 */
3776 emulate_1op("dec", c->dst, ctxt->eflags);
3777 break;
3778 case 0x58 ... 0x5f: /* pop reg */
3779 pop_instruction:
3780 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
3781 break;
3782 case 0x60: /* pusha */
3783 rc = emulate_pusha(ctxt);
3784 break;
3785 case 0x61: /* popa */
3786 rc = emulate_popa(ctxt, ops);
3787 break;
3788 case 0x63: /* movsxd */
3789 if (ctxt->mode != X86EMUL_MODE_PROT64)
3790 goto cannot_emulate;
3791 c->dst.val = (s32) c->src.val;
3792 break;
3793 case 0x6c: /* insb */
3794 case 0x6d: /* insw/insd */
3795 c->src.val = c->regs[VCPU_REGS_RDX];
3796 goto do_io_in;
3797 case 0x6e: /* outsb */
3798 case 0x6f: /* outsw/outsd */
3799 c->dst.val = c->regs[VCPU_REGS_RDX];
3800 goto do_io_out;
3801 break;
3802 case 0x70 ... 0x7f: /* jcc (short) */
3803 if (test_cc(c->b, ctxt->eflags))
3804 jmp_rel(c, c->src.val);
3805 break;
3806 case 0x80 ... 0x83: /* Grp1 */
3807 switch (c->modrm_reg) {
3808 case 0:
3809 goto add;
3810 case 1:
3811 goto or;
3812 case 2:
3813 goto adc;
3814 case 3:
3815 goto sbb;
3816 case 4:
3817 goto and;
3818 case 5:
3819 goto sub;
3820 case 6:
3821 goto xor;
3822 case 7:
3823 goto cmp;
3824 }
3825 break;
3826 case 0x84 ... 0x85:
3827 test:
3828 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
3829 break;
3830 case 0x86 ... 0x87: /* xchg */
3831 xchg:
3832 /* Write back the register source. */
3833 c->src.val = c->dst.val;
3834 write_register_operand(&c->src);
3835 /*
3836 * Write back the memory destination with implicit LOCK
3837 * prefix.
3838 */
3839 c->dst.val = c->src.orig_val;
3840 c->lock_prefix = 1;
3841 break;
3842 case 0x8c: /* mov r/m, sreg */
3843 if (c->modrm_reg > VCPU_SREG_GS) {
3844 rc = emulate_ud(ctxt);
3845 goto done;
3846 }
3847 c->dst.val = ops->get_segment_selector(ctxt, c->modrm_reg);
3848 break;
3849 case 0x8d: /* lea r16/r32, m */
3850 c->dst.val = c->src.addr.mem.ea;
3851 break;
3852 case 0x8e: { /* mov seg, r/m16 */
3853 uint16_t sel;
3854
3855 sel = c->src.val;
3856
3857 if (c->modrm_reg == VCPU_SREG_CS ||
3858 c->modrm_reg > VCPU_SREG_GS) {
3859 rc = emulate_ud(ctxt);
3860 goto done;
3861 }
3862
3863 if (c->modrm_reg == VCPU_SREG_SS)
3864 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3865
3866 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
3867
3868 c->dst.type = OP_NONE; /* Disable writeback. */
3869 break;
3870 }
3871 case 0x8f: /* pop (sole member of Grp1a) */
3872 rc = emulate_grp1a(ctxt, ops);
3873 break;
3874 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3875 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
3876 break;
3877 goto xchg;
3878 case 0x98: /* cbw/cwde/cdqe */
3879 switch (c->op_bytes) {
3880 case 2: c->dst.val = (s8)c->dst.val; break;
3881 case 4: c->dst.val = (s16)c->dst.val; break;
3882 case 8: c->dst.val = (s32)c->dst.val; break;
3883 }
3884 break;
3885 case 0x9c: /* pushf */
3886 c->src.val = (unsigned long) ctxt->eflags;
3887 rc = em_push(ctxt);
3888 break;
3889 case 0x9d: /* popf */
3890 c->dst.type = OP_REG;
3891 c->dst.addr.reg = &ctxt->eflags;
3892 c->dst.bytes = c->op_bytes;
3893 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
3894 break;
3895 case 0xa6 ... 0xa7: /* cmps */
3896 goto cmp;
3897 case 0xa8 ... 0xa9: /* test ax, imm */
3898 goto test;
3899 case 0xae ... 0xaf: /* scas */
3900 goto cmp;
3901 case 0xc0 ... 0xc1:
3902 emulate_grp2(ctxt);
3903 break;
3904 case 0xc3: /* ret */
3905 c->dst.type = OP_REG;
3906 c->dst.addr.reg = &c->eip;
3907 c->dst.bytes = c->op_bytes;
3908 goto pop_instruction;
3909 case 0xc4: /* les */
3910 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
3911 break;
3912 case 0xc5: /* lds */
3913 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
3914 break;
3915 case 0xcb: /* ret far */
3916 rc = emulate_ret_far(ctxt, ops);
3917 break;
3918 case 0xcc: /* int3 */
3919 irq = 3;
3920 goto do_interrupt;
3921 case 0xcd: /* int n */
3922 irq = c->src.val;
3923 do_interrupt:
3924 rc = emulate_int(ctxt, ops, irq);
3925 break;
3926 case 0xce: /* into */
3927 if (ctxt->eflags & EFLG_OF) {
3928 irq = 4;
3929 goto do_interrupt;
3930 }
3931 break;
3932 case 0xcf: /* iret */
3933 rc = emulate_iret(ctxt, ops);
3934 break;
3935 case 0xd0 ... 0xd1: /* Grp2 */
3936 emulate_grp2(ctxt);
3937 break;
3938 case 0xd2 ... 0xd3: /* Grp2 */
3939 c->src.val = c->regs[VCPU_REGS_RCX];
3940 emulate_grp2(ctxt);
3941 break;
3942 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3943 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3944 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3945 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3946 jmp_rel(c, c->src.val);
3947 break;
3948 case 0xe3: /* jcxz/jecxz/jrcxz */
3949 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3950 jmp_rel(c, c->src.val);
3951 break;
3952 case 0xe4: /* inb */
3953 case 0xe5: /* in */
3954 goto do_io_in;
3955 case 0xe6: /* outb */
3956 case 0xe7: /* out */
3957 goto do_io_out;
3958 case 0xe8: /* call (near) */ {
3959 long int rel = c->src.val;
3960 c->src.val = (unsigned long) c->eip;
3961 jmp_rel(c, rel);
3962 rc = em_push(ctxt);
3963 break;
3964 }
3965 case 0xe9: /* jmp rel */
3966 goto jmp;
3967 case 0xea: { /* jmp far */
3968 unsigned short sel;
3969 jump_far:
3970 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3971
3972 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
3973 goto done;
3974
3975 c->eip = 0;
3976 memcpy(&c->eip, c->src.valptr, c->op_bytes);
3977 break;
3978 }
3979 case 0xeb:
3980 jmp: /* jmp rel short */
3981 jmp_rel(c, c->src.val);
3982 c->dst.type = OP_NONE; /* Disable writeback. */
3983 break;
3984 case 0xec: /* in al,dx */
3985 case 0xed: /* in (e/r)ax,dx */
3986 c->src.val = c->regs[VCPU_REGS_RDX];
3987 do_io_in:
3988 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3989 &c->dst.val))
3990 goto done; /* IO is needed */
3991 break;
3992 case 0xee: /* out dx,al */
3993 case 0xef: /* out dx,(e/r)ax */
3994 c->dst.val = c->regs[VCPU_REGS_RDX];
3995 do_io_out:
3996 ops->pio_out_emulated(ctxt, c->src.bytes, c->dst.val,
3997 &c->src.val, 1);
3998 c->dst.type = OP_NONE; /* Disable writeback. */
3999 break;
4000 case 0xf4: /* hlt */
4001 ctxt->ops->halt(ctxt);
4002 break;
4003 case 0xf5: /* cmc */
4004 /* complement carry flag from eflags reg */
4005 ctxt->eflags ^= EFLG_CF;
4006 break;
4007 case 0xf6 ... 0xf7: /* Grp3 */
4008 rc = emulate_grp3(ctxt, ops);
4009 break;
4010 case 0xf8: /* clc */
4011 ctxt->eflags &= ~EFLG_CF;
4012 break;
4013 case 0xf9: /* stc */
4014 ctxt->eflags |= EFLG_CF;
4015 break;
4016 case 0xfa: /* cli */
4017 if (emulator_bad_iopl(ctxt, ops)) {
4018 rc = emulate_gp(ctxt, 0);
4019 goto done;
4020 } else
4021 ctxt->eflags &= ~X86_EFLAGS_IF;
4022 break;
4023 case 0xfb: /* sti */
4024 if (emulator_bad_iopl(ctxt, ops)) {
4025 rc = emulate_gp(ctxt, 0);
4026 goto done;
4027 } else {
4028 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
4029 ctxt->eflags |= X86_EFLAGS_IF;
4030 }
4031 break;
4032 case 0xfc: /* cld */
4033 ctxt->eflags &= ~EFLG_DF;
4034 break;
4035 case 0xfd: /* std */
4036 ctxt->eflags |= EFLG_DF;
4037 break;
4038 case 0xfe: /* Grp4 */
4039 grp45:
4040 rc = emulate_grp45(ctxt);
4041 break;
4042 case 0xff: /* Grp5 */
4043 if (c->modrm_reg == 5)
4044 goto jump_far;
4045 goto grp45;
4046 default:
4047 goto cannot_emulate;
4048 }
4049
4050 if (rc != X86EMUL_CONTINUE)
4051 goto done;
4052
4053 writeback:
4054 rc = writeback(ctxt, ops);
4055 if (rc != X86EMUL_CONTINUE)
4056 goto done;
4057
4058 /*
4059 * restore dst type in case the decoding will be reused
4060 * (happens for string instruction )
4061 */
4062 c->dst.type = saved_dst_type;
4063
4064 if ((c->d & SrcMask) == SrcSI)
4065 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
4066 VCPU_REGS_RSI, &c->src);
4067
4068 if ((c->d & DstMask) == DstDI)
4069 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
4070 &c->dst);
4071
4072 if (c->rep_prefix && (c->d & String)) {
4073 struct read_cache *r = &ctxt->decode.io_read;
4074 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
4075
4076 if (!string_insn_completed(ctxt)) {
4077 /*
4078 * Re-enter guest when pio read ahead buffer is empty
4079 * or, if it is not used, after each 1024 iteration.
4080 */
4081 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
4082 (r->end == 0 || r->end != r->pos)) {
4083 /*
4084 * Reset read cache. Usually happens before
4085 * decode, but since instruction is restarted
4086 * we have to do it here.
4087 */
4088 ctxt->decode.mem_read.end = 0;
4089 return EMULATION_RESTART;
4090 }
4091 goto done; /* skip rip writeback */
4092 }
4093 }
4094
4095 ctxt->eip = c->eip;
4096
4097 done:
4098 if (rc == X86EMUL_PROPAGATE_FAULT)
4099 ctxt->have_exception = true;
4100 if (rc == X86EMUL_INTERCEPTED)
4101 return EMULATION_INTERCEPTED;
4102
4103 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
4104
4105 twobyte_insn:
4106 switch (c->b) {
4107 case 0x05: /* syscall */
4108 rc = emulate_syscall(ctxt, ops);
4109 break;
4110 case 0x06:
4111 rc = em_clts(ctxt);
4112 break;
4113 case 0x09: /* wbinvd */
4114 (ctxt->ops->wbinvd)(ctxt);
4115 break;
4116 case 0x08: /* invd */
4117 case 0x0d: /* GrpP (prefetch) */
4118 case 0x18: /* Grp16 (prefetch/nop) */
4119 break;
4120 case 0x20: /* mov cr, reg */
4121 c->dst.val = ops->get_cr(ctxt, c->modrm_reg);
4122 break;
4123 case 0x21: /* mov from dr to reg */
4124 ops->get_dr(ctxt, c->modrm_reg, &c->dst.val);
4125 break;
4126 case 0x22: /* mov reg, cr */
4127 if (ops->set_cr(ctxt, c->modrm_reg, c->src.val)) {
4128 emulate_gp(ctxt, 0);
4129 rc = X86EMUL_PROPAGATE_FAULT;
4130 goto done;
4131 }
4132 c->dst.type = OP_NONE;
4133 break;
4134 case 0x23: /* mov from reg to dr */
4135 if (ops->set_dr(ctxt, c->modrm_reg, c->src.val &
4136 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
4137 ~0ULL : ~0U)) < 0) {
4138 /* #UD condition is already handled by the code above */
4139 emulate_gp(ctxt, 0);
4140 rc = X86EMUL_PROPAGATE_FAULT;
4141 goto done;
4142 }
4143
4144 c->dst.type = OP_NONE; /* no writeback */
4145 break;
4146 case 0x30:
4147 /* wrmsr */
4148 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4149 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
4150 if (ops->set_msr(ctxt, c->regs[VCPU_REGS_RCX], msr_data)) {
4151 emulate_gp(ctxt, 0);
4152 rc = X86EMUL_PROPAGATE_FAULT;
4153 goto done;
4154 }
4155 rc = X86EMUL_CONTINUE;
4156 break;
4157 case 0x32:
4158 /* rdmsr */
4159 if (ops->get_msr(ctxt, c->regs[VCPU_REGS_RCX], &msr_data)) {
4160 emulate_gp(ctxt, 0);
4161 rc = X86EMUL_PROPAGATE_FAULT;
4162 goto done;
4163 } else {
4164 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4165 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4166 }
4167 rc = X86EMUL_CONTINUE;
4168 break;
4169 case 0x34: /* sysenter */
4170 rc = emulate_sysenter(ctxt, ops);
4171 break;
4172 case 0x35: /* sysexit */
4173 rc = emulate_sysexit(ctxt, ops);
4174 break;
4175 case 0x40 ... 0x4f: /* cmov */
4176 c->dst.val = c->dst.orig_val = c->src.val;
4177 if (!test_cc(c->b, ctxt->eflags))
4178 c->dst.type = OP_NONE; /* no writeback */
4179 break;
4180 case 0x80 ... 0x8f: /* jnz rel, etc*/
4181 if (test_cc(c->b, ctxt->eflags))
4182 jmp_rel(c, c->src.val);
4183 break;
4184 case 0x90 ... 0x9f: /* setcc r/m8 */
4185 c->dst.val = test_cc(c->b, ctxt->eflags);
4186 break;
4187 case 0xa0: /* push fs */
4188 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
4189 break;
4190 case 0xa1: /* pop fs */
4191 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
4192 break;
4193 case 0xa3:
4194 bt: /* bt */
4195 c->dst.type = OP_NONE;
4196 /* only subword offset */
4197 c->src.val &= (c->dst.bytes << 3) - 1;
4198 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
4199 break;
4200 case 0xa4: /* shld imm8, r, r/m */
4201 case 0xa5: /* shld cl, r, r/m */
4202 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4203 break;
4204 case 0xa8: /* push gs */
4205 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
4206 break;
4207 case 0xa9: /* pop gs */
4208 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
4209 break;
4210 case 0xab:
4211 bts: /* bts */
4212 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
4213 break;
4214 case 0xac: /* shrd imm8, r, r/m */
4215 case 0xad: /* shrd cl, r, r/m */
4216 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4217 break;
4218 case 0xae: /* clflush */
4219 break;
4220 case 0xb0 ... 0xb1: /* cmpxchg */
4221 /*
4222 * Save real source value, then compare EAX against
4223 * destination.
4224 */
4225 c->src.orig_val = c->src.val;
4226 c->src.val = c->regs[VCPU_REGS_RAX];
4227 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4228 if (ctxt->eflags & EFLG_ZF) {
4229 /* Success: write back to memory. */
4230 c->dst.val = c->src.orig_val;
4231 } else {
4232 /* Failure: write the value we saw to EAX. */
4233 c->dst.type = OP_REG;
4234 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
4235 }
4236 break;
4237 case 0xb2: /* lss */
4238 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
4239 break;
4240 case 0xb3:
4241 btr: /* btr */
4242 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
4243 break;
4244 case 0xb4: /* lfs */
4245 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
4246 break;
4247 case 0xb5: /* lgs */
4248 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
4249 break;
4250 case 0xb6 ... 0xb7: /* movzx */
4251 c->dst.bytes = c->op_bytes;
4252 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4253 : (u16) c->src.val;
4254 break;
4255 case 0xba: /* Grp8 */
4256 switch (c->modrm_reg & 3) {
4257 case 0:
4258 goto bt;
4259 case 1:
4260 goto bts;
4261 case 2:
4262 goto btr;
4263 case 3:
4264 goto btc;
4265 }
4266 break;
4267 case 0xbb:
4268 btc: /* btc */
4269 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
4270 break;
4271 case 0xbc: { /* bsf */
4272 u8 zf;
4273 __asm__ ("bsf %2, %0; setz %1"
4274 : "=r"(c->dst.val), "=q"(zf)
4275 : "r"(c->src.val));
4276 ctxt->eflags &= ~X86_EFLAGS_ZF;
4277 if (zf) {
4278 ctxt->eflags |= X86_EFLAGS_ZF;
4279 c->dst.type = OP_NONE; /* Disable writeback. */
4280 }
4281 break;
4282 }
4283 case 0xbd: { /* bsr */
4284 u8 zf;
4285 __asm__ ("bsr %2, %0; setz %1"
4286 : "=r"(c->dst.val), "=q"(zf)
4287 : "r"(c->src.val));
4288 ctxt->eflags &= ~X86_EFLAGS_ZF;
4289 if (zf) {
4290 ctxt->eflags |= X86_EFLAGS_ZF;
4291 c->dst.type = OP_NONE; /* Disable writeback. */
4292 }
4293 break;
4294 }
4295 case 0xbe ... 0xbf: /* movsx */
4296 c->dst.bytes = c->op_bytes;
4297 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4298 (s16) c->src.val;
4299 break;
4300 case 0xc0 ... 0xc1: /* xadd */
4301 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4302 /* Write back the register source. */
4303 c->src.val = c->dst.orig_val;
4304 write_register_operand(&c->src);
4305 break;
4306 case 0xc3: /* movnti */
4307 c->dst.bytes = c->op_bytes;
4308 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4309 (u64) c->src.val;
4310 break;
4311 case 0xc7: /* Grp9 (cmpxchg8b) */
4312 rc = emulate_grp9(ctxt, ops);
4313 break;
4314 default:
4315 goto cannot_emulate;
4316 }
4317
4318 if (rc != X86EMUL_CONTINUE)
4319 goto done;
4320
4321 goto writeback;
4322
4323 cannot_emulate:
4324 return EMULATION_FAILED;
4325 }
Linux kernel - Deliverables
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