projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
KVM: MMU: Add unlikely() annotations to walk_addr_generic()
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
25 #include <linux/module.h>
26 #include <asm/kvm_emulate.h>
27
28 #include "x86.h"
29 #include "tss.h"
30
31 /*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40 /* Operand sizes: 8-bit operands or specified/overridden size. */
41 #define ByteOp (1<<0) /* 8-bit operands. */
42 /* Destination operand type. */
43 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44 #define DstReg (2<<1) /* Register operand. */
45 #define DstMem (3<<1) /* Memory operand. */
46 #define DstAcc (4<<1) /* Destination Accumulator */
47 #define DstDI (5<<1) /* Destination is in ES:(E)DI */
48 #define DstMem64 (6<<1) /* 64bit memory operand */
49 #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
50 #define DstMask (7<<1)
51 /* Source operand type. */
52 #define SrcNone (0<<4) /* No source operand. */
53 #define SrcReg (1<<4) /* Register operand. */
54 #define SrcMem (2<<4) /* Memory operand. */
55 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57 #define SrcImm (5<<4) /* Immediate operand. */
58 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
59 #define SrcOne (7<<4) /* Implied '1' */
60 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
61 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
62 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */
63 #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64 #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
65 #define SrcAcc (0xd<<4) /* Source Accumulator */
66 #define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
67 #define SrcMask (0xf<<4)
68 /* Generic ModRM decode. */
69 #define ModRM (1<<8)
70 /* Destination is only written; never read. */
71 #define Mov (1<<9)
72 #define BitOp (1<<10)
73 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
74 #define String (1<<12) /* String instruction (rep capable) */
75 #define Stack (1<<13) /* Stack instruction (push/pop) */
76 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
78 #define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */
79 #define Sse (1<<17) /* SSE Vector instruction */
80 #define RMExt (1<<18) /* Opcode extension in ModRM r/m if mod == 3 */
81 /* Misc flags */
82 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
83 #define VendorSpecific (1<<22) /* Vendor specific instruction */
84 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
85 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
86 #define Undefined (1<<25) /* No Such Instruction */
87 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
88 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
89 #define No64 (1<<28)
90 /* Source 2 operand type */
91 #define Src2None (0<<29)
92 #define Src2CL (1<<29)
93 #define Src2ImmByte (2<<29)
94 #define Src2One (3<<29)
95 #define Src2Imm (4<<29)
96 #define Src2Mask (7<<29)
97
98 #define X2(x...) x, x
99 #define X3(x...) X2(x), x
100 #define X4(x...) X2(x), X2(x)
101 #define X5(x...) X4(x), x
102 #define X6(x...) X4(x), X2(x)
103 #define X7(x...) X4(x), X3(x)
104 #define X8(x...) X4(x), X4(x)
105 #define X16(x...) X8(x), X8(x)
106
107 struct opcode {
108 u32 flags;
109 u8 intercept;
110 union {
111 int (*execute)(struct x86_emulate_ctxt *ctxt);
112 struct opcode *group;
113 struct group_dual *gdual;
114 struct gprefix *gprefix;
115 } u;
116 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
117 };
118
119 struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
122 };
123
124 struct gprefix {
125 struct opcode pfx_no;
126 struct opcode pfx_66;
127 struct opcode pfx_f2;
128 struct opcode pfx_f3;
129 };
130
131 /* EFLAGS bit definitions. */
132 #define EFLG_ID (1<<21)
133 #define EFLG_VIP (1<<20)
134 #define EFLG_VIF (1<<19)
135 #define EFLG_AC (1<<18)
136 #define EFLG_VM (1<<17)
137 #define EFLG_RF (1<<16)
138 #define EFLG_IOPL (3<<12)
139 #define EFLG_NT (1<<14)
140 #define EFLG_OF (1<<11)
141 #define EFLG_DF (1<<10)
142 #define EFLG_IF (1<<9)
143 #define EFLG_TF (1<<8)
144 #define EFLG_SF (1<<7)
145 #define EFLG_ZF (1<<6)
146 #define EFLG_AF (1<<4)
147 #define EFLG_PF (1<<2)
148 #define EFLG_CF (1<<0)
149
150 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
151 #define EFLG_RESERVED_ONE_MASK 2
152
153 /*
154 * Instruction emulation:
155 * Most instructions are emulated directly via a fragment of inline assembly
156 * code. This allows us to save/restore EFLAGS and thus very easily pick up
157 * any modified flags.
158 */
159
160 #if defined(CONFIG_X86_64)
161 #define _LO32 "k" /* force 32-bit operand */
162 #define _STK "%%rsp" /* stack pointer */
163 #elif defined(__i386__)
164 #define _LO32 "" /* force 32-bit operand */
165 #define _STK "%%esp" /* stack pointer */
166 #endif
167
168 /*
169 * These EFLAGS bits are restored from saved value during emulation, and
170 * any changes are written back to the saved value after emulation.
171 */
172 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
173
174 /* Before executing instruction: restore necessary bits in EFLAGS. */
175 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
176 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
177 "movl %"_sav",%"_LO32 _tmp"; " \
178 "push %"_tmp"; " \
179 "push %"_tmp"; " \
180 "movl %"_msk",%"_LO32 _tmp"; " \
181 "andl %"_LO32 _tmp",("_STK"); " \
182 "pushf; " \
183 "notl %"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
186 "pop %"_tmp"; " \
187 "orl %"_LO32 _tmp",("_STK"); " \
188 "popf; " \
189 "pop %"_sav"; "
190
191 /* After executing instruction: write-back necessary bits in EFLAGS. */
192 #define _POST_EFLAGS(_sav, _msk, _tmp) \
193 /* _sav |= EFLAGS & _msk; */ \
194 "pushf; " \
195 "pop %"_tmp"; " \
196 "andl %"_msk",%"_LO32 _tmp"; " \
197 "orl %"_LO32 _tmp",%"_sav"; "
198
199 #ifdef CONFIG_X86_64
200 #define ON64(x) x
201 #else
202 #define ON64(x)
203 #endif
204
205 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
206 do { \
207 __asm__ __volatile__ ( \
208 _PRE_EFLAGS("0", "4", "2") \
209 _op _suffix " %"_x"3,%1; " \
210 _POST_EFLAGS("0", "4", "2") \
211 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
212 "=&r" (_tmp) \
213 : _y ((_src).val), "i" (EFLAGS_MASK)); \
214 } while (0)
215
216
217 /* Raw emulation: instruction has two explicit operands. */
218 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
219 do { \
220 unsigned long _tmp; \
221 \
222 switch ((_dst).bytes) { \
223 case 2: \
224 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
225 break; \
226 case 4: \
227 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
228 break; \
229 case 8: \
230 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
231 break; \
232 } \
233 } while (0)
234
235 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
236 do { \
237 unsigned long _tmp; \
238 switch ((_dst).bytes) { \
239 case 1: \
240 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
241 break; \
242 default: \
243 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
244 _wx, _wy, _lx, _ly, _qx, _qy); \
245 break; \
246 } \
247 } while (0)
248
249 /* Source operand is byte-sized and may be restricted to just %cl. */
250 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
251 __emulate_2op(_op, _src, _dst, _eflags, \
252 "b", "c", "b", "c", "b", "c", "b", "c")
253
254 /* Source operand is byte, word, long or quad sized. */
255 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
256 __emulate_2op(_op, _src, _dst, _eflags, \
257 "b", "q", "w", "r", _LO32, "r", "", "r")
258
259 /* Source operand is word, long or quad sized. */
260 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
261 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
262 "w", "r", _LO32, "r", "", "r")
263
264 /* Instruction has three operands and one operand is stored in ECX register */
265 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
266 do { \
267 unsigned long _tmp; \
268 _type _clv = (_cl).val; \
269 _type _srcv = (_src).val; \
270 _type _dstv = (_dst).val; \
271 \
272 __asm__ __volatile__ ( \
273 _PRE_EFLAGS("0", "5", "2") \
274 _op _suffix " %4,%1 \n" \
275 _POST_EFLAGS("0", "5", "2") \
276 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
277 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
278 ); \
279 \
280 (_cl).val = (unsigned long) _clv; \
281 (_src).val = (unsigned long) _srcv; \
282 (_dst).val = (unsigned long) _dstv; \
283 } while (0)
284
285 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
286 do { \
287 switch ((_dst).bytes) { \
288 case 2: \
289 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
290 "w", unsigned short); \
291 break; \
292 case 4: \
293 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
294 "l", unsigned int); \
295 break; \
296 case 8: \
297 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
298 "q", unsigned long)); \
299 break; \
300 } \
301 } while (0)
302
303 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
304 do { \
305 unsigned long _tmp; \
306 \
307 __asm__ __volatile__ ( \
308 _PRE_EFLAGS("0", "3", "2") \
309 _op _suffix " %1; " \
310 _POST_EFLAGS("0", "3", "2") \
311 : "=m" (_eflags), "+m" ((_dst).val), \
312 "=&r" (_tmp) \
313 : "i" (EFLAGS_MASK)); \
314 } while (0)
315
316 /* Instruction has only one explicit operand (no source operand). */
317 #define emulate_1op(_op, _dst, _eflags) \
318 do { \
319 switch ((_dst).bytes) { \
320 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
321 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
322 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
323 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
324 } \
325 } while (0)
326
327 #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
328 do { \
329 unsigned long _tmp; \
330 \
331 __asm__ __volatile__ ( \
332 _PRE_EFLAGS("0", "4", "1") \
333 _op _suffix " %5; " \
334 _POST_EFLAGS("0", "4", "1") \
335 : "=m" (_eflags), "=&r" (_tmp), \
336 "+a" (_rax), "+d" (_rdx) \
337 : "i" (EFLAGS_MASK), "m" ((_src).val), \
338 "a" (_rax), "d" (_rdx)); \
339 } while (0)
340
341 #define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
342 do { \
343 unsigned long _tmp; \
344 \
345 __asm__ __volatile__ ( \
346 _PRE_EFLAGS("0", "5", "1") \
347 "1: \n\t" \
348 _op _suffix " %6; " \
349 "2: \n\t" \
350 _POST_EFLAGS("0", "5", "1") \
351 ".pushsection .fixup,\"ax\" \n\t" \
352 "3: movb $1, %4 \n\t" \
353 "jmp 2b \n\t" \
354 ".popsection \n\t" \
355 _ASM_EXTABLE(1b, 3b) \
356 : "=m" (_eflags), "=&r" (_tmp), \
357 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
358 : "i" (EFLAGS_MASK), "m" ((_src).val), \
359 "a" (_rax), "d" (_rdx)); \
360 } while (0)
361
362 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
363 #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
364 do { \
365 switch((_src).bytes) { \
366 case 1: \
367 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
368 _eflags, "b"); \
369 break; \
370 case 2: \
371 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
372 _eflags, "w"); \
373 break; \
374 case 4: \
375 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
376 _eflags, "l"); \
377 break; \
378 case 8: \
379 ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
380 _eflags, "q")); \
381 break; \
382 } \
383 } while (0)
384
385 #define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
386 do { \
387 switch((_src).bytes) { \
388 case 1: \
389 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
390 _eflags, "b", _ex); \
391 break; \
392 case 2: \
393 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
394 _eflags, "w", _ex); \
395 break; \
396 case 4: \
397 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
398 _eflags, "l", _ex); \
399 break; \
400 case 8: ON64( \
401 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
402 _eflags, "q", _ex)); \
403 break; \
404 } \
405 } while (0)
406
407 /* Fetch next part of the instruction being emulated. */
408 #define insn_fetch(_type, _size, _eip) \
409 ({ unsigned long _x; \
410 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
411 if (rc != X86EMUL_CONTINUE) \
412 goto done; \
413 (_eip) += (_size); \
414 (_type)_x; \
415 })
416
417 #define insn_fetch_arr(_arr, _size, _eip) \
418 ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
419 if (rc != X86EMUL_CONTINUE) \
420 goto done; \
421 (_eip) += (_size); \
422 })
423
424 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
425 enum x86_intercept intercept,
426 enum x86_intercept_stage stage)
427 {
428 struct x86_instruction_info info = {
429 .intercept = intercept,
430 .rep_prefix = ctxt->decode.rep_prefix,
431 .modrm_mod = ctxt->decode.modrm_mod,
432 .modrm_reg = ctxt->decode.modrm_reg,
433 .modrm_rm = ctxt->decode.modrm_rm,
434 .src_val = ctxt->decode.src.val64,
435 .src_bytes = ctxt->decode.src.bytes,
436 .dst_bytes = ctxt->decode.dst.bytes,
437 .ad_bytes = ctxt->decode.ad_bytes,
438 .next_rip = ctxt->eip,
439 };
440
441 return ctxt->ops->intercept(ctxt, &info, stage);
442 }
443
444 static inline unsigned long ad_mask(struct decode_cache *c)
445 {
446 return (1UL << (c->ad_bytes << 3)) - 1;
447 }
448
449 /* Access/update address held in a register, based on addressing mode. */
450 static inline unsigned long
451 address_mask(struct decode_cache *c, unsigned long reg)
452 {
453 if (c->ad_bytes == sizeof(unsigned long))
454 return reg;
455 else
456 return reg & ad_mask(c);
457 }
458
459 static inline unsigned long
460 register_address(struct decode_cache *c, unsigned long reg)
461 {
462 return address_mask(c, reg);
463 }
464
465 static inline void
466 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
467 {
468 if (c->ad_bytes == sizeof(unsigned long))
469 *reg += inc;
470 else
471 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
472 }
473
474 static inline void jmp_rel(struct decode_cache *c, int rel)
475 {
476 register_address_increment(c, &c->eip, rel);
477 }
478
479 static u32 desc_limit_scaled(struct desc_struct *desc)
480 {
481 u32 limit = get_desc_limit(desc);
482
483 return desc->g ? (limit << 12) | 0xfff : limit;
484 }
485
486 static void set_seg_override(struct decode_cache *c, int seg)
487 {
488 c->has_seg_override = true;
489 c->seg_override = seg;
490 }
491
492 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
493 struct x86_emulate_ops *ops, int seg)
494 {
495 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
496 return 0;
497
498 return ops->get_cached_segment_base(ctxt, seg);
499 }
500
501 static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
502 struct x86_emulate_ops *ops,
503 struct decode_cache *c)
504 {
505 if (!c->has_seg_override)
506 return 0;
507
508 return c->seg_override;
509 }
510
511 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
512 u32 error, bool valid)
513 {
514 ctxt->exception.vector = vec;
515 ctxt->exception.error_code = error;
516 ctxt->exception.error_code_valid = valid;
517 return X86EMUL_PROPAGATE_FAULT;
518 }
519
520 static int emulate_db(struct x86_emulate_ctxt *ctxt)
521 {
522 return emulate_exception(ctxt, DB_VECTOR, 0, false);
523 }
524
525 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
526 {
527 return emulate_exception(ctxt, GP_VECTOR, err, true);
528 }
529
530 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
531 {
532 return emulate_exception(ctxt, SS_VECTOR, err, true);
533 }
534
535 static int emulate_ud(struct x86_emulate_ctxt *ctxt)
536 {
537 return emulate_exception(ctxt, UD_VECTOR, 0, false);
538 }
539
540 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
541 {
542 return emulate_exception(ctxt, TS_VECTOR, err, true);
543 }
544
545 static int emulate_de(struct x86_emulate_ctxt *ctxt)
546 {
547 return emulate_exception(ctxt, DE_VECTOR, 0, false);
548 }
549
550 static int emulate_nm(struct x86_emulate_ctxt *ctxt)
551 {
552 return emulate_exception(ctxt, NM_VECTOR, 0, false);
553 }
554
555 static int __linearize(struct x86_emulate_ctxt *ctxt,
556 struct segmented_address addr,
557 unsigned size, bool write, bool fetch,
558 ulong *linear)
559 {
560 struct decode_cache *c = &ctxt->decode;
561 struct desc_struct desc;
562 bool usable;
563 ulong la;
564 u32 lim;
565 unsigned cpl, rpl;
566
567 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
568 switch (ctxt->mode) {
569 case X86EMUL_MODE_REAL:
570 break;
571 case X86EMUL_MODE_PROT64:
572 if (((signed long)la << 16) >> 16 != la)
573 return emulate_gp(ctxt, 0);
574 break;
575 default:
576 usable = ctxt->ops->get_cached_descriptor(ctxt, &desc, NULL,
577 addr.seg);
578 if (!usable)
579 goto bad;
580 /* code segment or read-only data segment */
581 if (((desc.type & 8) || !(desc.type & 2)) && write)
582 goto bad;
583 /* unreadable code segment */
584 if (!fetch && (desc.type & 8) && !(desc.type & 2))
585 goto bad;
586 lim = desc_limit_scaled(&desc);
587 if ((desc.type & 8) || !(desc.type & 4)) {
588 /* expand-up segment */
589 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
590 goto bad;
591 } else {
592 /* exapand-down segment */
593 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
594 goto bad;
595 lim = desc.d ? 0xffffffff : 0xffff;
596 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
597 goto bad;
598 }
599 cpl = ctxt->ops->cpl(ctxt);
600 rpl = ctxt->ops->get_segment_selector(ctxt, addr.seg) & 3;
601 cpl = max(cpl, rpl);
602 if (!(desc.type & 8)) {
603 /* data segment */
604 if (cpl > desc.dpl)
605 goto bad;
606 } else if ((desc.type & 8) && !(desc.type & 4)) {
607 /* nonconforming code segment */
608 if (cpl != desc.dpl)
609 goto bad;
610 } else if ((desc.type & 8) && (desc.type & 4)) {
611 /* conforming code segment */
612 if (cpl < desc.dpl)
613 goto bad;
614 }
615 break;
616 }
617 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : c->ad_bytes != 8)
618 la &= (u32)-1;
619 *linear = la;
620 return X86EMUL_CONTINUE;
621 bad:
622 if (addr.seg == VCPU_SREG_SS)
623 return emulate_ss(ctxt, addr.seg);
624 else
625 return emulate_gp(ctxt, addr.seg);
626 }
627
628 static int linearize(struct x86_emulate_ctxt *ctxt,
629 struct segmented_address addr,
630 unsigned size, bool write,
631 ulong *linear)
632 {
633 return __linearize(ctxt, addr, size, write, false, linear);
634 }
635
636
637 static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
638 struct segmented_address addr,
639 void *data,
640 unsigned size)
641 {
642 int rc;
643 ulong linear;
644
645 rc = linearize(ctxt, addr, size, false, &linear);
646 if (rc != X86EMUL_CONTINUE)
647 return rc;
648 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
649 }
650
651 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
652 struct x86_emulate_ops *ops,
653 unsigned long eip, u8 *dest)
654 {
655 struct fetch_cache *fc = &ctxt->decode.fetch;
656 int rc;
657 int size, cur_size;
658
659 if (eip == fc->end) {
660 unsigned long linear;
661 struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
662 cur_size = fc->end - fc->start;
663 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
664 rc = __linearize(ctxt, addr, size, false, true, &linear);
665 if (rc != X86EMUL_CONTINUE)
666 return rc;
667 rc = ops->fetch(ctxt, linear, fc->data + cur_size,
668 size, &ctxt->exception);
669 if (rc != X86EMUL_CONTINUE)
670 return rc;
671 fc->end += size;
672 }
673 *dest = fc->data[eip - fc->start];
674 return X86EMUL_CONTINUE;
675 }
676
677 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
678 struct x86_emulate_ops *ops,
679 unsigned long eip, void *dest, unsigned size)
680 {
681 int rc;
682
683 /* x86 instructions are limited to 15 bytes. */
684 if (eip + size - ctxt->eip > 15)
685 return X86EMUL_UNHANDLEABLE;
686 while (size--) {
687 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
688 if (rc != X86EMUL_CONTINUE)
689 return rc;
690 }
691 return X86EMUL_CONTINUE;
692 }
693
694 /*
695 * Given the 'reg' portion of a ModRM byte, and a register block, return a
696 * pointer into the block that addresses the relevant register.
697 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
698 */
699 static void *decode_register(u8 modrm_reg, unsigned long *regs,
700 int highbyte_regs)
701 {
702 void *p;
703
704 p = &regs[modrm_reg];
705 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
706 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
707 return p;
708 }
709
710 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
711 struct x86_emulate_ops *ops,
712 struct segmented_address addr,
713 u16 *size, unsigned long *address, int op_bytes)
714 {
715 int rc;
716
717 if (op_bytes == 2)
718 op_bytes = 3;
719 *address = 0;
720 rc = segmented_read_std(ctxt, addr, size, 2);
721 if (rc != X86EMUL_CONTINUE)
722 return rc;
723 addr.ea += 2;
724 rc = segmented_read_std(ctxt, addr, address, op_bytes);
725 return rc;
726 }
727
728 static int test_cc(unsigned int condition, unsigned int flags)
729 {
730 int rc = 0;
731
732 switch ((condition & 15) >> 1) {
733 case 0: /* o */
734 rc |= (flags & EFLG_OF);
735 break;
736 case 1: /* b/c/nae */
737 rc |= (flags & EFLG_CF);
738 break;
739 case 2: /* z/e */
740 rc |= (flags & EFLG_ZF);
741 break;
742 case 3: /* be/na */
743 rc |= (flags & (EFLG_CF|EFLG_ZF));
744 break;
745 case 4: /* s */
746 rc |= (flags & EFLG_SF);
747 break;
748 case 5: /* p/pe */
749 rc |= (flags & EFLG_PF);
750 break;
751 case 7: /* le/ng */
752 rc |= (flags & EFLG_ZF);
753 /* fall through */
754 case 6: /* l/nge */
755 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
756 break;
757 }
758
759 /* Odd condition identifiers (lsb == 1) have inverted sense. */
760 return (!!rc ^ (condition & 1));
761 }
762
763 static void fetch_register_operand(struct operand *op)
764 {
765 switch (op->bytes) {
766 case 1:
767 op->val = *(u8 *)op->addr.reg;
768 break;
769 case 2:
770 op->val = *(u16 *)op->addr.reg;
771 break;
772 case 4:
773 op->val = *(u32 *)op->addr.reg;
774 break;
775 case 8:
776 op->val = *(u64 *)op->addr.reg;
777 break;
778 }
779 }
780
781 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
782 {
783 ctxt->ops->get_fpu(ctxt);
784 switch (reg) {
785 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
786 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
787 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
788 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
789 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
790 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
791 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
792 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
793 #ifdef CONFIG_X86_64
794 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
795 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
796 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
797 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
798 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
799 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
800 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
801 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
802 #endif
803 default: BUG();
804 }
805 ctxt->ops->put_fpu(ctxt);
806 }
807
808 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
809 int reg)
810 {
811 ctxt->ops->get_fpu(ctxt);
812 switch (reg) {
813 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
814 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
815 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
816 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
817 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
818 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
819 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
820 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
821 #ifdef CONFIG_X86_64
822 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
823 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
824 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
825 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
826 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
827 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
828 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
829 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
830 #endif
831 default: BUG();
832 }
833 ctxt->ops->put_fpu(ctxt);
834 }
835
836 static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
837 struct operand *op,
838 struct decode_cache *c,
839 int inhibit_bytereg)
840 {
841 unsigned reg = c->modrm_reg;
842 int highbyte_regs = c->rex_prefix == 0;
843
844 if (!(c->d & ModRM))
845 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
846
847 if (c->d & Sse) {
848 op->type = OP_XMM;
849 op->bytes = 16;
850 op->addr.xmm = reg;
851 read_sse_reg(ctxt, &op->vec_val, reg);
852 return;
853 }
854
855 op->type = OP_REG;
856 if ((c->d & ByteOp) && !inhibit_bytereg) {
857 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
858 op->bytes = 1;
859 } else {
860 op->addr.reg = decode_register(reg, c->regs, 0);
861 op->bytes = c->op_bytes;
862 }
863 fetch_register_operand(op);
864 op->orig_val = op->val;
865 }
866
867 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
868 struct x86_emulate_ops *ops,
869 struct operand *op)
870 {
871 struct decode_cache *c = &ctxt->decode;
872 u8 sib;
873 int index_reg = 0, base_reg = 0, scale;
874 int rc = X86EMUL_CONTINUE;
875 ulong modrm_ea = 0;
876
877 if (c->rex_prefix) {
878 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
879 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
880 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
881 }
882
883 c->modrm = insn_fetch(u8, 1, c->eip);
884 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
885 c->modrm_reg |= (c->modrm & 0x38) >> 3;
886 c->modrm_rm |= (c->modrm & 0x07);
887 c->modrm_seg = VCPU_SREG_DS;
888
889 if (c->modrm_mod == 3) {
890 op->type = OP_REG;
891 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
892 op->addr.reg = decode_register(c->modrm_rm,
893 c->regs, c->d & ByteOp);
894 if (c->d & Sse) {
895 op->type = OP_XMM;
896 op->bytes = 16;
897 op->addr.xmm = c->modrm_rm;
898 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
899 return rc;
900 }
901 fetch_register_operand(op);
902 return rc;
903 }
904
905 op->type = OP_MEM;
906
907 if (c->ad_bytes == 2) {
908 unsigned bx = c->regs[VCPU_REGS_RBX];
909 unsigned bp = c->regs[VCPU_REGS_RBP];
910 unsigned si = c->regs[VCPU_REGS_RSI];
911 unsigned di = c->regs[VCPU_REGS_RDI];
912
913 /* 16-bit ModR/M decode. */
914 switch (c->modrm_mod) {
915 case 0:
916 if (c->modrm_rm == 6)
917 modrm_ea += insn_fetch(u16, 2, c->eip);
918 break;
919 case 1:
920 modrm_ea += insn_fetch(s8, 1, c->eip);
921 break;
922 case 2:
923 modrm_ea += insn_fetch(u16, 2, c->eip);
924 break;
925 }
926 switch (c->modrm_rm) {
927 case 0:
928 modrm_ea += bx + si;
929 break;
930 case 1:
931 modrm_ea += bx + di;
932 break;
933 case 2:
934 modrm_ea += bp + si;
935 break;
936 case 3:
937 modrm_ea += bp + di;
938 break;
939 case 4:
940 modrm_ea += si;
941 break;
942 case 5:
943 modrm_ea += di;
944 break;
945 case 6:
946 if (c->modrm_mod != 0)
947 modrm_ea += bp;
948 break;
949 case 7:
950 modrm_ea += bx;
951 break;
952 }
953 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
954 (c->modrm_rm == 6 && c->modrm_mod != 0))
955 c->modrm_seg = VCPU_SREG_SS;
956 modrm_ea = (u16)modrm_ea;
957 } else {
958 /* 32/64-bit ModR/M decode. */
959 if ((c->modrm_rm & 7) == 4) {
960 sib = insn_fetch(u8, 1, c->eip);
961 index_reg |= (sib >> 3) & 7;
962 base_reg |= sib & 7;
963 scale = sib >> 6;
964
965 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
966 modrm_ea += insn_fetch(s32, 4, c->eip);
967 else
968 modrm_ea += c->regs[base_reg];
969 if (index_reg != 4)
970 modrm_ea += c->regs[index_reg] << scale;
971 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
972 if (ctxt->mode == X86EMUL_MODE_PROT64)
973 c->rip_relative = 1;
974 } else
975 modrm_ea += c->regs[c->modrm_rm];
976 switch (c->modrm_mod) {
977 case 0:
978 if (c->modrm_rm == 5)
979 modrm_ea += insn_fetch(s32, 4, c->eip);
980 break;
981 case 1:
982 modrm_ea += insn_fetch(s8, 1, c->eip);
983 break;
984 case 2:
985 modrm_ea += insn_fetch(s32, 4, c->eip);
986 break;
987 }
988 }
989 op->addr.mem.ea = modrm_ea;
990 done:
991 return rc;
992 }
993
994 static int decode_abs(struct x86_emulate_ctxt *ctxt,
995 struct x86_emulate_ops *ops,
996 struct operand *op)
997 {
998 struct decode_cache *c = &ctxt->decode;
999 int rc = X86EMUL_CONTINUE;
1000
1001 op->type = OP_MEM;
1002 switch (c->ad_bytes) {
1003 case 2:
1004 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1005 break;
1006 case 4:
1007 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1008 break;
1009 case 8:
1010 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1011 break;
1012 }
1013 done:
1014 return rc;
1015 }
1016
1017 static void fetch_bit_operand(struct decode_cache *c)
1018 {
1019 long sv = 0, mask;
1020
1021 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
1022 mask = ~(c->dst.bytes * 8 - 1);
1023
1024 if (c->src.bytes == 2)
1025 sv = (s16)c->src.val & (s16)mask;
1026 else if (c->src.bytes == 4)
1027 sv = (s32)c->src.val & (s32)mask;
1028
1029 c->dst.addr.mem.ea += (sv >> 3);
1030 }
1031
1032 /* only subword offset */
1033 c->src.val &= (c->dst.bytes << 3) - 1;
1034 }
1035
1036 static int read_emulated(struct x86_emulate_ctxt *ctxt,
1037 struct x86_emulate_ops *ops,
1038 unsigned long addr, void *dest, unsigned size)
1039 {
1040 int rc;
1041 struct read_cache *mc = &ctxt->decode.mem_read;
1042
1043 while (size) {
1044 int n = min(size, 8u);
1045 size -= n;
1046 if (mc->pos < mc->end)
1047 goto read_cached;
1048
1049 rc = ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1050 &ctxt->exception);
1051 if (rc != X86EMUL_CONTINUE)
1052 return rc;
1053 mc->end += n;
1054
1055 read_cached:
1056 memcpy(dest, mc->data + mc->pos, n);
1057 mc->pos += n;
1058 dest += n;
1059 addr += n;
1060 }
1061 return X86EMUL_CONTINUE;
1062 }
1063
1064 static int segmented_read(struct x86_emulate_ctxt *ctxt,
1065 struct segmented_address addr,
1066 void *data,
1067 unsigned size)
1068 {
1069 int rc;
1070 ulong linear;
1071
1072 rc = linearize(ctxt, addr, size, false, &linear);
1073 if (rc != X86EMUL_CONTINUE)
1074 return rc;
1075 return read_emulated(ctxt, ctxt->ops, linear, data, size);
1076 }
1077
1078 static int segmented_write(struct x86_emulate_ctxt *ctxt,
1079 struct segmented_address addr,
1080 const void *data,
1081 unsigned size)
1082 {
1083 int rc;
1084 ulong linear;
1085
1086 rc = linearize(ctxt, addr, size, true, &linear);
1087 if (rc != X86EMUL_CONTINUE)
1088 return rc;
1089 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1090 &ctxt->exception);
1091 }
1092
1093 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1094 struct segmented_address addr,
1095 const void *orig_data, const void *data,
1096 unsigned size)
1097 {
1098 int rc;
1099 ulong linear;
1100
1101 rc = linearize(ctxt, addr, size, true, &linear);
1102 if (rc != X86EMUL_CONTINUE)
1103 return rc;
1104 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1105 size, &ctxt->exception);
1106 }
1107
1108 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1109 struct x86_emulate_ops *ops,
1110 unsigned int size, unsigned short port,
1111 void *dest)
1112 {
1113 struct read_cache *rc = &ctxt->decode.io_read;
1114
1115 if (rc->pos == rc->end) { /* refill pio read ahead */
1116 struct decode_cache *c = &ctxt->decode;
1117 unsigned int in_page, n;
1118 unsigned int count = c->rep_prefix ?
1119 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1120 in_page = (ctxt->eflags & EFLG_DF) ?
1121 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1122 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1123 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1124 count);
1125 if (n == 0)
1126 n = 1;
1127 rc->pos = rc->end = 0;
1128 if (!ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1129 return 0;
1130 rc->end = n * size;
1131 }
1132
1133 memcpy(dest, rc->data + rc->pos, size);
1134 rc->pos += size;
1135 return 1;
1136 }
1137
1138 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1139 struct x86_emulate_ops *ops,
1140 u16 selector, struct desc_ptr *dt)
1141 {
1142 if (selector & 1 << 2) {
1143 struct desc_struct desc;
1144 memset (dt, 0, sizeof *dt);
1145 if (!ops->get_cached_descriptor(ctxt, &desc, NULL,
1146 VCPU_SREG_LDTR))
1147 return;
1148
1149 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1150 dt->address = get_desc_base(&desc);
1151 } else
1152 ops->get_gdt(ctxt, dt);
1153 }
1154
1155 /* allowed just for 8 bytes segments */
1156 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1157 struct x86_emulate_ops *ops,
1158 u16 selector, struct desc_struct *desc)
1159 {
1160 struct desc_ptr dt;
1161 u16 index = selector >> 3;
1162 int ret;
1163 ulong addr;
1164
1165 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1166
1167 if (dt.size < index * 8 + 7)
1168 return emulate_gp(ctxt, selector & 0xfffc);
1169 addr = dt.address + index * 8;
1170 ret = ops->read_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
1171
1172 return ret;
1173 }
1174
1175 /* allowed just for 8 bytes segments */
1176 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1177 struct x86_emulate_ops *ops,
1178 u16 selector, struct desc_struct *desc)
1179 {
1180 struct desc_ptr dt;
1181 u16 index = selector >> 3;
1182 ulong addr;
1183 int ret;
1184
1185 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1186
1187 if (dt.size < index * 8 + 7)
1188 return emulate_gp(ctxt, selector & 0xfffc);
1189
1190 addr = dt.address + index * 8;
1191 ret = ops->write_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
1192
1193 return ret;
1194 }
1195
1196 /* Does not support long mode */
1197 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1198 struct x86_emulate_ops *ops,
1199 u16 selector, int seg)
1200 {
1201 struct desc_struct seg_desc;
1202 u8 dpl, rpl, cpl;
1203 unsigned err_vec = GP_VECTOR;
1204 u32 err_code = 0;
1205 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1206 int ret;
1207
1208 memset(&seg_desc, 0, sizeof seg_desc);
1209
1210 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1211 || ctxt->mode == X86EMUL_MODE_REAL) {
1212 /* set real mode segment descriptor */
1213 set_desc_base(&seg_desc, selector << 4);
1214 set_desc_limit(&seg_desc, 0xffff);
1215 seg_desc.type = 3;
1216 seg_desc.p = 1;
1217 seg_desc.s = 1;
1218 goto load;
1219 }
1220
1221 /* NULL selector is not valid for TR, CS and SS */
1222 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1223 && null_selector)
1224 goto exception;
1225
1226 /* TR should be in GDT only */
1227 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1228 goto exception;
1229
1230 if (null_selector) /* for NULL selector skip all following checks */
1231 goto load;
1232
1233 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1234 if (ret != X86EMUL_CONTINUE)
1235 return ret;
1236
1237 err_code = selector & 0xfffc;
1238 err_vec = GP_VECTOR;
1239
1240 /* can't load system descriptor into segment selecor */
1241 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1242 goto exception;
1243
1244 if (!seg_desc.p) {
1245 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1246 goto exception;
1247 }
1248
1249 rpl = selector & 3;
1250 dpl = seg_desc.dpl;
1251 cpl = ops->cpl(ctxt);
1252
1253 switch (seg) {
1254 case VCPU_SREG_SS:
1255 /*
1256 * segment is not a writable data segment or segment
1257 * selector's RPL != CPL or segment selector's RPL != CPL
1258 */
1259 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1260 goto exception;
1261 break;
1262 case VCPU_SREG_CS:
1263 if (!(seg_desc.type & 8))
1264 goto exception;
1265
1266 if (seg_desc.type & 4) {
1267 /* conforming */
1268 if (dpl > cpl)
1269 goto exception;
1270 } else {
1271 /* nonconforming */
1272 if (rpl > cpl || dpl != cpl)
1273 goto exception;
1274 }
1275 /* CS(RPL) <- CPL */
1276 selector = (selector & 0xfffc) | cpl;
1277 break;
1278 case VCPU_SREG_TR:
1279 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1280 goto exception;
1281 break;
1282 case VCPU_SREG_LDTR:
1283 if (seg_desc.s || seg_desc.type != 2)
1284 goto exception;
1285 break;
1286 default: /* DS, ES, FS, or GS */
1287 /*
1288 * segment is not a data or readable code segment or
1289 * ((segment is a data or nonconforming code segment)
1290 * and (both RPL and CPL > DPL))
1291 */
1292 if ((seg_desc.type & 0xa) == 0x8 ||
1293 (((seg_desc.type & 0xc) != 0xc) &&
1294 (rpl > dpl && cpl > dpl)))
1295 goto exception;
1296 break;
1297 }
1298
1299 if (seg_desc.s) {
1300 /* mark segment as accessed */
1301 seg_desc.type |= 1;
1302 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1303 if (ret != X86EMUL_CONTINUE)
1304 return ret;
1305 }
1306 load:
1307 ops->set_segment_selector(ctxt, selector, seg);
1308 ops->set_cached_descriptor(ctxt, &seg_desc, 0, seg);
1309 return X86EMUL_CONTINUE;
1310 exception:
1311 emulate_exception(ctxt, err_vec, err_code, true);
1312 return X86EMUL_PROPAGATE_FAULT;
1313 }
1314
1315 static void write_register_operand(struct operand *op)
1316 {
1317 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1318 switch (op->bytes) {
1319 case 1:
1320 *(u8 *)op->addr.reg = (u8)op->val;
1321 break;
1322 case 2:
1323 *(u16 *)op->addr.reg = (u16)op->val;
1324 break;
1325 case 4:
1326 *op->addr.reg = (u32)op->val;
1327 break; /* 64b: zero-extend */
1328 case 8:
1329 *op->addr.reg = op->val;
1330 break;
1331 }
1332 }
1333
1334 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1335 struct x86_emulate_ops *ops)
1336 {
1337 int rc;
1338 struct decode_cache *c = &ctxt->decode;
1339
1340 switch (c->dst.type) {
1341 case OP_REG:
1342 write_register_operand(&c->dst);
1343 break;
1344 case OP_MEM:
1345 if (c->lock_prefix)
1346 rc = segmented_cmpxchg(ctxt,
1347 c->dst.addr.mem,
1348 &c->dst.orig_val,
1349 &c->dst.val,
1350 c->dst.bytes);
1351 else
1352 rc = segmented_write(ctxt,
1353 c->dst.addr.mem,
1354 &c->dst.val,
1355 c->dst.bytes);
1356 if (rc != X86EMUL_CONTINUE)
1357 return rc;
1358 break;
1359 case OP_XMM:
1360 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1361 break;
1362 case OP_NONE:
1363 /* no writeback */
1364 break;
1365 default:
1366 break;
1367 }
1368 return X86EMUL_CONTINUE;
1369 }
1370
1371 static int em_push(struct x86_emulate_ctxt *ctxt)
1372 {
1373 struct decode_cache *c = &ctxt->decode;
1374 struct segmented_address addr;
1375
1376 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1377 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1378 addr.seg = VCPU_SREG_SS;
1379
1380 /* Disable writeback. */
1381 c->dst.type = OP_NONE;
1382 return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
1383 }
1384
1385 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1386 struct x86_emulate_ops *ops,
1387 void *dest, int len)
1388 {
1389 struct decode_cache *c = &ctxt->decode;
1390 int rc;
1391 struct segmented_address addr;
1392
1393 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1394 addr.seg = VCPU_SREG_SS;
1395 rc = segmented_read(ctxt, addr, dest, len);
1396 if (rc != X86EMUL_CONTINUE)
1397 return rc;
1398
1399 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1400 return rc;
1401 }
1402
1403 static int em_pop(struct x86_emulate_ctxt *ctxt)
1404 {
1405 struct decode_cache *c = &ctxt->decode;
1406
1407 return emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
1408 }
1409
1410 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1411 struct x86_emulate_ops *ops,
1412 void *dest, int len)
1413 {
1414 int rc;
1415 unsigned long val, change_mask;
1416 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1417 int cpl = ops->cpl(ctxt);
1418
1419 rc = emulate_pop(ctxt, ops, &val, len);
1420 if (rc != X86EMUL_CONTINUE)
1421 return rc;
1422
1423 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1424 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1425
1426 switch(ctxt->mode) {
1427 case X86EMUL_MODE_PROT64:
1428 case X86EMUL_MODE_PROT32:
1429 case X86EMUL_MODE_PROT16:
1430 if (cpl == 0)
1431 change_mask |= EFLG_IOPL;
1432 if (cpl <= iopl)
1433 change_mask |= EFLG_IF;
1434 break;
1435 case X86EMUL_MODE_VM86:
1436 if (iopl < 3)
1437 return emulate_gp(ctxt, 0);
1438 change_mask |= EFLG_IF;
1439 break;
1440 default: /* real mode */
1441 change_mask |= (EFLG_IOPL | EFLG_IF);
1442 break;
1443 }
1444
1445 *(unsigned long *)dest =
1446 (ctxt->eflags & ~change_mask) | (val & change_mask);
1447
1448 return rc;
1449 }
1450
1451 static int em_popf(struct x86_emulate_ctxt *ctxt)
1452 {
1453 struct decode_cache *c = &ctxt->decode;
1454
1455 c->dst.type = OP_REG;
1456 c->dst.addr.reg = &ctxt->eflags;
1457 c->dst.bytes = c->op_bytes;
1458 return emulate_popf(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
1459 }
1460
1461 static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1462 struct x86_emulate_ops *ops, int seg)
1463 {
1464 struct decode_cache *c = &ctxt->decode;
1465
1466 c->src.val = ops->get_segment_selector(ctxt, seg);
1467
1468 return em_push(ctxt);
1469 }
1470
1471 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1472 struct x86_emulate_ops *ops, int seg)
1473 {
1474 struct decode_cache *c = &ctxt->decode;
1475 unsigned long selector;
1476 int rc;
1477
1478 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1479 if (rc != X86EMUL_CONTINUE)
1480 return rc;
1481
1482 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1483 return rc;
1484 }
1485
1486 static int em_pusha(struct x86_emulate_ctxt *ctxt)
1487 {
1488 struct decode_cache *c = &ctxt->decode;
1489 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1490 int rc = X86EMUL_CONTINUE;
1491 int reg = VCPU_REGS_RAX;
1492
1493 while (reg <= VCPU_REGS_RDI) {
1494 (reg == VCPU_REGS_RSP) ?
1495 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1496
1497 rc = em_push(ctxt);
1498 if (rc != X86EMUL_CONTINUE)
1499 return rc;
1500
1501 ++reg;
1502 }
1503
1504 return rc;
1505 }
1506
1507 static int em_pushf(struct x86_emulate_ctxt *ctxt)
1508 {
1509 struct decode_cache *c = &ctxt->decode;
1510
1511 c->src.val = (unsigned long)ctxt->eflags;
1512 return em_push(ctxt);
1513 }
1514
1515 static int em_popa(struct x86_emulate_ctxt *ctxt)
1516 {
1517 struct decode_cache *c = &ctxt->decode;
1518 int rc = X86EMUL_CONTINUE;
1519 int reg = VCPU_REGS_RDI;
1520
1521 while (reg >= VCPU_REGS_RAX) {
1522 if (reg == VCPU_REGS_RSP) {
1523 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1524 c->op_bytes);
1525 --reg;
1526 }
1527
1528 rc = emulate_pop(ctxt, ctxt->ops, &c->regs[reg], c->op_bytes);
1529 if (rc != X86EMUL_CONTINUE)
1530 break;
1531 --reg;
1532 }
1533 return rc;
1534 }
1535
1536 int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1537 struct x86_emulate_ops *ops, int irq)
1538 {
1539 struct decode_cache *c = &ctxt->decode;
1540 int rc;
1541 struct desc_ptr dt;
1542 gva_t cs_addr;
1543 gva_t eip_addr;
1544 u16 cs, eip;
1545
1546 /* TODO: Add limit checks */
1547 c->src.val = ctxt->eflags;
1548 rc = em_push(ctxt);
1549 if (rc != X86EMUL_CONTINUE)
1550 return rc;
1551
1552 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1553
1554 c->src.val = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
1555 rc = em_push(ctxt);
1556 if (rc != X86EMUL_CONTINUE)
1557 return rc;
1558
1559 c->src.val = c->eip;
1560 rc = em_push(ctxt);
1561 if (rc != X86EMUL_CONTINUE)
1562 return rc;
1563
1564 ops->get_idt(ctxt, &dt);
1565
1566 eip_addr = dt.address + (irq << 2);
1567 cs_addr = dt.address + (irq << 2) + 2;
1568
1569 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1570 if (rc != X86EMUL_CONTINUE)
1571 return rc;
1572
1573 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1574 if (rc != X86EMUL_CONTINUE)
1575 return rc;
1576
1577 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1578 if (rc != X86EMUL_CONTINUE)
1579 return rc;
1580
1581 c->eip = eip;
1582
1583 return rc;
1584 }
1585
1586 static int emulate_int(struct x86_emulate_ctxt *ctxt,
1587 struct x86_emulate_ops *ops, int irq)
1588 {
1589 switch(ctxt->mode) {
1590 case X86EMUL_MODE_REAL:
1591 return emulate_int_real(ctxt, ops, irq);
1592 case X86EMUL_MODE_VM86:
1593 case X86EMUL_MODE_PROT16:
1594 case X86EMUL_MODE_PROT32:
1595 case X86EMUL_MODE_PROT64:
1596 default:
1597 /* Protected mode interrupts unimplemented yet */
1598 return X86EMUL_UNHANDLEABLE;
1599 }
1600 }
1601
1602 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1603 struct x86_emulate_ops *ops)
1604 {
1605 struct decode_cache *c = &ctxt->decode;
1606 int rc = X86EMUL_CONTINUE;
1607 unsigned long temp_eip = 0;
1608 unsigned long temp_eflags = 0;
1609 unsigned long cs = 0;
1610 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1611 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1612 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1613 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1614
1615 /* TODO: Add stack limit check */
1616
1617 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1618
1619 if (rc != X86EMUL_CONTINUE)
1620 return rc;
1621
1622 if (temp_eip & ~0xffff)
1623 return emulate_gp(ctxt, 0);
1624
1625 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1626
1627 if (rc != X86EMUL_CONTINUE)
1628 return rc;
1629
1630 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1631
1632 if (rc != X86EMUL_CONTINUE)
1633 return rc;
1634
1635 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1636
1637 if (rc != X86EMUL_CONTINUE)
1638 return rc;
1639
1640 c->eip = temp_eip;
1641
1642
1643 if (c->op_bytes == 4)
1644 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1645 else if (c->op_bytes == 2) {
1646 ctxt->eflags &= ~0xffff;
1647 ctxt->eflags |= temp_eflags;
1648 }
1649
1650 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1651 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1652
1653 return rc;
1654 }
1655
1656 static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1657 struct x86_emulate_ops* ops)
1658 {
1659 switch(ctxt->mode) {
1660 case X86EMUL_MODE_REAL:
1661 return emulate_iret_real(ctxt, ops);
1662 case X86EMUL_MODE_VM86:
1663 case X86EMUL_MODE_PROT16:
1664 case X86EMUL_MODE_PROT32:
1665 case X86EMUL_MODE_PROT64:
1666 default:
1667 /* iret from protected mode unimplemented yet */
1668 return X86EMUL_UNHANDLEABLE;
1669 }
1670 }
1671
1672 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1673 struct x86_emulate_ops *ops)
1674 {
1675 struct decode_cache *c = &ctxt->decode;
1676
1677 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1678 }
1679
1680 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1681 {
1682 struct decode_cache *c = &ctxt->decode;
1683 switch (c->modrm_reg) {
1684 case 0: /* rol */
1685 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1686 break;
1687 case 1: /* ror */
1688 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1689 break;
1690 case 2: /* rcl */
1691 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1692 break;
1693 case 3: /* rcr */
1694 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1695 break;
1696 case 4: /* sal/shl */
1697 case 6: /* sal/shl */
1698 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1699 break;
1700 case 5: /* shr */
1701 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1702 break;
1703 case 7: /* sar */
1704 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1705 break;
1706 }
1707 }
1708
1709 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1710 struct x86_emulate_ops *ops)
1711 {
1712 struct decode_cache *c = &ctxt->decode;
1713 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1714 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
1715 u8 de = 0;
1716
1717 switch (c->modrm_reg) {
1718 case 0 ... 1: /* test */
1719 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1720 break;
1721 case 2: /* not */
1722 c->dst.val = ~c->dst.val;
1723 break;
1724 case 3: /* neg */
1725 emulate_1op("neg", c->dst, ctxt->eflags);
1726 break;
1727 case 4: /* mul */
1728 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1729 break;
1730 case 5: /* imul */
1731 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1732 break;
1733 case 6: /* div */
1734 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1735 ctxt->eflags, de);
1736 break;
1737 case 7: /* idiv */
1738 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1739 ctxt->eflags, de);
1740 break;
1741 default:
1742 return X86EMUL_UNHANDLEABLE;
1743 }
1744 if (de)
1745 return emulate_de(ctxt);
1746 return X86EMUL_CONTINUE;
1747 }
1748
1749 static int emulate_grp45(struct x86_emulate_ctxt *ctxt)
1750 {
1751 struct decode_cache *c = &ctxt->decode;
1752 int rc = X86EMUL_CONTINUE;
1753
1754 switch (c->modrm_reg) {
1755 case 0: /* inc */
1756 emulate_1op("inc", c->dst, ctxt->eflags);
1757 break;
1758 case 1: /* dec */
1759 emulate_1op("dec", c->dst, ctxt->eflags);
1760 break;
1761 case 2: /* call near abs */ {
1762 long int old_eip;
1763 old_eip = c->eip;
1764 c->eip = c->src.val;
1765 c->src.val = old_eip;
1766 rc = em_push(ctxt);
1767 break;
1768 }
1769 case 4: /* jmp abs */
1770 c->eip = c->src.val;
1771 break;
1772 case 6: /* push */
1773 rc = em_push(ctxt);
1774 break;
1775 }
1776 return rc;
1777 }
1778
1779 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1780 struct x86_emulate_ops *ops)
1781 {
1782 struct decode_cache *c = &ctxt->decode;
1783 u64 old = c->dst.orig_val64;
1784
1785 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1786 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1787 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1788 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1789 ctxt->eflags &= ~EFLG_ZF;
1790 } else {
1791 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1792 (u32) c->regs[VCPU_REGS_RBX];
1793
1794 ctxt->eflags |= EFLG_ZF;
1795 }
1796 return X86EMUL_CONTINUE;
1797 }
1798
1799 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1800 struct x86_emulate_ops *ops)
1801 {
1802 struct decode_cache *c = &ctxt->decode;
1803 int rc;
1804 unsigned long cs;
1805
1806 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1807 if (rc != X86EMUL_CONTINUE)
1808 return rc;
1809 if (c->op_bytes == 4)
1810 c->eip = (u32)c->eip;
1811 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1812 if (rc != X86EMUL_CONTINUE)
1813 return rc;
1814 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1815 return rc;
1816 }
1817
1818 static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1819 struct x86_emulate_ops *ops, int seg)
1820 {
1821 struct decode_cache *c = &ctxt->decode;
1822 unsigned short sel;
1823 int rc;
1824
1825 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1826
1827 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1828 if (rc != X86EMUL_CONTINUE)
1829 return rc;
1830
1831 c->dst.val = c->src.val;
1832 return rc;
1833 }
1834
1835 static inline void
1836 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1837 struct x86_emulate_ops *ops, struct desc_struct *cs,
1838 struct desc_struct *ss)
1839 {
1840 memset(cs, 0, sizeof(struct desc_struct));
1841 ops->get_cached_descriptor(ctxt, cs, NULL, VCPU_SREG_CS);
1842 memset(ss, 0, sizeof(struct desc_struct));
1843
1844 cs->l = 0; /* will be adjusted later */
1845 set_desc_base(cs, 0); /* flat segment */
1846 cs->g = 1; /* 4kb granularity */
1847 set_desc_limit(cs, 0xfffff); /* 4GB limit */
1848 cs->type = 0x0b; /* Read, Execute, Accessed */
1849 cs->s = 1;
1850 cs->dpl = 0; /* will be adjusted later */
1851 cs->p = 1;
1852 cs->d = 1;
1853
1854 set_desc_base(ss, 0); /* flat segment */
1855 set_desc_limit(ss, 0xfffff); /* 4GB limit */
1856 ss->g = 1; /* 4kb granularity */
1857 ss->s = 1;
1858 ss->type = 0x03; /* Read/Write, Accessed */
1859 ss->d = 1; /* 32bit stack segment */
1860 ss->dpl = 0;
1861 ss->p = 1;
1862 }
1863
1864 static int
1865 emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1866 {
1867 struct decode_cache *c = &ctxt->decode;
1868 struct desc_struct cs, ss;
1869 u64 msr_data;
1870 u16 cs_sel, ss_sel;
1871 u64 efer = 0;
1872
1873 /* syscall is not available in real mode */
1874 if (ctxt->mode == X86EMUL_MODE_REAL ||
1875 ctxt->mode == X86EMUL_MODE_VM86)
1876 return emulate_ud(ctxt);
1877
1878 ops->get_msr(ctxt, MSR_EFER, &efer);
1879 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1880
1881 ops->get_msr(ctxt, MSR_STAR, &msr_data);
1882 msr_data >>= 32;
1883 cs_sel = (u16)(msr_data & 0xfffc);
1884 ss_sel = (u16)(msr_data + 8);
1885
1886 if (efer & EFER_LMA) {
1887 cs.d = 0;
1888 cs.l = 1;
1889 }
1890 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1891 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1892 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1893 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
1894
1895 c->regs[VCPU_REGS_RCX] = c->eip;
1896 if (efer & EFER_LMA) {
1897 #ifdef CONFIG_X86_64
1898 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1899
1900 ops->get_msr(ctxt,
1901 ctxt->mode == X86EMUL_MODE_PROT64 ?
1902 MSR_LSTAR : MSR_CSTAR, &msr_data);
1903 c->eip = msr_data;
1904
1905 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
1906 ctxt->eflags &= ~(msr_data | EFLG_RF);
1907 #endif
1908 } else {
1909 /* legacy mode */
1910 ops->get_msr(ctxt, MSR_STAR, &msr_data);
1911 c->eip = (u32)msr_data;
1912
1913 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1914 }
1915
1916 return X86EMUL_CONTINUE;
1917 }
1918
1919 static int
1920 emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1921 {
1922 struct decode_cache *c = &ctxt->decode;
1923 struct desc_struct cs, ss;
1924 u64 msr_data;
1925 u16 cs_sel, ss_sel;
1926 u64 efer = 0;
1927
1928 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1929 /* inject #GP if in real mode */
1930 if (ctxt->mode == X86EMUL_MODE_REAL)
1931 return emulate_gp(ctxt, 0);
1932
1933 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1934 * Therefore, we inject an #UD.
1935 */
1936 if (ctxt->mode == X86EMUL_MODE_PROT64)
1937 return emulate_ud(ctxt);
1938
1939 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1940
1941 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
1942 switch (ctxt->mode) {
1943 case X86EMUL_MODE_PROT32:
1944 if ((msr_data & 0xfffc) == 0x0)
1945 return emulate_gp(ctxt, 0);
1946 break;
1947 case X86EMUL_MODE_PROT64:
1948 if (msr_data == 0x0)
1949 return emulate_gp(ctxt, 0);
1950 break;
1951 }
1952
1953 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1954 cs_sel = (u16)msr_data;
1955 cs_sel &= ~SELECTOR_RPL_MASK;
1956 ss_sel = cs_sel + 8;
1957 ss_sel &= ~SELECTOR_RPL_MASK;
1958 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
1959 cs.d = 0;
1960 cs.l = 1;
1961 }
1962
1963 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1964 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1965 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1966 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
1967
1968 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
1969 c->eip = msr_data;
1970
1971 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
1972 c->regs[VCPU_REGS_RSP] = msr_data;
1973
1974 return X86EMUL_CONTINUE;
1975 }
1976
1977 static int
1978 emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1979 {
1980 struct decode_cache *c = &ctxt->decode;
1981 struct desc_struct cs, ss;
1982 u64 msr_data;
1983 int usermode;
1984 u16 cs_sel, ss_sel;
1985
1986 /* inject #GP if in real mode or Virtual 8086 mode */
1987 if (ctxt->mode == X86EMUL_MODE_REAL ||
1988 ctxt->mode == X86EMUL_MODE_VM86)
1989 return emulate_gp(ctxt, 0);
1990
1991 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1992
1993 if ((c->rex_prefix & 0x8) != 0x0)
1994 usermode = X86EMUL_MODE_PROT64;
1995 else
1996 usermode = X86EMUL_MODE_PROT32;
1997
1998 cs.dpl = 3;
1999 ss.dpl = 3;
2000 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2001 switch (usermode) {
2002 case X86EMUL_MODE_PROT32:
2003 cs_sel = (u16)(msr_data + 16);
2004 if ((msr_data & 0xfffc) == 0x0)
2005 return emulate_gp(ctxt, 0);
2006 ss_sel = (u16)(msr_data + 24);
2007 break;
2008 case X86EMUL_MODE_PROT64:
2009 cs_sel = (u16)(msr_data + 32);
2010 if (msr_data == 0x0)
2011 return emulate_gp(ctxt, 0);
2012 ss_sel = cs_sel + 8;
2013 cs.d = 0;
2014 cs.l = 1;
2015 break;
2016 }
2017 cs_sel |= SELECTOR_RPL_MASK;
2018 ss_sel |= SELECTOR_RPL_MASK;
2019
2020 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
2021 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
2022 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
2023 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
2024
2025 c->eip = c->regs[VCPU_REGS_RDX];
2026 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
2027
2028 return X86EMUL_CONTINUE;
2029 }
2030
2031 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2032 struct x86_emulate_ops *ops)
2033 {
2034 int iopl;
2035 if (ctxt->mode == X86EMUL_MODE_REAL)
2036 return false;
2037 if (ctxt->mode == X86EMUL_MODE_VM86)
2038 return true;
2039 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2040 return ops->cpl(ctxt) > iopl;
2041 }
2042
2043 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2044 struct x86_emulate_ops *ops,
2045 u16 port, u16 len)
2046 {
2047 struct desc_struct tr_seg;
2048 u32 base3;
2049 int r;
2050 u16 io_bitmap_ptr, perm, bit_idx = port & 0x7;
2051 unsigned mask = (1 << len) - 1;
2052 unsigned long base;
2053
2054 ops->get_cached_descriptor(ctxt, &tr_seg, &base3, VCPU_SREG_TR);
2055 if (!tr_seg.p)
2056 return false;
2057 if (desc_limit_scaled(&tr_seg) < 103)
2058 return false;
2059 base = get_desc_base(&tr_seg);
2060 #ifdef CONFIG_X86_64
2061 base |= ((u64)base3) << 32;
2062 #endif
2063 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2064 if (r != X86EMUL_CONTINUE)
2065 return false;
2066 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2067 return false;
2068 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2069 if (r != X86EMUL_CONTINUE)
2070 return false;
2071 if ((perm >> bit_idx) & mask)
2072 return false;
2073 return true;
2074 }
2075
2076 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2077 struct x86_emulate_ops *ops,
2078 u16 port, u16 len)
2079 {
2080 if (ctxt->perm_ok)
2081 return true;
2082
2083 if (emulator_bad_iopl(ctxt, ops))
2084 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2085 return false;
2086
2087 ctxt->perm_ok = true;
2088
2089 return true;
2090 }
2091
2092 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2093 struct x86_emulate_ops *ops,
2094 struct tss_segment_16 *tss)
2095 {
2096 struct decode_cache *c = &ctxt->decode;
2097
2098 tss->ip = c->eip;
2099 tss->flag = ctxt->eflags;
2100 tss->ax = c->regs[VCPU_REGS_RAX];
2101 tss->cx = c->regs[VCPU_REGS_RCX];
2102 tss->dx = c->regs[VCPU_REGS_RDX];
2103 tss->bx = c->regs[VCPU_REGS_RBX];
2104 tss->sp = c->regs[VCPU_REGS_RSP];
2105 tss->bp = c->regs[VCPU_REGS_RBP];
2106 tss->si = c->regs[VCPU_REGS_RSI];
2107 tss->di = c->regs[VCPU_REGS_RDI];
2108
2109 tss->es = ops->get_segment_selector(ctxt, VCPU_SREG_ES);
2110 tss->cs = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2111 tss->ss = ops->get_segment_selector(ctxt, VCPU_SREG_SS);
2112 tss->ds = ops->get_segment_selector(ctxt, VCPU_SREG_DS);
2113 tss->ldt = ops->get_segment_selector(ctxt, VCPU_SREG_LDTR);
2114 }
2115
2116 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2117 struct x86_emulate_ops *ops,
2118 struct tss_segment_16 *tss)
2119 {
2120 struct decode_cache *c = &ctxt->decode;
2121 int ret;
2122
2123 c->eip = tss->ip;
2124 ctxt->eflags = tss->flag | 2;
2125 c->regs[VCPU_REGS_RAX] = tss->ax;
2126 c->regs[VCPU_REGS_RCX] = tss->cx;
2127 c->regs[VCPU_REGS_RDX] = tss->dx;
2128 c->regs[VCPU_REGS_RBX] = tss->bx;
2129 c->regs[VCPU_REGS_RSP] = tss->sp;
2130 c->regs[VCPU_REGS_RBP] = tss->bp;
2131 c->regs[VCPU_REGS_RSI] = tss->si;
2132 c->regs[VCPU_REGS_RDI] = tss->di;
2133
2134 /*
2135 * SDM says that segment selectors are loaded before segment
2136 * descriptors
2137 */
2138 ops->set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2139 ops->set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2140 ops->set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2141 ops->set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2142 ops->set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2143
2144 /*
2145 * Now load segment descriptors. If fault happenes at this stage
2146 * it is handled in a context of new task
2147 */
2148 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2149 if (ret != X86EMUL_CONTINUE)
2150 return ret;
2151 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2152 if (ret != X86EMUL_CONTINUE)
2153 return ret;
2154 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2155 if (ret != X86EMUL_CONTINUE)
2156 return ret;
2157 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2158 if (ret != X86EMUL_CONTINUE)
2159 return ret;
2160 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2161 if (ret != X86EMUL_CONTINUE)
2162 return ret;
2163
2164 return X86EMUL_CONTINUE;
2165 }
2166
2167 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2168 struct x86_emulate_ops *ops,
2169 u16 tss_selector, u16 old_tss_sel,
2170 ulong old_tss_base, struct desc_struct *new_desc)
2171 {
2172 struct tss_segment_16 tss_seg;
2173 int ret;
2174 u32 new_tss_base = get_desc_base(new_desc);
2175
2176 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2177 &ctxt->exception);
2178 if (ret != X86EMUL_CONTINUE)
2179 /* FIXME: need to provide precise fault address */
2180 return ret;
2181
2182 save_state_to_tss16(ctxt, ops, &tss_seg);
2183
2184 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2185 &ctxt->exception);
2186 if (ret != X86EMUL_CONTINUE)
2187 /* FIXME: need to provide precise fault address */
2188 return ret;
2189
2190 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2191 &ctxt->exception);
2192 if (ret != X86EMUL_CONTINUE)
2193 /* FIXME: need to provide precise fault address */
2194 return ret;
2195
2196 if (old_tss_sel != 0xffff) {
2197 tss_seg.prev_task_link = old_tss_sel;
2198
2199 ret = ops->write_std(ctxt, new_tss_base,
2200 &tss_seg.prev_task_link,
2201 sizeof tss_seg.prev_task_link,
2202 &ctxt->exception);
2203 if (ret != X86EMUL_CONTINUE)
2204 /* FIXME: need to provide precise fault address */
2205 return ret;
2206 }
2207
2208 return load_state_from_tss16(ctxt, ops, &tss_seg);
2209 }
2210
2211 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2212 struct x86_emulate_ops *ops,
2213 struct tss_segment_32 *tss)
2214 {
2215 struct decode_cache *c = &ctxt->decode;
2216
2217 tss->cr3 = ops->get_cr(ctxt, 3);
2218 tss->eip = c->eip;
2219 tss->eflags = ctxt->eflags;
2220 tss->eax = c->regs[VCPU_REGS_RAX];
2221 tss->ecx = c->regs[VCPU_REGS_RCX];
2222 tss->edx = c->regs[VCPU_REGS_RDX];
2223 tss->ebx = c->regs[VCPU_REGS_RBX];
2224 tss->esp = c->regs[VCPU_REGS_RSP];
2225 tss->ebp = c->regs[VCPU_REGS_RBP];
2226 tss->esi = c->regs[VCPU_REGS_RSI];
2227 tss->edi = c->regs[VCPU_REGS_RDI];
2228
2229 tss->es = ops->get_segment_selector(ctxt, VCPU_SREG_ES);
2230 tss->cs = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2231 tss->ss = ops->get_segment_selector(ctxt, VCPU_SREG_SS);
2232 tss->ds = ops->get_segment_selector(ctxt, VCPU_SREG_DS);
2233 tss->fs = ops->get_segment_selector(ctxt, VCPU_SREG_FS);
2234 tss->gs = ops->get_segment_selector(ctxt, VCPU_SREG_GS);
2235 tss->ldt_selector = ops->get_segment_selector(ctxt, VCPU_SREG_LDTR);
2236 }
2237
2238 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2239 struct x86_emulate_ops *ops,
2240 struct tss_segment_32 *tss)
2241 {
2242 struct decode_cache *c = &ctxt->decode;
2243 int ret;
2244
2245 if (ops->set_cr(ctxt, 3, tss->cr3))
2246 return emulate_gp(ctxt, 0);
2247 c->eip = tss->eip;
2248 ctxt->eflags = tss->eflags | 2;
2249 c->regs[VCPU_REGS_RAX] = tss->eax;
2250 c->regs[VCPU_REGS_RCX] = tss->ecx;
2251 c->regs[VCPU_REGS_RDX] = tss->edx;
2252 c->regs[VCPU_REGS_RBX] = tss->ebx;
2253 c->regs[VCPU_REGS_RSP] = tss->esp;
2254 c->regs[VCPU_REGS_RBP] = tss->ebp;
2255 c->regs[VCPU_REGS_RSI] = tss->esi;
2256 c->regs[VCPU_REGS_RDI] = tss->edi;
2257
2258 /*
2259 * SDM says that segment selectors are loaded before segment
2260 * descriptors
2261 */
2262 ops->set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2263 ops->set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2264 ops->set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2265 ops->set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2266 ops->set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2267 ops->set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2268 ops->set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2269
2270 /*
2271 * Now load segment descriptors. If fault happenes at this stage
2272 * it is handled in a context of new task
2273 */
2274 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2275 if (ret != X86EMUL_CONTINUE)
2276 return ret;
2277 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2278 if (ret != X86EMUL_CONTINUE)
2279 return ret;
2280 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2281 if (ret != X86EMUL_CONTINUE)
2282 return ret;
2283 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2284 if (ret != X86EMUL_CONTINUE)
2285 return ret;
2286 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2287 if (ret != X86EMUL_CONTINUE)
2288 return ret;
2289 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2290 if (ret != X86EMUL_CONTINUE)
2291 return ret;
2292 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2293 if (ret != X86EMUL_CONTINUE)
2294 return ret;
2295
2296 return X86EMUL_CONTINUE;
2297 }
2298
2299 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2300 struct x86_emulate_ops *ops,
2301 u16 tss_selector, u16 old_tss_sel,
2302 ulong old_tss_base, struct desc_struct *new_desc)
2303 {
2304 struct tss_segment_32 tss_seg;
2305 int ret;
2306 u32 new_tss_base = get_desc_base(new_desc);
2307
2308 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2309 &ctxt->exception);
2310 if (ret != X86EMUL_CONTINUE)
2311 /* FIXME: need to provide precise fault address */
2312 return ret;
2313
2314 save_state_to_tss32(ctxt, ops, &tss_seg);
2315
2316 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2317 &ctxt->exception);
2318 if (ret != X86EMUL_CONTINUE)
2319 /* FIXME: need to provide precise fault address */
2320 return ret;
2321
2322 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2323 &ctxt->exception);
2324 if (ret != X86EMUL_CONTINUE)
2325 /* FIXME: need to provide precise fault address */
2326 return ret;
2327
2328 if (old_tss_sel != 0xffff) {
2329 tss_seg.prev_task_link = old_tss_sel;
2330
2331 ret = ops->write_std(ctxt, new_tss_base,
2332 &tss_seg.prev_task_link,
2333 sizeof tss_seg.prev_task_link,
2334 &ctxt->exception);
2335 if (ret != X86EMUL_CONTINUE)
2336 /* FIXME: need to provide precise fault address */
2337 return ret;
2338 }
2339
2340 return load_state_from_tss32(ctxt, ops, &tss_seg);
2341 }
2342
2343 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2344 struct x86_emulate_ops *ops,
2345 u16 tss_selector, int reason,
2346 bool has_error_code, u32 error_code)
2347 {
2348 struct desc_struct curr_tss_desc, next_tss_desc;
2349 int ret;
2350 u16 old_tss_sel = ops->get_segment_selector(ctxt, VCPU_SREG_TR);
2351 ulong old_tss_base =
2352 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2353 u32 desc_limit;
2354
2355 /* FIXME: old_tss_base == ~0 ? */
2356
2357 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2358 if (ret != X86EMUL_CONTINUE)
2359 return ret;
2360 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2361 if (ret != X86EMUL_CONTINUE)
2362 return ret;
2363
2364 /* FIXME: check that next_tss_desc is tss */
2365
2366 if (reason != TASK_SWITCH_IRET) {
2367 if ((tss_selector & 3) > next_tss_desc.dpl ||
2368 ops->cpl(ctxt) > next_tss_desc.dpl)
2369 return emulate_gp(ctxt, 0);
2370 }
2371
2372 desc_limit = desc_limit_scaled(&next_tss_desc);
2373 if (!next_tss_desc.p ||
2374 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2375 desc_limit < 0x2b)) {
2376 emulate_ts(ctxt, tss_selector & 0xfffc);
2377 return X86EMUL_PROPAGATE_FAULT;
2378 }
2379
2380 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2381 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2382 write_segment_descriptor(ctxt, ops, old_tss_sel,
2383 &curr_tss_desc);
2384 }
2385
2386 if (reason == TASK_SWITCH_IRET)
2387 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2388
2389 /* set back link to prev task only if NT bit is set in eflags
2390 note that old_tss_sel is not used afetr this point */
2391 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2392 old_tss_sel = 0xffff;
2393
2394 if (next_tss_desc.type & 8)
2395 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2396 old_tss_base, &next_tss_desc);
2397 else
2398 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2399 old_tss_base, &next_tss_desc);
2400 if (ret != X86EMUL_CONTINUE)
2401 return ret;
2402
2403 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2404 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2405
2406 if (reason != TASK_SWITCH_IRET) {
2407 next_tss_desc.type |= (1 << 1); /* set busy flag */
2408 write_segment_descriptor(ctxt, ops, tss_selector,
2409 &next_tss_desc);
2410 }
2411
2412 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
2413 ops->set_cached_descriptor(ctxt, &next_tss_desc, 0, VCPU_SREG_TR);
2414 ops->set_segment_selector(ctxt, tss_selector, VCPU_SREG_TR);
2415
2416 if (has_error_code) {
2417 struct decode_cache *c = &ctxt->decode;
2418
2419 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2420 c->lock_prefix = 0;
2421 c->src.val = (unsigned long) error_code;
2422 ret = em_push(ctxt);
2423 }
2424
2425 return ret;
2426 }
2427
2428 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2429 u16 tss_selector, int reason,
2430 bool has_error_code, u32 error_code)
2431 {
2432 struct x86_emulate_ops *ops = ctxt->ops;
2433 struct decode_cache *c = &ctxt->decode;
2434 int rc;
2435
2436 c->eip = ctxt->eip;
2437 c->dst.type = OP_NONE;
2438
2439 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2440 has_error_code, error_code);
2441
2442 if (rc == X86EMUL_CONTINUE)
2443 ctxt->eip = c->eip;
2444
2445 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2446 }
2447
2448 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
2449 int reg, struct operand *op)
2450 {
2451 struct decode_cache *c = &ctxt->decode;
2452 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2453
2454 register_address_increment(c, &c->regs[reg], df * op->bytes);
2455 op->addr.mem.ea = register_address(c, c->regs[reg]);
2456 op->addr.mem.seg = seg;
2457 }
2458
2459 static int em_das(struct x86_emulate_ctxt *ctxt)
2460 {
2461 struct decode_cache *c = &ctxt->decode;
2462 u8 al, old_al;
2463 bool af, cf, old_cf;
2464
2465 cf = ctxt->eflags & X86_EFLAGS_CF;
2466 al = c->dst.val;
2467
2468 old_al = al;
2469 old_cf = cf;
2470 cf = false;
2471 af = ctxt->eflags & X86_EFLAGS_AF;
2472 if ((al & 0x0f) > 9 || af) {
2473 al -= 6;
2474 cf = old_cf | (al >= 250);
2475 af = true;
2476 } else {
2477 af = false;
2478 }
2479 if (old_al > 0x99 || old_cf) {
2480 al -= 0x60;
2481 cf = true;
2482 }
2483
2484 c->dst.val = al;
2485 /* Set PF, ZF, SF */
2486 c->src.type = OP_IMM;
2487 c->src.val = 0;
2488 c->src.bytes = 1;
2489 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2490 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2491 if (cf)
2492 ctxt->eflags |= X86_EFLAGS_CF;
2493 if (af)
2494 ctxt->eflags |= X86_EFLAGS_AF;
2495 return X86EMUL_CONTINUE;
2496 }
2497
2498 static int em_call_far(struct x86_emulate_ctxt *ctxt)
2499 {
2500 struct decode_cache *c = &ctxt->decode;
2501 u16 sel, old_cs;
2502 ulong old_eip;
2503 int rc;
2504
2505 old_cs = ctxt->ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2506 old_eip = c->eip;
2507
2508 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2509 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2510 return X86EMUL_CONTINUE;
2511
2512 c->eip = 0;
2513 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2514
2515 c->src.val = old_cs;
2516 rc = em_push(ctxt);
2517 if (rc != X86EMUL_CONTINUE)
2518 return rc;
2519
2520 c->src.val = old_eip;
2521 return em_push(ctxt);
2522 }
2523
2524 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2525 {
2526 struct decode_cache *c = &ctxt->decode;
2527 int rc;
2528
2529 c->dst.type = OP_REG;
2530 c->dst.addr.reg = &c->eip;
2531 c->dst.bytes = c->op_bytes;
2532 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2533 if (rc != X86EMUL_CONTINUE)
2534 return rc;
2535 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2536 return X86EMUL_CONTINUE;
2537 }
2538
2539 static int em_add(struct x86_emulate_ctxt *ctxt)
2540 {
2541 struct decode_cache *c = &ctxt->decode;
2542
2543 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2544 return X86EMUL_CONTINUE;
2545 }
2546
2547 static int em_or(struct x86_emulate_ctxt *ctxt)
2548 {
2549 struct decode_cache *c = &ctxt->decode;
2550
2551 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2552 return X86EMUL_CONTINUE;
2553 }
2554
2555 static int em_adc(struct x86_emulate_ctxt *ctxt)
2556 {
2557 struct decode_cache *c = &ctxt->decode;
2558
2559 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2560 return X86EMUL_CONTINUE;
2561 }
2562
2563 static int em_sbb(struct x86_emulate_ctxt *ctxt)
2564 {
2565 struct decode_cache *c = &ctxt->decode;
2566
2567 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2568 return X86EMUL_CONTINUE;
2569 }
2570
2571 static int em_and(struct x86_emulate_ctxt *ctxt)
2572 {
2573 struct decode_cache *c = &ctxt->decode;
2574
2575 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2576 return X86EMUL_CONTINUE;
2577 }
2578
2579 static int em_sub(struct x86_emulate_ctxt *ctxt)
2580 {
2581 struct decode_cache *c = &ctxt->decode;
2582
2583 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2584 return X86EMUL_CONTINUE;
2585 }
2586
2587 static int em_xor(struct x86_emulate_ctxt *ctxt)
2588 {
2589 struct decode_cache *c = &ctxt->decode;
2590
2591 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2592 return X86EMUL_CONTINUE;
2593 }
2594
2595 static int em_cmp(struct x86_emulate_ctxt *ctxt)
2596 {
2597 struct decode_cache *c = &ctxt->decode;
2598
2599 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2600 /* Disable writeback. */
2601 c->dst.type = OP_NONE;
2602 return X86EMUL_CONTINUE;
2603 }
2604
2605 static int em_imul(struct x86_emulate_ctxt *ctxt)
2606 {
2607 struct decode_cache *c = &ctxt->decode;
2608
2609 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2610 return X86EMUL_CONTINUE;
2611 }
2612
2613 static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2614 {
2615 struct decode_cache *c = &ctxt->decode;
2616
2617 c->dst.val = c->src2.val;
2618 return em_imul(ctxt);
2619 }
2620
2621 static int em_cwd(struct x86_emulate_ctxt *ctxt)
2622 {
2623 struct decode_cache *c = &ctxt->decode;
2624
2625 c->dst.type = OP_REG;
2626 c->dst.bytes = c->src.bytes;
2627 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2628 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2629
2630 return X86EMUL_CONTINUE;
2631 }
2632
2633 static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2634 {
2635 struct decode_cache *c = &ctxt->decode;
2636 u64 tsc = 0;
2637
2638 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
2639 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2640 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2641 return X86EMUL_CONTINUE;
2642 }
2643
2644 static int em_mov(struct x86_emulate_ctxt *ctxt)
2645 {
2646 struct decode_cache *c = &ctxt->decode;
2647 c->dst.val = c->src.val;
2648 return X86EMUL_CONTINUE;
2649 }
2650
2651 static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2652 {
2653 struct decode_cache *c = &ctxt->decode;
2654 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2655 return X86EMUL_CONTINUE;
2656 }
2657
2658 static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2659 {
2660 struct decode_cache *c = &ctxt->decode;
2661 int rc;
2662 ulong linear;
2663
2664 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
2665 if (rc == X86EMUL_CONTINUE)
2666 ctxt->ops->invlpg(ctxt, linear);
2667 /* Disable writeback. */
2668 c->dst.type = OP_NONE;
2669 return X86EMUL_CONTINUE;
2670 }
2671
2672 static int em_clts(struct x86_emulate_ctxt *ctxt)
2673 {
2674 ulong cr0;
2675
2676 cr0 = ctxt->ops->get_cr(ctxt, 0);
2677 cr0 &= ~X86_CR0_TS;
2678 ctxt->ops->set_cr(ctxt, 0, cr0);
2679 return X86EMUL_CONTINUE;
2680 }
2681
2682 static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2683 {
2684 struct decode_cache *c = &ctxt->decode;
2685 int rc;
2686
2687 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2688 return X86EMUL_UNHANDLEABLE;
2689
2690 rc = ctxt->ops->fix_hypercall(ctxt);
2691 if (rc != X86EMUL_CONTINUE)
2692 return rc;
2693
2694 /* Let the processor re-execute the fixed hypercall */
2695 c->eip = ctxt->eip;
2696 /* Disable writeback. */
2697 c->dst.type = OP_NONE;
2698 return X86EMUL_CONTINUE;
2699 }
2700
2701 static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2702 {
2703 struct decode_cache *c = &ctxt->decode;
2704 struct desc_ptr desc_ptr;
2705 int rc;
2706
2707 rc = read_descriptor(ctxt, ctxt->ops, c->src.addr.mem,
2708 &desc_ptr.size, &desc_ptr.address,
2709 c->op_bytes);
2710 if (rc != X86EMUL_CONTINUE)
2711 return rc;
2712 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2713 /* Disable writeback. */
2714 c->dst.type = OP_NONE;
2715 return X86EMUL_CONTINUE;
2716 }
2717
2718 static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
2719 {
2720 struct decode_cache *c = &ctxt->decode;
2721 int rc;
2722
2723 rc = ctxt->ops->fix_hypercall(ctxt);
2724
2725 /* Disable writeback. */
2726 c->dst.type = OP_NONE;
2727 return rc;
2728 }
2729
2730 static int em_lidt(struct x86_emulate_ctxt *ctxt)
2731 {
2732 struct decode_cache *c = &ctxt->decode;
2733 struct desc_ptr desc_ptr;
2734 int rc;
2735
2736 rc = read_descriptor(ctxt, ctxt->ops, c->src.addr.mem,
2737 &desc_ptr.size,
2738 &desc_ptr.address,
2739 c->op_bytes);
2740 if (rc != X86EMUL_CONTINUE)
2741 return rc;
2742 ctxt->ops->set_idt(ctxt, &desc_ptr);
2743 /* Disable writeback. */
2744 c->dst.type = OP_NONE;
2745 return X86EMUL_CONTINUE;
2746 }
2747
2748 static int em_smsw(struct x86_emulate_ctxt *ctxt)
2749 {
2750 struct decode_cache *c = &ctxt->decode;
2751
2752 c->dst.bytes = 2;
2753 c->dst.val = ctxt->ops->get_cr(ctxt, 0);
2754 return X86EMUL_CONTINUE;
2755 }
2756
2757 static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2758 {
2759 struct decode_cache *c = &ctxt->decode;
2760 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
2761 | (c->src.val & 0x0f));
2762 c->dst.type = OP_NONE;
2763 return X86EMUL_CONTINUE;
2764 }
2765
2766 static bool valid_cr(int nr)
2767 {
2768 switch (nr) {
2769 case 0:
2770 case 2 ... 4:
2771 case 8:
2772 return true;
2773 default:
2774 return false;
2775 }
2776 }
2777
2778 static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2779 {
2780 struct decode_cache *c = &ctxt->decode;
2781
2782 if (!valid_cr(c->modrm_reg))
2783 return emulate_ud(ctxt);
2784
2785 return X86EMUL_CONTINUE;
2786 }
2787
2788 static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2789 {
2790 struct decode_cache *c = &ctxt->decode;
2791 u64 new_val = c->src.val64;
2792 int cr = c->modrm_reg;
2793 u64 efer = 0;
2794
2795 static u64 cr_reserved_bits[] = {
2796 0xffffffff00000000ULL,
2797 0, 0, 0, /* CR3 checked later */
2798 CR4_RESERVED_BITS,
2799 0, 0, 0,
2800 CR8_RESERVED_BITS,
2801 };
2802
2803 if (!valid_cr(cr))
2804 return emulate_ud(ctxt);
2805
2806 if (new_val & cr_reserved_bits[cr])
2807 return emulate_gp(ctxt, 0);
2808
2809 switch (cr) {
2810 case 0: {
2811 u64 cr4;
2812 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2813 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2814 return emulate_gp(ctxt, 0);
2815
2816 cr4 = ctxt->ops->get_cr(ctxt, 4);
2817 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2818
2819 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2820 !(cr4 & X86_CR4_PAE))
2821 return emulate_gp(ctxt, 0);
2822
2823 break;
2824 }
2825 case 3: {
2826 u64 rsvd = 0;
2827
2828 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2829 if (efer & EFER_LMA)
2830 rsvd = CR3_L_MODE_RESERVED_BITS;
2831 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
2832 rsvd = CR3_PAE_RESERVED_BITS;
2833 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
2834 rsvd = CR3_NONPAE_RESERVED_BITS;
2835
2836 if (new_val & rsvd)
2837 return emulate_gp(ctxt, 0);
2838
2839 break;
2840 }
2841 case 4: {
2842 u64 cr4;
2843
2844 cr4 = ctxt->ops->get_cr(ctxt, 4);
2845 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2846
2847 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2848 return emulate_gp(ctxt, 0);
2849
2850 break;
2851 }
2852 }
2853
2854 return X86EMUL_CONTINUE;
2855 }
2856
2857 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2858 {
2859 unsigned long dr7;
2860
2861 ctxt->ops->get_dr(ctxt, 7, &dr7);
2862
2863 /* Check if DR7.Global_Enable is set */
2864 return dr7 & (1 << 13);
2865 }
2866
2867 static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2868 {
2869 struct decode_cache *c = &ctxt->decode;
2870 int dr = c->modrm_reg;
2871 u64 cr4;
2872
2873 if (dr > 7)
2874 return emulate_ud(ctxt);
2875
2876 cr4 = ctxt->ops->get_cr(ctxt, 4);
2877 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2878 return emulate_ud(ctxt);
2879
2880 if (check_dr7_gd(ctxt))
2881 return emulate_db(ctxt);
2882
2883 return X86EMUL_CONTINUE;
2884 }
2885
2886 static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2887 {
2888 struct decode_cache *c = &ctxt->decode;
2889 u64 new_val = c->src.val64;
2890 int dr = c->modrm_reg;
2891
2892 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2893 return emulate_gp(ctxt, 0);
2894
2895 return check_dr_read(ctxt);
2896 }
2897
2898 static int check_svme(struct x86_emulate_ctxt *ctxt)
2899 {
2900 u64 efer;
2901
2902 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2903
2904 if (!(efer & EFER_SVME))
2905 return emulate_ud(ctxt);
2906
2907 return X86EMUL_CONTINUE;
2908 }
2909
2910 static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2911 {
2912 u64 rax = ctxt->decode.regs[VCPU_REGS_RAX];
2913
2914 /* Valid physical address? */
2915 if (rax & 0xffff000000000000ULL)
2916 return emulate_gp(ctxt, 0);
2917
2918 return check_svme(ctxt);
2919 }
2920
2921 static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2922 {
2923 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2924
2925 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
2926 return emulate_ud(ctxt);
2927
2928 return X86EMUL_CONTINUE;
2929 }
2930
2931 static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2932 {
2933 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2934 u64 rcx = ctxt->decode.regs[VCPU_REGS_RCX];
2935
2936 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
2937 (rcx > 3))
2938 return emulate_gp(ctxt, 0);
2939
2940 return X86EMUL_CONTINUE;
2941 }
2942
2943 static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2944 {
2945 struct decode_cache *c = &ctxt->decode;
2946
2947 c->dst.bytes = min(c->dst.bytes, 4u);
2948 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2949 return emulate_gp(ctxt, 0);
2950
2951 return X86EMUL_CONTINUE;
2952 }
2953
2954 static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2955 {
2956 struct decode_cache *c = &ctxt->decode;
2957
2958 c->src.bytes = min(c->src.bytes, 4u);
2959 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2960 return emulate_gp(ctxt, 0);
2961
2962 return X86EMUL_CONTINUE;
2963 }
2964
2965 #define D(_y) { .flags = (_y) }
2966 #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
2967 #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2968 .check_perm = (_p) }
2969 #define N D(0)
2970 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
2971 #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2972 #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2973 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2974 #define II(_f, _e, _i) \
2975 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
2976 #define IIP(_f, _e, _i, _p) \
2977 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2978 .check_perm = (_p) }
2979 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
2980
2981 #define D2bv(_f) D((_f) | ByteOp), D(_f)
2982 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
2983 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2984
2985 #define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
2986 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
2987 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
2988
2989 static struct opcode group7_rm1[] = {
2990 DI(SrcNone | ModRM | Priv, monitor),
2991 DI(SrcNone | ModRM | Priv, mwait),
2992 N, N, N, N, N, N,
2993 };
2994
2995 static struct opcode group7_rm3[] = {
2996 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
2997 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
2998 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
2999 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
3000 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
3001 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3002 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3003 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3004 };
3005
3006 static struct opcode group7_rm7[] = {
3007 N,
3008 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3009 N, N, N, N, N, N,
3010 };
3011
3012 static struct opcode group1[] = {
3013 I(Lock, em_add),
3014 I(Lock, em_or),
3015 I(Lock, em_adc),
3016 I(Lock, em_sbb),
3017 I(Lock, em_and),
3018 I(Lock, em_sub),
3019 I(Lock, em_xor),
3020 I(0, em_cmp),
3021 };
3022
3023 static struct opcode group1A[] = {
3024 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
3025 };
3026
3027 static struct opcode group3[] = {
3028 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
3029 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3030 X4(D(SrcMem | ModRM)),
3031 };
3032
3033 static struct opcode group4[] = {
3034 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3035 N, N, N, N, N, N,
3036 };
3037
3038 static struct opcode group5[] = {
3039 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3040 D(SrcMem | ModRM | Stack),
3041 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
3042 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3043 D(SrcMem | ModRM | Stack), N,
3044 };
3045
3046 static struct opcode group6[] = {
3047 DI(ModRM | Prot, sldt),
3048 DI(ModRM | Prot, str),
3049 DI(ModRM | Prot | Priv, lldt),
3050 DI(ModRM | Prot | Priv, ltr),
3051 N, N, N, N,
3052 };
3053
3054 static struct group_dual group7 = { {
3055 DI(ModRM | Mov | DstMem | Priv, sgdt),
3056 DI(ModRM | Mov | DstMem | Priv, sidt),
3057 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3058 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3059 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3060 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3061 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
3062 }, {
3063 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3064 EXT(0, group7_rm1),
3065 N, EXT(0, group7_rm3),
3066 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3067 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
3068 } };
3069
3070 static struct opcode group8[] = {
3071 N, N, N, N,
3072 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
3073 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
3074 };
3075
3076 static struct group_dual group9 = { {
3077 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
3078 }, {
3079 N, N, N, N, N, N, N, N,
3080 } };
3081
3082 static struct opcode group11[] = {
3083 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
3084 };
3085
3086 static struct gprefix pfx_0f_6f_0f_7f = {
3087 N, N, N, I(Sse, em_movdqu),
3088 };
3089
3090 static struct opcode opcode_table[256] = {
3091 /* 0x00 - 0x07 */
3092 I6ALU(Lock, em_add),
3093 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3094 /* 0x08 - 0x0F */
3095 I6ALU(Lock, em_or),
3096 D(ImplicitOps | Stack | No64), N,
3097 /* 0x10 - 0x17 */
3098 I6ALU(Lock, em_adc),
3099 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3100 /* 0x18 - 0x1F */
3101 I6ALU(Lock, em_sbb),
3102 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3103 /* 0x20 - 0x27 */
3104 I6ALU(Lock, em_and), N, N,
3105 /* 0x28 - 0x2F */
3106 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3107 /* 0x30 - 0x37 */
3108 I6ALU(Lock, em_xor), N, N,
3109 /* 0x38 - 0x3F */
3110 I6ALU(0, em_cmp), N, N,
3111 /* 0x40 - 0x4F */
3112 X16(D(DstReg)),
3113 /* 0x50 - 0x57 */
3114 X8(I(SrcReg | Stack, em_push)),
3115 /* 0x58 - 0x5F */
3116 X8(I(DstReg | Stack, em_pop)),
3117 /* 0x60 - 0x67 */
3118 I(ImplicitOps | Stack | No64, em_pusha),
3119 I(ImplicitOps | Stack | No64, em_popa),
3120 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3121 N, N, N, N,
3122 /* 0x68 - 0x6F */
3123 I(SrcImm | Mov | Stack, em_push),
3124 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3125 I(SrcImmByte | Mov | Stack, em_push),
3126 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3127 D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3128 D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
3129 /* 0x70 - 0x7F */
3130 X16(D(SrcImmByte)),
3131 /* 0x80 - 0x87 */
3132 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3133 G(DstMem | SrcImm | ModRM | Group, group1),
3134 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3135 G(DstMem | SrcImmByte | ModRM | Group, group1),
3136 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
3137 /* 0x88 - 0x8F */
3138 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3139 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3140 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
3141 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
3142 /* 0x90 - 0x97 */
3143 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3144 /* 0x98 - 0x9F */
3145 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3146 I(SrcImmFAddr | No64, em_call_far), N,
3147 II(ImplicitOps | Stack, em_pushf, pushf),
3148 II(ImplicitOps | Stack, em_popf, popf), N, N,
3149 /* 0xA0 - 0xA7 */
3150 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3151 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3152 I2bv(SrcSI | DstDI | Mov | String, em_mov),
3153 I2bv(SrcSI | DstDI | String, em_cmp),
3154 /* 0xA8 - 0xAF */
3155 D2bv(DstAcc | SrcImm),
3156 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3157 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3158 I2bv(SrcAcc | DstDI | String, em_cmp),
3159 /* 0xB0 - 0xB7 */
3160 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3161 /* 0xB8 - 0xBF */
3162 X8(I(DstReg | SrcImm | Mov, em_mov)),
3163 /* 0xC0 - 0xC7 */
3164 D2bv(DstMem | SrcImmByte | ModRM),
3165 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3166 D(ImplicitOps | Stack),
3167 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
3168 G(ByteOp, group11), G(0, group11),
3169 /* 0xC8 - 0xCF */
3170 N, N, N, D(ImplicitOps | Stack),
3171 D(ImplicitOps), DI(SrcImmByte, intn),
3172 D(ImplicitOps | No64), DI(ImplicitOps, iret),
3173 /* 0xD0 - 0xD7 */
3174 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
3175 N, N, N, N,
3176 /* 0xD8 - 0xDF */
3177 N, N, N, N, N, N, N, N,
3178 /* 0xE0 - 0xE7 */
3179 X4(D(SrcImmByte)),
3180 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3181 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
3182 /* 0xE8 - 0xEF */
3183 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
3184 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
3185 D2bvIP(SrcNone | DstAcc, in, check_perm_in),
3186 D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
3187 /* 0xF0 - 0xF7 */
3188 N, DI(ImplicitOps, icebp), N, N,
3189 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3190 G(ByteOp, group3), G(0, group3),
3191 /* 0xF8 - 0xFF */
3192 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
3193 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3194 };
3195
3196 static struct opcode twobyte_table[256] = {
3197 /* 0x00 - 0x0F */
3198 G(0, group6), GD(0, &group7), N, N,
3199 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
3200 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3201 N, D(ImplicitOps | ModRM), N, N,
3202 /* 0x10 - 0x1F */
3203 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3204 /* 0x20 - 0x2F */
3205 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3206 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
3207 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3208 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
3209 N, N, N, N,
3210 N, N, N, N, N, N, N, N,
3211 /* 0x30 - 0x3F */
3212 DI(ImplicitOps | Priv, wrmsr),
3213 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3214 DI(ImplicitOps | Priv, rdmsr),
3215 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
3216 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
3217 N, N,
3218 N, N, N, N, N, N, N, N,
3219 /* 0x40 - 0x4F */
3220 X16(D(DstReg | SrcMem | ModRM | Mov)),
3221 /* 0x50 - 0x5F */
3222 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3223 /* 0x60 - 0x6F */
3224 N, N, N, N,
3225 N, N, N, N,
3226 N, N, N, N,
3227 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
3228 /* 0x70 - 0x7F */
3229 N, N, N, N,
3230 N, N, N, N,
3231 N, N, N, N,
3232 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
3233 /* 0x80 - 0x8F */
3234 X16(D(SrcImm)),
3235 /* 0x90 - 0x9F */
3236 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
3237 /* 0xA0 - 0xA7 */
3238 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3239 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
3240 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3241 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3242 /* 0xA8 - 0xAF */
3243 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3244 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3245 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3246 D(DstMem | SrcReg | Src2CL | ModRM),
3247 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
3248 /* 0xB0 - 0xB7 */
3249 D2bv(DstMem | SrcReg | ModRM | Lock),
3250 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3251 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3252 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3253 /* 0xB8 - 0xBF */
3254 N, N,
3255 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3256 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3257 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3258 /* 0xC0 - 0xCF */
3259 D2bv(DstMem | SrcReg | ModRM | Lock),
3260 N, D(DstMem | SrcReg | ModRM | Mov),
3261 N, N, N, GD(0, &group9),
3262 N, N, N, N, N, N, N, N,
3263 /* 0xD0 - 0xDF */
3264 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3265 /* 0xE0 - 0xEF */
3266 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3267 /* 0xF0 - 0xFF */
3268 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3269 };
3270
3271 #undef D
3272 #undef N
3273 #undef G
3274 #undef GD
3275 #undef I
3276 #undef GP
3277 #undef EXT
3278
3279 #undef D2bv
3280 #undef D2bvIP
3281 #undef I2bv
3282 #undef I6ALU
3283
3284 static unsigned imm_size(struct decode_cache *c)
3285 {
3286 unsigned size;
3287
3288 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3289 if (size == 8)
3290 size = 4;
3291 return size;
3292 }
3293
3294 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3295 unsigned size, bool sign_extension)
3296 {
3297 struct decode_cache *c = &ctxt->decode;
3298 struct x86_emulate_ops *ops = ctxt->ops;
3299 int rc = X86EMUL_CONTINUE;
3300
3301 op->type = OP_IMM;
3302 op->bytes = size;
3303 op->addr.mem.ea = c->eip;
3304 /* NB. Immediates are sign-extended as necessary. */
3305 switch (op->bytes) {
3306 case 1:
3307 op->val = insn_fetch(s8, 1, c->eip);
3308 break;
3309 case 2:
3310 op->val = insn_fetch(s16, 2, c->eip);
3311 break;
3312 case 4:
3313 op->val = insn_fetch(s32, 4, c->eip);
3314 break;
3315 }
3316 if (!sign_extension) {
3317 switch (op->bytes) {
3318 case 1:
3319 op->val &= 0xff;
3320 break;
3321 case 2:
3322 op->val &= 0xffff;
3323 break;
3324 case 4:
3325 op->val &= 0xffffffff;
3326 break;
3327 }
3328 }
3329 done:
3330 return rc;
3331 }
3332
3333 int
3334 x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
3335 {
3336 struct x86_emulate_ops *ops = ctxt->ops;
3337 struct decode_cache *c = &ctxt->decode;
3338 int rc = X86EMUL_CONTINUE;
3339 int mode = ctxt->mode;
3340 int def_op_bytes, def_ad_bytes, dual, goffset, simd_prefix;
3341 bool op_prefix = false;
3342 struct opcode opcode, *g_mod012, *g_mod3;
3343 struct operand memop = { .type = OP_NONE };
3344
3345 c->eip = ctxt->eip;
3346 c->fetch.start = c->eip;
3347 c->fetch.end = c->fetch.start + insn_len;
3348 if (insn_len > 0)
3349 memcpy(c->fetch.data, insn, insn_len);
3350
3351 switch (mode) {
3352 case X86EMUL_MODE_REAL:
3353 case X86EMUL_MODE_VM86:
3354 case X86EMUL_MODE_PROT16:
3355 def_op_bytes = def_ad_bytes = 2;
3356 break;
3357 case X86EMUL_MODE_PROT32:
3358 def_op_bytes = def_ad_bytes = 4;
3359 break;
3360 #ifdef CONFIG_X86_64
3361 case X86EMUL_MODE_PROT64:
3362 def_op_bytes = 4;
3363 def_ad_bytes = 8;
3364 break;
3365 #endif
3366 default:
3367 return -1;
3368 }
3369
3370 c->op_bytes = def_op_bytes;
3371 c->ad_bytes = def_ad_bytes;
3372
3373 /* Legacy prefixes. */
3374 for (;;) {
3375 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3376 case 0x66: /* operand-size override */
3377 op_prefix = true;
3378 /* switch between 2/4 bytes */
3379 c->op_bytes = def_op_bytes ^ 6;
3380 break;
3381 case 0x67: /* address-size override */
3382 if (mode == X86EMUL_MODE_PROT64)
3383 /* switch between 4/8 bytes */
3384 c->ad_bytes = def_ad_bytes ^ 12;
3385 else
3386 /* switch between 2/4 bytes */
3387 c->ad_bytes = def_ad_bytes ^ 6;
3388 break;
3389 case 0x26: /* ES override */
3390 case 0x2e: /* CS override */
3391 case 0x36: /* SS override */
3392 case 0x3e: /* DS override */
3393 set_seg_override(c, (c->b >> 3) & 3);
3394 break;
3395 case 0x64: /* FS override */
3396 case 0x65: /* GS override */
3397 set_seg_override(c, c->b & 7);
3398 break;
3399 case 0x40 ... 0x4f: /* REX */
3400 if (mode != X86EMUL_MODE_PROT64)
3401 goto done_prefixes;
3402 c->rex_prefix = c->b;
3403 continue;
3404 case 0xf0: /* LOCK */
3405 c->lock_prefix = 1;
3406 break;
3407 case 0xf2: /* REPNE/REPNZ */
3408 case 0xf3: /* REP/REPE/REPZ */
3409 c->rep_prefix = c->b;
3410 break;
3411 default:
3412 goto done_prefixes;
3413 }
3414
3415 /* Any legacy prefix after a REX prefix nullifies its effect. */
3416
3417 c->rex_prefix = 0;
3418 }
3419
3420 done_prefixes:
3421
3422 /* REX prefix. */
3423 if (c->rex_prefix & 8)
3424 c->op_bytes = 8; /* REX.W */
3425
3426 /* Opcode byte(s). */
3427 opcode = opcode_table[c->b];
3428 /* Two-byte opcode? */
3429 if (c->b == 0x0f) {
3430 c->twobyte = 1;
3431 c->b = insn_fetch(u8, 1, c->eip);
3432 opcode = twobyte_table[c->b];
3433 }
3434 c->d = opcode.flags;
3435
3436 if (c->d & Group) {
3437 dual = c->d & GroupDual;
3438 c->modrm = insn_fetch(u8, 1, c->eip);
3439 --c->eip;
3440
3441 if (c->d & GroupDual) {
3442 g_mod012 = opcode.u.gdual->mod012;
3443 g_mod3 = opcode.u.gdual->mod3;
3444 } else
3445 g_mod012 = g_mod3 = opcode.u.group;
3446
3447 c->d &= ~(Group | GroupDual);
3448
3449 goffset = (c->modrm >> 3) & 7;
3450
3451 if ((c->modrm >> 6) == 3)
3452 opcode = g_mod3[goffset];
3453 else
3454 opcode = g_mod012[goffset];
3455
3456 if (opcode.flags & RMExt) {
3457 goffset = c->modrm & 7;
3458 opcode = opcode.u.group[goffset];
3459 }
3460
3461 c->d |= opcode.flags;
3462 }
3463
3464 if (c->d & Prefix) {
3465 if (c->rep_prefix && op_prefix)
3466 return X86EMUL_UNHANDLEABLE;
3467 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3468 switch (simd_prefix) {
3469 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3470 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3471 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3472 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3473 }
3474 c->d |= opcode.flags;
3475 }
3476
3477 c->execute = opcode.u.execute;
3478 c->check_perm = opcode.check_perm;
3479 c->intercept = opcode.intercept;
3480
3481 /* Unrecognised? */
3482 if (c->d == 0 || (c->d & Undefined))
3483 return -1;
3484
3485 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3486 return -1;
3487
3488 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3489 c->op_bytes = 8;
3490
3491 if (c->d & Op3264) {
3492 if (mode == X86EMUL_MODE_PROT64)
3493 c->op_bytes = 8;
3494 else
3495 c->op_bytes = 4;
3496 }
3497
3498 if (c->d & Sse)
3499 c->op_bytes = 16;
3500
3501 /* ModRM and SIB bytes. */
3502 if (c->d & ModRM) {
3503 rc = decode_modrm(ctxt, ops, &memop);
3504 if (!c->has_seg_override)
3505 set_seg_override(c, c->modrm_seg);
3506 } else if (c->d & MemAbs)
3507 rc = decode_abs(ctxt, ops, &memop);
3508 if (rc != X86EMUL_CONTINUE)
3509 goto done;
3510
3511 if (!c->has_seg_override)
3512 set_seg_override(c, VCPU_SREG_DS);
3513
3514 memop.addr.mem.seg = seg_override(ctxt, ops, c);
3515
3516 if (memop.type == OP_MEM && c->ad_bytes != 8)
3517 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
3518
3519 if (memop.type == OP_MEM && c->rip_relative)
3520 memop.addr.mem.ea += c->eip;
3521
3522 /*
3523 * Decode and fetch the source operand: register, memory
3524 * or immediate.
3525 */
3526 switch (c->d & SrcMask) {
3527 case SrcNone:
3528 break;
3529 case SrcReg:
3530 decode_register_operand(ctxt, &c->src, c, 0);
3531 break;
3532 case SrcMem16:
3533 memop.bytes = 2;
3534 goto srcmem_common;
3535 case SrcMem32:
3536 memop.bytes = 4;
3537 goto srcmem_common;
3538 case SrcMem:
3539 memop.bytes = (c->d & ByteOp) ? 1 :
3540 c->op_bytes;
3541 srcmem_common:
3542 c->src = memop;
3543 break;
3544 case SrcImmU16:
3545 rc = decode_imm(ctxt, &c->src, 2, false);
3546 break;
3547 case SrcImm:
3548 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3549 break;
3550 case SrcImmU:
3551 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
3552 break;
3553 case SrcImmByte:
3554 rc = decode_imm(ctxt, &c->src, 1, true);
3555 break;
3556 case SrcImmUByte:
3557 rc = decode_imm(ctxt, &c->src, 1, false);
3558 break;
3559 case SrcAcc:
3560 c->src.type = OP_REG;
3561 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3562 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
3563 fetch_register_operand(&c->src);
3564 break;
3565 case SrcOne:
3566 c->src.bytes = 1;
3567 c->src.val = 1;
3568 break;
3569 case SrcSI:
3570 c->src.type = OP_MEM;
3571 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3572 c->src.addr.mem.ea =
3573 register_address(c, c->regs[VCPU_REGS_RSI]);
3574 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
3575 c->src.val = 0;
3576 break;
3577 case SrcImmFAddr:
3578 c->src.type = OP_IMM;
3579 c->src.addr.mem.ea = c->eip;
3580 c->src.bytes = c->op_bytes + 2;
3581 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3582 break;
3583 case SrcMemFAddr:
3584 memop.bytes = c->op_bytes + 2;
3585 goto srcmem_common;
3586 break;
3587 }
3588
3589 if (rc != X86EMUL_CONTINUE)
3590 goto done;
3591
3592 /*
3593 * Decode and fetch the second source operand: register, memory
3594 * or immediate.
3595 */
3596 switch (c->d & Src2Mask) {
3597 case Src2None:
3598 break;
3599 case Src2CL:
3600 c->src2.bytes = 1;
3601 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3602 break;
3603 case Src2ImmByte:
3604 rc = decode_imm(ctxt, &c->src2, 1, true);
3605 break;
3606 case Src2One:
3607 c->src2.bytes = 1;
3608 c->src2.val = 1;
3609 break;
3610 case Src2Imm:
3611 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3612 break;
3613 }
3614
3615 if (rc != X86EMUL_CONTINUE)
3616 goto done;
3617
3618 /* Decode and fetch the destination operand: register or memory. */
3619 switch (c->d & DstMask) {
3620 case DstReg:
3621 decode_register_operand(ctxt, &c->dst, c,
3622 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3623 break;
3624 case DstImmUByte:
3625 c->dst.type = OP_IMM;
3626 c->dst.addr.mem.ea = c->eip;
3627 c->dst.bytes = 1;
3628 c->dst.val = insn_fetch(u8, 1, c->eip);
3629 break;
3630 case DstMem:
3631 case DstMem64:
3632 c->dst = memop;
3633 if ((c->d & DstMask) == DstMem64)
3634 c->dst.bytes = 8;
3635 else
3636 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3637 if (c->d & BitOp)
3638 fetch_bit_operand(c);
3639 c->dst.orig_val = c->dst.val;
3640 break;
3641 case DstAcc:
3642 c->dst.type = OP_REG;
3643 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3644 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
3645 fetch_register_operand(&c->dst);
3646 c->dst.orig_val = c->dst.val;
3647 break;
3648 case DstDI:
3649 c->dst.type = OP_MEM;
3650 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3651 c->dst.addr.mem.ea =
3652 register_address(c, c->regs[VCPU_REGS_RDI]);
3653 c->dst.addr.mem.seg = VCPU_SREG_ES;
3654 c->dst.val = 0;
3655 break;
3656 case ImplicitOps:
3657 /* Special instructions do their own operand decoding. */
3658 default:
3659 c->dst.type = OP_NONE; /* Disable writeback. */
3660 return 0;
3661 }
3662
3663 done:
3664 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3665 }
3666
3667 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3668 {
3669 struct decode_cache *c = &ctxt->decode;
3670
3671 /* The second termination condition only applies for REPE
3672 * and REPNE. Test if the repeat string operation prefix is
3673 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3674 * corresponding termination condition according to:
3675 * - if REPE/REPZ and ZF = 0 then done
3676 * - if REPNE/REPNZ and ZF = 1 then done
3677 */
3678 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3679 (c->b == 0xae) || (c->b == 0xaf))
3680 && (((c->rep_prefix == REPE_PREFIX) &&
3681 ((ctxt->eflags & EFLG_ZF) == 0))
3682 || ((c->rep_prefix == REPNE_PREFIX) &&
3683 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3684 return true;
3685
3686 return false;
3687 }
3688
3689 int
3690 x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
3691 {
3692 struct x86_emulate_ops *ops = ctxt->ops;
3693 u64 msr_data;
3694 struct decode_cache *c = &ctxt->decode;
3695 int rc = X86EMUL_CONTINUE;
3696 int saved_dst_type = c->dst.type;
3697 int irq; /* Used for int 3, int, and into */
3698
3699 ctxt->decode.mem_read.pos = 0;
3700
3701 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
3702 rc = emulate_ud(ctxt);
3703 goto done;
3704 }
3705
3706 /* LOCK prefix is allowed only with some instructions */
3707 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
3708 rc = emulate_ud(ctxt);
3709 goto done;
3710 }
3711
3712 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
3713 rc = emulate_ud(ctxt);
3714 goto done;
3715 }
3716
3717 if ((c->d & Sse)
3718 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3719 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
3720 rc = emulate_ud(ctxt);
3721 goto done;
3722 }
3723
3724 if ((c->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
3725 rc = emulate_nm(ctxt);
3726 goto done;
3727 }
3728
3729 if (unlikely(ctxt->guest_mode) && c->intercept) {
3730 rc = emulator_check_intercept(ctxt, c->intercept,
3731 X86_ICPT_PRE_EXCEPT);
3732 if (rc != X86EMUL_CONTINUE)
3733 goto done;
3734 }
3735
3736 /* Privileged instruction can be executed only in CPL=0 */
3737 if ((c->d & Priv) && ops->cpl(ctxt)) {
3738 rc = emulate_gp(ctxt, 0);
3739 goto done;
3740 }
3741
3742 /* Instruction can only be executed in protected mode */
3743 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3744 rc = emulate_ud(ctxt);
3745 goto done;
3746 }
3747
3748 /* Do instruction specific permission checks */
3749 if (c->check_perm) {
3750 rc = c->check_perm(ctxt);
3751 if (rc != X86EMUL_CONTINUE)
3752 goto done;
3753 }
3754
3755 if (unlikely(ctxt->guest_mode) && c->intercept) {
3756 rc = emulator_check_intercept(ctxt, c->intercept,
3757 X86_ICPT_POST_EXCEPT);
3758 if (rc != X86EMUL_CONTINUE)
3759 goto done;
3760 }
3761
3762 if (c->rep_prefix && (c->d & String)) {
3763 /* All REP prefixes have the same first termination condition */
3764 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
3765 ctxt->eip = c->eip;
3766 goto done;
3767 }
3768 }
3769
3770 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3771 rc = segmented_read(ctxt, c->src.addr.mem,
3772 c->src.valptr, c->src.bytes);
3773 if (rc != X86EMUL_CONTINUE)
3774 goto done;
3775 c->src.orig_val64 = c->src.val64;
3776 }
3777
3778 if (c->src2.type == OP_MEM) {
3779 rc = segmented_read(ctxt, c->src2.addr.mem,
3780 &c->src2.val, c->src2.bytes);
3781 if (rc != X86EMUL_CONTINUE)
3782 goto done;
3783 }
3784
3785 if ((c->d & DstMask) == ImplicitOps)
3786 goto special_insn;
3787
3788
3789 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3790 /* optimisation - avoid slow emulated read if Mov */
3791 rc = segmented_read(ctxt, c->dst.addr.mem,
3792 &c->dst.val, c->dst.bytes);
3793 if (rc != X86EMUL_CONTINUE)
3794 goto done;
3795 }
3796 c->dst.orig_val = c->dst.val;
3797
3798 special_insn:
3799
3800 if (unlikely(ctxt->guest_mode) && c->intercept) {
3801 rc = emulator_check_intercept(ctxt, c->intercept,
3802 X86_ICPT_POST_MEMACCESS);
3803 if (rc != X86EMUL_CONTINUE)
3804 goto done;
3805 }
3806
3807 if (c->execute) {
3808 rc = c->execute(ctxt);
3809 if (rc != X86EMUL_CONTINUE)
3810 goto done;
3811 goto writeback;
3812 }
3813
3814 if (c->twobyte)
3815 goto twobyte_insn;
3816
3817 switch (c->b) {
3818 case 0x06: /* push es */
3819 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
3820 break;
3821 case 0x07: /* pop es */
3822 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
3823 break;
3824 case 0x0e: /* push cs */
3825 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
3826 break;
3827 case 0x16: /* push ss */
3828 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
3829 break;
3830 case 0x17: /* pop ss */
3831 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
3832 break;
3833 case 0x1e: /* push ds */
3834 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
3835 break;
3836 case 0x1f: /* pop ds */
3837 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
3838 break;
3839 case 0x40 ... 0x47: /* inc r16/r32 */
3840 emulate_1op("inc", c->dst, ctxt->eflags);
3841 break;
3842 case 0x48 ... 0x4f: /* dec r16/r32 */
3843 emulate_1op("dec", c->dst, ctxt->eflags);
3844 break;
3845 case 0x63: /* movsxd */
3846 if (ctxt->mode != X86EMUL_MODE_PROT64)
3847 goto cannot_emulate;
3848 c->dst.val = (s32) c->src.val;
3849 break;
3850 case 0x6c: /* insb */
3851 case 0x6d: /* insw/insd */
3852 c->src.val = c->regs[VCPU_REGS_RDX];
3853 goto do_io_in;
3854 case 0x6e: /* outsb */
3855 case 0x6f: /* outsw/outsd */
3856 c->dst.val = c->regs[VCPU_REGS_RDX];
3857 goto do_io_out;
3858 break;
3859 case 0x70 ... 0x7f: /* jcc (short) */
3860 if (test_cc(c->b, ctxt->eflags))
3861 jmp_rel(c, c->src.val);
3862 break;
3863 case 0x84 ... 0x85:
3864 test:
3865 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
3866 break;
3867 case 0x86 ... 0x87: /* xchg */
3868 xchg:
3869 /* Write back the register source. */
3870 c->src.val = c->dst.val;
3871 write_register_operand(&c->src);
3872 /*
3873 * Write back the memory destination with implicit LOCK
3874 * prefix.
3875 */
3876 c->dst.val = c->src.orig_val;
3877 c->lock_prefix = 1;
3878 break;
3879 case 0x8c: /* mov r/m, sreg */
3880 if (c->modrm_reg > VCPU_SREG_GS) {
3881 rc = emulate_ud(ctxt);
3882 goto done;
3883 }
3884 c->dst.val = ops->get_segment_selector(ctxt, c->modrm_reg);
3885 break;
3886 case 0x8d: /* lea r16/r32, m */
3887 c->dst.val = c->src.addr.mem.ea;
3888 break;
3889 case 0x8e: { /* mov seg, r/m16 */
3890 uint16_t sel;
3891
3892 sel = c->src.val;
3893
3894 if (c->modrm_reg == VCPU_SREG_CS ||
3895 c->modrm_reg > VCPU_SREG_GS) {
3896 rc = emulate_ud(ctxt);
3897 goto done;
3898 }
3899
3900 if (c->modrm_reg == VCPU_SREG_SS)
3901 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3902
3903 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
3904
3905 c->dst.type = OP_NONE; /* Disable writeback. */
3906 break;
3907 }
3908 case 0x8f: /* pop (sole member of Grp1a) */
3909 rc = emulate_grp1a(ctxt, ops);
3910 break;
3911 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3912 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
3913 break;
3914 goto xchg;
3915 case 0x98: /* cbw/cwde/cdqe */
3916 switch (c->op_bytes) {
3917 case 2: c->dst.val = (s8)c->dst.val; break;
3918 case 4: c->dst.val = (s16)c->dst.val; break;
3919 case 8: c->dst.val = (s32)c->dst.val; break;
3920 }
3921 break;
3922 case 0xa8 ... 0xa9: /* test ax, imm */
3923 goto test;
3924 case 0xc0 ... 0xc1:
3925 emulate_grp2(ctxt);
3926 break;
3927 case 0xc3: /* ret */
3928 c->dst.type = OP_REG;
3929 c->dst.addr.reg = &c->eip;
3930 c->dst.bytes = c->op_bytes;
3931 rc = em_pop(ctxt);
3932 break;
3933 case 0xc4: /* les */
3934 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
3935 break;
3936 case 0xc5: /* lds */
3937 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
3938 break;
3939 case 0xcb: /* ret far */
3940 rc = emulate_ret_far(ctxt, ops);
3941 break;
3942 case 0xcc: /* int3 */
3943 irq = 3;
3944 goto do_interrupt;
3945 case 0xcd: /* int n */
3946 irq = c->src.val;
3947 do_interrupt:
3948 rc = emulate_int(ctxt, ops, irq);
3949 break;
3950 case 0xce: /* into */
3951 if (ctxt->eflags & EFLG_OF) {
3952 irq = 4;
3953 goto do_interrupt;
3954 }
3955 break;
3956 case 0xcf: /* iret */
3957 rc = emulate_iret(ctxt, ops);
3958 break;
3959 case 0xd0 ... 0xd1: /* Grp2 */
3960 emulate_grp2(ctxt);
3961 break;
3962 case 0xd2 ... 0xd3: /* Grp2 */
3963 c->src.val = c->regs[VCPU_REGS_RCX];
3964 emulate_grp2(ctxt);
3965 break;
3966 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3967 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3968 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3969 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3970 jmp_rel(c, c->src.val);
3971 break;
3972 case 0xe3: /* jcxz/jecxz/jrcxz */
3973 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3974 jmp_rel(c, c->src.val);
3975 break;
3976 case 0xe4: /* inb */
3977 case 0xe5: /* in */
3978 goto do_io_in;
3979 case 0xe6: /* outb */
3980 case 0xe7: /* out */
3981 goto do_io_out;
3982 case 0xe8: /* call (near) */ {
3983 long int rel = c->src.val;
3984 c->src.val = (unsigned long) c->eip;
3985 jmp_rel(c, rel);
3986 rc = em_push(ctxt);
3987 break;
3988 }
3989 case 0xe9: /* jmp rel */
3990 goto jmp;
3991 case 0xea: { /* jmp far */
3992 unsigned short sel;
3993 jump_far:
3994 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3995
3996 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
3997 goto done;
3998
3999 c->eip = 0;
4000 memcpy(&c->eip, c->src.valptr, c->op_bytes);
4001 break;
4002 }
4003 case 0xeb:
4004 jmp: /* jmp rel short */
4005 jmp_rel(c, c->src.val);
4006 c->dst.type = OP_NONE; /* Disable writeback. */
4007 break;
4008 case 0xec: /* in al,dx */
4009 case 0xed: /* in (e/r)ax,dx */
4010 c->src.val = c->regs[VCPU_REGS_RDX];
4011 do_io_in:
4012 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
4013 &c->dst.val))
4014 goto done; /* IO is needed */
4015 break;
4016 case 0xee: /* out dx,al */
4017 case 0xef: /* out dx,(e/r)ax */
4018 c->dst.val = c->regs[VCPU_REGS_RDX];
4019 do_io_out:
4020 ops->pio_out_emulated(ctxt, c->src.bytes, c->dst.val,
4021 &c->src.val, 1);
4022 c->dst.type = OP_NONE; /* Disable writeback. */
4023 break;
4024 case 0xf4: /* hlt */
4025 ctxt->ops->halt(ctxt);
4026 break;
4027 case 0xf5: /* cmc */
4028 /* complement carry flag from eflags reg */
4029 ctxt->eflags ^= EFLG_CF;
4030 break;
4031 case 0xf6 ... 0xf7: /* Grp3 */
4032 rc = emulate_grp3(ctxt, ops);
4033 break;
4034 case 0xf8: /* clc */
4035 ctxt->eflags &= ~EFLG_CF;
4036 break;
4037 case 0xf9: /* stc */
4038 ctxt->eflags |= EFLG_CF;
4039 break;
4040 case 0xfa: /* cli */
4041 if (emulator_bad_iopl(ctxt, ops)) {
4042 rc = emulate_gp(ctxt, 0);
4043 goto done;
4044 } else
4045 ctxt->eflags &= ~X86_EFLAGS_IF;
4046 break;
4047 case 0xfb: /* sti */
4048 if (emulator_bad_iopl(ctxt, ops)) {
4049 rc = emulate_gp(ctxt, 0);
4050 goto done;
4051 } else {
4052 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
4053 ctxt->eflags |= X86_EFLAGS_IF;
4054 }
4055 break;
4056 case 0xfc: /* cld */
4057 ctxt->eflags &= ~EFLG_DF;
4058 break;
4059 case 0xfd: /* std */
4060 ctxt->eflags |= EFLG_DF;
4061 break;
4062 case 0xfe: /* Grp4 */
4063 grp45:
4064 rc = emulate_grp45(ctxt);
4065 break;
4066 case 0xff: /* Grp5 */
4067 if (c->modrm_reg == 5)
4068 goto jump_far;
4069 goto grp45;
4070 default:
4071 goto cannot_emulate;
4072 }
4073
4074 if (rc != X86EMUL_CONTINUE)
4075 goto done;
4076
4077 writeback:
4078 rc = writeback(ctxt, ops);
4079 if (rc != X86EMUL_CONTINUE)
4080 goto done;
4081
4082 /*
4083 * restore dst type in case the decoding will be reused
4084 * (happens for string instruction )
4085 */
4086 c->dst.type = saved_dst_type;
4087
4088 if ((c->d & SrcMask) == SrcSI)
4089 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
4090 VCPU_REGS_RSI, &c->src);
4091
4092 if ((c->d & DstMask) == DstDI)
4093 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
4094 &c->dst);
4095
4096 if (c->rep_prefix && (c->d & String)) {
4097 struct read_cache *r = &ctxt->decode.io_read;
4098 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
4099
4100 if (!string_insn_completed(ctxt)) {
4101 /*
4102 * Re-enter guest when pio read ahead buffer is empty
4103 * or, if it is not used, after each 1024 iteration.
4104 */
4105 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
4106 (r->end == 0 || r->end != r->pos)) {
4107 /*
4108 * Reset read cache. Usually happens before
4109 * decode, but since instruction is restarted
4110 * we have to do it here.
4111 */
4112 ctxt->decode.mem_read.end = 0;
4113 return EMULATION_RESTART;
4114 }
4115 goto done; /* skip rip writeback */
4116 }
4117 }
4118
4119 ctxt->eip = c->eip;
4120
4121 done:
4122 if (rc == X86EMUL_PROPAGATE_FAULT)
4123 ctxt->have_exception = true;
4124 if (rc == X86EMUL_INTERCEPTED)
4125 return EMULATION_INTERCEPTED;
4126
4127 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
4128
4129 twobyte_insn:
4130 switch (c->b) {
4131 case 0x05: /* syscall */
4132 rc = emulate_syscall(ctxt, ops);
4133 break;
4134 case 0x06:
4135 rc = em_clts(ctxt);
4136 break;
4137 case 0x09: /* wbinvd */
4138 (ctxt->ops->wbinvd)(ctxt);
4139 break;
4140 case 0x08: /* invd */
4141 case 0x0d: /* GrpP (prefetch) */
4142 case 0x18: /* Grp16 (prefetch/nop) */
4143 break;
4144 case 0x20: /* mov cr, reg */
4145 c->dst.val = ops->get_cr(ctxt, c->modrm_reg);
4146 break;
4147 case 0x21: /* mov from dr to reg */
4148 ops->get_dr(ctxt, c->modrm_reg, &c->dst.val);
4149 break;
4150 case 0x22: /* mov reg, cr */
4151 if (ops->set_cr(ctxt, c->modrm_reg, c->src.val)) {
4152 emulate_gp(ctxt, 0);
4153 rc = X86EMUL_PROPAGATE_FAULT;
4154 goto done;
4155 }
4156 c->dst.type = OP_NONE;
4157 break;
4158 case 0x23: /* mov from reg to dr */
4159 if (ops->set_dr(ctxt, c->modrm_reg, c->src.val &
4160 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
4161 ~0ULL : ~0U)) < 0) {
4162 /* #UD condition is already handled by the code above */
4163 emulate_gp(ctxt, 0);
4164 rc = X86EMUL_PROPAGATE_FAULT;
4165 goto done;
4166 }
4167
4168 c->dst.type = OP_NONE; /* no writeback */
4169 break;
4170 case 0x30:
4171 /* wrmsr */
4172 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4173 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
4174 if (ops->set_msr(ctxt, c->regs[VCPU_REGS_RCX], msr_data)) {
4175 emulate_gp(ctxt, 0);
4176 rc = X86EMUL_PROPAGATE_FAULT;
4177 goto done;
4178 }
4179 rc = X86EMUL_CONTINUE;
4180 break;
4181 case 0x32:
4182 /* rdmsr */
4183 if (ops->get_msr(ctxt, c->regs[VCPU_REGS_RCX], &msr_data)) {
4184 emulate_gp(ctxt, 0);
4185 rc = X86EMUL_PROPAGATE_FAULT;
4186 goto done;
4187 } else {
4188 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4189 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4190 }
4191 rc = X86EMUL_CONTINUE;
4192 break;
4193 case 0x34: /* sysenter */
4194 rc = emulate_sysenter(ctxt, ops);
4195 break;
4196 case 0x35: /* sysexit */
4197 rc = emulate_sysexit(ctxt, ops);
4198 break;
4199 case 0x40 ... 0x4f: /* cmov */
4200 c->dst.val = c->dst.orig_val = c->src.val;
4201 if (!test_cc(c->b, ctxt->eflags))
4202 c->dst.type = OP_NONE; /* no writeback */
4203 break;
4204 case 0x80 ... 0x8f: /* jnz rel, etc*/
4205 if (test_cc(c->b, ctxt->eflags))
4206 jmp_rel(c, c->src.val);
4207 break;
4208 case 0x90 ... 0x9f: /* setcc r/m8 */
4209 c->dst.val = test_cc(c->b, ctxt->eflags);
4210 break;
4211 case 0xa0: /* push fs */
4212 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
4213 break;
4214 case 0xa1: /* pop fs */
4215 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
4216 break;
4217 case 0xa3:
4218 bt: /* bt */
4219 c->dst.type = OP_NONE;
4220 /* only subword offset */
4221 c->src.val &= (c->dst.bytes << 3) - 1;
4222 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
4223 break;
4224 case 0xa4: /* shld imm8, r, r/m */
4225 case 0xa5: /* shld cl, r, r/m */
4226 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4227 break;
4228 case 0xa8: /* push gs */
4229 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
4230 break;
4231 case 0xa9: /* pop gs */
4232 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
4233 break;
4234 case 0xab:
4235 bts: /* bts */
4236 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
4237 break;
4238 case 0xac: /* shrd imm8, r, r/m */
4239 case 0xad: /* shrd cl, r, r/m */
4240 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4241 break;
4242 case 0xae: /* clflush */
4243 break;
4244 case 0xb0 ... 0xb1: /* cmpxchg */
4245 /*
4246 * Save real source value, then compare EAX against
4247 * destination.
4248 */
4249 c->src.orig_val = c->src.val;
4250 c->src.val = c->regs[VCPU_REGS_RAX];
4251 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4252 if (ctxt->eflags & EFLG_ZF) {
4253 /* Success: write back to memory. */
4254 c->dst.val = c->src.orig_val;
4255 } else {
4256 /* Failure: write the value we saw to EAX. */
4257 c->dst.type = OP_REG;
4258 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
4259 }
4260 break;
4261 case 0xb2: /* lss */
4262 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
4263 break;
4264 case 0xb3:
4265 btr: /* btr */
4266 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
4267 break;
4268 case 0xb4: /* lfs */
4269 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
4270 break;
4271 case 0xb5: /* lgs */
4272 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
4273 break;
4274 case 0xb6 ... 0xb7: /* movzx */
4275 c->dst.bytes = c->op_bytes;
4276 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4277 : (u16) c->src.val;
4278 break;
4279 case 0xba: /* Grp8 */
4280 switch (c->modrm_reg & 3) {
4281 case 0:
4282 goto bt;
4283 case 1:
4284 goto bts;
4285 case 2:
4286 goto btr;
4287 case 3:
4288 goto btc;
4289 }
4290 break;
4291 case 0xbb:
4292 btc: /* btc */
4293 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
4294 break;
4295 case 0xbc: { /* bsf */
4296 u8 zf;
4297 __asm__ ("bsf %2, %0; setz %1"
4298 : "=r"(c->dst.val), "=q"(zf)
4299 : "r"(c->src.val));
4300 ctxt->eflags &= ~X86_EFLAGS_ZF;
4301 if (zf) {
4302 ctxt->eflags |= X86_EFLAGS_ZF;
4303 c->dst.type = OP_NONE; /* Disable writeback. */
4304 }
4305 break;
4306 }
4307 case 0xbd: { /* bsr */
4308 u8 zf;
4309 __asm__ ("bsr %2, %0; setz %1"
4310 : "=r"(c->dst.val), "=q"(zf)
4311 : "r"(c->src.val));
4312 ctxt->eflags &= ~X86_EFLAGS_ZF;
4313 if (zf) {
4314 ctxt->eflags |= X86_EFLAGS_ZF;
4315 c->dst.type = OP_NONE; /* Disable writeback. */
4316 }
4317 break;
4318 }
4319 case 0xbe ... 0xbf: /* movsx */
4320 c->dst.bytes = c->op_bytes;
4321 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4322 (s16) c->src.val;
4323 break;
4324 case 0xc0 ... 0xc1: /* xadd */
4325 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4326 /* Write back the register source. */
4327 c->src.val = c->dst.orig_val;
4328 write_register_operand(&c->src);
4329 break;
4330 case 0xc3: /* movnti */
4331 c->dst.bytes = c->op_bytes;
4332 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4333 (u64) c->src.val;
4334 break;
4335 case 0xc7: /* Grp9 (cmpxchg8b) */
4336 rc = emulate_grp9(ctxt, ops);
4337 break;
4338 default:
4339 goto cannot_emulate;
4340 }
4341
4342 if (rc != X86EMUL_CONTINUE)
4343 goto done;
4344
4345 goto writeback;
4346
4347 cannot_emulate:
4348 return EMULATION_FAILED;
4349 }
Linux kernel - Deliverables
This page took 0.167524 seconds and 6 git commands to generate.