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KVM: x86 emulator: get rid of "restart" in emulation context.
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #ifndef __KERNEL__
24 #include <stdio.h>
25 #include <stdint.h>
26 #include <public/xen.h>
27 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
28 #else
29 #include <linux/kvm_host.h>
30 #include "kvm_cache_regs.h"
31 #define DPRINTF(x...) do {} while (0)
32 #endif
33 #include <linux/module.h>
34 #include <asm/kvm_emulate.h>
35
36 #include "x86.h"
37 #include "tss.h"
38
39 /*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48 /* Operand sizes: 8-bit operands or specified/overridden size. */
49 #define ByteOp (1<<0) /* 8-bit operands. */
50 /* Destination operand type. */
51 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
52 #define DstReg (2<<1) /* Register operand. */
53 #define DstMem (3<<1) /* Memory operand. */
54 #define DstAcc (4<<1) /* Destination Accumulator */
55 #define DstDI (5<<1) /* Destination is in ES:(E)DI */
56 #define DstMem64 (6<<1) /* 64bit memory operand */
57 #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
58 #define DstMask (7<<1)
59 /* Source operand type. */
60 #define SrcNone (0<<4) /* No source operand. */
61 #define SrcReg (1<<4) /* Register operand. */
62 #define SrcMem (2<<4) /* Memory operand. */
63 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65 #define SrcImm (5<<4) /* Immediate operand. */
66 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
67 #define SrcOne (7<<4) /* Implied '1' */
68 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
69 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
70 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */
71 #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72 #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
73 #define SrcAcc (0xd<<4) /* Source Accumulator */
74 #define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
75 #define SrcMask (0xf<<4)
76 /* Generic ModRM decode. */
77 #define ModRM (1<<8)
78 /* Destination is only written; never read. */
79 #define Mov (1<<9)
80 #define BitOp (1<<10)
81 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
82 #define String (1<<12) /* String instruction (rep capable) */
83 #define Stack (1<<13) /* Stack instruction (push/pop) */
84 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
85 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
86 /* Misc flags */
87 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
88 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
89 #define Undefined (1<<25) /* No Such Instruction */
90 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
91 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
92 #define No64 (1<<28)
93 /* Source 2 operand type */
94 #define Src2None (0<<29)
95 #define Src2CL (1<<29)
96 #define Src2ImmByte (2<<29)
97 #define Src2One (3<<29)
98 #define Src2Imm (4<<29)
99 #define Src2Mask (7<<29)
100
101 #define X2(x...) x, x
102 #define X3(x...) X2(x), x
103 #define X4(x...) X2(x), X2(x)
104 #define X5(x...) X4(x), x
105 #define X6(x...) X4(x), X2(x)
106 #define X7(x...) X4(x), X3(x)
107 #define X8(x...) X4(x), X4(x)
108 #define X16(x...) X8(x), X8(x)
109
110 struct opcode {
111 u32 flags;
112 union {
113 int (*execute)(struct x86_emulate_ctxt *ctxt);
114 struct opcode *group;
115 struct group_dual *gdual;
116 } u;
117 };
118
119 struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
122 };
123
124 /* EFLAGS bit definitions. */
125 #define EFLG_ID (1<<21)
126 #define EFLG_VIP (1<<20)
127 #define EFLG_VIF (1<<19)
128 #define EFLG_AC (1<<18)
129 #define EFLG_VM (1<<17)
130 #define EFLG_RF (1<<16)
131 #define EFLG_IOPL (3<<12)
132 #define EFLG_NT (1<<14)
133 #define EFLG_OF (1<<11)
134 #define EFLG_DF (1<<10)
135 #define EFLG_IF (1<<9)
136 #define EFLG_TF (1<<8)
137 #define EFLG_SF (1<<7)
138 #define EFLG_ZF (1<<6)
139 #define EFLG_AF (1<<4)
140 #define EFLG_PF (1<<2)
141 #define EFLG_CF (1<<0)
142
143 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
144 #define EFLG_RESERVED_ONE_MASK 2
145
146 /*
147 * Instruction emulation:
148 * Most instructions are emulated directly via a fragment of inline assembly
149 * code. This allows us to save/restore EFLAGS and thus very easily pick up
150 * any modified flags.
151 */
152
153 #if defined(CONFIG_X86_64)
154 #define _LO32 "k" /* force 32-bit operand */
155 #define _STK "%%rsp" /* stack pointer */
156 #elif defined(__i386__)
157 #define _LO32 "" /* force 32-bit operand */
158 #define _STK "%%esp" /* stack pointer */
159 #endif
160
161 /*
162 * These EFLAGS bits are restored from saved value during emulation, and
163 * any changes are written back to the saved value after emulation.
164 */
165 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
166
167 /* Before executing instruction: restore necessary bits in EFLAGS. */
168 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
169 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
170 "movl %"_sav",%"_LO32 _tmp"; " \
171 "push %"_tmp"; " \
172 "push %"_tmp"; " \
173 "movl %"_msk",%"_LO32 _tmp"; " \
174 "andl %"_LO32 _tmp",("_STK"); " \
175 "pushf; " \
176 "notl %"_LO32 _tmp"; " \
177 "andl %"_LO32 _tmp",("_STK"); " \
178 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
179 "pop %"_tmp"; " \
180 "orl %"_LO32 _tmp",("_STK"); " \
181 "popf; " \
182 "pop %"_sav"; "
183
184 /* After executing instruction: write-back necessary bits in EFLAGS. */
185 #define _POST_EFLAGS(_sav, _msk, _tmp) \
186 /* _sav |= EFLAGS & _msk; */ \
187 "pushf; " \
188 "pop %"_tmp"; " \
189 "andl %"_msk",%"_LO32 _tmp"; " \
190 "orl %"_LO32 _tmp",%"_sav"; "
191
192 #ifdef CONFIG_X86_64
193 #define ON64(x) x
194 #else
195 #define ON64(x)
196 #endif
197
198 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
199 do { \
200 __asm__ __volatile__ ( \
201 _PRE_EFLAGS("0", "4", "2") \
202 _op _suffix " %"_x"3,%1; " \
203 _POST_EFLAGS("0", "4", "2") \
204 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
205 "=&r" (_tmp) \
206 : _y ((_src).val), "i" (EFLAGS_MASK)); \
207 } while (0)
208
209
210 /* Raw emulation: instruction has two explicit operands. */
211 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
212 do { \
213 unsigned long _tmp; \
214 \
215 switch ((_dst).bytes) { \
216 case 2: \
217 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
218 break; \
219 case 4: \
220 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
221 break; \
222 case 8: \
223 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
224 break; \
225 } \
226 } while (0)
227
228 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
229 do { \
230 unsigned long _tmp; \
231 switch ((_dst).bytes) { \
232 case 1: \
233 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
234 break; \
235 default: \
236 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
237 _wx, _wy, _lx, _ly, _qx, _qy); \
238 break; \
239 } \
240 } while (0)
241
242 /* Source operand is byte-sized and may be restricted to just %cl. */
243 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
244 __emulate_2op(_op, _src, _dst, _eflags, \
245 "b", "c", "b", "c", "b", "c", "b", "c")
246
247 /* Source operand is byte, word, long or quad sized. */
248 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
249 __emulate_2op(_op, _src, _dst, _eflags, \
250 "b", "q", "w", "r", _LO32, "r", "", "r")
251
252 /* Source operand is word, long or quad sized. */
253 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
254 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
255 "w", "r", _LO32, "r", "", "r")
256
257 /* Instruction has three operands and one operand is stored in ECX register */
258 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
259 do { \
260 unsigned long _tmp; \
261 _type _clv = (_cl).val; \
262 _type _srcv = (_src).val; \
263 _type _dstv = (_dst).val; \
264 \
265 __asm__ __volatile__ ( \
266 _PRE_EFLAGS("0", "5", "2") \
267 _op _suffix " %4,%1 \n" \
268 _POST_EFLAGS("0", "5", "2") \
269 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
270 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
271 ); \
272 \
273 (_cl).val = (unsigned long) _clv; \
274 (_src).val = (unsigned long) _srcv; \
275 (_dst).val = (unsigned long) _dstv; \
276 } while (0)
277
278 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
279 do { \
280 switch ((_dst).bytes) { \
281 case 2: \
282 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
283 "w", unsigned short); \
284 break; \
285 case 4: \
286 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
287 "l", unsigned int); \
288 break; \
289 case 8: \
290 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
291 "q", unsigned long)); \
292 break; \
293 } \
294 } while (0)
295
296 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
297 do { \
298 unsigned long _tmp; \
299 \
300 __asm__ __volatile__ ( \
301 _PRE_EFLAGS("0", "3", "2") \
302 _op _suffix " %1; " \
303 _POST_EFLAGS("0", "3", "2") \
304 : "=m" (_eflags), "+m" ((_dst).val), \
305 "=&r" (_tmp) \
306 : "i" (EFLAGS_MASK)); \
307 } while (0)
308
309 /* Instruction has only one explicit operand (no source operand). */
310 #define emulate_1op(_op, _dst, _eflags) \
311 do { \
312 switch ((_dst).bytes) { \
313 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
314 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
315 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
316 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
317 } \
318 } while (0)
319
320 #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
321 do { \
322 unsigned long _tmp; \
323 \
324 __asm__ __volatile__ ( \
325 _PRE_EFLAGS("0", "4", "1") \
326 _op _suffix " %5; " \
327 _POST_EFLAGS("0", "4", "1") \
328 : "=m" (_eflags), "=&r" (_tmp), \
329 "+a" (_rax), "+d" (_rdx) \
330 : "i" (EFLAGS_MASK), "m" ((_src).val), \
331 "a" (_rax), "d" (_rdx)); \
332 } while (0)
333
334 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
335 #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
336 do { \
337 switch((_src).bytes) { \
338 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
339 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
340 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
341 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
342 } \
343 } while (0)
344
345 /* Fetch next part of the instruction being emulated. */
346 #define insn_fetch(_type, _size, _eip) \
347 ({ unsigned long _x; \
348 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
349 if (rc != X86EMUL_CONTINUE) \
350 goto done; \
351 (_eip) += (_size); \
352 (_type)_x; \
353 })
354
355 #define insn_fetch_arr(_arr, _size, _eip) \
356 ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
357 if (rc != X86EMUL_CONTINUE) \
358 goto done; \
359 (_eip) += (_size); \
360 })
361
362 static inline unsigned long ad_mask(struct decode_cache *c)
363 {
364 return (1UL << (c->ad_bytes << 3)) - 1;
365 }
366
367 /* Access/update address held in a register, based on addressing mode. */
368 static inline unsigned long
369 address_mask(struct decode_cache *c, unsigned long reg)
370 {
371 if (c->ad_bytes == sizeof(unsigned long))
372 return reg;
373 else
374 return reg & ad_mask(c);
375 }
376
377 static inline unsigned long
378 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
379 {
380 return base + address_mask(c, reg);
381 }
382
383 static inline void
384 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
385 {
386 if (c->ad_bytes == sizeof(unsigned long))
387 *reg += inc;
388 else
389 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
390 }
391
392 static inline void jmp_rel(struct decode_cache *c, int rel)
393 {
394 register_address_increment(c, &c->eip, rel);
395 }
396
397 static void set_seg_override(struct decode_cache *c, int seg)
398 {
399 c->has_seg_override = true;
400 c->seg_override = seg;
401 }
402
403 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
404 struct x86_emulate_ops *ops, int seg)
405 {
406 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
407 return 0;
408
409 return ops->get_cached_segment_base(seg, ctxt->vcpu);
410 }
411
412 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
413 struct x86_emulate_ops *ops,
414 struct decode_cache *c)
415 {
416 if (!c->has_seg_override)
417 return 0;
418
419 return seg_base(ctxt, ops, c->seg_override);
420 }
421
422 static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
423 struct x86_emulate_ops *ops)
424 {
425 return seg_base(ctxt, ops, VCPU_SREG_ES);
426 }
427
428 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
429 struct x86_emulate_ops *ops)
430 {
431 return seg_base(ctxt, ops, VCPU_SREG_SS);
432 }
433
434 static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
435 u32 error, bool valid)
436 {
437 ctxt->exception = vec;
438 ctxt->error_code = error;
439 ctxt->error_code_valid = valid;
440 }
441
442 static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
443 {
444 emulate_exception(ctxt, GP_VECTOR, err, true);
445 }
446
447 static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
448 int err)
449 {
450 ctxt->cr2 = addr;
451 emulate_exception(ctxt, PF_VECTOR, err, true);
452 }
453
454 static void emulate_ud(struct x86_emulate_ctxt *ctxt)
455 {
456 emulate_exception(ctxt, UD_VECTOR, 0, false);
457 }
458
459 static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
460 {
461 emulate_exception(ctxt, TS_VECTOR, err, true);
462 }
463
464 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
465 struct x86_emulate_ops *ops,
466 unsigned long eip, u8 *dest)
467 {
468 struct fetch_cache *fc = &ctxt->decode.fetch;
469 int rc;
470 int size, cur_size;
471
472 if (eip == fc->end) {
473 cur_size = fc->end - fc->start;
474 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
475 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
476 size, ctxt->vcpu, NULL);
477 if (rc != X86EMUL_CONTINUE)
478 return rc;
479 fc->end += size;
480 }
481 *dest = fc->data[eip - fc->start];
482 return X86EMUL_CONTINUE;
483 }
484
485 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
486 struct x86_emulate_ops *ops,
487 unsigned long eip, void *dest, unsigned size)
488 {
489 int rc;
490
491 /* x86 instructions are limited to 15 bytes. */
492 if (eip + size - ctxt->eip > 15)
493 return X86EMUL_UNHANDLEABLE;
494 while (size--) {
495 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
496 if (rc != X86EMUL_CONTINUE)
497 return rc;
498 }
499 return X86EMUL_CONTINUE;
500 }
501
502 /*
503 * Given the 'reg' portion of a ModRM byte, and a register block, return a
504 * pointer into the block that addresses the relevant register.
505 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
506 */
507 static void *decode_register(u8 modrm_reg, unsigned long *regs,
508 int highbyte_regs)
509 {
510 void *p;
511
512 p = &regs[modrm_reg];
513 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
514 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
515 return p;
516 }
517
518 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
519 struct x86_emulate_ops *ops,
520 ulong addr,
521 u16 *size, unsigned long *address, int op_bytes)
522 {
523 int rc;
524
525 if (op_bytes == 2)
526 op_bytes = 3;
527 *address = 0;
528 rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL);
529 if (rc != X86EMUL_CONTINUE)
530 return rc;
531 rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL);
532 return rc;
533 }
534
535 static int test_cc(unsigned int condition, unsigned int flags)
536 {
537 int rc = 0;
538
539 switch ((condition & 15) >> 1) {
540 case 0: /* o */
541 rc |= (flags & EFLG_OF);
542 break;
543 case 1: /* b/c/nae */
544 rc |= (flags & EFLG_CF);
545 break;
546 case 2: /* z/e */
547 rc |= (flags & EFLG_ZF);
548 break;
549 case 3: /* be/na */
550 rc |= (flags & (EFLG_CF|EFLG_ZF));
551 break;
552 case 4: /* s */
553 rc |= (flags & EFLG_SF);
554 break;
555 case 5: /* p/pe */
556 rc |= (flags & EFLG_PF);
557 break;
558 case 7: /* le/ng */
559 rc |= (flags & EFLG_ZF);
560 /* fall through */
561 case 6: /* l/nge */
562 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
563 break;
564 }
565
566 /* Odd condition identifiers (lsb == 1) have inverted sense. */
567 return (!!rc ^ (condition & 1));
568 }
569
570 static void fetch_register_operand(struct operand *op)
571 {
572 switch (op->bytes) {
573 case 1:
574 op->val = *(u8 *)op->addr.reg;
575 break;
576 case 2:
577 op->val = *(u16 *)op->addr.reg;
578 break;
579 case 4:
580 op->val = *(u32 *)op->addr.reg;
581 break;
582 case 8:
583 op->val = *(u64 *)op->addr.reg;
584 break;
585 }
586 }
587
588 static void decode_register_operand(struct operand *op,
589 struct decode_cache *c,
590 int inhibit_bytereg)
591 {
592 unsigned reg = c->modrm_reg;
593 int highbyte_regs = c->rex_prefix == 0;
594
595 if (!(c->d & ModRM))
596 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
597 op->type = OP_REG;
598 if ((c->d & ByteOp) && !inhibit_bytereg) {
599 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
600 op->bytes = 1;
601 } else {
602 op->addr.reg = decode_register(reg, c->regs, 0);
603 op->bytes = c->op_bytes;
604 }
605 fetch_register_operand(op);
606 op->orig_val = op->val;
607 }
608
609 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
610 struct x86_emulate_ops *ops,
611 struct operand *op)
612 {
613 struct decode_cache *c = &ctxt->decode;
614 u8 sib;
615 int index_reg = 0, base_reg = 0, scale;
616 int rc = X86EMUL_CONTINUE;
617 ulong modrm_ea = 0;
618
619 if (c->rex_prefix) {
620 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
621 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
622 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
623 }
624
625 c->modrm = insn_fetch(u8, 1, c->eip);
626 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
627 c->modrm_reg |= (c->modrm & 0x38) >> 3;
628 c->modrm_rm |= (c->modrm & 0x07);
629 c->modrm_seg = VCPU_SREG_DS;
630
631 if (c->modrm_mod == 3) {
632 op->type = OP_REG;
633 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
634 op->addr.reg = decode_register(c->modrm_rm,
635 c->regs, c->d & ByteOp);
636 fetch_register_operand(op);
637 return rc;
638 }
639
640 op->type = OP_MEM;
641
642 if (c->ad_bytes == 2) {
643 unsigned bx = c->regs[VCPU_REGS_RBX];
644 unsigned bp = c->regs[VCPU_REGS_RBP];
645 unsigned si = c->regs[VCPU_REGS_RSI];
646 unsigned di = c->regs[VCPU_REGS_RDI];
647
648 /* 16-bit ModR/M decode. */
649 switch (c->modrm_mod) {
650 case 0:
651 if (c->modrm_rm == 6)
652 modrm_ea += insn_fetch(u16, 2, c->eip);
653 break;
654 case 1:
655 modrm_ea += insn_fetch(s8, 1, c->eip);
656 break;
657 case 2:
658 modrm_ea += insn_fetch(u16, 2, c->eip);
659 break;
660 }
661 switch (c->modrm_rm) {
662 case 0:
663 modrm_ea += bx + si;
664 break;
665 case 1:
666 modrm_ea += bx + di;
667 break;
668 case 2:
669 modrm_ea += bp + si;
670 break;
671 case 3:
672 modrm_ea += bp + di;
673 break;
674 case 4:
675 modrm_ea += si;
676 break;
677 case 5:
678 modrm_ea += di;
679 break;
680 case 6:
681 if (c->modrm_mod != 0)
682 modrm_ea += bp;
683 break;
684 case 7:
685 modrm_ea += bx;
686 break;
687 }
688 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
689 (c->modrm_rm == 6 && c->modrm_mod != 0))
690 c->modrm_seg = VCPU_SREG_SS;
691 modrm_ea = (u16)modrm_ea;
692 } else {
693 /* 32/64-bit ModR/M decode. */
694 if ((c->modrm_rm & 7) == 4) {
695 sib = insn_fetch(u8, 1, c->eip);
696 index_reg |= (sib >> 3) & 7;
697 base_reg |= sib & 7;
698 scale = sib >> 6;
699
700 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
701 modrm_ea += insn_fetch(s32, 4, c->eip);
702 else
703 modrm_ea += c->regs[base_reg];
704 if (index_reg != 4)
705 modrm_ea += c->regs[index_reg] << scale;
706 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
707 if (ctxt->mode == X86EMUL_MODE_PROT64)
708 c->rip_relative = 1;
709 } else
710 modrm_ea += c->regs[c->modrm_rm];
711 switch (c->modrm_mod) {
712 case 0:
713 if (c->modrm_rm == 5)
714 modrm_ea += insn_fetch(s32, 4, c->eip);
715 break;
716 case 1:
717 modrm_ea += insn_fetch(s8, 1, c->eip);
718 break;
719 case 2:
720 modrm_ea += insn_fetch(s32, 4, c->eip);
721 break;
722 }
723 }
724 op->addr.mem = modrm_ea;
725 done:
726 return rc;
727 }
728
729 static int decode_abs(struct x86_emulate_ctxt *ctxt,
730 struct x86_emulate_ops *ops,
731 struct operand *op)
732 {
733 struct decode_cache *c = &ctxt->decode;
734 int rc = X86EMUL_CONTINUE;
735
736 op->type = OP_MEM;
737 switch (c->ad_bytes) {
738 case 2:
739 op->addr.mem = insn_fetch(u16, 2, c->eip);
740 break;
741 case 4:
742 op->addr.mem = insn_fetch(u32, 4, c->eip);
743 break;
744 case 8:
745 op->addr.mem = insn_fetch(u64, 8, c->eip);
746 break;
747 }
748 done:
749 return rc;
750 }
751
752 static void fetch_bit_operand(struct decode_cache *c)
753 {
754 long sv, mask;
755
756 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
757 mask = ~(c->dst.bytes * 8 - 1);
758
759 if (c->src.bytes == 2)
760 sv = (s16)c->src.val & (s16)mask;
761 else if (c->src.bytes == 4)
762 sv = (s32)c->src.val & (s32)mask;
763
764 c->dst.addr.mem += (sv >> 3);
765 }
766
767 /* only subword offset */
768 c->src.val &= (c->dst.bytes << 3) - 1;
769 }
770
771 static int read_emulated(struct x86_emulate_ctxt *ctxt,
772 struct x86_emulate_ops *ops,
773 unsigned long addr, void *dest, unsigned size)
774 {
775 int rc;
776 struct read_cache *mc = &ctxt->decode.mem_read;
777 u32 err;
778
779 while (size) {
780 int n = min(size, 8u);
781 size -= n;
782 if (mc->pos < mc->end)
783 goto read_cached;
784
785 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
786 ctxt->vcpu);
787 if (rc == X86EMUL_PROPAGATE_FAULT)
788 emulate_pf(ctxt, addr, err);
789 if (rc != X86EMUL_CONTINUE)
790 return rc;
791 mc->end += n;
792
793 read_cached:
794 memcpy(dest, mc->data + mc->pos, n);
795 mc->pos += n;
796 dest += n;
797 addr += n;
798 }
799 return X86EMUL_CONTINUE;
800 }
801
802 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
803 struct x86_emulate_ops *ops,
804 unsigned int size, unsigned short port,
805 void *dest)
806 {
807 struct read_cache *rc = &ctxt->decode.io_read;
808
809 if (rc->pos == rc->end) { /* refill pio read ahead */
810 struct decode_cache *c = &ctxt->decode;
811 unsigned int in_page, n;
812 unsigned int count = c->rep_prefix ?
813 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
814 in_page = (ctxt->eflags & EFLG_DF) ?
815 offset_in_page(c->regs[VCPU_REGS_RDI]) :
816 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
817 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
818 count);
819 if (n == 0)
820 n = 1;
821 rc->pos = rc->end = 0;
822 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
823 return 0;
824 rc->end = n * size;
825 }
826
827 memcpy(dest, rc->data + rc->pos, size);
828 rc->pos += size;
829 return 1;
830 }
831
832 static u32 desc_limit_scaled(struct desc_struct *desc)
833 {
834 u32 limit = get_desc_limit(desc);
835
836 return desc->g ? (limit << 12) | 0xfff : limit;
837 }
838
839 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
840 struct x86_emulate_ops *ops,
841 u16 selector, struct desc_ptr *dt)
842 {
843 if (selector & 1 << 2) {
844 struct desc_struct desc;
845 memset (dt, 0, sizeof *dt);
846 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
847 return;
848
849 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
850 dt->address = get_desc_base(&desc);
851 } else
852 ops->get_gdt(dt, ctxt->vcpu);
853 }
854
855 /* allowed just for 8 bytes segments */
856 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
857 struct x86_emulate_ops *ops,
858 u16 selector, struct desc_struct *desc)
859 {
860 struct desc_ptr dt;
861 u16 index = selector >> 3;
862 int ret;
863 u32 err;
864 ulong addr;
865
866 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
867
868 if (dt.size < index * 8 + 7) {
869 emulate_gp(ctxt, selector & 0xfffc);
870 return X86EMUL_PROPAGATE_FAULT;
871 }
872 addr = dt.address + index * 8;
873 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
874 if (ret == X86EMUL_PROPAGATE_FAULT)
875 emulate_pf(ctxt, addr, err);
876
877 return ret;
878 }
879
880 /* allowed just for 8 bytes segments */
881 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
882 struct x86_emulate_ops *ops,
883 u16 selector, struct desc_struct *desc)
884 {
885 struct desc_ptr dt;
886 u16 index = selector >> 3;
887 u32 err;
888 ulong addr;
889 int ret;
890
891 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
892
893 if (dt.size < index * 8 + 7) {
894 emulate_gp(ctxt, selector & 0xfffc);
895 return X86EMUL_PROPAGATE_FAULT;
896 }
897
898 addr = dt.address + index * 8;
899 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
900 if (ret == X86EMUL_PROPAGATE_FAULT)
901 emulate_pf(ctxt, addr, err);
902
903 return ret;
904 }
905
906 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
907 struct x86_emulate_ops *ops,
908 u16 selector, int seg)
909 {
910 struct desc_struct seg_desc;
911 u8 dpl, rpl, cpl;
912 unsigned err_vec = GP_VECTOR;
913 u32 err_code = 0;
914 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
915 int ret;
916
917 memset(&seg_desc, 0, sizeof seg_desc);
918
919 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
920 || ctxt->mode == X86EMUL_MODE_REAL) {
921 /* set real mode segment descriptor */
922 set_desc_base(&seg_desc, selector << 4);
923 set_desc_limit(&seg_desc, 0xffff);
924 seg_desc.type = 3;
925 seg_desc.p = 1;
926 seg_desc.s = 1;
927 goto load;
928 }
929
930 /* NULL selector is not valid for TR, CS and SS */
931 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
932 && null_selector)
933 goto exception;
934
935 /* TR should be in GDT only */
936 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
937 goto exception;
938
939 if (null_selector) /* for NULL selector skip all following checks */
940 goto load;
941
942 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
943 if (ret != X86EMUL_CONTINUE)
944 return ret;
945
946 err_code = selector & 0xfffc;
947 err_vec = GP_VECTOR;
948
949 /* can't load system descriptor into segment selecor */
950 if (seg <= VCPU_SREG_GS && !seg_desc.s)
951 goto exception;
952
953 if (!seg_desc.p) {
954 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
955 goto exception;
956 }
957
958 rpl = selector & 3;
959 dpl = seg_desc.dpl;
960 cpl = ops->cpl(ctxt->vcpu);
961
962 switch (seg) {
963 case VCPU_SREG_SS:
964 /*
965 * segment is not a writable data segment or segment
966 * selector's RPL != CPL or segment selector's RPL != CPL
967 */
968 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
969 goto exception;
970 break;
971 case VCPU_SREG_CS:
972 if (!(seg_desc.type & 8))
973 goto exception;
974
975 if (seg_desc.type & 4) {
976 /* conforming */
977 if (dpl > cpl)
978 goto exception;
979 } else {
980 /* nonconforming */
981 if (rpl > cpl || dpl != cpl)
982 goto exception;
983 }
984 /* CS(RPL) <- CPL */
985 selector = (selector & 0xfffc) | cpl;
986 break;
987 case VCPU_SREG_TR:
988 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
989 goto exception;
990 break;
991 case VCPU_SREG_LDTR:
992 if (seg_desc.s || seg_desc.type != 2)
993 goto exception;
994 break;
995 default: /* DS, ES, FS, or GS */
996 /*
997 * segment is not a data or readable code segment or
998 * ((segment is a data or nonconforming code segment)
999 * and (both RPL and CPL > DPL))
1000 */
1001 if ((seg_desc.type & 0xa) == 0x8 ||
1002 (((seg_desc.type & 0xc) != 0xc) &&
1003 (rpl > dpl && cpl > dpl)))
1004 goto exception;
1005 break;
1006 }
1007
1008 if (seg_desc.s) {
1009 /* mark segment as accessed */
1010 seg_desc.type |= 1;
1011 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1012 if (ret != X86EMUL_CONTINUE)
1013 return ret;
1014 }
1015 load:
1016 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1017 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1018 return X86EMUL_CONTINUE;
1019 exception:
1020 emulate_exception(ctxt, err_vec, err_code, true);
1021 return X86EMUL_PROPAGATE_FAULT;
1022 }
1023
1024 static void write_register_operand(struct operand *op)
1025 {
1026 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1027 switch (op->bytes) {
1028 case 1:
1029 *(u8 *)op->addr.reg = (u8)op->val;
1030 break;
1031 case 2:
1032 *(u16 *)op->addr.reg = (u16)op->val;
1033 break;
1034 case 4:
1035 *op->addr.reg = (u32)op->val;
1036 break; /* 64b: zero-extend */
1037 case 8:
1038 *op->addr.reg = op->val;
1039 break;
1040 }
1041 }
1042
1043 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1044 struct x86_emulate_ops *ops)
1045 {
1046 int rc;
1047 struct decode_cache *c = &ctxt->decode;
1048 u32 err;
1049
1050 switch (c->dst.type) {
1051 case OP_REG:
1052 write_register_operand(&c->dst);
1053 break;
1054 case OP_MEM:
1055 if (c->lock_prefix)
1056 rc = ops->cmpxchg_emulated(
1057 c->dst.addr.mem,
1058 &c->dst.orig_val,
1059 &c->dst.val,
1060 c->dst.bytes,
1061 &err,
1062 ctxt->vcpu);
1063 else
1064 rc = ops->write_emulated(
1065 c->dst.addr.mem,
1066 &c->dst.val,
1067 c->dst.bytes,
1068 &err,
1069 ctxt->vcpu);
1070 if (rc == X86EMUL_PROPAGATE_FAULT)
1071 emulate_pf(ctxt, c->dst.addr.mem, err);
1072 if (rc != X86EMUL_CONTINUE)
1073 return rc;
1074 break;
1075 case OP_NONE:
1076 /* no writeback */
1077 break;
1078 default:
1079 break;
1080 }
1081 return X86EMUL_CONTINUE;
1082 }
1083
1084 static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1085 struct x86_emulate_ops *ops)
1086 {
1087 struct decode_cache *c = &ctxt->decode;
1088
1089 c->dst.type = OP_MEM;
1090 c->dst.bytes = c->op_bytes;
1091 c->dst.val = c->src.val;
1092 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1093 c->dst.addr.mem = register_address(c, ss_base(ctxt, ops),
1094 c->regs[VCPU_REGS_RSP]);
1095 }
1096
1097 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1098 struct x86_emulate_ops *ops,
1099 void *dest, int len)
1100 {
1101 struct decode_cache *c = &ctxt->decode;
1102 int rc;
1103
1104 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
1105 c->regs[VCPU_REGS_RSP]),
1106 dest, len);
1107 if (rc != X86EMUL_CONTINUE)
1108 return rc;
1109
1110 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1111 return rc;
1112 }
1113
1114 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1115 struct x86_emulate_ops *ops,
1116 void *dest, int len)
1117 {
1118 int rc;
1119 unsigned long val, change_mask;
1120 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1121 int cpl = ops->cpl(ctxt->vcpu);
1122
1123 rc = emulate_pop(ctxt, ops, &val, len);
1124 if (rc != X86EMUL_CONTINUE)
1125 return rc;
1126
1127 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1128 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1129
1130 switch(ctxt->mode) {
1131 case X86EMUL_MODE_PROT64:
1132 case X86EMUL_MODE_PROT32:
1133 case X86EMUL_MODE_PROT16:
1134 if (cpl == 0)
1135 change_mask |= EFLG_IOPL;
1136 if (cpl <= iopl)
1137 change_mask |= EFLG_IF;
1138 break;
1139 case X86EMUL_MODE_VM86:
1140 if (iopl < 3) {
1141 emulate_gp(ctxt, 0);
1142 return X86EMUL_PROPAGATE_FAULT;
1143 }
1144 change_mask |= EFLG_IF;
1145 break;
1146 default: /* real mode */
1147 change_mask |= (EFLG_IOPL | EFLG_IF);
1148 break;
1149 }
1150
1151 *(unsigned long *)dest =
1152 (ctxt->eflags & ~change_mask) | (val & change_mask);
1153
1154 return rc;
1155 }
1156
1157 static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1158 struct x86_emulate_ops *ops, int seg)
1159 {
1160 struct decode_cache *c = &ctxt->decode;
1161
1162 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
1163
1164 emulate_push(ctxt, ops);
1165 }
1166
1167 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1168 struct x86_emulate_ops *ops, int seg)
1169 {
1170 struct decode_cache *c = &ctxt->decode;
1171 unsigned long selector;
1172 int rc;
1173
1174 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1175 if (rc != X86EMUL_CONTINUE)
1176 return rc;
1177
1178 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1179 return rc;
1180 }
1181
1182 static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1183 struct x86_emulate_ops *ops)
1184 {
1185 struct decode_cache *c = &ctxt->decode;
1186 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1187 int rc = X86EMUL_CONTINUE;
1188 int reg = VCPU_REGS_RAX;
1189
1190 while (reg <= VCPU_REGS_RDI) {
1191 (reg == VCPU_REGS_RSP) ?
1192 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1193
1194 emulate_push(ctxt, ops);
1195
1196 rc = writeback(ctxt, ops);
1197 if (rc != X86EMUL_CONTINUE)
1198 return rc;
1199
1200 ++reg;
1201 }
1202
1203 /* Disable writeback. */
1204 c->dst.type = OP_NONE;
1205
1206 return rc;
1207 }
1208
1209 static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1210 struct x86_emulate_ops *ops)
1211 {
1212 struct decode_cache *c = &ctxt->decode;
1213 int rc = X86EMUL_CONTINUE;
1214 int reg = VCPU_REGS_RDI;
1215
1216 while (reg >= VCPU_REGS_RAX) {
1217 if (reg == VCPU_REGS_RSP) {
1218 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1219 c->op_bytes);
1220 --reg;
1221 }
1222
1223 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1224 if (rc != X86EMUL_CONTINUE)
1225 break;
1226 --reg;
1227 }
1228 return rc;
1229 }
1230
1231 int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1232 struct x86_emulate_ops *ops, int irq)
1233 {
1234 struct decode_cache *c = &ctxt->decode;
1235 int rc;
1236 struct desc_ptr dt;
1237 gva_t cs_addr;
1238 gva_t eip_addr;
1239 u16 cs, eip;
1240 u32 err;
1241
1242 /* TODO: Add limit checks */
1243 c->src.val = ctxt->eflags;
1244 emulate_push(ctxt, ops);
1245 rc = writeback(ctxt, ops);
1246 if (rc != X86EMUL_CONTINUE)
1247 return rc;
1248
1249 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1250
1251 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1252 emulate_push(ctxt, ops);
1253 rc = writeback(ctxt, ops);
1254 if (rc != X86EMUL_CONTINUE)
1255 return rc;
1256
1257 c->src.val = c->eip;
1258 emulate_push(ctxt, ops);
1259 rc = writeback(ctxt, ops);
1260 if (rc != X86EMUL_CONTINUE)
1261 return rc;
1262
1263 c->dst.type = OP_NONE;
1264
1265 ops->get_idt(&dt, ctxt->vcpu);
1266
1267 eip_addr = dt.address + (irq << 2);
1268 cs_addr = dt.address + (irq << 2) + 2;
1269
1270 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &err);
1271 if (rc != X86EMUL_CONTINUE)
1272 return rc;
1273
1274 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &err);
1275 if (rc != X86EMUL_CONTINUE)
1276 return rc;
1277
1278 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1279 if (rc != X86EMUL_CONTINUE)
1280 return rc;
1281
1282 c->eip = eip;
1283
1284 return rc;
1285 }
1286
1287 static int emulate_int(struct x86_emulate_ctxt *ctxt,
1288 struct x86_emulate_ops *ops, int irq)
1289 {
1290 switch(ctxt->mode) {
1291 case X86EMUL_MODE_REAL:
1292 return emulate_int_real(ctxt, ops, irq);
1293 case X86EMUL_MODE_VM86:
1294 case X86EMUL_MODE_PROT16:
1295 case X86EMUL_MODE_PROT32:
1296 case X86EMUL_MODE_PROT64:
1297 default:
1298 /* Protected mode interrupts unimplemented yet */
1299 return X86EMUL_UNHANDLEABLE;
1300 }
1301 }
1302
1303 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1304 struct x86_emulate_ops *ops)
1305 {
1306 struct decode_cache *c = &ctxt->decode;
1307 int rc = X86EMUL_CONTINUE;
1308 unsigned long temp_eip = 0;
1309 unsigned long temp_eflags = 0;
1310 unsigned long cs = 0;
1311 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1312 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1313 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1314 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1315
1316 /* TODO: Add stack limit check */
1317
1318 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1319
1320 if (rc != X86EMUL_CONTINUE)
1321 return rc;
1322
1323 if (temp_eip & ~0xffff) {
1324 emulate_gp(ctxt, 0);
1325 return X86EMUL_PROPAGATE_FAULT;
1326 }
1327
1328 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1329
1330 if (rc != X86EMUL_CONTINUE)
1331 return rc;
1332
1333 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1334
1335 if (rc != X86EMUL_CONTINUE)
1336 return rc;
1337
1338 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1339
1340 if (rc != X86EMUL_CONTINUE)
1341 return rc;
1342
1343 c->eip = temp_eip;
1344
1345
1346 if (c->op_bytes == 4)
1347 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1348 else if (c->op_bytes == 2) {
1349 ctxt->eflags &= ~0xffff;
1350 ctxt->eflags |= temp_eflags;
1351 }
1352
1353 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1354 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1355
1356 return rc;
1357 }
1358
1359 static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1360 struct x86_emulate_ops* ops)
1361 {
1362 switch(ctxt->mode) {
1363 case X86EMUL_MODE_REAL:
1364 return emulate_iret_real(ctxt, ops);
1365 case X86EMUL_MODE_VM86:
1366 case X86EMUL_MODE_PROT16:
1367 case X86EMUL_MODE_PROT32:
1368 case X86EMUL_MODE_PROT64:
1369 default:
1370 /* iret from protected mode unimplemented yet */
1371 return X86EMUL_UNHANDLEABLE;
1372 }
1373 }
1374
1375 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1376 struct x86_emulate_ops *ops)
1377 {
1378 struct decode_cache *c = &ctxt->decode;
1379
1380 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1381 }
1382
1383 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1384 {
1385 struct decode_cache *c = &ctxt->decode;
1386 switch (c->modrm_reg) {
1387 case 0: /* rol */
1388 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1389 break;
1390 case 1: /* ror */
1391 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1392 break;
1393 case 2: /* rcl */
1394 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1395 break;
1396 case 3: /* rcr */
1397 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1398 break;
1399 case 4: /* sal/shl */
1400 case 6: /* sal/shl */
1401 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1402 break;
1403 case 5: /* shr */
1404 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1405 break;
1406 case 7: /* sar */
1407 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1408 break;
1409 }
1410 }
1411
1412 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1413 struct x86_emulate_ops *ops)
1414 {
1415 struct decode_cache *c = &ctxt->decode;
1416 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1417 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
1418
1419 switch (c->modrm_reg) {
1420 case 0 ... 1: /* test */
1421 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1422 break;
1423 case 2: /* not */
1424 c->dst.val = ~c->dst.val;
1425 break;
1426 case 3: /* neg */
1427 emulate_1op("neg", c->dst, ctxt->eflags);
1428 break;
1429 case 4: /* mul */
1430 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1431 break;
1432 case 5: /* imul */
1433 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1434 break;
1435 case 6: /* div */
1436 emulate_1op_rax_rdx("div", c->src, *rax, *rdx, ctxt->eflags);
1437 break;
1438 case 7: /* idiv */
1439 emulate_1op_rax_rdx("idiv", c->src, *rax, *rdx, ctxt->eflags);
1440 break;
1441 default:
1442 return X86EMUL_UNHANDLEABLE;
1443 }
1444 return X86EMUL_CONTINUE;
1445 }
1446
1447 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1448 struct x86_emulate_ops *ops)
1449 {
1450 struct decode_cache *c = &ctxt->decode;
1451
1452 switch (c->modrm_reg) {
1453 case 0: /* inc */
1454 emulate_1op("inc", c->dst, ctxt->eflags);
1455 break;
1456 case 1: /* dec */
1457 emulate_1op("dec", c->dst, ctxt->eflags);
1458 break;
1459 case 2: /* call near abs */ {
1460 long int old_eip;
1461 old_eip = c->eip;
1462 c->eip = c->src.val;
1463 c->src.val = old_eip;
1464 emulate_push(ctxt, ops);
1465 break;
1466 }
1467 case 4: /* jmp abs */
1468 c->eip = c->src.val;
1469 break;
1470 case 6: /* push */
1471 emulate_push(ctxt, ops);
1472 break;
1473 }
1474 return X86EMUL_CONTINUE;
1475 }
1476
1477 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1478 struct x86_emulate_ops *ops)
1479 {
1480 struct decode_cache *c = &ctxt->decode;
1481 u64 old = c->dst.orig_val64;
1482
1483 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1484 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1485 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1486 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1487 ctxt->eflags &= ~EFLG_ZF;
1488 } else {
1489 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1490 (u32) c->regs[VCPU_REGS_RBX];
1491
1492 ctxt->eflags |= EFLG_ZF;
1493 }
1494 return X86EMUL_CONTINUE;
1495 }
1496
1497 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1498 struct x86_emulate_ops *ops)
1499 {
1500 struct decode_cache *c = &ctxt->decode;
1501 int rc;
1502 unsigned long cs;
1503
1504 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1505 if (rc != X86EMUL_CONTINUE)
1506 return rc;
1507 if (c->op_bytes == 4)
1508 c->eip = (u32)c->eip;
1509 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1510 if (rc != X86EMUL_CONTINUE)
1511 return rc;
1512 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1513 return rc;
1514 }
1515
1516 static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1517 struct x86_emulate_ops *ops, int seg)
1518 {
1519 struct decode_cache *c = &ctxt->decode;
1520 unsigned short sel;
1521 int rc;
1522
1523 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1524
1525 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1526 if (rc != X86EMUL_CONTINUE)
1527 return rc;
1528
1529 c->dst.val = c->src.val;
1530 return rc;
1531 }
1532
1533 static inline void
1534 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1535 struct x86_emulate_ops *ops, struct desc_struct *cs,
1536 struct desc_struct *ss)
1537 {
1538 memset(cs, 0, sizeof(struct desc_struct));
1539 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1540 memset(ss, 0, sizeof(struct desc_struct));
1541
1542 cs->l = 0; /* will be adjusted later */
1543 set_desc_base(cs, 0); /* flat segment */
1544 cs->g = 1; /* 4kb granularity */
1545 set_desc_limit(cs, 0xfffff); /* 4GB limit */
1546 cs->type = 0x0b; /* Read, Execute, Accessed */
1547 cs->s = 1;
1548 cs->dpl = 0; /* will be adjusted later */
1549 cs->p = 1;
1550 cs->d = 1;
1551
1552 set_desc_base(ss, 0); /* flat segment */
1553 set_desc_limit(ss, 0xfffff); /* 4GB limit */
1554 ss->g = 1; /* 4kb granularity */
1555 ss->s = 1;
1556 ss->type = 0x03; /* Read/Write, Accessed */
1557 ss->d = 1; /* 32bit stack segment */
1558 ss->dpl = 0;
1559 ss->p = 1;
1560 }
1561
1562 static int
1563 emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1564 {
1565 struct decode_cache *c = &ctxt->decode;
1566 struct desc_struct cs, ss;
1567 u64 msr_data;
1568 u16 cs_sel, ss_sel;
1569
1570 /* syscall is not available in real mode */
1571 if (ctxt->mode == X86EMUL_MODE_REAL ||
1572 ctxt->mode == X86EMUL_MODE_VM86) {
1573 emulate_ud(ctxt);
1574 return X86EMUL_PROPAGATE_FAULT;
1575 }
1576
1577 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1578
1579 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1580 msr_data >>= 32;
1581 cs_sel = (u16)(msr_data & 0xfffc);
1582 ss_sel = (u16)(msr_data + 8);
1583
1584 if (is_long_mode(ctxt->vcpu)) {
1585 cs.d = 0;
1586 cs.l = 1;
1587 }
1588 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1589 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1590 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1591 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1592
1593 c->regs[VCPU_REGS_RCX] = c->eip;
1594 if (is_long_mode(ctxt->vcpu)) {
1595 #ifdef CONFIG_X86_64
1596 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1597
1598 ops->get_msr(ctxt->vcpu,
1599 ctxt->mode == X86EMUL_MODE_PROT64 ?
1600 MSR_LSTAR : MSR_CSTAR, &msr_data);
1601 c->eip = msr_data;
1602
1603 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1604 ctxt->eflags &= ~(msr_data | EFLG_RF);
1605 #endif
1606 } else {
1607 /* legacy mode */
1608 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1609 c->eip = (u32)msr_data;
1610
1611 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1612 }
1613
1614 return X86EMUL_CONTINUE;
1615 }
1616
1617 static int
1618 emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1619 {
1620 struct decode_cache *c = &ctxt->decode;
1621 struct desc_struct cs, ss;
1622 u64 msr_data;
1623 u16 cs_sel, ss_sel;
1624
1625 /* inject #GP if in real mode */
1626 if (ctxt->mode == X86EMUL_MODE_REAL) {
1627 emulate_gp(ctxt, 0);
1628 return X86EMUL_PROPAGATE_FAULT;
1629 }
1630
1631 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1632 * Therefore, we inject an #UD.
1633 */
1634 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1635 emulate_ud(ctxt);
1636 return X86EMUL_PROPAGATE_FAULT;
1637 }
1638
1639 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1640
1641 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1642 switch (ctxt->mode) {
1643 case X86EMUL_MODE_PROT32:
1644 if ((msr_data & 0xfffc) == 0x0) {
1645 emulate_gp(ctxt, 0);
1646 return X86EMUL_PROPAGATE_FAULT;
1647 }
1648 break;
1649 case X86EMUL_MODE_PROT64:
1650 if (msr_data == 0x0) {
1651 emulate_gp(ctxt, 0);
1652 return X86EMUL_PROPAGATE_FAULT;
1653 }
1654 break;
1655 }
1656
1657 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1658 cs_sel = (u16)msr_data;
1659 cs_sel &= ~SELECTOR_RPL_MASK;
1660 ss_sel = cs_sel + 8;
1661 ss_sel &= ~SELECTOR_RPL_MASK;
1662 if (ctxt->mode == X86EMUL_MODE_PROT64
1663 || is_long_mode(ctxt->vcpu)) {
1664 cs.d = 0;
1665 cs.l = 1;
1666 }
1667
1668 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1669 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1670 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1671 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1672
1673 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1674 c->eip = msr_data;
1675
1676 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1677 c->regs[VCPU_REGS_RSP] = msr_data;
1678
1679 return X86EMUL_CONTINUE;
1680 }
1681
1682 static int
1683 emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1684 {
1685 struct decode_cache *c = &ctxt->decode;
1686 struct desc_struct cs, ss;
1687 u64 msr_data;
1688 int usermode;
1689 u16 cs_sel, ss_sel;
1690
1691 /* inject #GP if in real mode or Virtual 8086 mode */
1692 if (ctxt->mode == X86EMUL_MODE_REAL ||
1693 ctxt->mode == X86EMUL_MODE_VM86) {
1694 emulate_gp(ctxt, 0);
1695 return X86EMUL_PROPAGATE_FAULT;
1696 }
1697
1698 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1699
1700 if ((c->rex_prefix & 0x8) != 0x0)
1701 usermode = X86EMUL_MODE_PROT64;
1702 else
1703 usermode = X86EMUL_MODE_PROT32;
1704
1705 cs.dpl = 3;
1706 ss.dpl = 3;
1707 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1708 switch (usermode) {
1709 case X86EMUL_MODE_PROT32:
1710 cs_sel = (u16)(msr_data + 16);
1711 if ((msr_data & 0xfffc) == 0x0) {
1712 emulate_gp(ctxt, 0);
1713 return X86EMUL_PROPAGATE_FAULT;
1714 }
1715 ss_sel = (u16)(msr_data + 24);
1716 break;
1717 case X86EMUL_MODE_PROT64:
1718 cs_sel = (u16)(msr_data + 32);
1719 if (msr_data == 0x0) {
1720 emulate_gp(ctxt, 0);
1721 return X86EMUL_PROPAGATE_FAULT;
1722 }
1723 ss_sel = cs_sel + 8;
1724 cs.d = 0;
1725 cs.l = 1;
1726 break;
1727 }
1728 cs_sel |= SELECTOR_RPL_MASK;
1729 ss_sel |= SELECTOR_RPL_MASK;
1730
1731 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1732 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1733 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1734 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1735
1736 c->eip = c->regs[VCPU_REGS_RDX];
1737 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
1738
1739 return X86EMUL_CONTINUE;
1740 }
1741
1742 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1743 struct x86_emulate_ops *ops)
1744 {
1745 int iopl;
1746 if (ctxt->mode == X86EMUL_MODE_REAL)
1747 return false;
1748 if (ctxt->mode == X86EMUL_MODE_VM86)
1749 return true;
1750 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1751 return ops->cpl(ctxt->vcpu) > iopl;
1752 }
1753
1754 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1755 struct x86_emulate_ops *ops,
1756 u16 port, u16 len)
1757 {
1758 struct desc_struct tr_seg;
1759 int r;
1760 u16 io_bitmap_ptr;
1761 u8 perm, bit_idx = port & 0x7;
1762 unsigned mask = (1 << len) - 1;
1763
1764 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
1765 if (!tr_seg.p)
1766 return false;
1767 if (desc_limit_scaled(&tr_seg) < 103)
1768 return false;
1769 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
1770 ctxt->vcpu, NULL);
1771 if (r != X86EMUL_CONTINUE)
1772 return false;
1773 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
1774 return false;
1775 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
1776 &perm, 1, ctxt->vcpu, NULL);
1777 if (r != X86EMUL_CONTINUE)
1778 return false;
1779 if ((perm >> bit_idx) & mask)
1780 return false;
1781 return true;
1782 }
1783
1784 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1785 struct x86_emulate_ops *ops,
1786 u16 port, u16 len)
1787 {
1788 if (ctxt->perm_ok)
1789 return true;
1790
1791 if (emulator_bad_iopl(ctxt, ops))
1792 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1793 return false;
1794
1795 ctxt->perm_ok = true;
1796
1797 return true;
1798 }
1799
1800 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1801 struct x86_emulate_ops *ops,
1802 struct tss_segment_16 *tss)
1803 {
1804 struct decode_cache *c = &ctxt->decode;
1805
1806 tss->ip = c->eip;
1807 tss->flag = ctxt->eflags;
1808 tss->ax = c->regs[VCPU_REGS_RAX];
1809 tss->cx = c->regs[VCPU_REGS_RCX];
1810 tss->dx = c->regs[VCPU_REGS_RDX];
1811 tss->bx = c->regs[VCPU_REGS_RBX];
1812 tss->sp = c->regs[VCPU_REGS_RSP];
1813 tss->bp = c->regs[VCPU_REGS_RBP];
1814 tss->si = c->regs[VCPU_REGS_RSI];
1815 tss->di = c->regs[VCPU_REGS_RDI];
1816
1817 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1818 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1819 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1820 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1821 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1822 }
1823
1824 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1825 struct x86_emulate_ops *ops,
1826 struct tss_segment_16 *tss)
1827 {
1828 struct decode_cache *c = &ctxt->decode;
1829 int ret;
1830
1831 c->eip = tss->ip;
1832 ctxt->eflags = tss->flag | 2;
1833 c->regs[VCPU_REGS_RAX] = tss->ax;
1834 c->regs[VCPU_REGS_RCX] = tss->cx;
1835 c->regs[VCPU_REGS_RDX] = tss->dx;
1836 c->regs[VCPU_REGS_RBX] = tss->bx;
1837 c->regs[VCPU_REGS_RSP] = tss->sp;
1838 c->regs[VCPU_REGS_RBP] = tss->bp;
1839 c->regs[VCPU_REGS_RSI] = tss->si;
1840 c->regs[VCPU_REGS_RDI] = tss->di;
1841
1842 /*
1843 * SDM says that segment selectors are loaded before segment
1844 * descriptors
1845 */
1846 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1847 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1848 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1849 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1850 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1851
1852 /*
1853 * Now load segment descriptors. If fault happenes at this stage
1854 * it is handled in a context of new task
1855 */
1856 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1857 if (ret != X86EMUL_CONTINUE)
1858 return ret;
1859 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1860 if (ret != X86EMUL_CONTINUE)
1861 return ret;
1862 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1863 if (ret != X86EMUL_CONTINUE)
1864 return ret;
1865 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1866 if (ret != X86EMUL_CONTINUE)
1867 return ret;
1868 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1869 if (ret != X86EMUL_CONTINUE)
1870 return ret;
1871
1872 return X86EMUL_CONTINUE;
1873 }
1874
1875 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1876 struct x86_emulate_ops *ops,
1877 u16 tss_selector, u16 old_tss_sel,
1878 ulong old_tss_base, struct desc_struct *new_desc)
1879 {
1880 struct tss_segment_16 tss_seg;
1881 int ret;
1882 u32 err, new_tss_base = get_desc_base(new_desc);
1883
1884 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1885 &err);
1886 if (ret == X86EMUL_PROPAGATE_FAULT) {
1887 /* FIXME: need to provide precise fault address */
1888 emulate_pf(ctxt, old_tss_base, err);
1889 return ret;
1890 }
1891
1892 save_state_to_tss16(ctxt, ops, &tss_seg);
1893
1894 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1895 &err);
1896 if (ret == X86EMUL_PROPAGATE_FAULT) {
1897 /* FIXME: need to provide precise fault address */
1898 emulate_pf(ctxt, old_tss_base, err);
1899 return ret;
1900 }
1901
1902 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1903 &err);
1904 if (ret == X86EMUL_PROPAGATE_FAULT) {
1905 /* FIXME: need to provide precise fault address */
1906 emulate_pf(ctxt, new_tss_base, err);
1907 return ret;
1908 }
1909
1910 if (old_tss_sel != 0xffff) {
1911 tss_seg.prev_task_link = old_tss_sel;
1912
1913 ret = ops->write_std(new_tss_base,
1914 &tss_seg.prev_task_link,
1915 sizeof tss_seg.prev_task_link,
1916 ctxt->vcpu, &err);
1917 if (ret == X86EMUL_PROPAGATE_FAULT) {
1918 /* FIXME: need to provide precise fault address */
1919 emulate_pf(ctxt, new_tss_base, err);
1920 return ret;
1921 }
1922 }
1923
1924 return load_state_from_tss16(ctxt, ops, &tss_seg);
1925 }
1926
1927 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1928 struct x86_emulate_ops *ops,
1929 struct tss_segment_32 *tss)
1930 {
1931 struct decode_cache *c = &ctxt->decode;
1932
1933 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1934 tss->eip = c->eip;
1935 tss->eflags = ctxt->eflags;
1936 tss->eax = c->regs[VCPU_REGS_RAX];
1937 tss->ecx = c->regs[VCPU_REGS_RCX];
1938 tss->edx = c->regs[VCPU_REGS_RDX];
1939 tss->ebx = c->regs[VCPU_REGS_RBX];
1940 tss->esp = c->regs[VCPU_REGS_RSP];
1941 tss->ebp = c->regs[VCPU_REGS_RBP];
1942 tss->esi = c->regs[VCPU_REGS_RSI];
1943 tss->edi = c->regs[VCPU_REGS_RDI];
1944
1945 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1946 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1947 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1948 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1949 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
1950 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
1951 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1952 }
1953
1954 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
1955 struct x86_emulate_ops *ops,
1956 struct tss_segment_32 *tss)
1957 {
1958 struct decode_cache *c = &ctxt->decode;
1959 int ret;
1960
1961 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
1962 emulate_gp(ctxt, 0);
1963 return X86EMUL_PROPAGATE_FAULT;
1964 }
1965 c->eip = tss->eip;
1966 ctxt->eflags = tss->eflags | 2;
1967 c->regs[VCPU_REGS_RAX] = tss->eax;
1968 c->regs[VCPU_REGS_RCX] = tss->ecx;
1969 c->regs[VCPU_REGS_RDX] = tss->edx;
1970 c->regs[VCPU_REGS_RBX] = tss->ebx;
1971 c->regs[VCPU_REGS_RSP] = tss->esp;
1972 c->regs[VCPU_REGS_RBP] = tss->ebp;
1973 c->regs[VCPU_REGS_RSI] = tss->esi;
1974 c->regs[VCPU_REGS_RDI] = tss->edi;
1975
1976 /*
1977 * SDM says that segment selectors are loaded before segment
1978 * descriptors
1979 */
1980 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
1981 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1982 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1983 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1984 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1985 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
1986 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
1987
1988 /*
1989 * Now load segment descriptors. If fault happenes at this stage
1990 * it is handled in a context of new task
1991 */
1992 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
1993 if (ret != X86EMUL_CONTINUE)
1994 return ret;
1995 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1996 if (ret != X86EMUL_CONTINUE)
1997 return ret;
1998 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1999 if (ret != X86EMUL_CONTINUE)
2000 return ret;
2001 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2002 if (ret != X86EMUL_CONTINUE)
2003 return ret;
2004 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2005 if (ret != X86EMUL_CONTINUE)
2006 return ret;
2007 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2008 if (ret != X86EMUL_CONTINUE)
2009 return ret;
2010 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2011 if (ret != X86EMUL_CONTINUE)
2012 return ret;
2013
2014 return X86EMUL_CONTINUE;
2015 }
2016
2017 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2018 struct x86_emulate_ops *ops,
2019 u16 tss_selector, u16 old_tss_sel,
2020 ulong old_tss_base, struct desc_struct *new_desc)
2021 {
2022 struct tss_segment_32 tss_seg;
2023 int ret;
2024 u32 err, new_tss_base = get_desc_base(new_desc);
2025
2026 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2027 &err);
2028 if (ret == X86EMUL_PROPAGATE_FAULT) {
2029 /* FIXME: need to provide precise fault address */
2030 emulate_pf(ctxt, old_tss_base, err);
2031 return ret;
2032 }
2033
2034 save_state_to_tss32(ctxt, ops, &tss_seg);
2035
2036 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2037 &err);
2038 if (ret == X86EMUL_PROPAGATE_FAULT) {
2039 /* FIXME: need to provide precise fault address */
2040 emulate_pf(ctxt, old_tss_base, err);
2041 return ret;
2042 }
2043
2044 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2045 &err);
2046 if (ret == X86EMUL_PROPAGATE_FAULT) {
2047 /* FIXME: need to provide precise fault address */
2048 emulate_pf(ctxt, new_tss_base, err);
2049 return ret;
2050 }
2051
2052 if (old_tss_sel != 0xffff) {
2053 tss_seg.prev_task_link = old_tss_sel;
2054
2055 ret = ops->write_std(new_tss_base,
2056 &tss_seg.prev_task_link,
2057 sizeof tss_seg.prev_task_link,
2058 ctxt->vcpu, &err);
2059 if (ret == X86EMUL_PROPAGATE_FAULT) {
2060 /* FIXME: need to provide precise fault address */
2061 emulate_pf(ctxt, new_tss_base, err);
2062 return ret;
2063 }
2064 }
2065
2066 return load_state_from_tss32(ctxt, ops, &tss_seg);
2067 }
2068
2069 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2070 struct x86_emulate_ops *ops,
2071 u16 tss_selector, int reason,
2072 bool has_error_code, u32 error_code)
2073 {
2074 struct desc_struct curr_tss_desc, next_tss_desc;
2075 int ret;
2076 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2077 ulong old_tss_base =
2078 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
2079 u32 desc_limit;
2080
2081 /* FIXME: old_tss_base == ~0 ? */
2082
2083 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2084 if (ret != X86EMUL_CONTINUE)
2085 return ret;
2086 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2087 if (ret != X86EMUL_CONTINUE)
2088 return ret;
2089
2090 /* FIXME: check that next_tss_desc is tss */
2091
2092 if (reason != TASK_SWITCH_IRET) {
2093 if ((tss_selector & 3) > next_tss_desc.dpl ||
2094 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
2095 emulate_gp(ctxt, 0);
2096 return X86EMUL_PROPAGATE_FAULT;
2097 }
2098 }
2099
2100 desc_limit = desc_limit_scaled(&next_tss_desc);
2101 if (!next_tss_desc.p ||
2102 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2103 desc_limit < 0x2b)) {
2104 emulate_ts(ctxt, tss_selector & 0xfffc);
2105 return X86EMUL_PROPAGATE_FAULT;
2106 }
2107
2108 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2109 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2110 write_segment_descriptor(ctxt, ops, old_tss_sel,
2111 &curr_tss_desc);
2112 }
2113
2114 if (reason == TASK_SWITCH_IRET)
2115 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2116
2117 /* set back link to prev task only if NT bit is set in eflags
2118 note that old_tss_sel is not used afetr this point */
2119 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2120 old_tss_sel = 0xffff;
2121
2122 if (next_tss_desc.type & 8)
2123 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2124 old_tss_base, &next_tss_desc);
2125 else
2126 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2127 old_tss_base, &next_tss_desc);
2128 if (ret != X86EMUL_CONTINUE)
2129 return ret;
2130
2131 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2132 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2133
2134 if (reason != TASK_SWITCH_IRET) {
2135 next_tss_desc.type |= (1 << 1); /* set busy flag */
2136 write_segment_descriptor(ctxt, ops, tss_selector,
2137 &next_tss_desc);
2138 }
2139
2140 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2141 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2142 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2143
2144 if (has_error_code) {
2145 struct decode_cache *c = &ctxt->decode;
2146
2147 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2148 c->lock_prefix = 0;
2149 c->src.val = (unsigned long) error_code;
2150 emulate_push(ctxt, ops);
2151 }
2152
2153 return ret;
2154 }
2155
2156 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2157 u16 tss_selector, int reason,
2158 bool has_error_code, u32 error_code)
2159 {
2160 struct x86_emulate_ops *ops = ctxt->ops;
2161 struct decode_cache *c = &ctxt->decode;
2162 int rc;
2163
2164 c->eip = ctxt->eip;
2165 c->dst.type = OP_NONE;
2166
2167 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2168 has_error_code, error_code);
2169
2170 if (rc == X86EMUL_CONTINUE) {
2171 rc = writeback(ctxt, ops);
2172 if (rc == X86EMUL_CONTINUE)
2173 ctxt->eip = c->eip;
2174 }
2175
2176 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2177 }
2178
2179 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
2180 int reg, struct operand *op)
2181 {
2182 struct decode_cache *c = &ctxt->decode;
2183 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2184
2185 register_address_increment(c, &c->regs[reg], df * op->bytes);
2186 op->addr.mem = register_address(c, base, c->regs[reg]);
2187 }
2188
2189 static int em_push(struct x86_emulate_ctxt *ctxt)
2190 {
2191 emulate_push(ctxt, ctxt->ops);
2192 return X86EMUL_CONTINUE;
2193 }
2194
2195 static int em_das(struct x86_emulate_ctxt *ctxt)
2196 {
2197 struct decode_cache *c = &ctxt->decode;
2198 u8 al, old_al;
2199 bool af, cf, old_cf;
2200
2201 cf = ctxt->eflags & X86_EFLAGS_CF;
2202 al = c->dst.val;
2203
2204 old_al = al;
2205 old_cf = cf;
2206 cf = false;
2207 af = ctxt->eflags & X86_EFLAGS_AF;
2208 if ((al & 0x0f) > 9 || af) {
2209 al -= 6;
2210 cf = old_cf | (al >= 250);
2211 af = true;
2212 } else {
2213 af = false;
2214 }
2215 if (old_al > 0x99 || old_cf) {
2216 al -= 0x60;
2217 cf = true;
2218 }
2219
2220 c->dst.val = al;
2221 /* Set PF, ZF, SF */
2222 c->src.type = OP_IMM;
2223 c->src.val = 0;
2224 c->src.bytes = 1;
2225 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2226 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2227 if (cf)
2228 ctxt->eflags |= X86_EFLAGS_CF;
2229 if (af)
2230 ctxt->eflags |= X86_EFLAGS_AF;
2231 return X86EMUL_CONTINUE;
2232 }
2233
2234 static int em_call_far(struct x86_emulate_ctxt *ctxt)
2235 {
2236 struct decode_cache *c = &ctxt->decode;
2237 u16 sel, old_cs;
2238 ulong old_eip;
2239 int rc;
2240
2241 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2242 old_eip = c->eip;
2243
2244 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2245 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2246 return X86EMUL_CONTINUE;
2247
2248 c->eip = 0;
2249 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2250
2251 c->src.val = old_cs;
2252 emulate_push(ctxt, ctxt->ops);
2253 rc = writeback(ctxt, ctxt->ops);
2254 if (rc != X86EMUL_CONTINUE)
2255 return rc;
2256
2257 c->src.val = old_eip;
2258 emulate_push(ctxt, ctxt->ops);
2259 rc = writeback(ctxt, ctxt->ops);
2260 if (rc != X86EMUL_CONTINUE)
2261 return rc;
2262
2263 c->dst.type = OP_NONE;
2264
2265 return X86EMUL_CONTINUE;
2266 }
2267
2268 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2269 {
2270 struct decode_cache *c = &ctxt->decode;
2271 int rc;
2272
2273 c->dst.type = OP_REG;
2274 c->dst.addr.reg = &c->eip;
2275 c->dst.bytes = c->op_bytes;
2276 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2277 if (rc != X86EMUL_CONTINUE)
2278 return rc;
2279 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2280 return X86EMUL_CONTINUE;
2281 }
2282
2283 static int em_imul(struct x86_emulate_ctxt *ctxt)
2284 {
2285 struct decode_cache *c = &ctxt->decode;
2286
2287 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2288 return X86EMUL_CONTINUE;
2289 }
2290
2291 static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2292 {
2293 struct decode_cache *c = &ctxt->decode;
2294
2295 c->dst.val = c->src2.val;
2296 return em_imul(ctxt);
2297 }
2298
2299 static int em_cwd(struct x86_emulate_ctxt *ctxt)
2300 {
2301 struct decode_cache *c = &ctxt->decode;
2302
2303 c->dst.type = OP_REG;
2304 c->dst.bytes = c->src.bytes;
2305 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2306 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2307
2308 return X86EMUL_CONTINUE;
2309 }
2310
2311 static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2312 {
2313 unsigned cpl = ctxt->ops->cpl(ctxt->vcpu);
2314 struct decode_cache *c = &ctxt->decode;
2315 u64 tsc = 0;
2316
2317 if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD)) {
2318 emulate_gp(ctxt, 0);
2319 return X86EMUL_PROPAGATE_FAULT;
2320 }
2321 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2322 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2323 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2324 return X86EMUL_CONTINUE;
2325 }
2326
2327 #define D(_y) { .flags = (_y) }
2328 #define N D(0)
2329 #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2330 #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2331 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2332
2333 static struct opcode group1[] = {
2334 X7(D(Lock)), N
2335 };
2336
2337 static struct opcode group1A[] = {
2338 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2339 };
2340
2341 static struct opcode group3[] = {
2342 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2343 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2344 X4(D(SrcMem | ModRM)),
2345 };
2346
2347 static struct opcode group4[] = {
2348 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2349 N, N, N, N, N, N,
2350 };
2351
2352 static struct opcode group5[] = {
2353 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2354 D(SrcMem | ModRM | Stack),
2355 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
2356 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2357 D(SrcMem | ModRM | Stack), N,
2358 };
2359
2360 static struct group_dual group7 = { {
2361 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2362 D(SrcNone | ModRM | DstMem | Mov), N,
2363 D(SrcMem16 | ModRM | Mov | Priv),
2364 D(SrcMem | ModRM | ByteOp | Priv | NoAccess),
2365 }, {
2366 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
2367 D(SrcNone | ModRM | DstMem | Mov), N,
2368 D(SrcMem16 | ModRM | Mov | Priv), N,
2369 } };
2370
2371 static struct opcode group8[] = {
2372 N, N, N, N,
2373 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2374 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2375 };
2376
2377 static struct group_dual group9 = { {
2378 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2379 }, {
2380 N, N, N, N, N, N, N, N,
2381 } };
2382
2383 static struct opcode opcode_table[256] = {
2384 /* 0x00 - 0x07 */
2385 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2386 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2387 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2388 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2389 /* 0x08 - 0x0F */
2390 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2391 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2392 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2393 D(ImplicitOps | Stack | No64), N,
2394 /* 0x10 - 0x17 */
2395 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2396 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2397 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2398 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2399 /* 0x18 - 0x1F */
2400 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2401 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2402 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2403 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2404 /* 0x20 - 0x27 */
2405 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2406 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2407 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2408 /* 0x28 - 0x2F */
2409 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2410 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2411 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm),
2412 N, I(ByteOp | DstAcc | No64, em_das),
2413 /* 0x30 - 0x37 */
2414 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2415 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2416 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2417 /* 0x38 - 0x3F */
2418 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2419 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2420 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2421 N, N,
2422 /* 0x40 - 0x4F */
2423 X16(D(DstReg)),
2424 /* 0x50 - 0x57 */
2425 X8(I(SrcReg | Stack, em_push)),
2426 /* 0x58 - 0x5F */
2427 X8(D(DstReg | Stack)),
2428 /* 0x60 - 0x67 */
2429 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2430 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2431 N, N, N, N,
2432 /* 0x68 - 0x6F */
2433 I(SrcImm | Mov | Stack, em_push),
2434 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
2435 I(SrcImmByte | Mov | Stack, em_push),
2436 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2437 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
2438 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
2439 /* 0x70 - 0x7F */
2440 X16(D(SrcImmByte)),
2441 /* 0x80 - 0x87 */
2442 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2443 G(DstMem | SrcImm | ModRM | Group, group1),
2444 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2445 G(DstMem | SrcImmByte | ModRM | Group, group1),
2446 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2447 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2448 /* 0x88 - 0x8F */
2449 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
2450 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
2451 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
2452 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2453 /* 0x90 - 0x97 */
2454 X8(D(SrcAcc | DstReg)),
2455 /* 0x98 - 0x9F */
2456 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
2457 I(SrcImmFAddr | No64, em_call_far), N,
2458 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2459 /* 0xA0 - 0xA7 */
2460 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
2461 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
2462 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
2463 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
2464 /* 0xA8 - 0xAF */
2465 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm),
2466 D(ByteOp | SrcAcc | DstDI | Mov | String), D(SrcAcc | DstDI | Mov | String),
2467 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
2468 D(ByteOp | SrcAcc | DstDI | String), D(SrcAcc | DstDI | String),
2469 /* 0xB0 - 0xB7 */
2470 X8(D(ByteOp | DstReg | SrcImm | Mov)),
2471 /* 0xB8 - 0xBF */
2472 X8(D(DstReg | SrcImm | Mov)),
2473 /* 0xC0 - 0xC7 */
2474 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
2475 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2476 D(ImplicitOps | Stack),
2477 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
2478 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
2479 /* 0xC8 - 0xCF */
2480 N, N, N, D(ImplicitOps | Stack),
2481 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2482 /* 0xD0 - 0xD7 */
2483 D(ByteOp | DstMem | SrcOne | ModRM), D(DstMem | SrcOne | ModRM),
2484 D(ByteOp | DstMem | ModRM), D(DstMem | ModRM),
2485 N, N, N, N,
2486 /* 0xD8 - 0xDF */
2487 N, N, N, N, N, N, N, N,
2488 /* 0xE0 - 0xE7 */
2489 X4(D(SrcImmByte)),
2490 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
2491 D(ByteOp | SrcAcc | DstImmUByte), D(SrcAcc | DstImmUByte),
2492 /* 0xE8 - 0xEF */
2493 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2494 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
2495 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
2496 D(ByteOp | SrcAcc | ImplicitOps), D(SrcAcc | ImplicitOps),
2497 /* 0xF0 - 0xF7 */
2498 N, N, N, N,
2499 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2500 /* 0xF8 - 0xFF */
2501 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
2502 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2503 };
2504
2505 static struct opcode twobyte_table[256] = {
2506 /* 0x00 - 0x0F */
2507 N, GD(0, &group7), N, N,
2508 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
2509 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2510 N, D(ImplicitOps | ModRM), N, N,
2511 /* 0x10 - 0x1F */
2512 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2513 /* 0x20 - 0x2F */
2514 D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264),
2515 D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264),
2516 N, N, N, N,
2517 N, N, N, N, N, N, N, N,
2518 /* 0x30 - 0x3F */
2519 D(ImplicitOps | Priv), I(ImplicitOps, em_rdtsc),
2520 D(ImplicitOps | Priv), N,
2521 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
2522 N, N, N, N, N, N, N, N,
2523 /* 0x40 - 0x4F */
2524 X16(D(DstReg | SrcMem | ModRM | Mov)),
2525 /* 0x50 - 0x5F */
2526 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2527 /* 0x60 - 0x6F */
2528 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2529 /* 0x70 - 0x7F */
2530 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2531 /* 0x80 - 0x8F */
2532 X16(D(SrcImm)),
2533 /* 0x90 - 0x9F */
2534 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
2535 /* 0xA0 - 0xA7 */
2536 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2537 N, D(DstMem | SrcReg | ModRM | BitOp),
2538 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2539 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2540 /* 0xA8 - 0xAF */
2541 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2542 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2543 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2544 D(DstMem | SrcReg | Src2CL | ModRM),
2545 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
2546 /* 0xB0 - 0xB7 */
2547 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2548 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2549 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
2550 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
2551 /* 0xB8 - 0xBF */
2552 N, N,
2553 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2554 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2555 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
2556 /* 0xC0 - 0xCF */
2557 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2558 N, D(DstMem | SrcReg | ModRM | Mov),
2559 N, N, N, GD(0, &group9),
2560 N, N, N, N, N, N, N, N,
2561 /* 0xD0 - 0xDF */
2562 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2563 /* 0xE0 - 0xEF */
2564 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2565 /* 0xF0 - 0xFF */
2566 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2567 };
2568
2569 #undef D
2570 #undef N
2571 #undef G
2572 #undef GD
2573 #undef I
2574
2575 static unsigned imm_size(struct decode_cache *c)
2576 {
2577 unsigned size;
2578
2579 size = (c->d & ByteOp) ? 1 : c->op_bytes;
2580 if (size == 8)
2581 size = 4;
2582 return size;
2583 }
2584
2585 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
2586 unsigned size, bool sign_extension)
2587 {
2588 struct decode_cache *c = &ctxt->decode;
2589 struct x86_emulate_ops *ops = ctxt->ops;
2590 int rc = X86EMUL_CONTINUE;
2591
2592 op->type = OP_IMM;
2593 op->bytes = size;
2594 op->addr.mem = c->eip;
2595 /* NB. Immediates are sign-extended as necessary. */
2596 switch (op->bytes) {
2597 case 1:
2598 op->val = insn_fetch(s8, 1, c->eip);
2599 break;
2600 case 2:
2601 op->val = insn_fetch(s16, 2, c->eip);
2602 break;
2603 case 4:
2604 op->val = insn_fetch(s32, 4, c->eip);
2605 break;
2606 }
2607 if (!sign_extension) {
2608 switch (op->bytes) {
2609 case 1:
2610 op->val &= 0xff;
2611 break;
2612 case 2:
2613 op->val &= 0xffff;
2614 break;
2615 case 4:
2616 op->val &= 0xffffffff;
2617 break;
2618 }
2619 }
2620 done:
2621 return rc;
2622 }
2623
2624 int
2625 x86_decode_insn(struct x86_emulate_ctxt *ctxt)
2626 {
2627 struct x86_emulate_ops *ops = ctxt->ops;
2628 struct decode_cache *c = &ctxt->decode;
2629 int rc = X86EMUL_CONTINUE;
2630 int mode = ctxt->mode;
2631 int def_op_bytes, def_ad_bytes, dual, goffset;
2632 struct opcode opcode, *g_mod012, *g_mod3;
2633 struct operand memop = { .type = OP_NONE };
2634
2635 c->eip = ctxt->eip;
2636 c->fetch.start = c->fetch.end = c->eip;
2637 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2638
2639 switch (mode) {
2640 case X86EMUL_MODE_REAL:
2641 case X86EMUL_MODE_VM86:
2642 case X86EMUL_MODE_PROT16:
2643 def_op_bytes = def_ad_bytes = 2;
2644 break;
2645 case X86EMUL_MODE_PROT32:
2646 def_op_bytes = def_ad_bytes = 4;
2647 break;
2648 #ifdef CONFIG_X86_64
2649 case X86EMUL_MODE_PROT64:
2650 def_op_bytes = 4;
2651 def_ad_bytes = 8;
2652 break;
2653 #endif
2654 default:
2655 return -1;
2656 }
2657
2658 c->op_bytes = def_op_bytes;
2659 c->ad_bytes = def_ad_bytes;
2660
2661 /* Legacy prefixes. */
2662 for (;;) {
2663 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2664 case 0x66: /* operand-size override */
2665 /* switch between 2/4 bytes */
2666 c->op_bytes = def_op_bytes ^ 6;
2667 break;
2668 case 0x67: /* address-size override */
2669 if (mode == X86EMUL_MODE_PROT64)
2670 /* switch between 4/8 bytes */
2671 c->ad_bytes = def_ad_bytes ^ 12;
2672 else
2673 /* switch between 2/4 bytes */
2674 c->ad_bytes = def_ad_bytes ^ 6;
2675 break;
2676 case 0x26: /* ES override */
2677 case 0x2e: /* CS override */
2678 case 0x36: /* SS override */
2679 case 0x3e: /* DS override */
2680 set_seg_override(c, (c->b >> 3) & 3);
2681 break;
2682 case 0x64: /* FS override */
2683 case 0x65: /* GS override */
2684 set_seg_override(c, c->b & 7);
2685 break;
2686 case 0x40 ... 0x4f: /* REX */
2687 if (mode != X86EMUL_MODE_PROT64)
2688 goto done_prefixes;
2689 c->rex_prefix = c->b;
2690 continue;
2691 case 0xf0: /* LOCK */
2692 c->lock_prefix = 1;
2693 break;
2694 case 0xf2: /* REPNE/REPNZ */
2695 c->rep_prefix = REPNE_PREFIX;
2696 break;
2697 case 0xf3: /* REP/REPE/REPZ */
2698 c->rep_prefix = REPE_PREFIX;
2699 break;
2700 default:
2701 goto done_prefixes;
2702 }
2703
2704 /* Any legacy prefix after a REX prefix nullifies its effect. */
2705
2706 c->rex_prefix = 0;
2707 }
2708
2709 done_prefixes:
2710
2711 /* REX prefix. */
2712 if (c->rex_prefix & 8)
2713 c->op_bytes = 8; /* REX.W */
2714
2715 /* Opcode byte(s). */
2716 opcode = opcode_table[c->b];
2717 /* Two-byte opcode? */
2718 if (c->b == 0x0f) {
2719 c->twobyte = 1;
2720 c->b = insn_fetch(u8, 1, c->eip);
2721 opcode = twobyte_table[c->b];
2722 }
2723 c->d = opcode.flags;
2724
2725 if (c->d & Group) {
2726 dual = c->d & GroupDual;
2727 c->modrm = insn_fetch(u8, 1, c->eip);
2728 --c->eip;
2729
2730 if (c->d & GroupDual) {
2731 g_mod012 = opcode.u.gdual->mod012;
2732 g_mod3 = opcode.u.gdual->mod3;
2733 } else
2734 g_mod012 = g_mod3 = opcode.u.group;
2735
2736 c->d &= ~(Group | GroupDual);
2737
2738 goffset = (c->modrm >> 3) & 7;
2739
2740 if ((c->modrm >> 6) == 3)
2741 opcode = g_mod3[goffset];
2742 else
2743 opcode = g_mod012[goffset];
2744 c->d |= opcode.flags;
2745 }
2746
2747 c->execute = opcode.u.execute;
2748
2749 /* Unrecognised? */
2750 if (c->d == 0 || (c->d & Undefined)) {
2751 DPRINTF("Cannot emulate %02x\n", c->b);
2752 return -1;
2753 }
2754
2755 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2756 c->op_bytes = 8;
2757
2758 if (c->d & Op3264) {
2759 if (mode == X86EMUL_MODE_PROT64)
2760 c->op_bytes = 8;
2761 else
2762 c->op_bytes = 4;
2763 }
2764
2765 /* ModRM and SIB bytes. */
2766 if (c->d & ModRM) {
2767 rc = decode_modrm(ctxt, ops, &memop);
2768 if (!c->has_seg_override)
2769 set_seg_override(c, c->modrm_seg);
2770 } else if (c->d & MemAbs)
2771 rc = decode_abs(ctxt, ops, &memop);
2772 if (rc != X86EMUL_CONTINUE)
2773 goto done;
2774
2775 if (!c->has_seg_override)
2776 set_seg_override(c, VCPU_SREG_DS);
2777
2778 if (memop.type == OP_MEM && !(!c->twobyte && c->b == 0x8d))
2779 memop.addr.mem += seg_override_base(ctxt, ops, c);
2780
2781 if (memop.type == OP_MEM && c->ad_bytes != 8)
2782 memop.addr.mem = (u32)memop.addr.mem;
2783
2784 if (memop.type == OP_MEM && c->rip_relative)
2785 memop.addr.mem += c->eip;
2786
2787 /*
2788 * Decode and fetch the source operand: register, memory
2789 * or immediate.
2790 */
2791 switch (c->d & SrcMask) {
2792 case SrcNone:
2793 break;
2794 case SrcReg:
2795 decode_register_operand(&c->src, c, 0);
2796 break;
2797 case SrcMem16:
2798 memop.bytes = 2;
2799 goto srcmem_common;
2800 case SrcMem32:
2801 memop.bytes = 4;
2802 goto srcmem_common;
2803 case SrcMem:
2804 memop.bytes = (c->d & ByteOp) ? 1 :
2805 c->op_bytes;
2806 srcmem_common:
2807 c->src = memop;
2808 break;
2809 case SrcImmU16:
2810 rc = decode_imm(ctxt, &c->src, 2, false);
2811 break;
2812 case SrcImm:
2813 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
2814 break;
2815 case SrcImmU:
2816 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
2817 break;
2818 case SrcImmByte:
2819 rc = decode_imm(ctxt, &c->src, 1, true);
2820 break;
2821 case SrcImmUByte:
2822 rc = decode_imm(ctxt, &c->src, 1, false);
2823 break;
2824 case SrcAcc:
2825 c->src.type = OP_REG;
2826 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2827 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
2828 fetch_register_operand(&c->src);
2829 break;
2830 case SrcOne:
2831 c->src.bytes = 1;
2832 c->src.val = 1;
2833 break;
2834 case SrcSI:
2835 c->src.type = OP_MEM;
2836 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2837 c->src.addr.mem =
2838 register_address(c, seg_override_base(ctxt, ops, c),
2839 c->regs[VCPU_REGS_RSI]);
2840 c->src.val = 0;
2841 break;
2842 case SrcImmFAddr:
2843 c->src.type = OP_IMM;
2844 c->src.addr.mem = c->eip;
2845 c->src.bytes = c->op_bytes + 2;
2846 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2847 break;
2848 case SrcMemFAddr:
2849 memop.bytes = c->op_bytes + 2;
2850 goto srcmem_common;
2851 break;
2852 }
2853
2854 if (rc != X86EMUL_CONTINUE)
2855 goto done;
2856
2857 /*
2858 * Decode and fetch the second source operand: register, memory
2859 * or immediate.
2860 */
2861 switch (c->d & Src2Mask) {
2862 case Src2None:
2863 break;
2864 case Src2CL:
2865 c->src2.bytes = 1;
2866 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2867 break;
2868 case Src2ImmByte:
2869 rc = decode_imm(ctxt, &c->src2, 1, true);
2870 break;
2871 case Src2One:
2872 c->src2.bytes = 1;
2873 c->src2.val = 1;
2874 break;
2875 case Src2Imm:
2876 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
2877 break;
2878 }
2879
2880 if (rc != X86EMUL_CONTINUE)
2881 goto done;
2882
2883 /* Decode and fetch the destination operand: register or memory. */
2884 switch (c->d & DstMask) {
2885 case DstReg:
2886 decode_register_operand(&c->dst, c,
2887 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2888 break;
2889 case DstImmUByte:
2890 c->dst.type = OP_IMM;
2891 c->dst.addr.mem = c->eip;
2892 c->dst.bytes = 1;
2893 c->dst.val = insn_fetch(u8, 1, c->eip);
2894 break;
2895 case DstMem:
2896 case DstMem64:
2897 c->dst = memop;
2898 if ((c->d & DstMask) == DstMem64)
2899 c->dst.bytes = 8;
2900 else
2901 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2902 if (c->d & BitOp)
2903 fetch_bit_operand(c);
2904 c->dst.orig_val = c->dst.val;
2905 break;
2906 case DstAcc:
2907 c->dst.type = OP_REG;
2908 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2909 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
2910 fetch_register_operand(&c->dst);
2911 c->dst.orig_val = c->dst.val;
2912 break;
2913 case DstDI:
2914 c->dst.type = OP_MEM;
2915 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2916 c->dst.addr.mem =
2917 register_address(c, es_base(ctxt, ops),
2918 c->regs[VCPU_REGS_RDI]);
2919 c->dst.val = 0;
2920 break;
2921 case ImplicitOps:
2922 /* Special instructions do their own operand decoding. */
2923 default:
2924 c->dst.type = OP_NONE; /* Disable writeback. */
2925 return 0;
2926 }
2927
2928 done:
2929 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2930 }
2931
2932 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
2933 {
2934 struct decode_cache *c = &ctxt->decode;
2935
2936 /* The second termination condition only applies for REPE
2937 * and REPNE. Test if the repeat string operation prefix is
2938 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2939 * corresponding termination condition according to:
2940 * - if REPE/REPZ and ZF = 0 then done
2941 * - if REPNE/REPNZ and ZF = 1 then done
2942 */
2943 if (((c->b == 0xa6) || (c->b == 0xa7) ||
2944 (c->b == 0xae) || (c->b == 0xaf))
2945 && (((c->rep_prefix == REPE_PREFIX) &&
2946 ((ctxt->eflags & EFLG_ZF) == 0))
2947 || ((c->rep_prefix == REPNE_PREFIX) &&
2948 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
2949 return true;
2950
2951 return false;
2952 }
2953
2954 int
2955 x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
2956 {
2957 struct x86_emulate_ops *ops = ctxt->ops;
2958 u64 msr_data;
2959 struct decode_cache *c = &ctxt->decode;
2960 int rc = X86EMUL_CONTINUE;
2961 int saved_dst_type = c->dst.type;
2962 int irq; /* Used for int 3, int, and into */
2963
2964 ctxt->decode.mem_read.pos = 0;
2965
2966 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
2967 emulate_ud(ctxt);
2968 goto done;
2969 }
2970
2971 /* LOCK prefix is allowed only with some instructions */
2972 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
2973 emulate_ud(ctxt);
2974 goto done;
2975 }
2976
2977 /* Privileged instruction can be executed only in CPL=0 */
2978 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
2979 emulate_gp(ctxt, 0);
2980 goto done;
2981 }
2982
2983 if (c->rep_prefix && (c->d & String)) {
2984 /* All REP prefixes have the same first termination condition */
2985 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
2986 ctxt->eip = c->eip;
2987 goto done;
2988 }
2989 }
2990
2991 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
2992 rc = read_emulated(ctxt, ops, c->src.addr.mem,
2993 c->src.valptr, c->src.bytes);
2994 if (rc != X86EMUL_CONTINUE)
2995 goto done;
2996 c->src.orig_val64 = c->src.val64;
2997 }
2998
2999 if (c->src2.type == OP_MEM) {
3000 rc = read_emulated(ctxt, ops, c->src2.addr.mem,
3001 &c->src2.val, c->src2.bytes);
3002 if (rc != X86EMUL_CONTINUE)
3003 goto done;
3004 }
3005
3006 if ((c->d & DstMask) == ImplicitOps)
3007 goto special_insn;
3008
3009
3010 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3011 /* optimisation - avoid slow emulated read if Mov */
3012 rc = read_emulated(ctxt, ops, c->dst.addr.mem,
3013 &c->dst.val, c->dst.bytes);
3014 if (rc != X86EMUL_CONTINUE)
3015 goto done;
3016 }
3017 c->dst.orig_val = c->dst.val;
3018
3019 special_insn:
3020
3021 if (c->execute) {
3022 rc = c->execute(ctxt);
3023 if (rc != X86EMUL_CONTINUE)
3024 goto done;
3025 goto writeback;
3026 }
3027
3028 if (c->twobyte)
3029 goto twobyte_insn;
3030
3031 switch (c->b) {
3032 case 0x00 ... 0x05:
3033 add: /* add */
3034 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3035 break;
3036 case 0x06: /* push es */
3037 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
3038 break;
3039 case 0x07: /* pop es */
3040 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
3041 if (rc != X86EMUL_CONTINUE)
3042 goto done;
3043 break;
3044 case 0x08 ... 0x0d:
3045 or: /* or */
3046 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
3047 break;
3048 case 0x0e: /* push cs */
3049 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
3050 break;
3051 case 0x10 ... 0x15:
3052 adc: /* adc */
3053 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
3054 break;
3055 case 0x16: /* push ss */
3056 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
3057 break;
3058 case 0x17: /* pop ss */
3059 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
3060 if (rc != X86EMUL_CONTINUE)
3061 goto done;
3062 break;
3063 case 0x18 ... 0x1d:
3064 sbb: /* sbb */
3065 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
3066 break;
3067 case 0x1e: /* push ds */
3068 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
3069 break;
3070 case 0x1f: /* pop ds */
3071 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
3072 if (rc != X86EMUL_CONTINUE)
3073 goto done;
3074 break;
3075 case 0x20 ... 0x25:
3076 and: /* and */
3077 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
3078 break;
3079 case 0x28 ... 0x2d:
3080 sub: /* sub */
3081 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
3082 break;
3083 case 0x30 ... 0x35:
3084 xor: /* xor */
3085 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
3086 break;
3087 case 0x38 ... 0x3d:
3088 cmp: /* cmp */
3089 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3090 break;
3091 case 0x40 ... 0x47: /* inc r16/r32 */
3092 emulate_1op("inc", c->dst, ctxt->eflags);
3093 break;
3094 case 0x48 ... 0x4f: /* dec r16/r32 */
3095 emulate_1op("dec", c->dst, ctxt->eflags);
3096 break;
3097 case 0x58 ... 0x5f: /* pop reg */
3098 pop_instruction:
3099 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
3100 if (rc != X86EMUL_CONTINUE)
3101 goto done;
3102 break;
3103 case 0x60: /* pusha */
3104 rc = emulate_pusha(ctxt, ops);
3105 if (rc != X86EMUL_CONTINUE)
3106 goto done;
3107 break;
3108 case 0x61: /* popa */
3109 rc = emulate_popa(ctxt, ops);
3110 if (rc != X86EMUL_CONTINUE)
3111 goto done;
3112 break;
3113 case 0x63: /* movsxd */
3114 if (ctxt->mode != X86EMUL_MODE_PROT64)
3115 goto cannot_emulate;
3116 c->dst.val = (s32) c->src.val;
3117 break;
3118 case 0x6c: /* insb */
3119 case 0x6d: /* insw/insd */
3120 c->src.val = c->regs[VCPU_REGS_RDX];
3121 goto do_io_in;
3122 case 0x6e: /* outsb */
3123 case 0x6f: /* outsw/outsd */
3124 c->dst.val = c->regs[VCPU_REGS_RDX];
3125 goto do_io_out;
3126 break;
3127 case 0x70 ... 0x7f: /* jcc (short) */
3128 if (test_cc(c->b, ctxt->eflags))
3129 jmp_rel(c, c->src.val);
3130 break;
3131 case 0x80 ... 0x83: /* Grp1 */
3132 switch (c->modrm_reg) {
3133 case 0:
3134 goto add;
3135 case 1:
3136 goto or;
3137 case 2:
3138 goto adc;
3139 case 3:
3140 goto sbb;
3141 case 4:
3142 goto and;
3143 case 5:
3144 goto sub;
3145 case 6:
3146 goto xor;
3147 case 7:
3148 goto cmp;
3149 }
3150 break;
3151 case 0x84 ... 0x85:
3152 test:
3153 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
3154 break;
3155 case 0x86 ... 0x87: /* xchg */
3156 xchg:
3157 /* Write back the register source. */
3158 c->src.val = c->dst.val;
3159 write_register_operand(&c->src);
3160 /*
3161 * Write back the memory destination with implicit LOCK
3162 * prefix.
3163 */
3164 c->dst.val = c->src.orig_val;
3165 c->lock_prefix = 1;
3166 break;
3167 case 0x88 ... 0x8b: /* mov */
3168 goto mov;
3169 case 0x8c: /* mov r/m, sreg */
3170 if (c->modrm_reg > VCPU_SREG_GS) {
3171 emulate_ud(ctxt);
3172 goto done;
3173 }
3174 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
3175 break;
3176 case 0x8d: /* lea r16/r32, m */
3177 c->dst.val = c->src.addr.mem;
3178 break;
3179 case 0x8e: { /* mov seg, r/m16 */
3180 uint16_t sel;
3181
3182 sel = c->src.val;
3183
3184 if (c->modrm_reg == VCPU_SREG_CS ||
3185 c->modrm_reg > VCPU_SREG_GS) {
3186 emulate_ud(ctxt);
3187 goto done;
3188 }
3189
3190 if (c->modrm_reg == VCPU_SREG_SS)
3191 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3192
3193 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
3194
3195 c->dst.type = OP_NONE; /* Disable writeback. */
3196 break;
3197 }
3198 case 0x8f: /* pop (sole member of Grp1a) */
3199 rc = emulate_grp1a(ctxt, ops);
3200 if (rc != X86EMUL_CONTINUE)
3201 goto done;
3202 break;
3203 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3204 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
3205 break;
3206 goto xchg;
3207 case 0x98: /* cbw/cwde/cdqe */
3208 switch (c->op_bytes) {
3209 case 2: c->dst.val = (s8)c->dst.val; break;
3210 case 4: c->dst.val = (s16)c->dst.val; break;
3211 case 8: c->dst.val = (s32)c->dst.val; break;
3212 }
3213 break;
3214 case 0x9c: /* pushf */
3215 c->src.val = (unsigned long) ctxt->eflags;
3216 emulate_push(ctxt, ops);
3217 break;
3218 case 0x9d: /* popf */
3219 c->dst.type = OP_REG;
3220 c->dst.addr.reg = &ctxt->eflags;
3221 c->dst.bytes = c->op_bytes;
3222 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
3223 if (rc != X86EMUL_CONTINUE)
3224 goto done;
3225 break;
3226 case 0xa0 ... 0xa3: /* mov */
3227 case 0xa4 ... 0xa5: /* movs */
3228 goto mov;
3229 case 0xa6 ... 0xa7: /* cmps */
3230 c->dst.type = OP_NONE; /* Disable writeback. */
3231 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.addr.mem, c->dst.addr.mem);
3232 goto cmp;
3233 case 0xa8 ... 0xa9: /* test ax, imm */
3234 goto test;
3235 case 0xaa ... 0xab: /* stos */
3236 case 0xac ... 0xad: /* lods */
3237 goto mov;
3238 case 0xae ... 0xaf: /* scas */
3239 goto cmp;
3240 case 0xb0 ... 0xbf: /* mov r, imm */
3241 goto mov;
3242 case 0xc0 ... 0xc1:
3243 emulate_grp2(ctxt);
3244 break;
3245 case 0xc3: /* ret */
3246 c->dst.type = OP_REG;
3247 c->dst.addr.reg = &c->eip;
3248 c->dst.bytes = c->op_bytes;
3249 goto pop_instruction;
3250 case 0xc4: /* les */
3251 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
3252 if (rc != X86EMUL_CONTINUE)
3253 goto done;
3254 break;
3255 case 0xc5: /* lds */
3256 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
3257 if (rc != X86EMUL_CONTINUE)
3258 goto done;
3259 break;
3260 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
3261 mov:
3262 c->dst.val = c->src.val;
3263 break;
3264 case 0xcb: /* ret far */
3265 rc = emulate_ret_far(ctxt, ops);
3266 if (rc != X86EMUL_CONTINUE)
3267 goto done;
3268 break;
3269 case 0xcc: /* int3 */
3270 irq = 3;
3271 goto do_interrupt;
3272 case 0xcd: /* int n */
3273 irq = c->src.val;
3274 do_interrupt:
3275 rc = emulate_int(ctxt, ops, irq);
3276 if (rc != X86EMUL_CONTINUE)
3277 goto done;
3278 break;
3279 case 0xce: /* into */
3280 if (ctxt->eflags & EFLG_OF) {
3281 irq = 4;
3282 goto do_interrupt;
3283 }
3284 break;
3285 case 0xcf: /* iret */
3286 rc = emulate_iret(ctxt, ops);
3287
3288 if (rc != X86EMUL_CONTINUE)
3289 goto done;
3290 break;
3291 case 0xd0 ... 0xd1: /* Grp2 */
3292 emulate_grp2(ctxt);
3293 break;
3294 case 0xd2 ... 0xd3: /* Grp2 */
3295 c->src.val = c->regs[VCPU_REGS_RCX];
3296 emulate_grp2(ctxt);
3297 break;
3298 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3299 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3300 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3301 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3302 jmp_rel(c, c->src.val);
3303 break;
3304 case 0xe3: /* jcxz/jecxz/jrcxz */
3305 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3306 jmp_rel(c, c->src.val);
3307 break;
3308 case 0xe4: /* inb */
3309 case 0xe5: /* in */
3310 goto do_io_in;
3311 case 0xe6: /* outb */
3312 case 0xe7: /* out */
3313 goto do_io_out;
3314 case 0xe8: /* call (near) */ {
3315 long int rel = c->src.val;
3316 c->src.val = (unsigned long) c->eip;
3317 jmp_rel(c, rel);
3318 emulate_push(ctxt, ops);
3319 break;
3320 }
3321 case 0xe9: /* jmp rel */
3322 goto jmp;
3323 case 0xea: { /* jmp far */
3324 unsigned short sel;
3325 jump_far:
3326 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3327
3328 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
3329 goto done;
3330
3331 c->eip = 0;
3332 memcpy(&c->eip, c->src.valptr, c->op_bytes);
3333 break;
3334 }
3335 case 0xeb:
3336 jmp: /* jmp rel short */
3337 jmp_rel(c, c->src.val);
3338 c->dst.type = OP_NONE; /* Disable writeback. */
3339 break;
3340 case 0xec: /* in al,dx */
3341 case 0xed: /* in (e/r)ax,dx */
3342 c->src.val = c->regs[VCPU_REGS_RDX];
3343 do_io_in:
3344 c->dst.bytes = min(c->dst.bytes, 4u);
3345 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
3346 emulate_gp(ctxt, 0);
3347 goto done;
3348 }
3349 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3350 &c->dst.val))
3351 goto done; /* IO is needed */
3352 break;
3353 case 0xee: /* out dx,al */
3354 case 0xef: /* out dx,(e/r)ax */
3355 c->dst.val = c->regs[VCPU_REGS_RDX];
3356 do_io_out:
3357 c->src.bytes = min(c->src.bytes, 4u);
3358 if (!emulator_io_permited(ctxt, ops, c->dst.val,
3359 c->src.bytes)) {
3360 emulate_gp(ctxt, 0);
3361 goto done;
3362 }
3363 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3364 &c->src.val, 1, ctxt->vcpu);
3365 c->dst.type = OP_NONE; /* Disable writeback. */
3366 break;
3367 case 0xf4: /* hlt */
3368 ctxt->vcpu->arch.halt_request = 1;
3369 break;
3370 case 0xf5: /* cmc */
3371 /* complement carry flag from eflags reg */
3372 ctxt->eflags ^= EFLG_CF;
3373 break;
3374 case 0xf6 ... 0xf7: /* Grp3 */
3375 if (emulate_grp3(ctxt, ops) != X86EMUL_CONTINUE)
3376 goto cannot_emulate;
3377 break;
3378 case 0xf8: /* clc */
3379 ctxt->eflags &= ~EFLG_CF;
3380 break;
3381 case 0xf9: /* stc */
3382 ctxt->eflags |= EFLG_CF;
3383 break;
3384 case 0xfa: /* cli */
3385 if (emulator_bad_iopl(ctxt, ops)) {
3386 emulate_gp(ctxt, 0);
3387 goto done;
3388 } else
3389 ctxt->eflags &= ~X86_EFLAGS_IF;
3390 break;
3391 case 0xfb: /* sti */
3392 if (emulator_bad_iopl(ctxt, ops)) {
3393 emulate_gp(ctxt, 0);
3394 goto done;
3395 } else {
3396 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3397 ctxt->eflags |= X86_EFLAGS_IF;
3398 }
3399 break;
3400 case 0xfc: /* cld */
3401 ctxt->eflags &= ~EFLG_DF;
3402 break;
3403 case 0xfd: /* std */
3404 ctxt->eflags |= EFLG_DF;
3405 break;
3406 case 0xfe: /* Grp4 */
3407 grp45:
3408 rc = emulate_grp45(ctxt, ops);
3409 if (rc != X86EMUL_CONTINUE)
3410 goto done;
3411 break;
3412 case 0xff: /* Grp5 */
3413 if (c->modrm_reg == 5)
3414 goto jump_far;
3415 goto grp45;
3416 default:
3417 goto cannot_emulate;
3418 }
3419
3420 writeback:
3421 rc = writeback(ctxt, ops);
3422 if (rc != X86EMUL_CONTINUE)
3423 goto done;
3424
3425 /*
3426 * restore dst type in case the decoding will be reused
3427 * (happens for string instruction )
3428 */
3429 c->dst.type = saved_dst_type;
3430
3431 if ((c->d & SrcMask) == SrcSI)
3432 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3433 VCPU_REGS_RSI, &c->src);
3434
3435 if ((c->d & DstMask) == DstDI)
3436 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3437 &c->dst);
3438
3439 if (c->rep_prefix && (c->d & String)) {
3440 struct read_cache *r = &ctxt->decode.io_read;
3441 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3442
3443 if (!string_insn_completed(ctxt)) {
3444 /*
3445 * Re-enter guest when pio read ahead buffer is empty
3446 * or, if it is not used, after each 1024 iteration.
3447 */
3448 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3449 (r->end == 0 || r->end != r->pos)) {
3450 /*
3451 * Reset read cache. Usually happens before
3452 * decode, but since instruction is restarted
3453 * we have to do it here.
3454 */
3455 ctxt->decode.mem_read.end = 0;
3456 return EMULATION_RESTART;
3457 }
3458 goto done; /* skip rip writeback */
3459 }
3460 }
3461
3462 ctxt->eip = c->eip;
3463
3464 done:
3465 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3466
3467 twobyte_insn:
3468 switch (c->b) {
3469 case 0x01: /* lgdt, lidt, lmsw */
3470 switch (c->modrm_reg) {
3471 u16 size;
3472 unsigned long address;
3473
3474 case 0: /* vmcall */
3475 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3476 goto cannot_emulate;
3477
3478 rc = kvm_fix_hypercall(ctxt->vcpu);
3479 if (rc != X86EMUL_CONTINUE)
3480 goto done;
3481
3482 /* Let the processor re-execute the fixed hypercall */
3483 c->eip = ctxt->eip;
3484 /* Disable writeback. */
3485 c->dst.type = OP_NONE;
3486 break;
3487 case 2: /* lgdt */
3488 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
3489 &size, &address, c->op_bytes);
3490 if (rc != X86EMUL_CONTINUE)
3491 goto done;
3492 realmode_lgdt(ctxt->vcpu, size, address);
3493 /* Disable writeback. */
3494 c->dst.type = OP_NONE;
3495 break;
3496 case 3: /* lidt/vmmcall */
3497 if (c->modrm_mod == 3) {
3498 switch (c->modrm_rm) {
3499 case 1:
3500 rc = kvm_fix_hypercall(ctxt->vcpu);
3501 if (rc != X86EMUL_CONTINUE)
3502 goto done;
3503 break;
3504 default:
3505 goto cannot_emulate;
3506 }
3507 } else {
3508 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
3509 &size, &address,
3510 c->op_bytes);
3511 if (rc != X86EMUL_CONTINUE)
3512 goto done;
3513 realmode_lidt(ctxt->vcpu, size, address);
3514 }
3515 /* Disable writeback. */
3516 c->dst.type = OP_NONE;
3517 break;
3518 case 4: /* smsw */
3519 c->dst.bytes = 2;
3520 c->dst.val = ops->get_cr(0, ctxt->vcpu);
3521 break;
3522 case 6: /* lmsw */
3523 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
3524 (c->src.val & 0x0f), ctxt->vcpu);
3525 c->dst.type = OP_NONE;
3526 break;
3527 case 5: /* not defined */
3528 emulate_ud(ctxt);
3529 goto done;
3530 case 7: /* invlpg*/
3531 emulate_invlpg(ctxt->vcpu, c->src.addr.mem);
3532 /* Disable writeback. */
3533 c->dst.type = OP_NONE;
3534 break;
3535 default:
3536 goto cannot_emulate;
3537 }
3538 break;
3539 case 0x05: /* syscall */
3540 rc = emulate_syscall(ctxt, ops);
3541 if (rc != X86EMUL_CONTINUE)
3542 goto done;
3543 else
3544 goto writeback;
3545 break;
3546 case 0x06:
3547 emulate_clts(ctxt->vcpu);
3548 break;
3549 case 0x09: /* wbinvd */
3550 kvm_emulate_wbinvd(ctxt->vcpu);
3551 break;
3552 case 0x08: /* invd */
3553 case 0x0d: /* GrpP (prefetch) */
3554 case 0x18: /* Grp16 (prefetch/nop) */
3555 break;
3556 case 0x20: /* mov cr, reg */
3557 switch (c->modrm_reg) {
3558 case 1:
3559 case 5 ... 7:
3560 case 9 ... 15:
3561 emulate_ud(ctxt);
3562 goto done;
3563 }
3564 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
3565 break;
3566 case 0x21: /* mov from dr to reg */
3567 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3568 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3569 emulate_ud(ctxt);
3570 goto done;
3571 }
3572 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
3573 break;
3574 case 0x22: /* mov reg, cr */
3575 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
3576 emulate_gp(ctxt, 0);
3577 goto done;
3578 }
3579 c->dst.type = OP_NONE;
3580 break;
3581 case 0x23: /* mov from reg to dr */
3582 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3583 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3584 emulate_ud(ctxt);
3585 goto done;
3586 }
3587
3588 if (ops->set_dr(c->modrm_reg, c->src.val &
3589 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3590 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3591 /* #UD condition is already handled by the code above */
3592 emulate_gp(ctxt, 0);
3593 goto done;
3594 }
3595
3596 c->dst.type = OP_NONE; /* no writeback */
3597 break;
3598 case 0x30:
3599 /* wrmsr */
3600 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3601 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3602 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
3603 emulate_gp(ctxt, 0);
3604 goto done;
3605 }
3606 rc = X86EMUL_CONTINUE;
3607 break;
3608 case 0x32:
3609 /* rdmsr */
3610 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
3611 emulate_gp(ctxt, 0);
3612 goto done;
3613 } else {
3614 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3615 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3616 }
3617 rc = X86EMUL_CONTINUE;
3618 break;
3619 case 0x34: /* sysenter */
3620 rc = emulate_sysenter(ctxt, ops);
3621 if (rc != X86EMUL_CONTINUE)
3622 goto done;
3623 else
3624 goto writeback;
3625 break;
3626 case 0x35: /* sysexit */
3627 rc = emulate_sysexit(ctxt, ops);
3628 if (rc != X86EMUL_CONTINUE)
3629 goto done;
3630 else
3631 goto writeback;
3632 break;
3633 case 0x40 ... 0x4f: /* cmov */
3634 c->dst.val = c->dst.orig_val = c->src.val;
3635 if (!test_cc(c->b, ctxt->eflags))
3636 c->dst.type = OP_NONE; /* no writeback */
3637 break;
3638 case 0x80 ... 0x8f: /* jnz rel, etc*/
3639 if (test_cc(c->b, ctxt->eflags))
3640 jmp_rel(c, c->src.val);
3641 break;
3642 case 0x90 ... 0x9f: /* setcc r/m8 */
3643 c->dst.val = test_cc(c->b, ctxt->eflags);
3644 break;
3645 case 0xa0: /* push fs */
3646 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
3647 break;
3648 case 0xa1: /* pop fs */
3649 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
3650 if (rc != X86EMUL_CONTINUE)
3651 goto done;
3652 break;
3653 case 0xa3:
3654 bt: /* bt */
3655 c->dst.type = OP_NONE;
3656 /* only subword offset */
3657 c->src.val &= (c->dst.bytes << 3) - 1;
3658 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
3659 break;
3660 case 0xa4: /* shld imm8, r, r/m */
3661 case 0xa5: /* shld cl, r, r/m */
3662 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3663 break;
3664 case 0xa8: /* push gs */
3665 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
3666 break;
3667 case 0xa9: /* pop gs */
3668 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
3669 if (rc != X86EMUL_CONTINUE)
3670 goto done;
3671 break;
3672 case 0xab:
3673 bts: /* bts */
3674 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
3675 break;
3676 case 0xac: /* shrd imm8, r, r/m */
3677 case 0xad: /* shrd cl, r, r/m */
3678 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3679 break;
3680 case 0xae: /* clflush */
3681 break;
3682 case 0xb0 ... 0xb1: /* cmpxchg */
3683 /*
3684 * Save real source value, then compare EAX against
3685 * destination.
3686 */
3687 c->src.orig_val = c->src.val;
3688 c->src.val = c->regs[VCPU_REGS_RAX];
3689 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3690 if (ctxt->eflags & EFLG_ZF) {
3691 /* Success: write back to memory. */
3692 c->dst.val = c->src.orig_val;
3693 } else {
3694 /* Failure: write the value we saw to EAX. */
3695 c->dst.type = OP_REG;
3696 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
3697 }
3698 break;
3699 case 0xb2: /* lss */
3700 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
3701 if (rc != X86EMUL_CONTINUE)
3702 goto done;
3703 break;
3704 case 0xb3:
3705 btr: /* btr */
3706 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
3707 break;
3708 case 0xb4: /* lfs */
3709 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
3710 if (rc != X86EMUL_CONTINUE)
3711 goto done;
3712 break;
3713 case 0xb5: /* lgs */
3714 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
3715 if (rc != X86EMUL_CONTINUE)
3716 goto done;
3717 break;
3718 case 0xb6 ... 0xb7: /* movzx */
3719 c->dst.bytes = c->op_bytes;
3720 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3721 : (u16) c->src.val;
3722 break;
3723 case 0xba: /* Grp8 */
3724 switch (c->modrm_reg & 3) {
3725 case 0:
3726 goto bt;
3727 case 1:
3728 goto bts;
3729 case 2:
3730 goto btr;
3731 case 3:
3732 goto btc;
3733 }
3734 break;
3735 case 0xbb:
3736 btc: /* btc */
3737 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
3738 break;
3739 case 0xbc: { /* bsf */
3740 u8 zf;
3741 __asm__ ("bsf %2, %0; setz %1"
3742 : "=r"(c->dst.val), "=q"(zf)
3743 : "r"(c->src.val));
3744 ctxt->eflags &= ~X86_EFLAGS_ZF;
3745 if (zf) {
3746 ctxt->eflags |= X86_EFLAGS_ZF;
3747 c->dst.type = OP_NONE; /* Disable writeback. */
3748 }
3749 break;
3750 }
3751 case 0xbd: { /* bsr */
3752 u8 zf;
3753 __asm__ ("bsr %2, %0; setz %1"
3754 : "=r"(c->dst.val), "=q"(zf)
3755 : "r"(c->src.val));
3756 ctxt->eflags &= ~X86_EFLAGS_ZF;
3757 if (zf) {
3758 ctxt->eflags |= X86_EFLAGS_ZF;
3759 c->dst.type = OP_NONE; /* Disable writeback. */
3760 }
3761 break;
3762 }
3763 case 0xbe ... 0xbf: /* movsx */
3764 c->dst.bytes = c->op_bytes;
3765 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3766 (s16) c->src.val;
3767 break;
3768 case 0xc0 ... 0xc1: /* xadd */
3769 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3770 /* Write back the register source. */
3771 c->src.val = c->dst.orig_val;
3772 write_register_operand(&c->src);
3773 break;
3774 case 0xc3: /* movnti */
3775 c->dst.bytes = c->op_bytes;
3776 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3777 (u64) c->src.val;
3778 break;
3779 case 0xc7: /* Grp9 (cmpxchg8b) */
3780 rc = emulate_grp9(ctxt, ops);
3781 if (rc != X86EMUL_CONTINUE)
3782 goto done;
3783 break;
3784 default:
3785 goto cannot_emulate;
3786 }
3787 goto writeback;
3788
3789 cannot_emulate:
3790 DPRINTF("Cannot emulate %02x\n", c->b);
3791 return -1;
3792 }
Linux kernel - Deliverables
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