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KVM: x86 emulator: implement IMUL REG, R/M, IMM (opcode 69)
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #ifndef __KERNEL__
24 #include <stdio.h>
25 #include <stdint.h>
26 #include <public/xen.h>
27 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
28 #else
29 #include <linux/kvm_host.h>
30 #include "kvm_cache_regs.h"
31 #define DPRINTF(x...) do {} while (0)
32 #endif
33 #include <linux/module.h>
34 #include <asm/kvm_emulate.h>
35
36 #include "x86.h"
37 #include "tss.h"
38
39 /*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48 /* Operand sizes: 8-bit operands or specified/overridden size. */
49 #define ByteOp (1<<0) /* 8-bit operands. */
50 /* Destination operand type. */
51 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
52 #define DstReg (2<<1) /* Register operand. */
53 #define DstMem (3<<1) /* Memory operand. */
54 #define DstAcc (4<<1) /* Destination Accumulator */
55 #define DstDI (5<<1) /* Destination is in ES:(E)DI */
56 #define DstMem64 (6<<1) /* 64bit memory operand */
57 #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
58 #define DstMask (7<<1)
59 /* Source operand type. */
60 #define SrcNone (0<<4) /* No source operand. */
61 #define SrcReg (1<<4) /* Register operand. */
62 #define SrcMem (2<<4) /* Memory operand. */
63 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65 #define SrcImm (5<<4) /* Immediate operand. */
66 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
67 #define SrcOne (7<<4) /* Implied '1' */
68 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
69 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
70 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */
71 #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72 #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
73 #define SrcAcc (0xd<<4) /* Source Accumulator */
74 #define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
75 #define SrcMask (0xf<<4)
76 /* Generic ModRM decode. */
77 #define ModRM (1<<8)
78 /* Destination is only written; never read. */
79 #define Mov (1<<9)
80 #define BitOp (1<<10)
81 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
82 #define String (1<<12) /* String instruction (rep capable) */
83 #define Stack (1<<13) /* Stack instruction (push/pop) */
84 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
85 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
86 /* Misc flags */
87 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
88 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
89 #define Undefined (1<<25) /* No Such Instruction */
90 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
91 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
92 #define No64 (1<<28)
93 /* Source 2 operand type */
94 #define Src2None (0<<29)
95 #define Src2CL (1<<29)
96 #define Src2ImmByte (2<<29)
97 #define Src2One (3<<29)
98 #define Src2Imm (4<<29)
99 #define Src2Mask (7<<29)
100
101 #define X2(x...) x, x
102 #define X3(x...) X2(x), x
103 #define X4(x...) X2(x), X2(x)
104 #define X5(x...) X4(x), x
105 #define X6(x...) X4(x), X2(x)
106 #define X7(x...) X4(x), X3(x)
107 #define X8(x...) X4(x), X4(x)
108 #define X16(x...) X8(x), X8(x)
109
110 struct opcode {
111 u32 flags;
112 union {
113 int (*execute)(struct x86_emulate_ctxt *ctxt);
114 struct opcode *group;
115 struct group_dual *gdual;
116 } u;
117 };
118
119 struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
122 };
123
124 /* EFLAGS bit definitions. */
125 #define EFLG_ID (1<<21)
126 #define EFLG_VIP (1<<20)
127 #define EFLG_VIF (1<<19)
128 #define EFLG_AC (1<<18)
129 #define EFLG_VM (1<<17)
130 #define EFLG_RF (1<<16)
131 #define EFLG_IOPL (3<<12)
132 #define EFLG_NT (1<<14)
133 #define EFLG_OF (1<<11)
134 #define EFLG_DF (1<<10)
135 #define EFLG_IF (1<<9)
136 #define EFLG_TF (1<<8)
137 #define EFLG_SF (1<<7)
138 #define EFLG_ZF (1<<6)
139 #define EFLG_AF (1<<4)
140 #define EFLG_PF (1<<2)
141 #define EFLG_CF (1<<0)
142
143 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
144 #define EFLG_RESERVED_ONE_MASK 2
145
146 /*
147 * Instruction emulation:
148 * Most instructions are emulated directly via a fragment of inline assembly
149 * code. This allows us to save/restore EFLAGS and thus very easily pick up
150 * any modified flags.
151 */
152
153 #if defined(CONFIG_X86_64)
154 #define _LO32 "k" /* force 32-bit operand */
155 #define _STK "%%rsp" /* stack pointer */
156 #elif defined(__i386__)
157 #define _LO32 "" /* force 32-bit operand */
158 #define _STK "%%esp" /* stack pointer */
159 #endif
160
161 /*
162 * These EFLAGS bits are restored from saved value during emulation, and
163 * any changes are written back to the saved value after emulation.
164 */
165 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
166
167 /* Before executing instruction: restore necessary bits in EFLAGS. */
168 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
169 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
170 "movl %"_sav",%"_LO32 _tmp"; " \
171 "push %"_tmp"; " \
172 "push %"_tmp"; " \
173 "movl %"_msk",%"_LO32 _tmp"; " \
174 "andl %"_LO32 _tmp",("_STK"); " \
175 "pushf; " \
176 "notl %"_LO32 _tmp"; " \
177 "andl %"_LO32 _tmp",("_STK"); " \
178 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
179 "pop %"_tmp"; " \
180 "orl %"_LO32 _tmp",("_STK"); " \
181 "popf; " \
182 "pop %"_sav"; "
183
184 /* After executing instruction: write-back necessary bits in EFLAGS. */
185 #define _POST_EFLAGS(_sav, _msk, _tmp) \
186 /* _sav |= EFLAGS & _msk; */ \
187 "pushf; " \
188 "pop %"_tmp"; " \
189 "andl %"_msk",%"_LO32 _tmp"; " \
190 "orl %"_LO32 _tmp",%"_sav"; "
191
192 #ifdef CONFIG_X86_64
193 #define ON64(x) x
194 #else
195 #define ON64(x)
196 #endif
197
198 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
199 do { \
200 __asm__ __volatile__ ( \
201 _PRE_EFLAGS("0", "4", "2") \
202 _op _suffix " %"_x"3,%1; " \
203 _POST_EFLAGS("0", "4", "2") \
204 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
205 "=&r" (_tmp) \
206 : _y ((_src).val), "i" (EFLAGS_MASK)); \
207 } while (0)
208
209
210 /* Raw emulation: instruction has two explicit operands. */
211 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
212 do { \
213 unsigned long _tmp; \
214 \
215 switch ((_dst).bytes) { \
216 case 2: \
217 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
218 break; \
219 case 4: \
220 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
221 break; \
222 case 8: \
223 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
224 break; \
225 } \
226 } while (0)
227
228 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
229 do { \
230 unsigned long _tmp; \
231 switch ((_dst).bytes) { \
232 case 1: \
233 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
234 break; \
235 default: \
236 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
237 _wx, _wy, _lx, _ly, _qx, _qy); \
238 break; \
239 } \
240 } while (0)
241
242 /* Source operand is byte-sized and may be restricted to just %cl. */
243 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
244 __emulate_2op(_op, _src, _dst, _eflags, \
245 "b", "c", "b", "c", "b", "c", "b", "c")
246
247 /* Source operand is byte, word, long or quad sized. */
248 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
249 __emulate_2op(_op, _src, _dst, _eflags, \
250 "b", "q", "w", "r", _LO32, "r", "", "r")
251
252 /* Source operand is word, long or quad sized. */
253 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
254 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
255 "w", "r", _LO32, "r", "", "r")
256
257 /* Instruction has three operands and one operand is stored in ECX register */
258 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
259 do { \
260 unsigned long _tmp; \
261 _type _clv = (_cl).val; \
262 _type _srcv = (_src).val; \
263 _type _dstv = (_dst).val; \
264 \
265 __asm__ __volatile__ ( \
266 _PRE_EFLAGS("0", "5", "2") \
267 _op _suffix " %4,%1 \n" \
268 _POST_EFLAGS("0", "5", "2") \
269 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
270 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
271 ); \
272 \
273 (_cl).val = (unsigned long) _clv; \
274 (_src).val = (unsigned long) _srcv; \
275 (_dst).val = (unsigned long) _dstv; \
276 } while (0)
277
278 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
279 do { \
280 switch ((_dst).bytes) { \
281 case 2: \
282 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
283 "w", unsigned short); \
284 break; \
285 case 4: \
286 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
287 "l", unsigned int); \
288 break; \
289 case 8: \
290 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
291 "q", unsigned long)); \
292 break; \
293 } \
294 } while (0)
295
296 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
297 do { \
298 unsigned long _tmp; \
299 \
300 __asm__ __volatile__ ( \
301 _PRE_EFLAGS("0", "3", "2") \
302 _op _suffix " %1; " \
303 _POST_EFLAGS("0", "3", "2") \
304 : "=m" (_eflags), "+m" ((_dst).val), \
305 "=&r" (_tmp) \
306 : "i" (EFLAGS_MASK)); \
307 } while (0)
308
309 /* Instruction has only one explicit operand (no source operand). */
310 #define emulate_1op(_op, _dst, _eflags) \
311 do { \
312 switch ((_dst).bytes) { \
313 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
314 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
315 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
316 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
317 } \
318 } while (0)
319
320 #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
321 do { \
322 unsigned long _tmp; \
323 \
324 __asm__ __volatile__ ( \
325 _PRE_EFLAGS("0", "4", "1") \
326 _op _suffix " %5; " \
327 _POST_EFLAGS("0", "4", "1") \
328 : "=m" (_eflags), "=&r" (_tmp), \
329 "+a" (_rax), "+d" (_rdx) \
330 : "i" (EFLAGS_MASK), "m" ((_src).val), \
331 "a" (_rax), "d" (_rdx)); \
332 } while (0)
333
334 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
335 #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
336 do { \
337 switch((_src).bytes) { \
338 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
339 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
340 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
341 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
342 } \
343 } while (0)
344
345 /* Fetch next part of the instruction being emulated. */
346 #define insn_fetch(_type, _size, _eip) \
347 ({ unsigned long _x; \
348 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
349 if (rc != X86EMUL_CONTINUE) \
350 goto done; \
351 (_eip) += (_size); \
352 (_type)_x; \
353 })
354
355 #define insn_fetch_arr(_arr, _size, _eip) \
356 ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
357 if (rc != X86EMUL_CONTINUE) \
358 goto done; \
359 (_eip) += (_size); \
360 })
361
362 static inline unsigned long ad_mask(struct decode_cache *c)
363 {
364 return (1UL << (c->ad_bytes << 3)) - 1;
365 }
366
367 /* Access/update address held in a register, based on addressing mode. */
368 static inline unsigned long
369 address_mask(struct decode_cache *c, unsigned long reg)
370 {
371 if (c->ad_bytes == sizeof(unsigned long))
372 return reg;
373 else
374 return reg & ad_mask(c);
375 }
376
377 static inline unsigned long
378 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
379 {
380 return base + address_mask(c, reg);
381 }
382
383 static inline void
384 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
385 {
386 if (c->ad_bytes == sizeof(unsigned long))
387 *reg += inc;
388 else
389 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
390 }
391
392 static inline void jmp_rel(struct decode_cache *c, int rel)
393 {
394 register_address_increment(c, &c->eip, rel);
395 }
396
397 static void set_seg_override(struct decode_cache *c, int seg)
398 {
399 c->has_seg_override = true;
400 c->seg_override = seg;
401 }
402
403 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
404 struct x86_emulate_ops *ops, int seg)
405 {
406 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
407 return 0;
408
409 return ops->get_cached_segment_base(seg, ctxt->vcpu);
410 }
411
412 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
413 struct x86_emulate_ops *ops,
414 struct decode_cache *c)
415 {
416 if (!c->has_seg_override)
417 return 0;
418
419 return seg_base(ctxt, ops, c->seg_override);
420 }
421
422 static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
423 struct x86_emulate_ops *ops)
424 {
425 return seg_base(ctxt, ops, VCPU_SREG_ES);
426 }
427
428 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
429 struct x86_emulate_ops *ops)
430 {
431 return seg_base(ctxt, ops, VCPU_SREG_SS);
432 }
433
434 static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
435 u32 error, bool valid)
436 {
437 ctxt->exception = vec;
438 ctxt->error_code = error;
439 ctxt->error_code_valid = valid;
440 ctxt->restart = false;
441 }
442
443 static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
444 {
445 emulate_exception(ctxt, GP_VECTOR, err, true);
446 }
447
448 static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
449 int err)
450 {
451 ctxt->cr2 = addr;
452 emulate_exception(ctxt, PF_VECTOR, err, true);
453 }
454
455 static void emulate_ud(struct x86_emulate_ctxt *ctxt)
456 {
457 emulate_exception(ctxt, UD_VECTOR, 0, false);
458 }
459
460 static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
461 {
462 emulate_exception(ctxt, TS_VECTOR, err, true);
463 }
464
465 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
466 struct x86_emulate_ops *ops,
467 unsigned long eip, u8 *dest)
468 {
469 struct fetch_cache *fc = &ctxt->decode.fetch;
470 int rc;
471 int size, cur_size;
472
473 if (eip == fc->end) {
474 cur_size = fc->end - fc->start;
475 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
476 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
477 size, ctxt->vcpu, NULL);
478 if (rc != X86EMUL_CONTINUE)
479 return rc;
480 fc->end += size;
481 }
482 *dest = fc->data[eip - fc->start];
483 return X86EMUL_CONTINUE;
484 }
485
486 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
487 struct x86_emulate_ops *ops,
488 unsigned long eip, void *dest, unsigned size)
489 {
490 int rc;
491
492 /* x86 instructions are limited to 15 bytes. */
493 if (eip + size - ctxt->eip > 15)
494 return X86EMUL_UNHANDLEABLE;
495 while (size--) {
496 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
497 if (rc != X86EMUL_CONTINUE)
498 return rc;
499 }
500 return X86EMUL_CONTINUE;
501 }
502
503 /*
504 * Given the 'reg' portion of a ModRM byte, and a register block, return a
505 * pointer into the block that addresses the relevant register.
506 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
507 */
508 static void *decode_register(u8 modrm_reg, unsigned long *regs,
509 int highbyte_regs)
510 {
511 void *p;
512
513 p = &regs[modrm_reg];
514 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
515 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
516 return p;
517 }
518
519 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
520 struct x86_emulate_ops *ops,
521 ulong addr,
522 u16 *size, unsigned long *address, int op_bytes)
523 {
524 int rc;
525
526 if (op_bytes == 2)
527 op_bytes = 3;
528 *address = 0;
529 rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL);
530 if (rc != X86EMUL_CONTINUE)
531 return rc;
532 rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL);
533 return rc;
534 }
535
536 static int test_cc(unsigned int condition, unsigned int flags)
537 {
538 int rc = 0;
539
540 switch ((condition & 15) >> 1) {
541 case 0: /* o */
542 rc |= (flags & EFLG_OF);
543 break;
544 case 1: /* b/c/nae */
545 rc |= (flags & EFLG_CF);
546 break;
547 case 2: /* z/e */
548 rc |= (flags & EFLG_ZF);
549 break;
550 case 3: /* be/na */
551 rc |= (flags & (EFLG_CF|EFLG_ZF));
552 break;
553 case 4: /* s */
554 rc |= (flags & EFLG_SF);
555 break;
556 case 5: /* p/pe */
557 rc |= (flags & EFLG_PF);
558 break;
559 case 7: /* le/ng */
560 rc |= (flags & EFLG_ZF);
561 /* fall through */
562 case 6: /* l/nge */
563 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
564 break;
565 }
566
567 /* Odd condition identifiers (lsb == 1) have inverted sense. */
568 return (!!rc ^ (condition & 1));
569 }
570
571 static void fetch_register_operand(struct operand *op)
572 {
573 switch (op->bytes) {
574 case 1:
575 op->val = *(u8 *)op->addr.reg;
576 break;
577 case 2:
578 op->val = *(u16 *)op->addr.reg;
579 break;
580 case 4:
581 op->val = *(u32 *)op->addr.reg;
582 break;
583 case 8:
584 op->val = *(u64 *)op->addr.reg;
585 break;
586 }
587 }
588
589 static void decode_register_operand(struct operand *op,
590 struct decode_cache *c,
591 int inhibit_bytereg)
592 {
593 unsigned reg = c->modrm_reg;
594 int highbyte_regs = c->rex_prefix == 0;
595
596 if (!(c->d & ModRM))
597 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
598 op->type = OP_REG;
599 if ((c->d & ByteOp) && !inhibit_bytereg) {
600 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
601 op->bytes = 1;
602 } else {
603 op->addr.reg = decode_register(reg, c->regs, 0);
604 op->bytes = c->op_bytes;
605 }
606 fetch_register_operand(op);
607 op->orig_val = op->val;
608 }
609
610 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
611 struct x86_emulate_ops *ops,
612 struct operand *op)
613 {
614 struct decode_cache *c = &ctxt->decode;
615 u8 sib;
616 int index_reg = 0, base_reg = 0, scale;
617 int rc = X86EMUL_CONTINUE;
618 ulong modrm_ea = 0;
619
620 if (c->rex_prefix) {
621 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
622 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
623 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
624 }
625
626 c->modrm = insn_fetch(u8, 1, c->eip);
627 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
628 c->modrm_reg |= (c->modrm & 0x38) >> 3;
629 c->modrm_rm |= (c->modrm & 0x07);
630 c->modrm_seg = VCPU_SREG_DS;
631
632 if (c->modrm_mod == 3) {
633 op->type = OP_REG;
634 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
635 op->addr.reg = decode_register(c->modrm_rm,
636 c->regs, c->d & ByteOp);
637 fetch_register_operand(op);
638 return rc;
639 }
640
641 op->type = OP_MEM;
642
643 if (c->ad_bytes == 2) {
644 unsigned bx = c->regs[VCPU_REGS_RBX];
645 unsigned bp = c->regs[VCPU_REGS_RBP];
646 unsigned si = c->regs[VCPU_REGS_RSI];
647 unsigned di = c->regs[VCPU_REGS_RDI];
648
649 /* 16-bit ModR/M decode. */
650 switch (c->modrm_mod) {
651 case 0:
652 if (c->modrm_rm == 6)
653 modrm_ea += insn_fetch(u16, 2, c->eip);
654 break;
655 case 1:
656 modrm_ea += insn_fetch(s8, 1, c->eip);
657 break;
658 case 2:
659 modrm_ea += insn_fetch(u16, 2, c->eip);
660 break;
661 }
662 switch (c->modrm_rm) {
663 case 0:
664 modrm_ea += bx + si;
665 break;
666 case 1:
667 modrm_ea += bx + di;
668 break;
669 case 2:
670 modrm_ea += bp + si;
671 break;
672 case 3:
673 modrm_ea += bp + di;
674 break;
675 case 4:
676 modrm_ea += si;
677 break;
678 case 5:
679 modrm_ea += di;
680 break;
681 case 6:
682 if (c->modrm_mod != 0)
683 modrm_ea += bp;
684 break;
685 case 7:
686 modrm_ea += bx;
687 break;
688 }
689 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
690 (c->modrm_rm == 6 && c->modrm_mod != 0))
691 c->modrm_seg = VCPU_SREG_SS;
692 modrm_ea = (u16)modrm_ea;
693 } else {
694 /* 32/64-bit ModR/M decode. */
695 if ((c->modrm_rm & 7) == 4) {
696 sib = insn_fetch(u8, 1, c->eip);
697 index_reg |= (sib >> 3) & 7;
698 base_reg |= sib & 7;
699 scale = sib >> 6;
700
701 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
702 modrm_ea += insn_fetch(s32, 4, c->eip);
703 else
704 modrm_ea += c->regs[base_reg];
705 if (index_reg != 4)
706 modrm_ea += c->regs[index_reg] << scale;
707 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
708 if (ctxt->mode == X86EMUL_MODE_PROT64)
709 c->rip_relative = 1;
710 } else
711 modrm_ea += c->regs[c->modrm_rm];
712 switch (c->modrm_mod) {
713 case 0:
714 if (c->modrm_rm == 5)
715 modrm_ea += insn_fetch(s32, 4, c->eip);
716 break;
717 case 1:
718 modrm_ea += insn_fetch(s8, 1, c->eip);
719 break;
720 case 2:
721 modrm_ea += insn_fetch(s32, 4, c->eip);
722 break;
723 }
724 }
725 op->addr.mem = modrm_ea;
726 done:
727 return rc;
728 }
729
730 static int decode_abs(struct x86_emulate_ctxt *ctxt,
731 struct x86_emulate_ops *ops,
732 struct operand *op)
733 {
734 struct decode_cache *c = &ctxt->decode;
735 int rc = X86EMUL_CONTINUE;
736
737 op->type = OP_MEM;
738 switch (c->ad_bytes) {
739 case 2:
740 op->addr.mem = insn_fetch(u16, 2, c->eip);
741 break;
742 case 4:
743 op->addr.mem = insn_fetch(u32, 4, c->eip);
744 break;
745 case 8:
746 op->addr.mem = insn_fetch(u64, 8, c->eip);
747 break;
748 }
749 done:
750 return rc;
751 }
752
753 static void fetch_bit_operand(struct decode_cache *c)
754 {
755 long sv, mask;
756
757 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
758 mask = ~(c->dst.bytes * 8 - 1);
759
760 if (c->src.bytes == 2)
761 sv = (s16)c->src.val & (s16)mask;
762 else if (c->src.bytes == 4)
763 sv = (s32)c->src.val & (s32)mask;
764
765 c->dst.addr.mem += (sv >> 3);
766 }
767
768 /* only subword offset */
769 c->src.val &= (c->dst.bytes << 3) - 1;
770 }
771
772 static int read_emulated(struct x86_emulate_ctxt *ctxt,
773 struct x86_emulate_ops *ops,
774 unsigned long addr, void *dest, unsigned size)
775 {
776 int rc;
777 struct read_cache *mc = &ctxt->decode.mem_read;
778 u32 err;
779
780 while (size) {
781 int n = min(size, 8u);
782 size -= n;
783 if (mc->pos < mc->end)
784 goto read_cached;
785
786 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
787 ctxt->vcpu);
788 if (rc == X86EMUL_PROPAGATE_FAULT)
789 emulate_pf(ctxt, addr, err);
790 if (rc != X86EMUL_CONTINUE)
791 return rc;
792 mc->end += n;
793
794 read_cached:
795 memcpy(dest, mc->data + mc->pos, n);
796 mc->pos += n;
797 dest += n;
798 addr += n;
799 }
800 return X86EMUL_CONTINUE;
801 }
802
803 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
804 struct x86_emulate_ops *ops,
805 unsigned int size, unsigned short port,
806 void *dest)
807 {
808 struct read_cache *rc = &ctxt->decode.io_read;
809
810 if (rc->pos == rc->end) { /* refill pio read ahead */
811 struct decode_cache *c = &ctxt->decode;
812 unsigned int in_page, n;
813 unsigned int count = c->rep_prefix ?
814 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
815 in_page = (ctxt->eflags & EFLG_DF) ?
816 offset_in_page(c->regs[VCPU_REGS_RDI]) :
817 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
818 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
819 count);
820 if (n == 0)
821 n = 1;
822 rc->pos = rc->end = 0;
823 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
824 return 0;
825 rc->end = n * size;
826 }
827
828 memcpy(dest, rc->data + rc->pos, size);
829 rc->pos += size;
830 return 1;
831 }
832
833 static u32 desc_limit_scaled(struct desc_struct *desc)
834 {
835 u32 limit = get_desc_limit(desc);
836
837 return desc->g ? (limit << 12) | 0xfff : limit;
838 }
839
840 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
841 struct x86_emulate_ops *ops,
842 u16 selector, struct desc_ptr *dt)
843 {
844 if (selector & 1 << 2) {
845 struct desc_struct desc;
846 memset (dt, 0, sizeof *dt);
847 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
848 return;
849
850 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
851 dt->address = get_desc_base(&desc);
852 } else
853 ops->get_gdt(dt, ctxt->vcpu);
854 }
855
856 /* allowed just for 8 bytes segments */
857 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
858 struct x86_emulate_ops *ops,
859 u16 selector, struct desc_struct *desc)
860 {
861 struct desc_ptr dt;
862 u16 index = selector >> 3;
863 int ret;
864 u32 err;
865 ulong addr;
866
867 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
868
869 if (dt.size < index * 8 + 7) {
870 emulate_gp(ctxt, selector & 0xfffc);
871 return X86EMUL_PROPAGATE_FAULT;
872 }
873 addr = dt.address + index * 8;
874 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
875 if (ret == X86EMUL_PROPAGATE_FAULT)
876 emulate_pf(ctxt, addr, err);
877
878 return ret;
879 }
880
881 /* allowed just for 8 bytes segments */
882 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
883 struct x86_emulate_ops *ops,
884 u16 selector, struct desc_struct *desc)
885 {
886 struct desc_ptr dt;
887 u16 index = selector >> 3;
888 u32 err;
889 ulong addr;
890 int ret;
891
892 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
893
894 if (dt.size < index * 8 + 7) {
895 emulate_gp(ctxt, selector & 0xfffc);
896 return X86EMUL_PROPAGATE_FAULT;
897 }
898
899 addr = dt.address + index * 8;
900 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
901 if (ret == X86EMUL_PROPAGATE_FAULT)
902 emulate_pf(ctxt, addr, err);
903
904 return ret;
905 }
906
907 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
908 struct x86_emulate_ops *ops,
909 u16 selector, int seg)
910 {
911 struct desc_struct seg_desc;
912 u8 dpl, rpl, cpl;
913 unsigned err_vec = GP_VECTOR;
914 u32 err_code = 0;
915 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
916 int ret;
917
918 memset(&seg_desc, 0, sizeof seg_desc);
919
920 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
921 || ctxt->mode == X86EMUL_MODE_REAL) {
922 /* set real mode segment descriptor */
923 set_desc_base(&seg_desc, selector << 4);
924 set_desc_limit(&seg_desc, 0xffff);
925 seg_desc.type = 3;
926 seg_desc.p = 1;
927 seg_desc.s = 1;
928 goto load;
929 }
930
931 /* NULL selector is not valid for TR, CS and SS */
932 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
933 && null_selector)
934 goto exception;
935
936 /* TR should be in GDT only */
937 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
938 goto exception;
939
940 if (null_selector) /* for NULL selector skip all following checks */
941 goto load;
942
943 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
944 if (ret != X86EMUL_CONTINUE)
945 return ret;
946
947 err_code = selector & 0xfffc;
948 err_vec = GP_VECTOR;
949
950 /* can't load system descriptor into segment selecor */
951 if (seg <= VCPU_SREG_GS && !seg_desc.s)
952 goto exception;
953
954 if (!seg_desc.p) {
955 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
956 goto exception;
957 }
958
959 rpl = selector & 3;
960 dpl = seg_desc.dpl;
961 cpl = ops->cpl(ctxt->vcpu);
962
963 switch (seg) {
964 case VCPU_SREG_SS:
965 /*
966 * segment is not a writable data segment or segment
967 * selector's RPL != CPL or segment selector's RPL != CPL
968 */
969 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
970 goto exception;
971 break;
972 case VCPU_SREG_CS:
973 if (!(seg_desc.type & 8))
974 goto exception;
975
976 if (seg_desc.type & 4) {
977 /* conforming */
978 if (dpl > cpl)
979 goto exception;
980 } else {
981 /* nonconforming */
982 if (rpl > cpl || dpl != cpl)
983 goto exception;
984 }
985 /* CS(RPL) <- CPL */
986 selector = (selector & 0xfffc) | cpl;
987 break;
988 case VCPU_SREG_TR:
989 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
990 goto exception;
991 break;
992 case VCPU_SREG_LDTR:
993 if (seg_desc.s || seg_desc.type != 2)
994 goto exception;
995 break;
996 default: /* DS, ES, FS, or GS */
997 /*
998 * segment is not a data or readable code segment or
999 * ((segment is a data or nonconforming code segment)
1000 * and (both RPL and CPL > DPL))
1001 */
1002 if ((seg_desc.type & 0xa) == 0x8 ||
1003 (((seg_desc.type & 0xc) != 0xc) &&
1004 (rpl > dpl && cpl > dpl)))
1005 goto exception;
1006 break;
1007 }
1008
1009 if (seg_desc.s) {
1010 /* mark segment as accessed */
1011 seg_desc.type |= 1;
1012 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1013 if (ret != X86EMUL_CONTINUE)
1014 return ret;
1015 }
1016 load:
1017 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1018 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1019 return X86EMUL_CONTINUE;
1020 exception:
1021 emulate_exception(ctxt, err_vec, err_code, true);
1022 return X86EMUL_PROPAGATE_FAULT;
1023 }
1024
1025 static void write_register_operand(struct operand *op)
1026 {
1027 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1028 switch (op->bytes) {
1029 case 1:
1030 *(u8 *)op->addr.reg = (u8)op->val;
1031 break;
1032 case 2:
1033 *(u16 *)op->addr.reg = (u16)op->val;
1034 break;
1035 case 4:
1036 *op->addr.reg = (u32)op->val;
1037 break; /* 64b: zero-extend */
1038 case 8:
1039 *op->addr.reg = op->val;
1040 break;
1041 }
1042 }
1043
1044 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1045 struct x86_emulate_ops *ops)
1046 {
1047 int rc;
1048 struct decode_cache *c = &ctxt->decode;
1049 u32 err;
1050
1051 switch (c->dst.type) {
1052 case OP_REG:
1053 write_register_operand(&c->dst);
1054 break;
1055 case OP_MEM:
1056 if (c->lock_prefix)
1057 rc = ops->cmpxchg_emulated(
1058 c->dst.addr.mem,
1059 &c->dst.orig_val,
1060 &c->dst.val,
1061 c->dst.bytes,
1062 &err,
1063 ctxt->vcpu);
1064 else
1065 rc = ops->write_emulated(
1066 c->dst.addr.mem,
1067 &c->dst.val,
1068 c->dst.bytes,
1069 &err,
1070 ctxt->vcpu);
1071 if (rc == X86EMUL_PROPAGATE_FAULT)
1072 emulate_pf(ctxt, c->dst.addr.mem, err);
1073 if (rc != X86EMUL_CONTINUE)
1074 return rc;
1075 break;
1076 case OP_NONE:
1077 /* no writeback */
1078 break;
1079 default:
1080 break;
1081 }
1082 return X86EMUL_CONTINUE;
1083 }
1084
1085 static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1086 struct x86_emulate_ops *ops)
1087 {
1088 struct decode_cache *c = &ctxt->decode;
1089
1090 c->dst.type = OP_MEM;
1091 c->dst.bytes = c->op_bytes;
1092 c->dst.val = c->src.val;
1093 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1094 c->dst.addr.mem = register_address(c, ss_base(ctxt, ops),
1095 c->regs[VCPU_REGS_RSP]);
1096 }
1097
1098 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1099 struct x86_emulate_ops *ops,
1100 void *dest, int len)
1101 {
1102 struct decode_cache *c = &ctxt->decode;
1103 int rc;
1104
1105 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
1106 c->regs[VCPU_REGS_RSP]),
1107 dest, len);
1108 if (rc != X86EMUL_CONTINUE)
1109 return rc;
1110
1111 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1112 return rc;
1113 }
1114
1115 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1116 struct x86_emulate_ops *ops,
1117 void *dest, int len)
1118 {
1119 int rc;
1120 unsigned long val, change_mask;
1121 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1122 int cpl = ops->cpl(ctxt->vcpu);
1123
1124 rc = emulate_pop(ctxt, ops, &val, len);
1125 if (rc != X86EMUL_CONTINUE)
1126 return rc;
1127
1128 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1129 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1130
1131 switch(ctxt->mode) {
1132 case X86EMUL_MODE_PROT64:
1133 case X86EMUL_MODE_PROT32:
1134 case X86EMUL_MODE_PROT16:
1135 if (cpl == 0)
1136 change_mask |= EFLG_IOPL;
1137 if (cpl <= iopl)
1138 change_mask |= EFLG_IF;
1139 break;
1140 case X86EMUL_MODE_VM86:
1141 if (iopl < 3) {
1142 emulate_gp(ctxt, 0);
1143 return X86EMUL_PROPAGATE_FAULT;
1144 }
1145 change_mask |= EFLG_IF;
1146 break;
1147 default: /* real mode */
1148 change_mask |= (EFLG_IOPL | EFLG_IF);
1149 break;
1150 }
1151
1152 *(unsigned long *)dest =
1153 (ctxt->eflags & ~change_mask) | (val & change_mask);
1154
1155 return rc;
1156 }
1157
1158 static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1159 struct x86_emulate_ops *ops, int seg)
1160 {
1161 struct decode_cache *c = &ctxt->decode;
1162
1163 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
1164
1165 emulate_push(ctxt, ops);
1166 }
1167
1168 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1169 struct x86_emulate_ops *ops, int seg)
1170 {
1171 struct decode_cache *c = &ctxt->decode;
1172 unsigned long selector;
1173 int rc;
1174
1175 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1176 if (rc != X86EMUL_CONTINUE)
1177 return rc;
1178
1179 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1180 return rc;
1181 }
1182
1183 static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1184 struct x86_emulate_ops *ops)
1185 {
1186 struct decode_cache *c = &ctxt->decode;
1187 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1188 int rc = X86EMUL_CONTINUE;
1189 int reg = VCPU_REGS_RAX;
1190
1191 while (reg <= VCPU_REGS_RDI) {
1192 (reg == VCPU_REGS_RSP) ?
1193 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1194
1195 emulate_push(ctxt, ops);
1196
1197 rc = writeback(ctxt, ops);
1198 if (rc != X86EMUL_CONTINUE)
1199 return rc;
1200
1201 ++reg;
1202 }
1203
1204 /* Disable writeback. */
1205 c->dst.type = OP_NONE;
1206
1207 return rc;
1208 }
1209
1210 static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1211 struct x86_emulate_ops *ops)
1212 {
1213 struct decode_cache *c = &ctxt->decode;
1214 int rc = X86EMUL_CONTINUE;
1215 int reg = VCPU_REGS_RDI;
1216
1217 while (reg >= VCPU_REGS_RAX) {
1218 if (reg == VCPU_REGS_RSP) {
1219 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1220 c->op_bytes);
1221 --reg;
1222 }
1223
1224 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1225 if (rc != X86EMUL_CONTINUE)
1226 break;
1227 --reg;
1228 }
1229 return rc;
1230 }
1231
1232 int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1233 struct x86_emulate_ops *ops, int irq)
1234 {
1235 struct decode_cache *c = &ctxt->decode;
1236 int rc;
1237 struct desc_ptr dt;
1238 gva_t cs_addr;
1239 gva_t eip_addr;
1240 u16 cs, eip;
1241 u32 err;
1242
1243 /* TODO: Add limit checks */
1244 c->src.val = ctxt->eflags;
1245 emulate_push(ctxt, ops);
1246 rc = writeback(ctxt, ops);
1247 if (rc != X86EMUL_CONTINUE)
1248 return rc;
1249
1250 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1251
1252 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1253 emulate_push(ctxt, ops);
1254 rc = writeback(ctxt, ops);
1255 if (rc != X86EMUL_CONTINUE)
1256 return rc;
1257
1258 c->src.val = c->eip;
1259 emulate_push(ctxt, ops);
1260 rc = writeback(ctxt, ops);
1261 if (rc != X86EMUL_CONTINUE)
1262 return rc;
1263
1264 c->dst.type = OP_NONE;
1265
1266 ops->get_idt(&dt, ctxt->vcpu);
1267
1268 eip_addr = dt.address + (irq << 2);
1269 cs_addr = dt.address + (irq << 2) + 2;
1270
1271 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &err);
1272 if (rc != X86EMUL_CONTINUE)
1273 return rc;
1274
1275 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &err);
1276 if (rc != X86EMUL_CONTINUE)
1277 return rc;
1278
1279 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1280 if (rc != X86EMUL_CONTINUE)
1281 return rc;
1282
1283 c->eip = eip;
1284
1285 return rc;
1286 }
1287
1288 static int emulate_int(struct x86_emulate_ctxt *ctxt,
1289 struct x86_emulate_ops *ops, int irq)
1290 {
1291 switch(ctxt->mode) {
1292 case X86EMUL_MODE_REAL:
1293 return emulate_int_real(ctxt, ops, irq);
1294 case X86EMUL_MODE_VM86:
1295 case X86EMUL_MODE_PROT16:
1296 case X86EMUL_MODE_PROT32:
1297 case X86EMUL_MODE_PROT64:
1298 default:
1299 /* Protected mode interrupts unimplemented yet */
1300 return X86EMUL_UNHANDLEABLE;
1301 }
1302 }
1303
1304 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1305 struct x86_emulate_ops *ops)
1306 {
1307 struct decode_cache *c = &ctxt->decode;
1308 int rc = X86EMUL_CONTINUE;
1309 unsigned long temp_eip = 0;
1310 unsigned long temp_eflags = 0;
1311 unsigned long cs = 0;
1312 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1313 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1314 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1315 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1316
1317 /* TODO: Add stack limit check */
1318
1319 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1320
1321 if (rc != X86EMUL_CONTINUE)
1322 return rc;
1323
1324 if (temp_eip & ~0xffff) {
1325 emulate_gp(ctxt, 0);
1326 return X86EMUL_PROPAGATE_FAULT;
1327 }
1328
1329 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1330
1331 if (rc != X86EMUL_CONTINUE)
1332 return rc;
1333
1334 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1335
1336 if (rc != X86EMUL_CONTINUE)
1337 return rc;
1338
1339 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1340
1341 if (rc != X86EMUL_CONTINUE)
1342 return rc;
1343
1344 c->eip = temp_eip;
1345
1346
1347 if (c->op_bytes == 4)
1348 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1349 else if (c->op_bytes == 2) {
1350 ctxt->eflags &= ~0xffff;
1351 ctxt->eflags |= temp_eflags;
1352 }
1353
1354 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1355 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1356
1357 return rc;
1358 }
1359
1360 static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1361 struct x86_emulate_ops* ops)
1362 {
1363 switch(ctxt->mode) {
1364 case X86EMUL_MODE_REAL:
1365 return emulate_iret_real(ctxt, ops);
1366 case X86EMUL_MODE_VM86:
1367 case X86EMUL_MODE_PROT16:
1368 case X86EMUL_MODE_PROT32:
1369 case X86EMUL_MODE_PROT64:
1370 default:
1371 /* iret from protected mode unimplemented yet */
1372 return X86EMUL_UNHANDLEABLE;
1373 }
1374 }
1375
1376 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1377 struct x86_emulate_ops *ops)
1378 {
1379 struct decode_cache *c = &ctxt->decode;
1380
1381 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1382 }
1383
1384 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1385 {
1386 struct decode_cache *c = &ctxt->decode;
1387 switch (c->modrm_reg) {
1388 case 0: /* rol */
1389 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1390 break;
1391 case 1: /* ror */
1392 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1393 break;
1394 case 2: /* rcl */
1395 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1396 break;
1397 case 3: /* rcr */
1398 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1399 break;
1400 case 4: /* sal/shl */
1401 case 6: /* sal/shl */
1402 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1403 break;
1404 case 5: /* shr */
1405 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1406 break;
1407 case 7: /* sar */
1408 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1409 break;
1410 }
1411 }
1412
1413 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1414 struct x86_emulate_ops *ops)
1415 {
1416 struct decode_cache *c = &ctxt->decode;
1417 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1418 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
1419
1420 switch (c->modrm_reg) {
1421 case 0 ... 1: /* test */
1422 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1423 break;
1424 case 2: /* not */
1425 c->dst.val = ~c->dst.val;
1426 break;
1427 case 3: /* neg */
1428 emulate_1op("neg", c->dst, ctxt->eflags);
1429 break;
1430 case 4: /* mul */
1431 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1432 break;
1433 case 5: /* imul */
1434 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1435 break;
1436 case 6: /* div */
1437 emulate_1op_rax_rdx("div", c->src, *rax, *rdx, ctxt->eflags);
1438 break;
1439 case 7: /* idiv */
1440 emulate_1op_rax_rdx("idiv", c->src, *rax, *rdx, ctxt->eflags);
1441 break;
1442 default:
1443 return X86EMUL_UNHANDLEABLE;
1444 }
1445 return X86EMUL_CONTINUE;
1446 }
1447
1448 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1449 struct x86_emulate_ops *ops)
1450 {
1451 struct decode_cache *c = &ctxt->decode;
1452
1453 switch (c->modrm_reg) {
1454 case 0: /* inc */
1455 emulate_1op("inc", c->dst, ctxt->eflags);
1456 break;
1457 case 1: /* dec */
1458 emulate_1op("dec", c->dst, ctxt->eflags);
1459 break;
1460 case 2: /* call near abs */ {
1461 long int old_eip;
1462 old_eip = c->eip;
1463 c->eip = c->src.val;
1464 c->src.val = old_eip;
1465 emulate_push(ctxt, ops);
1466 break;
1467 }
1468 case 4: /* jmp abs */
1469 c->eip = c->src.val;
1470 break;
1471 case 6: /* push */
1472 emulate_push(ctxt, ops);
1473 break;
1474 }
1475 return X86EMUL_CONTINUE;
1476 }
1477
1478 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1479 struct x86_emulate_ops *ops)
1480 {
1481 struct decode_cache *c = &ctxt->decode;
1482 u64 old = c->dst.orig_val64;
1483
1484 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1485 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1486 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1487 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1488 ctxt->eflags &= ~EFLG_ZF;
1489 } else {
1490 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1491 (u32) c->regs[VCPU_REGS_RBX];
1492
1493 ctxt->eflags |= EFLG_ZF;
1494 }
1495 return X86EMUL_CONTINUE;
1496 }
1497
1498 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1499 struct x86_emulate_ops *ops)
1500 {
1501 struct decode_cache *c = &ctxt->decode;
1502 int rc;
1503 unsigned long cs;
1504
1505 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1506 if (rc != X86EMUL_CONTINUE)
1507 return rc;
1508 if (c->op_bytes == 4)
1509 c->eip = (u32)c->eip;
1510 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1511 if (rc != X86EMUL_CONTINUE)
1512 return rc;
1513 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1514 return rc;
1515 }
1516
1517 static inline void
1518 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1519 struct x86_emulate_ops *ops, struct desc_struct *cs,
1520 struct desc_struct *ss)
1521 {
1522 memset(cs, 0, sizeof(struct desc_struct));
1523 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1524 memset(ss, 0, sizeof(struct desc_struct));
1525
1526 cs->l = 0; /* will be adjusted later */
1527 set_desc_base(cs, 0); /* flat segment */
1528 cs->g = 1; /* 4kb granularity */
1529 set_desc_limit(cs, 0xfffff); /* 4GB limit */
1530 cs->type = 0x0b; /* Read, Execute, Accessed */
1531 cs->s = 1;
1532 cs->dpl = 0; /* will be adjusted later */
1533 cs->p = 1;
1534 cs->d = 1;
1535
1536 set_desc_base(ss, 0); /* flat segment */
1537 set_desc_limit(ss, 0xfffff); /* 4GB limit */
1538 ss->g = 1; /* 4kb granularity */
1539 ss->s = 1;
1540 ss->type = 0x03; /* Read/Write, Accessed */
1541 ss->d = 1; /* 32bit stack segment */
1542 ss->dpl = 0;
1543 ss->p = 1;
1544 }
1545
1546 static int
1547 emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1548 {
1549 struct decode_cache *c = &ctxt->decode;
1550 struct desc_struct cs, ss;
1551 u64 msr_data;
1552 u16 cs_sel, ss_sel;
1553
1554 /* syscall is not available in real mode */
1555 if (ctxt->mode == X86EMUL_MODE_REAL ||
1556 ctxt->mode == X86EMUL_MODE_VM86) {
1557 emulate_ud(ctxt);
1558 return X86EMUL_PROPAGATE_FAULT;
1559 }
1560
1561 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1562
1563 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1564 msr_data >>= 32;
1565 cs_sel = (u16)(msr_data & 0xfffc);
1566 ss_sel = (u16)(msr_data + 8);
1567
1568 if (is_long_mode(ctxt->vcpu)) {
1569 cs.d = 0;
1570 cs.l = 1;
1571 }
1572 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1573 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1574 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1575 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1576
1577 c->regs[VCPU_REGS_RCX] = c->eip;
1578 if (is_long_mode(ctxt->vcpu)) {
1579 #ifdef CONFIG_X86_64
1580 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1581
1582 ops->get_msr(ctxt->vcpu,
1583 ctxt->mode == X86EMUL_MODE_PROT64 ?
1584 MSR_LSTAR : MSR_CSTAR, &msr_data);
1585 c->eip = msr_data;
1586
1587 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1588 ctxt->eflags &= ~(msr_data | EFLG_RF);
1589 #endif
1590 } else {
1591 /* legacy mode */
1592 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1593 c->eip = (u32)msr_data;
1594
1595 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1596 }
1597
1598 return X86EMUL_CONTINUE;
1599 }
1600
1601 static int
1602 emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1603 {
1604 struct decode_cache *c = &ctxt->decode;
1605 struct desc_struct cs, ss;
1606 u64 msr_data;
1607 u16 cs_sel, ss_sel;
1608
1609 /* inject #GP if in real mode */
1610 if (ctxt->mode == X86EMUL_MODE_REAL) {
1611 emulate_gp(ctxt, 0);
1612 return X86EMUL_PROPAGATE_FAULT;
1613 }
1614
1615 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1616 * Therefore, we inject an #UD.
1617 */
1618 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1619 emulate_ud(ctxt);
1620 return X86EMUL_PROPAGATE_FAULT;
1621 }
1622
1623 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1624
1625 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1626 switch (ctxt->mode) {
1627 case X86EMUL_MODE_PROT32:
1628 if ((msr_data & 0xfffc) == 0x0) {
1629 emulate_gp(ctxt, 0);
1630 return X86EMUL_PROPAGATE_FAULT;
1631 }
1632 break;
1633 case X86EMUL_MODE_PROT64:
1634 if (msr_data == 0x0) {
1635 emulate_gp(ctxt, 0);
1636 return X86EMUL_PROPAGATE_FAULT;
1637 }
1638 break;
1639 }
1640
1641 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1642 cs_sel = (u16)msr_data;
1643 cs_sel &= ~SELECTOR_RPL_MASK;
1644 ss_sel = cs_sel + 8;
1645 ss_sel &= ~SELECTOR_RPL_MASK;
1646 if (ctxt->mode == X86EMUL_MODE_PROT64
1647 || is_long_mode(ctxt->vcpu)) {
1648 cs.d = 0;
1649 cs.l = 1;
1650 }
1651
1652 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1653 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1654 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1655 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1656
1657 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1658 c->eip = msr_data;
1659
1660 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1661 c->regs[VCPU_REGS_RSP] = msr_data;
1662
1663 return X86EMUL_CONTINUE;
1664 }
1665
1666 static int
1667 emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1668 {
1669 struct decode_cache *c = &ctxt->decode;
1670 struct desc_struct cs, ss;
1671 u64 msr_data;
1672 int usermode;
1673 u16 cs_sel, ss_sel;
1674
1675 /* inject #GP if in real mode or Virtual 8086 mode */
1676 if (ctxt->mode == X86EMUL_MODE_REAL ||
1677 ctxt->mode == X86EMUL_MODE_VM86) {
1678 emulate_gp(ctxt, 0);
1679 return X86EMUL_PROPAGATE_FAULT;
1680 }
1681
1682 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1683
1684 if ((c->rex_prefix & 0x8) != 0x0)
1685 usermode = X86EMUL_MODE_PROT64;
1686 else
1687 usermode = X86EMUL_MODE_PROT32;
1688
1689 cs.dpl = 3;
1690 ss.dpl = 3;
1691 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1692 switch (usermode) {
1693 case X86EMUL_MODE_PROT32:
1694 cs_sel = (u16)(msr_data + 16);
1695 if ((msr_data & 0xfffc) == 0x0) {
1696 emulate_gp(ctxt, 0);
1697 return X86EMUL_PROPAGATE_FAULT;
1698 }
1699 ss_sel = (u16)(msr_data + 24);
1700 break;
1701 case X86EMUL_MODE_PROT64:
1702 cs_sel = (u16)(msr_data + 32);
1703 if (msr_data == 0x0) {
1704 emulate_gp(ctxt, 0);
1705 return X86EMUL_PROPAGATE_FAULT;
1706 }
1707 ss_sel = cs_sel + 8;
1708 cs.d = 0;
1709 cs.l = 1;
1710 break;
1711 }
1712 cs_sel |= SELECTOR_RPL_MASK;
1713 ss_sel |= SELECTOR_RPL_MASK;
1714
1715 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1716 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1717 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1718 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1719
1720 c->eip = c->regs[VCPU_REGS_RDX];
1721 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
1722
1723 return X86EMUL_CONTINUE;
1724 }
1725
1726 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1727 struct x86_emulate_ops *ops)
1728 {
1729 int iopl;
1730 if (ctxt->mode == X86EMUL_MODE_REAL)
1731 return false;
1732 if (ctxt->mode == X86EMUL_MODE_VM86)
1733 return true;
1734 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1735 return ops->cpl(ctxt->vcpu) > iopl;
1736 }
1737
1738 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1739 struct x86_emulate_ops *ops,
1740 u16 port, u16 len)
1741 {
1742 struct desc_struct tr_seg;
1743 int r;
1744 u16 io_bitmap_ptr;
1745 u8 perm, bit_idx = port & 0x7;
1746 unsigned mask = (1 << len) - 1;
1747
1748 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
1749 if (!tr_seg.p)
1750 return false;
1751 if (desc_limit_scaled(&tr_seg) < 103)
1752 return false;
1753 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
1754 ctxt->vcpu, NULL);
1755 if (r != X86EMUL_CONTINUE)
1756 return false;
1757 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
1758 return false;
1759 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
1760 &perm, 1, ctxt->vcpu, NULL);
1761 if (r != X86EMUL_CONTINUE)
1762 return false;
1763 if ((perm >> bit_idx) & mask)
1764 return false;
1765 return true;
1766 }
1767
1768 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1769 struct x86_emulate_ops *ops,
1770 u16 port, u16 len)
1771 {
1772 if (ctxt->perm_ok)
1773 return true;
1774
1775 if (emulator_bad_iopl(ctxt, ops))
1776 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1777 return false;
1778
1779 ctxt->perm_ok = true;
1780
1781 return true;
1782 }
1783
1784 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1785 struct x86_emulate_ops *ops,
1786 struct tss_segment_16 *tss)
1787 {
1788 struct decode_cache *c = &ctxt->decode;
1789
1790 tss->ip = c->eip;
1791 tss->flag = ctxt->eflags;
1792 tss->ax = c->regs[VCPU_REGS_RAX];
1793 tss->cx = c->regs[VCPU_REGS_RCX];
1794 tss->dx = c->regs[VCPU_REGS_RDX];
1795 tss->bx = c->regs[VCPU_REGS_RBX];
1796 tss->sp = c->regs[VCPU_REGS_RSP];
1797 tss->bp = c->regs[VCPU_REGS_RBP];
1798 tss->si = c->regs[VCPU_REGS_RSI];
1799 tss->di = c->regs[VCPU_REGS_RDI];
1800
1801 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1802 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1803 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1804 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1805 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1806 }
1807
1808 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1809 struct x86_emulate_ops *ops,
1810 struct tss_segment_16 *tss)
1811 {
1812 struct decode_cache *c = &ctxt->decode;
1813 int ret;
1814
1815 c->eip = tss->ip;
1816 ctxt->eflags = tss->flag | 2;
1817 c->regs[VCPU_REGS_RAX] = tss->ax;
1818 c->regs[VCPU_REGS_RCX] = tss->cx;
1819 c->regs[VCPU_REGS_RDX] = tss->dx;
1820 c->regs[VCPU_REGS_RBX] = tss->bx;
1821 c->regs[VCPU_REGS_RSP] = tss->sp;
1822 c->regs[VCPU_REGS_RBP] = tss->bp;
1823 c->regs[VCPU_REGS_RSI] = tss->si;
1824 c->regs[VCPU_REGS_RDI] = tss->di;
1825
1826 /*
1827 * SDM says that segment selectors are loaded before segment
1828 * descriptors
1829 */
1830 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1831 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1832 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1833 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1834 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1835
1836 /*
1837 * Now load segment descriptors. If fault happenes at this stage
1838 * it is handled in a context of new task
1839 */
1840 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1841 if (ret != X86EMUL_CONTINUE)
1842 return ret;
1843 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1844 if (ret != X86EMUL_CONTINUE)
1845 return ret;
1846 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1847 if (ret != X86EMUL_CONTINUE)
1848 return ret;
1849 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1850 if (ret != X86EMUL_CONTINUE)
1851 return ret;
1852 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1853 if (ret != X86EMUL_CONTINUE)
1854 return ret;
1855
1856 return X86EMUL_CONTINUE;
1857 }
1858
1859 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1860 struct x86_emulate_ops *ops,
1861 u16 tss_selector, u16 old_tss_sel,
1862 ulong old_tss_base, struct desc_struct *new_desc)
1863 {
1864 struct tss_segment_16 tss_seg;
1865 int ret;
1866 u32 err, new_tss_base = get_desc_base(new_desc);
1867
1868 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1869 &err);
1870 if (ret == X86EMUL_PROPAGATE_FAULT) {
1871 /* FIXME: need to provide precise fault address */
1872 emulate_pf(ctxt, old_tss_base, err);
1873 return ret;
1874 }
1875
1876 save_state_to_tss16(ctxt, ops, &tss_seg);
1877
1878 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1879 &err);
1880 if (ret == X86EMUL_PROPAGATE_FAULT) {
1881 /* FIXME: need to provide precise fault address */
1882 emulate_pf(ctxt, old_tss_base, err);
1883 return ret;
1884 }
1885
1886 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1887 &err);
1888 if (ret == X86EMUL_PROPAGATE_FAULT) {
1889 /* FIXME: need to provide precise fault address */
1890 emulate_pf(ctxt, new_tss_base, err);
1891 return ret;
1892 }
1893
1894 if (old_tss_sel != 0xffff) {
1895 tss_seg.prev_task_link = old_tss_sel;
1896
1897 ret = ops->write_std(new_tss_base,
1898 &tss_seg.prev_task_link,
1899 sizeof tss_seg.prev_task_link,
1900 ctxt->vcpu, &err);
1901 if (ret == X86EMUL_PROPAGATE_FAULT) {
1902 /* FIXME: need to provide precise fault address */
1903 emulate_pf(ctxt, new_tss_base, err);
1904 return ret;
1905 }
1906 }
1907
1908 return load_state_from_tss16(ctxt, ops, &tss_seg);
1909 }
1910
1911 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1912 struct x86_emulate_ops *ops,
1913 struct tss_segment_32 *tss)
1914 {
1915 struct decode_cache *c = &ctxt->decode;
1916
1917 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1918 tss->eip = c->eip;
1919 tss->eflags = ctxt->eflags;
1920 tss->eax = c->regs[VCPU_REGS_RAX];
1921 tss->ecx = c->regs[VCPU_REGS_RCX];
1922 tss->edx = c->regs[VCPU_REGS_RDX];
1923 tss->ebx = c->regs[VCPU_REGS_RBX];
1924 tss->esp = c->regs[VCPU_REGS_RSP];
1925 tss->ebp = c->regs[VCPU_REGS_RBP];
1926 tss->esi = c->regs[VCPU_REGS_RSI];
1927 tss->edi = c->regs[VCPU_REGS_RDI];
1928
1929 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1930 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1931 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1932 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1933 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
1934 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
1935 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1936 }
1937
1938 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
1939 struct x86_emulate_ops *ops,
1940 struct tss_segment_32 *tss)
1941 {
1942 struct decode_cache *c = &ctxt->decode;
1943 int ret;
1944
1945 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
1946 emulate_gp(ctxt, 0);
1947 return X86EMUL_PROPAGATE_FAULT;
1948 }
1949 c->eip = tss->eip;
1950 ctxt->eflags = tss->eflags | 2;
1951 c->regs[VCPU_REGS_RAX] = tss->eax;
1952 c->regs[VCPU_REGS_RCX] = tss->ecx;
1953 c->regs[VCPU_REGS_RDX] = tss->edx;
1954 c->regs[VCPU_REGS_RBX] = tss->ebx;
1955 c->regs[VCPU_REGS_RSP] = tss->esp;
1956 c->regs[VCPU_REGS_RBP] = tss->ebp;
1957 c->regs[VCPU_REGS_RSI] = tss->esi;
1958 c->regs[VCPU_REGS_RDI] = tss->edi;
1959
1960 /*
1961 * SDM says that segment selectors are loaded before segment
1962 * descriptors
1963 */
1964 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
1965 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1966 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1967 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1968 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1969 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
1970 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
1971
1972 /*
1973 * Now load segment descriptors. If fault happenes at this stage
1974 * it is handled in a context of new task
1975 */
1976 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
1977 if (ret != X86EMUL_CONTINUE)
1978 return ret;
1979 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1980 if (ret != X86EMUL_CONTINUE)
1981 return ret;
1982 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1983 if (ret != X86EMUL_CONTINUE)
1984 return ret;
1985 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1986 if (ret != X86EMUL_CONTINUE)
1987 return ret;
1988 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1989 if (ret != X86EMUL_CONTINUE)
1990 return ret;
1991 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
1992 if (ret != X86EMUL_CONTINUE)
1993 return ret;
1994 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
1995 if (ret != X86EMUL_CONTINUE)
1996 return ret;
1997
1998 return X86EMUL_CONTINUE;
1999 }
2000
2001 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2002 struct x86_emulate_ops *ops,
2003 u16 tss_selector, u16 old_tss_sel,
2004 ulong old_tss_base, struct desc_struct *new_desc)
2005 {
2006 struct tss_segment_32 tss_seg;
2007 int ret;
2008 u32 err, new_tss_base = get_desc_base(new_desc);
2009
2010 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2011 &err);
2012 if (ret == X86EMUL_PROPAGATE_FAULT) {
2013 /* FIXME: need to provide precise fault address */
2014 emulate_pf(ctxt, old_tss_base, err);
2015 return ret;
2016 }
2017
2018 save_state_to_tss32(ctxt, ops, &tss_seg);
2019
2020 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2021 &err);
2022 if (ret == X86EMUL_PROPAGATE_FAULT) {
2023 /* FIXME: need to provide precise fault address */
2024 emulate_pf(ctxt, old_tss_base, err);
2025 return ret;
2026 }
2027
2028 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2029 &err);
2030 if (ret == X86EMUL_PROPAGATE_FAULT) {
2031 /* FIXME: need to provide precise fault address */
2032 emulate_pf(ctxt, new_tss_base, err);
2033 return ret;
2034 }
2035
2036 if (old_tss_sel != 0xffff) {
2037 tss_seg.prev_task_link = old_tss_sel;
2038
2039 ret = ops->write_std(new_tss_base,
2040 &tss_seg.prev_task_link,
2041 sizeof tss_seg.prev_task_link,
2042 ctxt->vcpu, &err);
2043 if (ret == X86EMUL_PROPAGATE_FAULT) {
2044 /* FIXME: need to provide precise fault address */
2045 emulate_pf(ctxt, new_tss_base, err);
2046 return ret;
2047 }
2048 }
2049
2050 return load_state_from_tss32(ctxt, ops, &tss_seg);
2051 }
2052
2053 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2054 struct x86_emulate_ops *ops,
2055 u16 tss_selector, int reason,
2056 bool has_error_code, u32 error_code)
2057 {
2058 struct desc_struct curr_tss_desc, next_tss_desc;
2059 int ret;
2060 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2061 ulong old_tss_base =
2062 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
2063 u32 desc_limit;
2064
2065 /* FIXME: old_tss_base == ~0 ? */
2066
2067 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2068 if (ret != X86EMUL_CONTINUE)
2069 return ret;
2070 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2071 if (ret != X86EMUL_CONTINUE)
2072 return ret;
2073
2074 /* FIXME: check that next_tss_desc is tss */
2075
2076 if (reason != TASK_SWITCH_IRET) {
2077 if ((tss_selector & 3) > next_tss_desc.dpl ||
2078 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
2079 emulate_gp(ctxt, 0);
2080 return X86EMUL_PROPAGATE_FAULT;
2081 }
2082 }
2083
2084 desc_limit = desc_limit_scaled(&next_tss_desc);
2085 if (!next_tss_desc.p ||
2086 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2087 desc_limit < 0x2b)) {
2088 emulate_ts(ctxt, tss_selector & 0xfffc);
2089 return X86EMUL_PROPAGATE_FAULT;
2090 }
2091
2092 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2093 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2094 write_segment_descriptor(ctxt, ops, old_tss_sel,
2095 &curr_tss_desc);
2096 }
2097
2098 if (reason == TASK_SWITCH_IRET)
2099 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2100
2101 /* set back link to prev task only if NT bit is set in eflags
2102 note that old_tss_sel is not used afetr this point */
2103 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2104 old_tss_sel = 0xffff;
2105
2106 if (next_tss_desc.type & 8)
2107 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2108 old_tss_base, &next_tss_desc);
2109 else
2110 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2111 old_tss_base, &next_tss_desc);
2112 if (ret != X86EMUL_CONTINUE)
2113 return ret;
2114
2115 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2116 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2117
2118 if (reason != TASK_SWITCH_IRET) {
2119 next_tss_desc.type |= (1 << 1); /* set busy flag */
2120 write_segment_descriptor(ctxt, ops, tss_selector,
2121 &next_tss_desc);
2122 }
2123
2124 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2125 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2126 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2127
2128 if (has_error_code) {
2129 struct decode_cache *c = &ctxt->decode;
2130
2131 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2132 c->lock_prefix = 0;
2133 c->src.val = (unsigned long) error_code;
2134 emulate_push(ctxt, ops);
2135 }
2136
2137 return ret;
2138 }
2139
2140 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2141 u16 tss_selector, int reason,
2142 bool has_error_code, u32 error_code)
2143 {
2144 struct x86_emulate_ops *ops = ctxt->ops;
2145 struct decode_cache *c = &ctxt->decode;
2146 int rc;
2147
2148 c->eip = ctxt->eip;
2149 c->dst.type = OP_NONE;
2150
2151 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2152 has_error_code, error_code);
2153
2154 if (rc == X86EMUL_CONTINUE) {
2155 rc = writeback(ctxt, ops);
2156 if (rc == X86EMUL_CONTINUE)
2157 ctxt->eip = c->eip;
2158 }
2159
2160 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2161 }
2162
2163 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
2164 int reg, struct operand *op)
2165 {
2166 struct decode_cache *c = &ctxt->decode;
2167 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2168
2169 register_address_increment(c, &c->regs[reg], df * op->bytes);
2170 op->addr.mem = register_address(c, base, c->regs[reg]);
2171 }
2172
2173 static int em_push(struct x86_emulate_ctxt *ctxt)
2174 {
2175 emulate_push(ctxt, ctxt->ops);
2176 return X86EMUL_CONTINUE;
2177 }
2178
2179 static int em_das(struct x86_emulate_ctxt *ctxt)
2180 {
2181 struct decode_cache *c = &ctxt->decode;
2182 u8 al, old_al;
2183 bool af, cf, old_cf;
2184
2185 cf = ctxt->eflags & X86_EFLAGS_CF;
2186 al = c->dst.val;
2187
2188 old_al = al;
2189 old_cf = cf;
2190 cf = false;
2191 af = ctxt->eflags & X86_EFLAGS_AF;
2192 if ((al & 0x0f) > 9 || af) {
2193 al -= 6;
2194 cf = old_cf | (al >= 250);
2195 af = true;
2196 } else {
2197 af = false;
2198 }
2199 if (old_al > 0x99 || old_cf) {
2200 al -= 0x60;
2201 cf = true;
2202 }
2203
2204 c->dst.val = al;
2205 /* Set PF, ZF, SF */
2206 c->src.type = OP_IMM;
2207 c->src.val = 0;
2208 c->src.bytes = 1;
2209 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2210 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2211 if (cf)
2212 ctxt->eflags |= X86_EFLAGS_CF;
2213 if (af)
2214 ctxt->eflags |= X86_EFLAGS_AF;
2215 return X86EMUL_CONTINUE;
2216 }
2217
2218 static int em_call_far(struct x86_emulate_ctxt *ctxt)
2219 {
2220 struct decode_cache *c = &ctxt->decode;
2221 u16 sel, old_cs;
2222 ulong old_eip;
2223 int rc;
2224
2225 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2226 old_eip = c->eip;
2227
2228 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2229 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2230 return X86EMUL_CONTINUE;
2231
2232 c->eip = 0;
2233 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2234
2235 c->src.val = old_cs;
2236 emulate_push(ctxt, ctxt->ops);
2237 rc = writeback(ctxt, ctxt->ops);
2238 if (rc != X86EMUL_CONTINUE)
2239 return rc;
2240
2241 c->src.val = old_eip;
2242 emulate_push(ctxt, ctxt->ops);
2243 rc = writeback(ctxt, ctxt->ops);
2244 if (rc != X86EMUL_CONTINUE)
2245 return rc;
2246
2247 c->dst.type = OP_NONE;
2248
2249 return X86EMUL_CONTINUE;
2250 }
2251
2252 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2253 {
2254 struct decode_cache *c = &ctxt->decode;
2255 int rc;
2256
2257 c->dst.type = OP_REG;
2258 c->dst.addr.reg = &c->eip;
2259 c->dst.bytes = c->op_bytes;
2260 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2261 if (rc != X86EMUL_CONTINUE)
2262 return rc;
2263 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2264 return X86EMUL_CONTINUE;
2265 }
2266
2267 static int em_imul(struct x86_emulate_ctxt *ctxt)
2268 {
2269 struct decode_cache *c = &ctxt->decode;
2270
2271 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2272 return X86EMUL_CONTINUE;
2273 }
2274
2275 static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2276 {
2277 struct decode_cache *c = &ctxt->decode;
2278
2279 c->dst.val = c->src2.val;
2280 return em_imul(ctxt);
2281 }
2282
2283 static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2284 {
2285 unsigned cpl = ctxt->ops->cpl(ctxt->vcpu);
2286 struct decode_cache *c = &ctxt->decode;
2287 u64 tsc = 0;
2288
2289 if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD)) {
2290 emulate_gp(ctxt, 0);
2291 return X86EMUL_PROPAGATE_FAULT;
2292 }
2293 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2294 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2295 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2296 return X86EMUL_CONTINUE;
2297 }
2298
2299 #define D(_y) { .flags = (_y) }
2300 #define N D(0)
2301 #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2302 #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2303 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2304
2305 static struct opcode group1[] = {
2306 X7(D(Lock)), N
2307 };
2308
2309 static struct opcode group1A[] = {
2310 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2311 };
2312
2313 static struct opcode group3[] = {
2314 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2315 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2316 X4(D(SrcMem | ModRM)),
2317 };
2318
2319 static struct opcode group4[] = {
2320 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2321 N, N, N, N, N, N,
2322 };
2323
2324 static struct opcode group5[] = {
2325 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2326 D(SrcMem | ModRM | Stack),
2327 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
2328 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2329 D(SrcMem | ModRM | Stack), N,
2330 };
2331
2332 static struct group_dual group7 = { {
2333 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2334 D(SrcNone | ModRM | DstMem | Mov), N,
2335 D(SrcMem16 | ModRM | Mov | Priv),
2336 D(SrcMem | ModRM | ByteOp | Priv | NoAccess),
2337 }, {
2338 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
2339 D(SrcNone | ModRM | DstMem | Mov), N,
2340 D(SrcMem16 | ModRM | Mov | Priv), N,
2341 } };
2342
2343 static struct opcode group8[] = {
2344 N, N, N, N,
2345 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2346 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2347 };
2348
2349 static struct group_dual group9 = { {
2350 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2351 }, {
2352 N, N, N, N, N, N, N, N,
2353 } };
2354
2355 static struct opcode opcode_table[256] = {
2356 /* 0x00 - 0x07 */
2357 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2358 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2359 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2360 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2361 /* 0x08 - 0x0F */
2362 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2363 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2364 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2365 D(ImplicitOps | Stack | No64), N,
2366 /* 0x10 - 0x17 */
2367 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2368 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2369 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2370 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2371 /* 0x18 - 0x1F */
2372 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2373 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2374 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2375 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2376 /* 0x20 - 0x27 */
2377 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2378 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2379 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2380 /* 0x28 - 0x2F */
2381 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2382 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2383 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm),
2384 N, I(ByteOp | DstAcc | No64, em_das),
2385 /* 0x30 - 0x37 */
2386 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2387 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2388 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2389 /* 0x38 - 0x3F */
2390 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2391 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2392 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2393 N, N,
2394 /* 0x40 - 0x4F */
2395 X16(D(DstReg)),
2396 /* 0x50 - 0x57 */
2397 X8(I(SrcReg | Stack, em_push)),
2398 /* 0x58 - 0x5F */
2399 X8(D(DstReg | Stack)),
2400 /* 0x60 - 0x67 */
2401 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2402 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2403 N, N, N, N,
2404 /* 0x68 - 0x6F */
2405 I(SrcImm | Mov | Stack, em_push),
2406 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
2407 I(SrcImmByte | Mov | Stack, em_push),
2408 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2409 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
2410 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
2411 /* 0x70 - 0x7F */
2412 X16(D(SrcImmByte)),
2413 /* 0x80 - 0x87 */
2414 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2415 G(DstMem | SrcImm | ModRM | Group, group1),
2416 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2417 G(DstMem | SrcImmByte | ModRM | Group, group1),
2418 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2419 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2420 /* 0x88 - 0x8F */
2421 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
2422 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
2423 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
2424 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2425 /* 0x90 - 0x97 */
2426 X8(D(SrcAcc | DstReg)),
2427 /* 0x98 - 0x9F */
2428 D(DstAcc | SrcNone), N, D(SrcImmFAddr | No64), N,
2429 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2430 /* 0xA0 - 0xA7 */
2431 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
2432 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
2433 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
2434 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
2435 /* 0xA8 - 0xAF */
2436 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm),
2437 D(ByteOp | SrcAcc | DstDI | Mov | String), D(SrcAcc | DstDI | Mov | String),
2438 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
2439 D(ByteOp | SrcAcc | DstDI | String), D(SrcAcc | DstDI | String),
2440 /* 0xB0 - 0xB7 */
2441 X8(D(ByteOp | DstReg | SrcImm | Mov)),
2442 /* 0xB8 - 0xBF */
2443 X8(D(DstReg | SrcImm | Mov)),
2444 /* 0xC0 - 0xC7 */
2445 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
2446 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2447 D(ImplicitOps | Stack),
2448 N, N,
2449 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
2450 /* 0xC8 - 0xCF */
2451 N, N, N, D(ImplicitOps | Stack),
2452 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2453 /* 0xD0 - 0xD7 */
2454 D(ByteOp | DstMem | SrcOne | ModRM), D(DstMem | SrcOne | ModRM),
2455 D(ByteOp | DstMem | ModRM), D(DstMem | ModRM),
2456 N, N, N, N,
2457 /* 0xD8 - 0xDF */
2458 N, N, N, N, N, N, N, N,
2459 /* 0xE0 - 0xE7 */
2460 X3(D(SrcImmByte)), N,
2461 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
2462 D(ByteOp | SrcAcc | DstImmUByte), D(SrcAcc | DstImmUByte),
2463 /* 0xE8 - 0xEF */
2464 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2465 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
2466 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
2467 D(ByteOp | SrcAcc | ImplicitOps), D(SrcAcc | ImplicitOps),
2468 /* 0xF0 - 0xF7 */
2469 N, N, N, N,
2470 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2471 /* 0xF8 - 0xFF */
2472 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
2473 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2474 };
2475
2476 static struct opcode twobyte_table[256] = {
2477 /* 0x00 - 0x0F */
2478 N, GD(0, &group7), N, N,
2479 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
2480 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2481 N, D(ImplicitOps | ModRM), N, N,
2482 /* 0x10 - 0x1F */
2483 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2484 /* 0x20 - 0x2F */
2485 D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264),
2486 D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264),
2487 N, N, N, N,
2488 N, N, N, N, N, N, N, N,
2489 /* 0x30 - 0x3F */
2490 D(ImplicitOps | Priv), I(ImplicitOps, em_rdtsc),
2491 D(ImplicitOps | Priv), N,
2492 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
2493 N, N, N, N, N, N, N, N,
2494 /* 0x40 - 0x4F */
2495 X16(D(DstReg | SrcMem | ModRM | Mov)),
2496 /* 0x50 - 0x5F */
2497 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2498 /* 0x60 - 0x6F */
2499 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2500 /* 0x70 - 0x7F */
2501 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2502 /* 0x80 - 0x8F */
2503 X16(D(SrcImm)),
2504 /* 0x90 - 0x9F */
2505 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
2506 /* 0xA0 - 0xA7 */
2507 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2508 N, D(DstMem | SrcReg | ModRM | BitOp),
2509 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2510 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2511 /* 0xA8 - 0xAF */
2512 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2513 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2514 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2515 D(DstMem | SrcReg | Src2CL | ModRM),
2516 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
2517 /* 0xB0 - 0xB7 */
2518 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2519 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2520 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
2521 D(DstReg | SrcMem16 | ModRM | Mov),
2522 /* 0xB8 - 0xBF */
2523 N, N,
2524 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2525 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2526 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
2527 /* 0xC0 - 0xCF */
2528 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2529 N, D(DstMem | SrcReg | ModRM | Mov),
2530 N, N, N, GD(0, &group9),
2531 N, N, N, N, N, N, N, N,
2532 /* 0xD0 - 0xDF */
2533 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2534 /* 0xE0 - 0xEF */
2535 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2536 /* 0xF0 - 0xFF */
2537 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2538 };
2539
2540 #undef D
2541 #undef N
2542 #undef G
2543 #undef GD
2544 #undef I
2545
2546 static unsigned imm_size(struct decode_cache *c)
2547 {
2548 unsigned size;
2549
2550 size = (c->d & ByteOp) ? 1 : c->op_bytes;
2551 if (size == 8)
2552 size = 4;
2553 return size;
2554 }
2555
2556 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
2557 unsigned size, bool sign_extension)
2558 {
2559 struct decode_cache *c = &ctxt->decode;
2560 struct x86_emulate_ops *ops = ctxt->ops;
2561 int rc = X86EMUL_CONTINUE;
2562
2563 op->type = OP_IMM;
2564 op->bytes = size;
2565 op->addr.mem = c->eip;
2566 /* NB. Immediates are sign-extended as necessary. */
2567 switch (op->bytes) {
2568 case 1:
2569 op->val = insn_fetch(s8, 1, c->eip);
2570 break;
2571 case 2:
2572 op->val = insn_fetch(s16, 2, c->eip);
2573 break;
2574 case 4:
2575 op->val = insn_fetch(s32, 4, c->eip);
2576 break;
2577 }
2578 if (!sign_extension) {
2579 switch (op->bytes) {
2580 case 1:
2581 op->val &= 0xff;
2582 break;
2583 case 2:
2584 op->val &= 0xffff;
2585 break;
2586 case 4:
2587 op->val &= 0xffffffff;
2588 break;
2589 }
2590 }
2591 done:
2592 return rc;
2593 }
2594
2595 int
2596 x86_decode_insn(struct x86_emulate_ctxt *ctxt)
2597 {
2598 struct x86_emulate_ops *ops = ctxt->ops;
2599 struct decode_cache *c = &ctxt->decode;
2600 int rc = X86EMUL_CONTINUE;
2601 int mode = ctxt->mode;
2602 int def_op_bytes, def_ad_bytes, dual, goffset;
2603 struct opcode opcode, *g_mod012, *g_mod3;
2604 struct operand memop = { .type = OP_NONE };
2605
2606 /* we cannot decode insn before we complete previous rep insn */
2607 WARN_ON(ctxt->restart);
2608
2609 c->eip = ctxt->eip;
2610 c->fetch.start = c->fetch.end = c->eip;
2611 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2612
2613 switch (mode) {
2614 case X86EMUL_MODE_REAL:
2615 case X86EMUL_MODE_VM86:
2616 case X86EMUL_MODE_PROT16:
2617 def_op_bytes = def_ad_bytes = 2;
2618 break;
2619 case X86EMUL_MODE_PROT32:
2620 def_op_bytes = def_ad_bytes = 4;
2621 break;
2622 #ifdef CONFIG_X86_64
2623 case X86EMUL_MODE_PROT64:
2624 def_op_bytes = 4;
2625 def_ad_bytes = 8;
2626 break;
2627 #endif
2628 default:
2629 return -1;
2630 }
2631
2632 c->op_bytes = def_op_bytes;
2633 c->ad_bytes = def_ad_bytes;
2634
2635 /* Legacy prefixes. */
2636 for (;;) {
2637 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2638 case 0x66: /* operand-size override */
2639 /* switch between 2/4 bytes */
2640 c->op_bytes = def_op_bytes ^ 6;
2641 break;
2642 case 0x67: /* address-size override */
2643 if (mode == X86EMUL_MODE_PROT64)
2644 /* switch between 4/8 bytes */
2645 c->ad_bytes = def_ad_bytes ^ 12;
2646 else
2647 /* switch between 2/4 bytes */
2648 c->ad_bytes = def_ad_bytes ^ 6;
2649 break;
2650 case 0x26: /* ES override */
2651 case 0x2e: /* CS override */
2652 case 0x36: /* SS override */
2653 case 0x3e: /* DS override */
2654 set_seg_override(c, (c->b >> 3) & 3);
2655 break;
2656 case 0x64: /* FS override */
2657 case 0x65: /* GS override */
2658 set_seg_override(c, c->b & 7);
2659 break;
2660 case 0x40 ... 0x4f: /* REX */
2661 if (mode != X86EMUL_MODE_PROT64)
2662 goto done_prefixes;
2663 c->rex_prefix = c->b;
2664 continue;
2665 case 0xf0: /* LOCK */
2666 c->lock_prefix = 1;
2667 break;
2668 case 0xf2: /* REPNE/REPNZ */
2669 c->rep_prefix = REPNE_PREFIX;
2670 break;
2671 case 0xf3: /* REP/REPE/REPZ */
2672 c->rep_prefix = REPE_PREFIX;
2673 break;
2674 default:
2675 goto done_prefixes;
2676 }
2677
2678 /* Any legacy prefix after a REX prefix nullifies its effect. */
2679
2680 c->rex_prefix = 0;
2681 }
2682
2683 done_prefixes:
2684
2685 /* REX prefix. */
2686 if (c->rex_prefix & 8)
2687 c->op_bytes = 8; /* REX.W */
2688
2689 /* Opcode byte(s). */
2690 opcode = opcode_table[c->b];
2691 /* Two-byte opcode? */
2692 if (c->b == 0x0f) {
2693 c->twobyte = 1;
2694 c->b = insn_fetch(u8, 1, c->eip);
2695 opcode = twobyte_table[c->b];
2696 }
2697 c->d = opcode.flags;
2698
2699 if (c->d & Group) {
2700 dual = c->d & GroupDual;
2701 c->modrm = insn_fetch(u8, 1, c->eip);
2702 --c->eip;
2703
2704 if (c->d & GroupDual) {
2705 g_mod012 = opcode.u.gdual->mod012;
2706 g_mod3 = opcode.u.gdual->mod3;
2707 } else
2708 g_mod012 = g_mod3 = opcode.u.group;
2709
2710 c->d &= ~(Group | GroupDual);
2711
2712 goffset = (c->modrm >> 3) & 7;
2713
2714 if ((c->modrm >> 6) == 3)
2715 opcode = g_mod3[goffset];
2716 else
2717 opcode = g_mod012[goffset];
2718 c->d |= opcode.flags;
2719 }
2720
2721 c->execute = opcode.u.execute;
2722
2723 /* Unrecognised? */
2724 if (c->d == 0 || (c->d & Undefined)) {
2725 DPRINTF("Cannot emulate %02x\n", c->b);
2726 return -1;
2727 }
2728
2729 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2730 c->op_bytes = 8;
2731
2732 if (c->d & Op3264) {
2733 if (mode == X86EMUL_MODE_PROT64)
2734 c->op_bytes = 8;
2735 else
2736 c->op_bytes = 4;
2737 }
2738
2739 /* ModRM and SIB bytes. */
2740 if (c->d & ModRM) {
2741 rc = decode_modrm(ctxt, ops, &memop);
2742 if (!c->has_seg_override)
2743 set_seg_override(c, c->modrm_seg);
2744 } else if (c->d & MemAbs)
2745 rc = decode_abs(ctxt, ops, &memop);
2746 if (rc != X86EMUL_CONTINUE)
2747 goto done;
2748
2749 if (!c->has_seg_override)
2750 set_seg_override(c, VCPU_SREG_DS);
2751
2752 if (memop.type == OP_MEM && !(!c->twobyte && c->b == 0x8d))
2753 memop.addr.mem += seg_override_base(ctxt, ops, c);
2754
2755 if (memop.type == OP_MEM && c->ad_bytes != 8)
2756 memop.addr.mem = (u32)memop.addr.mem;
2757
2758 if (memop.type == OP_MEM && c->rip_relative)
2759 memop.addr.mem += c->eip;
2760
2761 /*
2762 * Decode and fetch the source operand: register, memory
2763 * or immediate.
2764 */
2765 switch (c->d & SrcMask) {
2766 case SrcNone:
2767 break;
2768 case SrcReg:
2769 decode_register_operand(&c->src, c, 0);
2770 break;
2771 case SrcMem16:
2772 memop.bytes = 2;
2773 goto srcmem_common;
2774 case SrcMem32:
2775 memop.bytes = 4;
2776 goto srcmem_common;
2777 case SrcMem:
2778 memop.bytes = (c->d & ByteOp) ? 1 :
2779 c->op_bytes;
2780 srcmem_common:
2781 c->src = memop;
2782 break;
2783 case SrcImmU16:
2784 rc = decode_imm(ctxt, &c->src, 2, false);
2785 break;
2786 case SrcImm:
2787 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
2788 break;
2789 case SrcImmU:
2790 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
2791 break;
2792 case SrcImmByte:
2793 rc = decode_imm(ctxt, &c->src, 1, true);
2794 break;
2795 case SrcImmUByte:
2796 rc = decode_imm(ctxt, &c->src, 1, false);
2797 break;
2798 case SrcAcc:
2799 c->src.type = OP_REG;
2800 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2801 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
2802 fetch_register_operand(&c->src);
2803 break;
2804 case SrcOne:
2805 c->src.bytes = 1;
2806 c->src.val = 1;
2807 break;
2808 case SrcSI:
2809 c->src.type = OP_MEM;
2810 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2811 c->src.addr.mem =
2812 register_address(c, seg_override_base(ctxt, ops, c),
2813 c->regs[VCPU_REGS_RSI]);
2814 c->src.val = 0;
2815 break;
2816 case SrcImmFAddr:
2817 c->src.type = OP_IMM;
2818 c->src.addr.mem = c->eip;
2819 c->src.bytes = c->op_bytes + 2;
2820 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2821 break;
2822 case SrcMemFAddr:
2823 memop.bytes = c->op_bytes + 2;
2824 goto srcmem_common;
2825 break;
2826 }
2827
2828 if (rc != X86EMUL_CONTINUE)
2829 goto done;
2830
2831 /*
2832 * Decode and fetch the second source operand: register, memory
2833 * or immediate.
2834 */
2835 switch (c->d & Src2Mask) {
2836 case Src2None:
2837 break;
2838 case Src2CL:
2839 c->src2.bytes = 1;
2840 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2841 break;
2842 case Src2ImmByte:
2843 rc = decode_imm(ctxt, &c->src2, 1, true);
2844 break;
2845 case Src2One:
2846 c->src2.bytes = 1;
2847 c->src2.val = 1;
2848 break;
2849 case Src2Imm:
2850 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
2851 break;
2852 }
2853
2854 if (rc != X86EMUL_CONTINUE)
2855 goto done;
2856
2857 /* Decode and fetch the destination operand: register or memory. */
2858 switch (c->d & DstMask) {
2859 case DstReg:
2860 decode_register_operand(&c->dst, c,
2861 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2862 break;
2863 case DstImmUByte:
2864 c->dst.type = OP_IMM;
2865 c->dst.addr.mem = c->eip;
2866 c->dst.bytes = 1;
2867 c->dst.val = insn_fetch(u8, 1, c->eip);
2868 break;
2869 case DstMem:
2870 case DstMem64:
2871 c->dst = memop;
2872 if ((c->d & DstMask) == DstMem64)
2873 c->dst.bytes = 8;
2874 else
2875 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2876 if (c->d & BitOp)
2877 fetch_bit_operand(c);
2878 c->dst.orig_val = c->dst.val;
2879 break;
2880 case DstAcc:
2881 c->dst.type = OP_REG;
2882 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2883 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
2884 fetch_register_operand(&c->dst);
2885 c->dst.orig_val = c->dst.val;
2886 break;
2887 case DstDI:
2888 c->dst.type = OP_MEM;
2889 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2890 c->dst.addr.mem =
2891 register_address(c, es_base(ctxt, ops),
2892 c->regs[VCPU_REGS_RDI]);
2893 c->dst.val = 0;
2894 break;
2895 case ImplicitOps:
2896 /* Special instructions do their own operand decoding. */
2897 default:
2898 c->dst.type = OP_NONE; /* Disable writeback. */
2899 return 0;
2900 }
2901
2902 done:
2903 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2904 }
2905
2906 int
2907 x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
2908 {
2909 struct x86_emulate_ops *ops = ctxt->ops;
2910 u64 msr_data;
2911 struct decode_cache *c = &ctxt->decode;
2912 int rc = X86EMUL_CONTINUE;
2913 int saved_dst_type = c->dst.type;
2914 int irq; /* Used for int 3, int, and into */
2915
2916 ctxt->decode.mem_read.pos = 0;
2917
2918 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
2919 emulate_ud(ctxt);
2920 goto done;
2921 }
2922
2923 /* LOCK prefix is allowed only with some instructions */
2924 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
2925 emulate_ud(ctxt);
2926 goto done;
2927 }
2928
2929 /* Privileged instruction can be executed only in CPL=0 */
2930 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
2931 emulate_gp(ctxt, 0);
2932 goto done;
2933 }
2934
2935 if (c->rep_prefix && (c->d & String)) {
2936 ctxt->restart = true;
2937 /* All REP prefixes have the same first termination condition */
2938 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
2939 ctxt->restart = false;
2940 ctxt->eip = c->eip;
2941 goto done;
2942 }
2943 }
2944
2945 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
2946 rc = read_emulated(ctxt, ops, c->src.addr.mem,
2947 c->src.valptr, c->src.bytes);
2948 if (rc != X86EMUL_CONTINUE)
2949 goto done;
2950 c->src.orig_val64 = c->src.val64;
2951 }
2952
2953 if (c->src2.type == OP_MEM) {
2954 rc = read_emulated(ctxt, ops, c->src2.addr.mem,
2955 &c->src2.val, c->src2.bytes);
2956 if (rc != X86EMUL_CONTINUE)
2957 goto done;
2958 }
2959
2960 if ((c->d & DstMask) == ImplicitOps)
2961 goto special_insn;
2962
2963
2964 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2965 /* optimisation - avoid slow emulated read if Mov */
2966 rc = read_emulated(ctxt, ops, c->dst.addr.mem,
2967 &c->dst.val, c->dst.bytes);
2968 if (rc != X86EMUL_CONTINUE)
2969 goto done;
2970 }
2971 c->dst.orig_val = c->dst.val;
2972
2973 special_insn:
2974
2975 if (c->execute) {
2976 rc = c->execute(ctxt);
2977 if (rc != X86EMUL_CONTINUE)
2978 goto done;
2979 goto writeback;
2980 }
2981
2982 if (c->twobyte)
2983 goto twobyte_insn;
2984
2985 switch (c->b) {
2986 case 0x00 ... 0x05:
2987 add: /* add */
2988 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2989 break;
2990 case 0x06: /* push es */
2991 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
2992 break;
2993 case 0x07: /* pop es */
2994 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
2995 if (rc != X86EMUL_CONTINUE)
2996 goto done;
2997 break;
2998 case 0x08 ... 0x0d:
2999 or: /* or */
3000 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
3001 break;
3002 case 0x0e: /* push cs */
3003 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
3004 break;
3005 case 0x10 ... 0x15:
3006 adc: /* adc */
3007 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
3008 break;
3009 case 0x16: /* push ss */
3010 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
3011 break;
3012 case 0x17: /* pop ss */
3013 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
3014 if (rc != X86EMUL_CONTINUE)
3015 goto done;
3016 break;
3017 case 0x18 ... 0x1d:
3018 sbb: /* sbb */
3019 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
3020 break;
3021 case 0x1e: /* push ds */
3022 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
3023 break;
3024 case 0x1f: /* pop ds */
3025 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
3026 if (rc != X86EMUL_CONTINUE)
3027 goto done;
3028 break;
3029 case 0x20 ... 0x25:
3030 and: /* and */
3031 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
3032 break;
3033 case 0x28 ... 0x2d:
3034 sub: /* sub */
3035 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
3036 break;
3037 case 0x30 ... 0x35:
3038 xor: /* xor */
3039 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
3040 break;
3041 case 0x38 ... 0x3d:
3042 cmp: /* cmp */
3043 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3044 break;
3045 case 0x40 ... 0x47: /* inc r16/r32 */
3046 emulate_1op("inc", c->dst, ctxt->eflags);
3047 break;
3048 case 0x48 ... 0x4f: /* dec r16/r32 */
3049 emulate_1op("dec", c->dst, ctxt->eflags);
3050 break;
3051 case 0x58 ... 0x5f: /* pop reg */
3052 pop_instruction:
3053 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
3054 if (rc != X86EMUL_CONTINUE)
3055 goto done;
3056 break;
3057 case 0x60: /* pusha */
3058 rc = emulate_pusha(ctxt, ops);
3059 if (rc != X86EMUL_CONTINUE)
3060 goto done;
3061 break;
3062 case 0x61: /* popa */
3063 rc = emulate_popa(ctxt, ops);
3064 if (rc != X86EMUL_CONTINUE)
3065 goto done;
3066 break;
3067 case 0x63: /* movsxd */
3068 if (ctxt->mode != X86EMUL_MODE_PROT64)
3069 goto cannot_emulate;
3070 c->dst.val = (s32) c->src.val;
3071 break;
3072 case 0x6c: /* insb */
3073 case 0x6d: /* insw/insd */
3074 c->src.val = c->regs[VCPU_REGS_RDX];
3075 goto do_io_in;
3076 case 0x6e: /* outsb */
3077 case 0x6f: /* outsw/outsd */
3078 c->dst.val = c->regs[VCPU_REGS_RDX];
3079 goto do_io_out;
3080 break;
3081 case 0x70 ... 0x7f: /* jcc (short) */
3082 if (test_cc(c->b, ctxt->eflags))
3083 jmp_rel(c, c->src.val);
3084 break;
3085 case 0x80 ... 0x83: /* Grp1 */
3086 switch (c->modrm_reg) {
3087 case 0:
3088 goto add;
3089 case 1:
3090 goto or;
3091 case 2:
3092 goto adc;
3093 case 3:
3094 goto sbb;
3095 case 4:
3096 goto and;
3097 case 5:
3098 goto sub;
3099 case 6:
3100 goto xor;
3101 case 7:
3102 goto cmp;
3103 }
3104 break;
3105 case 0x84 ... 0x85:
3106 test:
3107 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
3108 break;
3109 case 0x86 ... 0x87: /* xchg */
3110 xchg:
3111 /* Write back the register source. */
3112 c->src.val = c->dst.val;
3113 write_register_operand(&c->src);
3114 /*
3115 * Write back the memory destination with implicit LOCK
3116 * prefix.
3117 */
3118 c->dst.val = c->src.orig_val;
3119 c->lock_prefix = 1;
3120 break;
3121 case 0x88 ... 0x8b: /* mov */
3122 goto mov;
3123 case 0x8c: /* mov r/m, sreg */
3124 if (c->modrm_reg > VCPU_SREG_GS) {
3125 emulate_ud(ctxt);
3126 goto done;
3127 }
3128 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
3129 break;
3130 case 0x8d: /* lea r16/r32, m */
3131 c->dst.val = c->src.addr.mem;
3132 break;
3133 case 0x8e: { /* mov seg, r/m16 */
3134 uint16_t sel;
3135
3136 sel = c->src.val;
3137
3138 if (c->modrm_reg == VCPU_SREG_CS ||
3139 c->modrm_reg > VCPU_SREG_GS) {
3140 emulate_ud(ctxt);
3141 goto done;
3142 }
3143
3144 if (c->modrm_reg == VCPU_SREG_SS)
3145 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3146
3147 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
3148
3149 c->dst.type = OP_NONE; /* Disable writeback. */
3150 break;
3151 }
3152 case 0x8f: /* pop (sole member of Grp1a) */
3153 rc = emulate_grp1a(ctxt, ops);
3154 if (rc != X86EMUL_CONTINUE)
3155 goto done;
3156 break;
3157 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3158 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
3159 break;
3160 goto xchg;
3161 case 0x98: /* cbw/cwde/cdqe */
3162 switch (c->op_bytes) {
3163 case 2: c->dst.val = (s8)c->dst.val; break;
3164 case 4: c->dst.val = (s16)c->dst.val; break;
3165 case 8: c->dst.val = (s32)c->dst.val; break;
3166 }
3167 break;
3168 case 0x9c: /* pushf */
3169 c->src.val = (unsigned long) ctxt->eflags;
3170 emulate_push(ctxt, ops);
3171 break;
3172 case 0x9d: /* popf */
3173 c->dst.type = OP_REG;
3174 c->dst.addr.reg = &ctxt->eflags;
3175 c->dst.bytes = c->op_bytes;
3176 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
3177 if (rc != X86EMUL_CONTINUE)
3178 goto done;
3179 break;
3180 case 0xa0 ... 0xa3: /* mov */
3181 case 0xa4 ... 0xa5: /* movs */
3182 goto mov;
3183 case 0xa6 ... 0xa7: /* cmps */
3184 c->dst.type = OP_NONE; /* Disable writeback. */
3185 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.addr.mem, c->dst.addr.mem);
3186 goto cmp;
3187 case 0xa8 ... 0xa9: /* test ax, imm */
3188 goto test;
3189 case 0xaa ... 0xab: /* stos */
3190 case 0xac ... 0xad: /* lods */
3191 goto mov;
3192 case 0xae ... 0xaf: /* scas */
3193 goto cmp;
3194 case 0xb0 ... 0xbf: /* mov r, imm */
3195 goto mov;
3196 case 0xc0 ... 0xc1:
3197 emulate_grp2(ctxt);
3198 break;
3199 case 0xc3: /* ret */
3200 c->dst.type = OP_REG;
3201 c->dst.addr.reg = &c->eip;
3202 c->dst.bytes = c->op_bytes;
3203 goto pop_instruction;
3204 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
3205 mov:
3206 c->dst.val = c->src.val;
3207 break;
3208 case 0xcb: /* ret far */
3209 rc = emulate_ret_far(ctxt, ops);
3210 if (rc != X86EMUL_CONTINUE)
3211 goto done;
3212 break;
3213 case 0xcc: /* int3 */
3214 irq = 3;
3215 goto do_interrupt;
3216 case 0xcd: /* int n */
3217 irq = c->src.val;
3218 do_interrupt:
3219 rc = emulate_int(ctxt, ops, irq);
3220 if (rc != X86EMUL_CONTINUE)
3221 goto done;
3222 break;
3223 case 0xce: /* into */
3224 if (ctxt->eflags & EFLG_OF) {
3225 irq = 4;
3226 goto do_interrupt;
3227 }
3228 break;
3229 case 0xcf: /* iret */
3230 rc = emulate_iret(ctxt, ops);
3231
3232 if (rc != X86EMUL_CONTINUE)
3233 goto done;
3234 break;
3235 case 0xd0 ... 0xd1: /* Grp2 */
3236 emulate_grp2(ctxt);
3237 break;
3238 case 0xd2 ... 0xd3: /* Grp2 */
3239 c->src.val = c->regs[VCPU_REGS_RCX];
3240 emulate_grp2(ctxt);
3241 break;
3242 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3243 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3244 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3245 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3246 jmp_rel(c, c->src.val);
3247 break;
3248 case 0xe4: /* inb */
3249 case 0xe5: /* in */
3250 goto do_io_in;
3251 case 0xe6: /* outb */
3252 case 0xe7: /* out */
3253 goto do_io_out;
3254 case 0xe8: /* call (near) */ {
3255 long int rel = c->src.val;
3256 c->src.val = (unsigned long) c->eip;
3257 jmp_rel(c, rel);
3258 emulate_push(ctxt, ops);
3259 break;
3260 }
3261 case 0xe9: /* jmp rel */
3262 goto jmp;
3263 case 0xea: { /* jmp far */
3264 unsigned short sel;
3265 jump_far:
3266 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3267
3268 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
3269 goto done;
3270
3271 c->eip = 0;
3272 memcpy(&c->eip, c->src.valptr, c->op_bytes);
3273 break;
3274 }
3275 case 0xeb:
3276 jmp: /* jmp rel short */
3277 jmp_rel(c, c->src.val);
3278 c->dst.type = OP_NONE; /* Disable writeback. */
3279 break;
3280 case 0xec: /* in al,dx */
3281 case 0xed: /* in (e/r)ax,dx */
3282 c->src.val = c->regs[VCPU_REGS_RDX];
3283 do_io_in:
3284 c->dst.bytes = min(c->dst.bytes, 4u);
3285 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
3286 emulate_gp(ctxt, 0);
3287 goto done;
3288 }
3289 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3290 &c->dst.val))
3291 goto done; /* IO is needed */
3292 break;
3293 case 0xee: /* out dx,al */
3294 case 0xef: /* out dx,(e/r)ax */
3295 c->dst.val = c->regs[VCPU_REGS_RDX];
3296 do_io_out:
3297 c->src.bytes = min(c->src.bytes, 4u);
3298 if (!emulator_io_permited(ctxt, ops, c->dst.val,
3299 c->src.bytes)) {
3300 emulate_gp(ctxt, 0);
3301 goto done;
3302 }
3303 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3304 &c->src.val, 1, ctxt->vcpu);
3305 c->dst.type = OP_NONE; /* Disable writeback. */
3306 break;
3307 case 0xf4: /* hlt */
3308 ctxt->vcpu->arch.halt_request = 1;
3309 break;
3310 case 0xf5: /* cmc */
3311 /* complement carry flag from eflags reg */
3312 ctxt->eflags ^= EFLG_CF;
3313 break;
3314 case 0xf6 ... 0xf7: /* Grp3 */
3315 if (emulate_grp3(ctxt, ops) != X86EMUL_CONTINUE)
3316 goto cannot_emulate;
3317 break;
3318 case 0xf8: /* clc */
3319 ctxt->eflags &= ~EFLG_CF;
3320 break;
3321 case 0xf9: /* stc */
3322 ctxt->eflags |= EFLG_CF;
3323 break;
3324 case 0xfa: /* cli */
3325 if (emulator_bad_iopl(ctxt, ops)) {
3326 emulate_gp(ctxt, 0);
3327 goto done;
3328 } else
3329 ctxt->eflags &= ~X86_EFLAGS_IF;
3330 break;
3331 case 0xfb: /* sti */
3332 if (emulator_bad_iopl(ctxt, ops)) {
3333 emulate_gp(ctxt, 0);
3334 goto done;
3335 } else {
3336 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3337 ctxt->eflags |= X86_EFLAGS_IF;
3338 }
3339 break;
3340 case 0xfc: /* cld */
3341 ctxt->eflags &= ~EFLG_DF;
3342 break;
3343 case 0xfd: /* std */
3344 ctxt->eflags |= EFLG_DF;
3345 break;
3346 case 0xfe: /* Grp4 */
3347 grp45:
3348 rc = emulate_grp45(ctxt, ops);
3349 if (rc != X86EMUL_CONTINUE)
3350 goto done;
3351 break;
3352 case 0xff: /* Grp5 */
3353 if (c->modrm_reg == 5)
3354 goto jump_far;
3355 goto grp45;
3356 default:
3357 goto cannot_emulate;
3358 }
3359
3360 writeback:
3361 rc = writeback(ctxt, ops);
3362 if (rc != X86EMUL_CONTINUE)
3363 goto done;
3364
3365 /*
3366 * restore dst type in case the decoding will be reused
3367 * (happens for string instruction )
3368 */
3369 c->dst.type = saved_dst_type;
3370
3371 if ((c->d & SrcMask) == SrcSI)
3372 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3373 VCPU_REGS_RSI, &c->src);
3374
3375 if ((c->d & DstMask) == DstDI)
3376 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3377 &c->dst);
3378
3379 if (c->rep_prefix && (c->d & String)) {
3380 struct read_cache *rc = &ctxt->decode.io_read;
3381 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3382 /* The second termination condition only applies for REPE
3383 * and REPNE. Test if the repeat string operation prefix is
3384 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3385 * corresponding termination condition according to:
3386 * - if REPE/REPZ and ZF = 0 then done
3387 * - if REPNE/REPNZ and ZF = 1 then done
3388 */
3389 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3390 (c->b == 0xae) || (c->b == 0xaf))
3391 && (((c->rep_prefix == REPE_PREFIX) &&
3392 ((ctxt->eflags & EFLG_ZF) == 0))
3393 || ((c->rep_prefix == REPNE_PREFIX) &&
3394 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3395 ctxt->restart = false;
3396 /*
3397 * Re-enter guest when pio read ahead buffer is empty or,
3398 * if it is not used, after each 1024 iteration.
3399 */
3400 else if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3401 (rc->end != 0 && rc->end == rc->pos)) {
3402 ctxt->restart = false;
3403 c->eip = ctxt->eip;
3404 }
3405 }
3406 /*
3407 * reset read cache here in case string instruction is restared
3408 * without decoding
3409 */
3410 ctxt->decode.mem_read.end = 0;
3411 if (!ctxt->restart)
3412 ctxt->eip = c->eip;
3413
3414 done:
3415 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
3416
3417 twobyte_insn:
3418 switch (c->b) {
3419 case 0x01: /* lgdt, lidt, lmsw */
3420 switch (c->modrm_reg) {
3421 u16 size;
3422 unsigned long address;
3423
3424 case 0: /* vmcall */
3425 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3426 goto cannot_emulate;
3427
3428 rc = kvm_fix_hypercall(ctxt->vcpu);
3429 if (rc != X86EMUL_CONTINUE)
3430 goto done;
3431
3432 /* Let the processor re-execute the fixed hypercall */
3433 c->eip = ctxt->eip;
3434 /* Disable writeback. */
3435 c->dst.type = OP_NONE;
3436 break;
3437 case 2: /* lgdt */
3438 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
3439 &size, &address, c->op_bytes);
3440 if (rc != X86EMUL_CONTINUE)
3441 goto done;
3442 realmode_lgdt(ctxt->vcpu, size, address);
3443 /* Disable writeback. */
3444 c->dst.type = OP_NONE;
3445 break;
3446 case 3: /* lidt/vmmcall */
3447 if (c->modrm_mod == 3) {
3448 switch (c->modrm_rm) {
3449 case 1:
3450 rc = kvm_fix_hypercall(ctxt->vcpu);
3451 if (rc != X86EMUL_CONTINUE)
3452 goto done;
3453 break;
3454 default:
3455 goto cannot_emulate;
3456 }
3457 } else {
3458 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
3459 &size, &address,
3460 c->op_bytes);
3461 if (rc != X86EMUL_CONTINUE)
3462 goto done;
3463 realmode_lidt(ctxt->vcpu, size, address);
3464 }
3465 /* Disable writeback. */
3466 c->dst.type = OP_NONE;
3467 break;
3468 case 4: /* smsw */
3469 c->dst.bytes = 2;
3470 c->dst.val = ops->get_cr(0, ctxt->vcpu);
3471 break;
3472 case 6: /* lmsw */
3473 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
3474 (c->src.val & 0x0f), ctxt->vcpu);
3475 c->dst.type = OP_NONE;
3476 break;
3477 case 5: /* not defined */
3478 emulate_ud(ctxt);
3479 goto done;
3480 case 7: /* invlpg*/
3481 emulate_invlpg(ctxt->vcpu, c->src.addr.mem);
3482 /* Disable writeback. */
3483 c->dst.type = OP_NONE;
3484 break;
3485 default:
3486 goto cannot_emulate;
3487 }
3488 break;
3489 case 0x05: /* syscall */
3490 rc = emulate_syscall(ctxt, ops);
3491 if (rc != X86EMUL_CONTINUE)
3492 goto done;
3493 else
3494 goto writeback;
3495 break;
3496 case 0x06:
3497 emulate_clts(ctxt->vcpu);
3498 break;
3499 case 0x09: /* wbinvd */
3500 kvm_emulate_wbinvd(ctxt->vcpu);
3501 break;
3502 case 0x08: /* invd */
3503 case 0x0d: /* GrpP (prefetch) */
3504 case 0x18: /* Grp16 (prefetch/nop) */
3505 break;
3506 case 0x20: /* mov cr, reg */
3507 switch (c->modrm_reg) {
3508 case 1:
3509 case 5 ... 7:
3510 case 9 ... 15:
3511 emulate_ud(ctxt);
3512 goto done;
3513 }
3514 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
3515 break;
3516 case 0x21: /* mov from dr to reg */
3517 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3518 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3519 emulate_ud(ctxt);
3520 goto done;
3521 }
3522 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
3523 break;
3524 case 0x22: /* mov reg, cr */
3525 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
3526 emulate_gp(ctxt, 0);
3527 goto done;
3528 }
3529 c->dst.type = OP_NONE;
3530 break;
3531 case 0x23: /* mov from reg to dr */
3532 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3533 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3534 emulate_ud(ctxt);
3535 goto done;
3536 }
3537
3538 if (ops->set_dr(c->modrm_reg, c->src.val &
3539 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3540 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3541 /* #UD condition is already handled by the code above */
3542 emulate_gp(ctxt, 0);
3543 goto done;
3544 }
3545
3546 c->dst.type = OP_NONE; /* no writeback */
3547 break;
3548 case 0x30:
3549 /* wrmsr */
3550 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3551 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3552 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
3553 emulate_gp(ctxt, 0);
3554 goto done;
3555 }
3556 rc = X86EMUL_CONTINUE;
3557 break;
3558 case 0x32:
3559 /* rdmsr */
3560 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
3561 emulate_gp(ctxt, 0);
3562 goto done;
3563 } else {
3564 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3565 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3566 }
3567 rc = X86EMUL_CONTINUE;
3568 break;
3569 case 0x34: /* sysenter */
3570 rc = emulate_sysenter(ctxt, ops);
3571 if (rc != X86EMUL_CONTINUE)
3572 goto done;
3573 else
3574 goto writeback;
3575 break;
3576 case 0x35: /* sysexit */
3577 rc = emulate_sysexit(ctxt, ops);
3578 if (rc != X86EMUL_CONTINUE)
3579 goto done;
3580 else
3581 goto writeback;
3582 break;
3583 case 0x40 ... 0x4f: /* cmov */
3584 c->dst.val = c->dst.orig_val = c->src.val;
3585 if (!test_cc(c->b, ctxt->eflags))
3586 c->dst.type = OP_NONE; /* no writeback */
3587 break;
3588 case 0x80 ... 0x8f: /* jnz rel, etc*/
3589 if (test_cc(c->b, ctxt->eflags))
3590 jmp_rel(c, c->src.val);
3591 break;
3592 case 0x90 ... 0x9f: /* setcc r/m8 */
3593 c->dst.val = test_cc(c->b, ctxt->eflags);
3594 break;
3595 case 0xa0: /* push fs */
3596 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
3597 break;
3598 case 0xa1: /* pop fs */
3599 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
3600 if (rc != X86EMUL_CONTINUE)
3601 goto done;
3602 break;
3603 case 0xa3:
3604 bt: /* bt */
3605 c->dst.type = OP_NONE;
3606 /* only subword offset */
3607 c->src.val &= (c->dst.bytes << 3) - 1;
3608 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
3609 break;
3610 case 0xa4: /* shld imm8, r, r/m */
3611 case 0xa5: /* shld cl, r, r/m */
3612 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3613 break;
3614 case 0xa8: /* push gs */
3615 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
3616 break;
3617 case 0xa9: /* pop gs */
3618 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
3619 if (rc != X86EMUL_CONTINUE)
3620 goto done;
3621 break;
3622 case 0xab:
3623 bts: /* bts */
3624 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
3625 break;
3626 case 0xac: /* shrd imm8, r, r/m */
3627 case 0xad: /* shrd cl, r, r/m */
3628 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3629 break;
3630 case 0xae: /* clflush */
3631 break;
3632 case 0xb0 ... 0xb1: /* cmpxchg */
3633 /*
3634 * Save real source value, then compare EAX against
3635 * destination.
3636 */
3637 c->src.orig_val = c->src.val;
3638 c->src.val = c->regs[VCPU_REGS_RAX];
3639 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3640 if (ctxt->eflags & EFLG_ZF) {
3641 /* Success: write back to memory. */
3642 c->dst.val = c->src.orig_val;
3643 } else {
3644 /* Failure: write the value we saw to EAX. */
3645 c->dst.type = OP_REG;
3646 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
3647 }
3648 break;
3649 case 0xb3:
3650 btr: /* btr */
3651 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
3652 break;
3653 case 0xb6 ... 0xb7: /* movzx */
3654 c->dst.bytes = c->op_bytes;
3655 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3656 : (u16) c->src.val;
3657 break;
3658 case 0xba: /* Grp8 */
3659 switch (c->modrm_reg & 3) {
3660 case 0:
3661 goto bt;
3662 case 1:
3663 goto bts;
3664 case 2:
3665 goto btr;
3666 case 3:
3667 goto btc;
3668 }
3669 break;
3670 case 0xbb:
3671 btc: /* btc */
3672 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
3673 break;
3674 case 0xbc: { /* bsf */
3675 u8 zf;
3676 __asm__ ("bsf %2, %0; setz %1"
3677 : "=r"(c->dst.val), "=q"(zf)
3678 : "r"(c->src.val));
3679 ctxt->eflags &= ~X86_EFLAGS_ZF;
3680 if (zf) {
3681 ctxt->eflags |= X86_EFLAGS_ZF;
3682 c->dst.type = OP_NONE; /* Disable writeback. */
3683 }
3684 break;
3685 }
3686 case 0xbd: { /* bsr */
3687 u8 zf;
3688 __asm__ ("bsr %2, %0; setz %1"
3689 : "=r"(c->dst.val), "=q"(zf)
3690 : "r"(c->src.val));
3691 ctxt->eflags &= ~X86_EFLAGS_ZF;
3692 if (zf) {
3693 ctxt->eflags |= X86_EFLAGS_ZF;
3694 c->dst.type = OP_NONE; /* Disable writeback. */
3695 }
3696 break;
3697 }
3698 case 0xbe ... 0xbf: /* movsx */
3699 c->dst.bytes = c->op_bytes;
3700 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3701 (s16) c->src.val;
3702 break;
3703 case 0xc0 ... 0xc1: /* xadd */
3704 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3705 /* Write back the register source. */
3706 c->src.val = c->dst.orig_val;
3707 write_register_operand(&c->src);
3708 break;
3709 case 0xc3: /* movnti */
3710 c->dst.bytes = c->op_bytes;
3711 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3712 (u64) c->src.val;
3713 break;
3714 case 0xc7: /* Grp9 (cmpxchg8b) */
3715 rc = emulate_grp9(ctxt, ops);
3716 if (rc != X86EMUL_CONTINUE)
3717 goto done;
3718 break;
3719 default:
3720 goto cannot_emulate;
3721 }
3722 goto writeback;
3723
3724 cannot_emulate:
3725 DPRINTF("Cannot emulate %02x\n", c->b);
3726 return -1;
3727 }
Linux kernel - Deliverables
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