2 * 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2007 Intel Corporation
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * Yaozu (Eddie) Dong <Eddie.dong@intel.com>
29 #include <linux/bitops.h>
32 #include <linux/kvm_host.h>
34 static void pic_lock(struct kvm_pic
*s
)
40 static void pic_unlock(struct kvm_pic
*s
)
43 struct kvm
*kvm
= s
->kvm
;
44 unsigned acks
= s
->pending_acks
;
45 bool wakeup
= s
->wakeup_needed
;
46 struct kvm_vcpu
*vcpu
;
49 s
->wakeup_needed
= false;
51 spin_unlock(&s
->lock
);
54 kvm_notify_acked_irq(kvm
, SELECT_PIC(__ffs(acks
)),
60 vcpu
= s
->kvm
->bsp_vcpu
;
66 static void pic_clear_isr(struct kvm_kpic_state
*s
, int irq
)
68 s
->isr
&= ~(1 << irq
);
69 s
->isr_ack
|= (1 << irq
);
72 void kvm_pic_clear_isr_ack(struct kvm
*kvm
)
74 struct kvm_pic
*s
= pic_irqchip(kvm
);
76 s
->pics
[0].isr_ack
= 0xff;
77 s
->pics
[1].isr_ack
= 0xff;
82 * set irq level. If an edge is detected, then the IRR is set to 1
84 static inline int pic_set_irq1(struct kvm_kpic_state
*s
, int irq
, int level
)
88 if (s
->elcr
& mask
) /* level triggered */
90 ret
= !(s
->irr
& mask
);
97 else /* edge triggered */
99 if ((s
->last_irr
& mask
) == 0) {
100 ret
= !(s
->irr
& mask
);
105 s
->last_irr
&= ~mask
;
107 return (s
->imr
& mask
) ? -1 : ret
;
111 * return the highest priority found in mask (highest = smallest
112 * number). Return 8 if no irq
114 static inline int get_priority(struct kvm_kpic_state
*s
, int mask
)
120 while ((mask
& (1 << ((priority
+ s
->priority_add
) & 7))) == 0)
126 * return the pic wanted interrupt. return -1 if none
128 static int pic_get_irq(struct kvm_kpic_state
*s
)
130 int mask
, cur_priority
, priority
;
132 mask
= s
->irr
& ~s
->imr
;
133 priority
= get_priority(s
, mask
);
137 * compute current priority. If special fully nested mode on the
138 * master, the IRQ coming from the slave is not taken into account
139 * for the priority computation.
142 if (s
->special_fully_nested_mode
&& s
== &s
->pics_state
->pics
[0])
144 cur_priority
= get_priority(s
, mask
);
145 if (priority
< cur_priority
)
147 * higher priority found: an irq should be generated
149 return (priority
+ s
->priority_add
) & 7;
155 * raise irq to CPU if necessary. must be called every time the active
158 static void pic_update_irq(struct kvm_pic
*s
)
162 irq2
= pic_get_irq(&s
->pics
[1]);
165 * if irq request by slave pic, signal master PIC
167 pic_set_irq1(&s
->pics
[0], 2, 1);
168 pic_set_irq1(&s
->pics
[0], 2, 0);
170 irq
= pic_get_irq(&s
->pics
[0]);
172 s
->irq_request(s
->irq_request_opaque
, 1);
174 s
->irq_request(s
->irq_request_opaque
, 0);
177 void kvm_pic_update_irq(struct kvm_pic
*s
)
184 int kvm_pic_set_irq(void *opaque
, int irq
, int level
)
186 struct kvm_pic
*s
= opaque
;
190 if (irq
>= 0 && irq
< PIC_NUM_PINS
) {
191 ret
= pic_set_irq1(&s
->pics
[irq
>> 3], irq
& 7, level
);
200 * acknowledge interrupt 'irq'
202 static inline void pic_intack(struct kvm_kpic_state
*s
, int irq
)
206 if (s
->rotate_on_auto_eoi
)
207 s
->priority_add
= (irq
+ 1) & 7;
208 pic_clear_isr(s
, irq
);
211 * We don't clear a level sensitive interrupt here
213 if (!(s
->elcr
& (1 << irq
)))
214 s
->irr
&= ~(1 << irq
);
217 int kvm_pic_read_irq(struct kvm
*kvm
)
219 int irq
, irq2
, intno
;
220 struct kvm_pic
*s
= pic_irqchip(kvm
);
223 irq
= pic_get_irq(&s
->pics
[0]);
225 pic_intack(&s
->pics
[0], irq
);
227 irq2
= pic_get_irq(&s
->pics
[1]);
229 pic_intack(&s
->pics
[1], irq2
);
232 * spurious IRQ on slave controller
235 intno
= s
->pics
[1].irq_base
+ irq2
;
238 intno
= s
->pics
[0].irq_base
+ irq
;
241 * spurious IRQ on host controller
244 intno
= s
->pics
[0].irq_base
+ irq
;
248 kvm_notify_acked_irq(kvm
, SELECT_PIC(irq
), irq
);
253 void kvm_pic_reset(struct kvm_kpic_state
*s
)
256 struct kvm
*kvm
= s
->pics_state
->irq_request_opaque
;
257 struct kvm_vcpu
*vcpu0
= kvm
->bsp_vcpu
;
259 if (s
== &s
->pics_state
->pics
[0])
264 for (irq
= 0; irq
< PIC_NUM_PINS
/2; irq
++) {
265 if (vcpu0
&& kvm_apic_accept_pic_intr(vcpu0
))
266 if (s
->irr
& (1 << irq
) || s
->isr
& (1 << irq
)) {
268 s
->pics_state
->pending_acks
|= 1 << n
;
278 s
->read_reg_select
= 0;
283 s
->rotate_on_auto_eoi
= 0;
284 s
->special_fully_nested_mode
= 0;
288 static void pic_ioport_write(void *opaque
, u32 addr
, u32 val
)
290 struct kvm_kpic_state
*s
= opaque
;
291 int priority
, cmd
, irq
;
296 kvm_pic_reset(s
); /* init */
298 * deassert a pending interrupt
300 s
->pics_state
->irq_request(s
->pics_state
->
301 irq_request_opaque
, 0);
305 printk(KERN_ERR
"single mode not supported");
308 "level sensitive irq not supported");
309 } else if (val
& 0x08) {
313 s
->read_reg_select
= val
& 1;
315 s
->special_mask
= (val
>> 5) & 1;
321 s
->rotate_on_auto_eoi
= cmd
>> 2;
323 case 1: /* end of interrupt */
325 priority
= get_priority(s
, s
->isr
);
327 irq
= (priority
+ s
->priority_add
) & 7;
328 pic_clear_isr(s
, irq
);
330 s
->priority_add
= (irq
+ 1) & 7;
331 pic_update_irq(s
->pics_state
);
336 pic_clear_isr(s
, irq
);
337 pic_update_irq(s
->pics_state
);
340 s
->priority_add
= (val
+ 1) & 7;
341 pic_update_irq(s
->pics_state
);
345 s
->priority_add
= (irq
+ 1) & 7;
346 pic_clear_isr(s
, irq
);
347 pic_update_irq(s
->pics_state
);
350 break; /* no operation */
354 switch (s
->init_state
) {
355 case 0: /* normal mode */
357 pic_update_irq(s
->pics_state
);
360 s
->irq_base
= val
& 0xf8;
370 s
->special_fully_nested_mode
= (val
>> 4) & 1;
371 s
->auto_eoi
= (val
>> 1) & 1;
377 static u32
pic_poll_read(struct kvm_kpic_state
*s
, u32 addr1
)
381 ret
= pic_get_irq(s
);
384 s
->pics_state
->pics
[0].isr
&= ~(1 << 2);
385 s
->pics_state
->pics
[0].irr
&= ~(1 << 2);
387 s
->irr
&= ~(1 << ret
);
388 pic_clear_isr(s
, ret
);
389 if (addr1
>> 7 || ret
!= 2)
390 pic_update_irq(s
->pics_state
);
393 pic_update_irq(s
->pics_state
);
399 static u32
pic_ioport_read(void *opaque
, u32 addr1
)
401 struct kvm_kpic_state
*s
= opaque
;
408 ret
= pic_poll_read(s
, addr1
);
412 if (s
->read_reg_select
)
421 static void elcr_ioport_write(void *opaque
, u32 addr
, u32 val
)
423 struct kvm_kpic_state
*s
= opaque
;
424 s
->elcr
= val
& s
->elcr_mask
;
427 static u32
elcr_ioport_read(void *opaque
, u32 addr1
)
429 struct kvm_kpic_state
*s
= opaque
;
433 static int picdev_in_range(gpa_t addr
)
448 static inline struct kvm_pic
*to_pic(struct kvm_io_device
*dev
)
450 return container_of(dev
, struct kvm_pic
, dev
);
453 static int picdev_write(struct kvm_io_device
*this,
454 gpa_t addr
, int len
, const void *val
)
456 struct kvm_pic
*s
= to_pic(this);
457 unsigned char data
= *(unsigned char *)val
;
458 if (!picdev_in_range(addr
))
462 if (printk_ratelimit())
463 printk(KERN_ERR
"PIC: non byte write\n");
472 pic_ioport_write(&s
->pics
[addr
>> 7], addr
, data
);
476 elcr_ioport_write(&s
->pics
[addr
& 1], addr
, data
);
483 static int picdev_read(struct kvm_io_device
*this,
484 gpa_t addr
, int len
, void *val
)
486 struct kvm_pic
*s
= to_pic(this);
487 unsigned char data
= 0;
488 if (!picdev_in_range(addr
))
492 if (printk_ratelimit())
493 printk(KERN_ERR
"PIC: non byte read\n");
502 data
= pic_ioport_read(&s
->pics
[addr
>> 7], addr
);
506 data
= elcr_ioport_read(&s
->pics
[addr
& 1], addr
);
509 *(unsigned char *)val
= data
;
515 * callback when PIC0 irq status changed
517 static void pic_irq_request(void *opaque
, int level
)
519 struct kvm
*kvm
= opaque
;
520 struct kvm_vcpu
*vcpu
= kvm
->bsp_vcpu
;
521 struct kvm_pic
*s
= pic_irqchip(kvm
);
522 int irq
= pic_get_irq(&s
->pics
[0]);
525 if (vcpu
&& level
&& (s
->pics
[0].isr_ack
& (1 << irq
))) {
526 s
->pics
[0].isr_ack
&= ~(1 << irq
);
527 s
->wakeup_needed
= true;
531 static const struct kvm_io_device_ops picdev_ops
= {
533 .write
= picdev_write
,
536 struct kvm_pic
*kvm_create_pic(struct kvm
*kvm
)
539 s
= kzalloc(sizeof(struct kvm_pic
), GFP_KERNEL
);
542 spin_lock_init(&s
->lock
);
544 s
->pics
[0].elcr_mask
= 0xf8;
545 s
->pics
[1].elcr_mask
= 0xde;
546 s
->irq_request
= pic_irq_request
;
547 s
->irq_request_opaque
= kvm
;
548 s
->pics
[0].pics_state
= s
;
549 s
->pics
[1].pics_state
= s
;
552 * Initialize PIO device
554 kvm_iodevice_init(&s
->dev
, &picdev_ops
);
555 kvm_io_bus_register_dev(kvm
, &kvm
->pio_bus
, &s
->dev
);