arch/x86/kvm/i8259.c

   1 /*
   2  * 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2007 Intel Corporation
   6  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  * Authors:
  26  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
  27  *   Port from Qemu.
  28  */
  29 #include <linux/mm.h>
  30 #include <linux/slab.h>
  31 #include <linux/bitops.h>
  32 #include "irq.h"
  33
  34 #include <linux/kvm_host.h>
  35 #include "trace.h"
  36
  37 #define pr_pic_unimpl(fmt, ...) \
  38         pr_err_ratelimited("kvm: pic: " fmt, ## __VA_ARGS__)
  39
  40 static void pic_irq_request(struct kvm *kvm, int level);
  41
  42 static void pic_lock(struct kvm_pic *s)
  43         __acquires(&s->lock)
  44 {
  45         spin_lock(&s->lock);
  46 }
  47
  48 static void pic_unlock(struct kvm_pic *s)
  49         __releases(&s->lock)
  50 {
  51         bool wakeup = s->wakeup_needed;
  52         struct kvm_vcpu *vcpu, *found = NULL;
  53         int i;
  54
  55         s->wakeup_needed = false;
  56
  57         spin_unlock(&s->lock);
  58
  59         if (wakeup) {
  60                 kvm_for_each_vcpu(i, vcpu, s->kvm) {
  61                         if (kvm_apic_accept_pic_intr(vcpu)) {
  62                                 found = vcpu;
  63                                 break;
  64                         }
  65                 }
  66
  67                 if (!found)
  68                         return;
  69
  70                 kvm_make_request(KVM_REQ_EVENT, found);
  71                 kvm_vcpu_kick(found);
  72         }
  73 }
  74
  75 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
  76 {
  77         s->isr &= ~(1 << irq);
  78         if (s != &s->pics_state->pics[0])
  79                 irq += 8;
  80         /*
  81          * We are dropping lock while calling ack notifiers since ack
  82          * notifier callbacks for assigned devices call into PIC recursively.
  83          * Other interrupt may be delivered to PIC while lock is dropped but
  84          * it should be safe since PIC state is already updated at this stage.
  85          */
  86         pic_unlock(s->pics_state);
  87         kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
  88         pic_lock(s->pics_state);
  89 }
  90
  91 /*
  92  * set irq level. If an edge is detected, then the IRR is set to 1
  93  */
  94 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
  95 {
  96         int mask, ret = 1;
  97         mask = 1 << irq;
  98         if (s->elcr & mask)     /* level triggered */
  99                 if (level) {
 100                         ret = !(s->irr & mask);
 101                         s->irr |= mask;
 102                         s->last_irr |= mask;
 103                 } else {
 104                         s->irr &= ~mask;
 105                         s->last_irr &= ~mask;
 106                 }
 107         else    /* edge triggered */
 108                 if (level) {
 109                         if ((s->last_irr & mask) == 0) {
 110                                 ret = !(s->irr & mask);
 111                                 s->irr |= mask;
 112                         }
 113                         s->last_irr |= mask;
 114                 } else
 115                         s->last_irr &= ~mask;
 116
 117         return (s->imr & mask) ? -1 : ret;
 118 }
 119
 120 /*
 121  * return the highest priority found in mask (highest = smallest
 122  * number). Return 8 if no irq
 123  */
 124 static inline int get_priority(struct kvm_kpic_state *s, int mask)
 125 {
 126         int priority;
 127         if (mask == 0)
 128                 return 8;
 129         priority = 0;
 130         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 131                 priority++;
 132         return priority;
 133 }
 134
 135 /*
 136  * return the pic wanted interrupt. return -1 if none
 137  */
 138 static int pic_get_irq(struct kvm_kpic_state *s)
 139 {
 140         int mask, cur_priority, priority;
 141
 142         mask = s->irr & ~s->imr;
 143         priority = get_priority(s, mask);
 144         if (priority == 8)
 145                 return -1;
 146         /*
 147          * compute current priority. If special fully nested mode on the
 148          * master, the IRQ coming from the slave is not taken into account
 149          * for the priority computation.
 150          */
 151         mask = s->isr;
 152         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 153                 mask &= ~(1 << 2);
 154         cur_priority = get_priority(s, mask);
 155         if (priority < cur_priority)
 156                 /*
 157                  * higher priority found: an irq should be generated
 158                  */
 159                 return (priority + s->priority_add) & 7;
 160         else
 161                 return -1;
 162 }
 163
 164 /*
 165  * raise irq to CPU if necessary. must be called every time the active
 166  * irq may change
 167  */
 168 static void pic_update_irq(struct kvm_pic *s)
 169 {
 170         int irq2, irq;
 171
 172         irq2 = pic_get_irq(&s->pics[1]);
 173         if (irq2 >= 0) {
 174                 /*
 175                  * if irq request by slave pic, signal master PIC
 176                  */
 177                 pic_set_irq1(&s->pics[0], 2, 1);
 178                 pic_set_irq1(&s->pics[0], 2, 0);
 179         }
 180         irq = pic_get_irq(&s->pics[0]);
 181         pic_irq_request(s->kvm, irq >= 0);
 182 }
 183
 184 void kvm_pic_update_irq(struct kvm_pic *s)
 185 {
 186         pic_lock(s);
 187         pic_update_irq(s);
 188         pic_unlock(s);
 189 }
 190
 191 int kvm_pic_set_irq(struct kvm_pic *s, int irq, int irq_source_id, int level)
 192 {
 193         int ret = -1;
 194
 195         pic_lock(s);
 196         if (irq >= 0 && irq < PIC_NUM_PINS) {
 197                 int irq_level = __kvm_irq_line_state(&s->irq_states[irq],
 198                                                      irq_source_id, level);
 199                 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, irq_level);
 200                 pic_update_irq(s);
 201                 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
 202                                       s->pics[irq >> 3].imr, ret == 0);
 203         }
 204         pic_unlock(s);
 205
 206         return ret;
 207 }
 208
 209 void kvm_pic_clear_all(struct kvm_pic *s, int irq_source_id)
 210 {
 211         int i;
 212
 213         pic_lock(s);
 214         for (i = 0; i < PIC_NUM_PINS; i++)
 215                 __clear_bit(irq_source_id, &s->irq_states[i]);
 216         pic_unlock(s);
 217 }
 218
 219 /*
 220  * acknowledge interrupt 'irq'
 221  */
 222 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
 223 {
 224         s->isr |= 1 << irq;
 225         /*
 226          * We don't clear a level sensitive interrupt here
 227          */
 228         if (!(s->elcr & (1 << irq)))
 229                 s->irr &= ~(1 << irq);
 230
 231         if (s->auto_eoi) {
 232                 if (s->rotate_on_auto_eoi)
 233                         s->priority_add = (irq + 1) & 7;
 234                 pic_clear_isr(s, irq);
 235         }
 236
 237 }
 238
 239 int kvm_pic_read_irq(struct kvm *kvm)
 240 {
 241         int irq, irq2, intno;
 242         struct kvm_pic *s = pic_irqchip(kvm);
 243
 244         pic_lock(s);
 245         irq = pic_get_irq(&s->pics[0]);
 246         if (irq >= 0) {
 247                 pic_intack(&s->pics[0], irq);
 248                 if (irq == 2) {
 249                         irq2 = pic_get_irq(&s->pics[1]);
 250                         if (irq2 >= 0)
 251                                 pic_intack(&s->pics[1], irq2);
 252                         else
 253                                 /*
 254                                  * spurious IRQ on slave controller
 255                                  */
 256                                 irq2 = 7;
 257                         intno = s->pics[1].irq_base + irq2;
 258                         irq = irq2 + 8;
 259                 } else
 260                         intno = s->pics[0].irq_base + irq;
 261         } else {
 262                 /*
 263                  * spurious IRQ on host controller
 264                  */
 265                 irq = 7;
 266                 intno = s->pics[0].irq_base + irq;
 267         }
 268         pic_update_irq(s);
 269         pic_unlock(s);
 270
 271         return intno;
 272 }
 273
 274 void kvm_pic_reset(struct kvm_kpic_state *s)
 275 {
 276         int irq, i;
 277         struct kvm_vcpu *vcpu;
 278         u8 irr = s->irr, isr = s->imr;
 279         bool found = false;
 280
 281         s->last_irr = 0;
 282         s->irr = 0;
 283         s->imr = 0;
 284         s->isr = 0;
 285         s->priority_add = 0;
 286         s->irq_base = 0;
 287         s->read_reg_select = 0;
 288         s->poll = 0;
 289         s->special_mask = 0;
 290         s->init_state = 0;
 291         s->auto_eoi = 0;
 292         s->rotate_on_auto_eoi = 0;
 293         s->special_fully_nested_mode = 0;
 294         s->init4 = 0;
 295
 296         kvm_for_each_vcpu(i, vcpu, s->pics_state->kvm)
 297                 if (kvm_apic_accept_pic_intr(vcpu)) {
 298                         found = true;
 299                         break;
 300                 }
 301
 302
 303         if (!found)
 304                 return;
 305
 306         for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
 307                 if (irr & (1 << irq) || isr & (1 << irq))
 308                         pic_clear_isr(s, irq);
 309 }
 310
 311 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
 312 {
 313         struct kvm_kpic_state *s = opaque;
 314         int priority, cmd, irq;
 315
 316         addr &= 1;
 317         if (addr == 0) {
 318                 if (val & 0x10) {
 319                         s->init4 = val & 1;
 320                         s->last_irr = 0;
 321                         s->irr &= s->elcr;
 322                         s->imr = 0;
 323                         s->priority_add = 0;
 324                         s->special_mask = 0;
 325                         s->read_reg_select = 0;
 326                         if (!s->init4) {
 327                                 s->special_fully_nested_mode = 0;
 328                                 s->auto_eoi = 0;
 329                         }
 330                         s->init_state = 1;
 331                         if (val & 0x02)
 332                                 pr_pic_unimpl("single mode not supported");
 333                         if (val & 0x08)
 334                                 pr_pic_unimpl(
 335                                         "level sensitive irq not supported");
 336                 } else if (val & 0x08) {
 337                         if (val & 0x04)
 338                                 s->poll = 1;
 339                         if (val & 0x02)
 340                                 s->read_reg_select = val & 1;
 341                         if (val & 0x40)
 342                                 s->special_mask = (val >> 5) & 1;
 343                 } else {
 344                         cmd = val >> 5;
 345                         switch (cmd) {
 346                         case 0:
 347                         case 4:
 348                                 s->rotate_on_auto_eoi = cmd >> 2;
 349                                 break;
 350                         case 1: /* end of interrupt */
 351                         case 5:
 352                                 priority = get_priority(s, s->isr);
 353                                 if (priority != 8) {
 354                                         irq = (priority + s->priority_add) & 7;
 355                                         if (cmd == 5)
 356                                                 s->priority_add = (irq + 1) & 7;
 357                                         pic_clear_isr(s, irq);
 358                                         pic_update_irq(s->pics_state);
 359                                 }
 360                                 break;
 361                         case 3:
 362                                 irq = val & 7;
 363                                 pic_clear_isr(s, irq);
 364                                 pic_update_irq(s->pics_state);
 365                                 break;
 366                         case 6:
 367                                 s->priority_add = (val + 1) & 7;
 368                                 pic_update_irq(s->pics_state);
 369                                 break;
 370                         case 7:
 371                                 irq = val & 7;
 372                                 s->priority_add = (irq + 1) & 7;
 373                                 pic_clear_isr(s, irq);
 374                                 pic_update_irq(s->pics_state);
 375                                 break;
 376                         default:
 377                                 break;  /* no operation */
 378                         }
 379                 }
 380         } else
 381                 switch (s->init_state) {
 382                 case 0: { /* normal mode */
 383                         u8 imr_diff = s->imr ^ val,
 384                                 off = (s == &s->pics_state->pics[0]) ? 0 : 8;
 385                         s->imr = val;
 386                         for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
 387                                 if (imr_diff & (1 << irq))
 388                                         kvm_fire_mask_notifiers(
 389                                                 s->pics_state->kvm,
 390                                                 SELECT_PIC(irq + off),
 391                                                 irq + off,
 392                                                 !!(s->imr & (1 << irq)));
 393                         pic_update_irq(s->pics_state);
 394                         break;
 395                 }
 396                 case 1:
 397                         s->irq_base = val & 0xf8;
 398                         s->init_state = 2;
 399                         break;
 400                 case 2:
 401                         if (s->init4)
 402                                 s->init_state = 3;
 403                         else
 404                                 s->init_state = 0;
 405                         break;
 406                 case 3:
 407                         s->special_fully_nested_mode = (val >> 4) & 1;
 408                         s->auto_eoi = (val >> 1) & 1;
 409                         s->init_state = 0;
 410                         break;
 411                 }
 412 }
 413
 414 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
 415 {
 416         int ret;
 417
 418         ret = pic_get_irq(s);
 419         if (ret >= 0) {
 420                 if (addr1 >> 7) {
 421                         s->pics_state->pics[0].isr &= ~(1 << 2);
 422                         s->pics_state->pics[0].irr &= ~(1 << 2);
 423                 }
 424                 s->irr &= ~(1 << ret);
 425                 pic_clear_isr(s, ret);
 426                 if (addr1 >> 7 || ret != 2)
 427                         pic_update_irq(s->pics_state);
 428         } else {
 429                 ret = 0x07;
 430                 pic_update_irq(s->pics_state);
 431         }
 432
 433         return ret;
 434 }
 435
 436 static u32 pic_ioport_read(void *opaque, u32 addr1)
 437 {
 438         struct kvm_kpic_state *s = opaque;
 439         unsigned int addr;
 440         int ret;
 441
 442         addr = addr1;
 443         addr &= 1;
 444         if (s->poll) {
 445                 ret = pic_poll_read(s, addr1);
 446                 s->poll = 0;
 447         } else
 448                 if (addr == 0)
 449                         if (s->read_reg_select)
 450                                 ret = s->isr;
 451                         else
 452                                 ret = s->irr;
 453                 else
 454                         ret = s->imr;
 455         return ret;
 456 }
 457
 458 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
 459 {
 460         struct kvm_kpic_state *s = opaque;
 461         s->elcr = val & s->elcr_mask;
 462 }
 463
 464 static u32 elcr_ioport_read(void *opaque, u32 addr1)
 465 {
 466         struct kvm_kpic_state *s = opaque;
 467         return s->elcr;
 468 }
 469
 470 static int picdev_in_range(gpa_t addr)
 471 {
 472         switch (addr) {
 473         case 0x20:
 474         case 0x21:
 475         case 0xa0:
 476         case 0xa1:
 477         case 0x4d0:
 478         case 0x4d1:
 479                 return 1;
 480         default:
 481                 return 0;
 482         }
 483 }
 484
 485 static int picdev_write(struct kvm_pic *s,
 486                          gpa_t addr, int len, const void *val)
 487 {
 488         unsigned char data = *(unsigned char *)val;
 489         if (!picdev_in_range(addr))
 490                 return -EOPNOTSUPP;
 491
 492         if (len != 1) {
 493                 pr_pic_unimpl("non byte write\n");
 494                 return 0;
 495         }
 496         pic_lock(s);
 497         switch (addr) {
 498         case 0x20:
 499         case 0x21:
 500         case 0xa0:
 501         case 0xa1:
 502                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
 503                 break;
 504         case 0x4d0:
 505         case 0x4d1:
 506                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
 507                 break;
 508         }
 509         pic_unlock(s);
 510         return 0;
 511 }
 512
 513 static int picdev_read(struct kvm_pic *s,
 514                        gpa_t addr, int len, void *val)
 515 {
 516         unsigned char data = 0;
 517         if (!picdev_in_range(addr))
 518                 return -EOPNOTSUPP;
 519
 520         if (len != 1) {
 521                 pr_pic_unimpl("non byte read\n");
 522                 return 0;
 523         }
 524         pic_lock(s);
 525         switch (addr) {
 526         case 0x20:
 527         case 0x21:
 528         case 0xa0:
 529         case 0xa1:
 530                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
 531                 break;
 532         case 0x4d0:
 533         case 0x4d1:
 534                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
 535                 break;
 536         }
 537         *(unsigned char *)val = data;
 538         pic_unlock(s);
 539         return 0;
 540 }
 541
 542 static int picdev_master_write(struct kvm_io_device *dev,
 543                                gpa_t addr, int len, const void *val)
 544 {
 545         return picdev_write(container_of(dev, struct kvm_pic, dev_master),
 546                             addr, len, val);
 547 }
 548
 549 static int picdev_master_read(struct kvm_io_device *dev,
 550                               gpa_t addr, int len, void *val)
 551 {
 552         return picdev_read(container_of(dev, struct kvm_pic, dev_master),
 553                             addr, len, val);
 554 }
 555
 556 static int picdev_slave_write(struct kvm_io_device *dev,
 557                               gpa_t addr, int len, const void *val)
 558 {
 559         return picdev_write(container_of(dev, struct kvm_pic, dev_slave),
 560                             addr, len, val);
 561 }
 562
 563 static int picdev_slave_read(struct kvm_io_device *dev,
 564                              gpa_t addr, int len, void *val)
 565 {
 566         return picdev_read(container_of(dev, struct kvm_pic, dev_slave),
 567                             addr, len, val);
 568 }
 569
 570 static int picdev_eclr_write(struct kvm_io_device *dev,
 571                              gpa_t addr, int len, const void *val)
 572 {
 573         return picdev_write(container_of(dev, struct kvm_pic, dev_eclr),
 574                             addr, len, val);
 575 }
 576
 577 static int picdev_eclr_read(struct kvm_io_device *dev,
 578                             gpa_t addr, int len, void *val)
 579 {
 580         return picdev_read(container_of(dev, struct kvm_pic, dev_eclr),
 581                             addr, len, val);
 582 }
 583
 584 /*
 585  * callback when PIC0 irq status changed
 586  */
 587 static void pic_irq_request(struct kvm *kvm, int level)
 588 {
 589         struct kvm_pic *s = pic_irqchip(kvm);
 590
 591         if (!s->output)
 592                 s->wakeup_needed = true;
 593         s->output = level;
 594 }
 595
 596 static const struct kvm_io_device_ops picdev_master_ops = {
 597         .read     = picdev_master_read,
 598         .write    = picdev_master_write,
 599 };
 600
 601 static const struct kvm_io_device_ops picdev_slave_ops = {
 602         .read     = picdev_slave_read,
 603         .write    = picdev_slave_write,
 604 };
 605
 606 static const struct kvm_io_device_ops picdev_eclr_ops = {
 607         .read     = picdev_eclr_read,
 608         .write    = picdev_eclr_write,
 609 };
 610
 611 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
 612 {
 613         struct kvm_pic *s;
 614         int ret;
 615
 616         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
 617         if (!s)
 618                 return NULL;
 619         spin_lock_init(&s->lock);
 620         s->kvm = kvm;
 621         s->pics[0].elcr_mask = 0xf8;
 622         s->pics[1].elcr_mask = 0xde;
 623         s->pics[0].pics_state = s;
 624         s->pics[1].pics_state = s;
 625
 626         /*
 627          * Initialize PIO device
 628          */
 629         kvm_iodevice_init(&s->dev_master, &picdev_master_ops);
 630         kvm_iodevice_init(&s->dev_slave, &picdev_slave_ops);
 631         kvm_iodevice_init(&s->dev_eclr, &picdev_eclr_ops);
 632         mutex_lock(&kvm->slots_lock);
 633         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x20, 2,
 634                                       &s->dev_master);
 635         if (ret < 0)
 636                 goto fail_unlock;
 637
 638         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0xa0, 2, &s->dev_slave);
 639         if (ret < 0)
 640                 goto fail_unreg_2;
 641
 642         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x4d0, 2, &s->dev_eclr);
 643         if (ret < 0)
 644                 goto fail_unreg_1;
 645
 646         mutex_unlock(&kvm->slots_lock);
 647
 648         return s;
 649
 650 fail_unreg_1:
 651         kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_slave);
 652
 653 fail_unreg_2:
 654         kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_master);
 655
 656 fail_unlock:
 657         mutex_unlock(&kvm->slots_lock);
 658
 659         kfree(s);
 660
 661         return NULL;
 662 }
 663
 664 void kvm_destroy_pic(struct kvm *kvm)
 665 {
 666         struct kvm_pic *vpic = kvm->arch.vpic;
 667
 668         if (vpic) {
 669                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_master);
 670                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_slave);
 671                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_eclr);
 672                 kvm->arch.vpic = NULL;
 673                 kfree(vpic);
 674         }
 675 }