arch/x86/kvm/i8259.c

   1 /*
   2  * 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2007 Intel Corporation
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  * Authors:
  25  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
  26  *   Port from Qemu.
  27  */
  28 #include <linux/mm.h>
  29 #include <linux/bitops.h>
  30 #include "irq.h"
  31
  32 #include <linux/kvm_host.h>
  33
  34 static void pic_lock(struct kvm_pic *s)
  35 {
  36         spin_lock(&s->lock);
  37 }
  38
  39 static void pic_unlock(struct kvm_pic *s)
  40 {
  41         struct kvm *kvm = s->kvm;
  42         unsigned acks = s->pending_acks;
  43         bool wakeup = s->wakeup_needed;
  44         struct kvm_vcpu *vcpu;
  45
  46         s->pending_acks = 0;
  47         s->wakeup_needed = false;
  48
  49         spin_unlock(&s->lock);
  50
  51         while (acks) {
  52                 kvm_notify_acked_irq(kvm, SELECT_PIC(__ffs(acks)),
  53                                      __ffs(acks));
  54                 acks &= acks - 1;
  55         }
  56
  57         if (wakeup) {
  58                 vcpu = s->kvm->vcpus[0];
  59                 if (vcpu)
  60                         kvm_vcpu_kick(vcpu);
  61         }
  62 }
  63
  64 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
  65 {
  66         s->isr &= ~(1 << irq);
  67         s->isr_ack |= (1 << irq);
  68 }
  69
  70 void kvm_pic_clear_isr_ack(struct kvm *kvm)
  71 {
  72         struct kvm_pic *s = pic_irqchip(kvm);
  73         s->pics[0].isr_ack = 0xff;
  74         s->pics[1].isr_ack = 0xff;
  75 }
  76
  77 /*
  78  * set irq level. If an edge is detected, then the IRR is set to 1
  79  */
  80 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
  81 {
  82         int mask, ret = 1;
  83         mask = 1 << irq;
  84         if (s->elcr & mask)     /* level triggered */
  85                 if (level) {
  86                         ret = !(s->irr & mask);
  87                         s->irr |= mask;
  88                         s->last_irr |= mask;
  89                 } else {
  90                         s->irr &= ~mask;
  91                         s->last_irr &= ~mask;
  92                 }
  93         else    /* edge triggered */
  94                 if (level) {
  95                         if ((s->last_irr & mask) == 0) {
  96                                 ret = !(s->irr & mask);
  97                                 s->irr |= mask;
  98                         }
  99                         s->last_irr |= mask;
 100                 } else
 101                         s->last_irr &= ~mask;
 102
 103         return (s->imr & mask) ? -1 : ret;
 104 }
 105
 106 /*
 107  * return the highest priority found in mask (highest = smallest
 108  * number). Return 8 if no irq
 109  */
 110 static inline int get_priority(struct kvm_kpic_state *s, int mask)
 111 {
 112         int priority;
 113         if (mask == 0)
 114                 return 8;
 115         priority = 0;
 116         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 117                 priority++;
 118         return priority;
 119 }
 120
 121 /*
 122  * return the pic wanted interrupt. return -1 if none
 123  */
 124 static int pic_get_irq(struct kvm_kpic_state *s)
 125 {
 126         int mask, cur_priority, priority;
 127
 128         mask = s->irr & ~s->imr;
 129         priority = get_priority(s, mask);
 130         if (priority == 8)
 131                 return -1;
 132         /*
 133          * compute current priority. If special fully nested mode on the
 134          * master, the IRQ coming from the slave is not taken into account
 135          * for the priority computation.
 136          */
 137         mask = s->isr;
 138         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 139                 mask &= ~(1 << 2);
 140         cur_priority = get_priority(s, mask);
 141         if (priority < cur_priority)
 142                 /*
 143                  * higher priority found: an irq should be generated
 144                  */
 145                 return (priority + s->priority_add) & 7;
 146         else
 147                 return -1;
 148 }
 149
 150 /*
 151  * raise irq to CPU if necessary. must be called every time the active
 152  * irq may change
 153  */
 154 static void pic_update_irq(struct kvm_pic *s)
 155 {
 156         int irq2, irq;
 157
 158         irq2 = pic_get_irq(&s->pics[1]);
 159         if (irq2 >= 0) {
 160                 /*
 161                  * if irq request by slave pic, signal master PIC
 162                  */
 163                 pic_set_irq1(&s->pics[0], 2, 1);
 164                 pic_set_irq1(&s->pics[0], 2, 0);
 165         }
 166         irq = pic_get_irq(&s->pics[0]);
 167         if (irq >= 0)
 168                 s->irq_request(s->irq_request_opaque, 1);
 169         else
 170                 s->irq_request(s->irq_request_opaque, 0);
 171 }
 172
 173 void kvm_pic_update_irq(struct kvm_pic *s)
 174 {
 175         pic_lock(s);
 176         pic_update_irq(s);
 177         pic_unlock(s);
 178 }
 179
 180 int kvm_pic_set_irq(void *opaque, int irq, int level)
 181 {
 182         struct kvm_pic *s = opaque;
 183         int ret = -1;
 184
 185         pic_lock(s);
 186         if (irq >= 0 && irq < PIC_NUM_PINS) {
 187                 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 188                 pic_update_irq(s);
 189         }
 190         pic_unlock(s);
 191
 192         return ret;
 193 }
 194
 195 /*
 196  * acknowledge interrupt 'irq'
 197  */
 198 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
 199 {
 200         s->isr |= 1 << irq;
 201         if (s->auto_eoi) {
 202                 if (s->rotate_on_auto_eoi)
 203                         s->priority_add = (irq + 1) & 7;
 204                 pic_clear_isr(s, irq);
 205         }
 206         /*
 207          * We don't clear a level sensitive interrupt here
 208          */
 209         if (!(s->elcr & (1 << irq)))
 210                 s->irr &= ~(1 << irq);
 211 }
 212
 213 int kvm_pic_read_irq(struct kvm *kvm)
 214 {
 215         int irq, irq2, intno;
 216         struct kvm_pic *s = pic_irqchip(kvm);
 217
 218         pic_lock(s);
 219         irq = pic_get_irq(&s->pics[0]);
 220         if (irq >= 0) {
 221                 pic_intack(&s->pics[0], irq);
 222                 if (irq == 2) {
 223                         irq2 = pic_get_irq(&s->pics[1]);
 224                         if (irq2 >= 0)
 225                                 pic_intack(&s->pics[1], irq2);
 226                         else
 227                                 /*
 228                                  * spurious IRQ on slave controller
 229                                  */
 230                                 irq2 = 7;
 231                         intno = s->pics[1].irq_base + irq2;
 232                         irq = irq2 + 8;
 233                 } else
 234                         intno = s->pics[0].irq_base + irq;
 235         } else {
 236                 /*
 237                  * spurious IRQ on host controller
 238                  */
 239                 irq = 7;
 240                 intno = s->pics[0].irq_base + irq;
 241         }
 242         pic_update_irq(s);
 243         pic_unlock(s);
 244         kvm_notify_acked_irq(kvm, SELECT_PIC(irq), irq);
 245
 246         return intno;
 247 }
 248
 249 void kvm_pic_reset(struct kvm_kpic_state *s)
 250 {
 251         int irq, irqbase, n;
 252         struct kvm *kvm = s->pics_state->irq_request_opaque;
 253         struct kvm_vcpu *vcpu0 = kvm->vcpus[0];
 254
 255         if (s == &s->pics_state->pics[0])
 256                 irqbase = 0;
 257         else
 258                 irqbase = 8;
 259
 260         for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
 261                 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
 262                         if (s->irr & (1 << irq) || s->isr & (1 << irq)) {
 263                                 n = irq + irqbase;
 264                                 s->pics_state->pending_acks |= 1 << n;
 265                         }
 266         }
 267         s->last_irr = 0;
 268         s->irr = 0;
 269         s->imr = 0;
 270         s->isr = 0;
 271         s->isr_ack = 0xff;
 272         s->priority_add = 0;
 273         s->irq_base = 0;
 274         s->read_reg_select = 0;
 275         s->poll = 0;
 276         s->special_mask = 0;
 277         s->init_state = 0;
 278         s->auto_eoi = 0;
 279         s->rotate_on_auto_eoi = 0;
 280         s->special_fully_nested_mode = 0;
 281         s->init4 = 0;
 282 }
 283
 284 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
 285 {
 286         struct kvm_kpic_state *s = opaque;
 287         int priority, cmd, irq;
 288
 289         addr &= 1;
 290         if (addr == 0) {
 291                 if (val & 0x10) {
 292                         kvm_pic_reset(s);       /* init */
 293                         /*
 294                          * deassert a pending interrupt
 295                          */
 296                         s->pics_state->irq_request(s->pics_state->
 297                                                    irq_request_opaque, 0);
 298                         s->init_state = 1;
 299                         s->init4 = val & 1;
 300                         if (val & 0x02)
 301                                 printk(KERN_ERR "single mode not supported");
 302                         if (val & 0x08)
 303                                 printk(KERN_ERR
 304                                        "level sensitive irq not supported");
 305                 } else if (val & 0x08) {
 306                         if (val & 0x04)
 307                                 s->poll = 1;
 308                         if (val & 0x02)
 309                                 s->read_reg_select = val & 1;
 310                         if (val & 0x40)
 311                                 s->special_mask = (val >> 5) & 1;
 312                 } else {
 313                         cmd = val >> 5;
 314                         switch (cmd) {
 315                         case 0:
 316                         case 4:
 317                                 s->rotate_on_auto_eoi = cmd >> 2;
 318                                 break;
 319                         case 1: /* end of interrupt */
 320                         case 5:
 321                                 priority = get_priority(s, s->isr);
 322                                 if (priority != 8) {
 323                                         irq = (priority + s->priority_add) & 7;
 324                                         pic_clear_isr(s, irq);
 325                                         if (cmd == 5)
 326                                                 s->priority_add = (irq + 1) & 7;
 327                                         pic_update_irq(s->pics_state);
 328                                 }
 329                                 break;
 330                         case 3:
 331                                 irq = val & 7;
 332                                 pic_clear_isr(s, irq);
 333                                 pic_update_irq(s->pics_state);
 334                                 break;
 335                         case 6:
 336                                 s->priority_add = (val + 1) & 7;
 337                                 pic_update_irq(s->pics_state);
 338                                 break;
 339                         case 7:
 340                                 irq = val & 7;
 341                                 s->priority_add = (irq + 1) & 7;
 342                                 pic_clear_isr(s, irq);
 343                                 pic_update_irq(s->pics_state);
 344                                 break;
 345                         default:
 346                                 break;  /* no operation */
 347                         }
 348                 }
 349         } else
 350                 switch (s->init_state) {
 351                 case 0:         /* normal mode */
 352                         s->imr = val;
 353                         pic_update_irq(s->pics_state);
 354                         break;
 355                 case 1:
 356                         s->irq_base = val & 0xf8;
 357                         s->init_state = 2;
 358                         break;
 359                 case 2:
 360                         if (s->init4)
 361                                 s->init_state = 3;
 362                         else
 363                                 s->init_state = 0;
 364                         break;
 365                 case 3:
 366                         s->special_fully_nested_mode = (val >> 4) & 1;
 367                         s->auto_eoi = (val >> 1) & 1;
 368                         s->init_state = 0;
 369                         break;
 370                 }
 371 }
 372
 373 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
 374 {
 375         int ret;
 376
 377         ret = pic_get_irq(s);
 378         if (ret >= 0) {
 379                 if (addr1 >> 7) {
 380                         s->pics_state->pics[0].isr &= ~(1 << 2);
 381                         s->pics_state->pics[0].irr &= ~(1 << 2);
 382                 }
 383                 s->irr &= ~(1 << ret);
 384                 pic_clear_isr(s, ret);
 385                 if (addr1 >> 7 || ret != 2)
 386                         pic_update_irq(s->pics_state);
 387         } else {
 388                 ret = 0x07;
 389                 pic_update_irq(s->pics_state);
 390         }
 391
 392         return ret;
 393 }
 394
 395 static u32 pic_ioport_read(void *opaque, u32 addr1)
 396 {
 397         struct kvm_kpic_state *s = opaque;
 398         unsigned int addr;
 399         int ret;
 400
 401         addr = addr1;
 402         addr &= 1;
 403         if (s->poll) {
 404                 ret = pic_poll_read(s, addr1);
 405                 s->poll = 0;
 406         } else
 407                 if (addr == 0)
 408                         if (s->read_reg_select)
 409                                 ret = s->isr;
 410                         else
 411                                 ret = s->irr;
 412                 else
 413                         ret = s->imr;
 414         return ret;
 415 }
 416
 417 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
 418 {
 419         struct kvm_kpic_state *s = opaque;
 420         s->elcr = val & s->elcr_mask;
 421 }
 422
 423 static u32 elcr_ioport_read(void *opaque, u32 addr1)
 424 {
 425         struct kvm_kpic_state *s = opaque;
 426         return s->elcr;
 427 }
 428
 429 static int picdev_in_range(struct kvm_io_device *this, gpa_t addr,
 430                            int len, int is_write)
 431 {
 432         switch (addr) {
 433         case 0x20:
 434         case 0x21:
 435         case 0xa0:
 436         case 0xa1:
 437         case 0x4d0:
 438         case 0x4d1:
 439                 return 1;
 440         default:
 441                 return 0;
 442         }
 443 }
 444
 445 static void picdev_write(struct kvm_io_device *this,
 446                          gpa_t addr, int len, const void *val)
 447 {
 448         struct kvm_pic *s = this->private;
 449         unsigned char data = *(unsigned char *)val;
 450
 451         if (len != 1) {
 452                 if (printk_ratelimit())
 453                         printk(KERN_ERR "PIC: non byte write\n");
 454                 return;
 455         }
 456         pic_lock(s);
 457         switch (addr) {
 458         case 0x20:
 459         case 0x21:
 460         case 0xa0:
 461         case 0xa1:
 462                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
 463                 break;
 464         case 0x4d0:
 465         case 0x4d1:
 466                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
 467                 break;
 468         }
 469         pic_unlock(s);
 470 }
 471
 472 static void picdev_read(struct kvm_io_device *this,
 473                         gpa_t addr, int len, void *val)
 474 {
 475         struct kvm_pic *s = this->private;
 476         unsigned char data = 0;
 477
 478         if (len != 1) {
 479                 if (printk_ratelimit())
 480                         printk(KERN_ERR "PIC: non byte read\n");
 481                 return;
 482         }
 483         pic_lock(s);
 484         switch (addr) {
 485         case 0x20:
 486         case 0x21:
 487         case 0xa0:
 488         case 0xa1:
 489                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
 490                 break;
 491         case 0x4d0:
 492         case 0x4d1:
 493                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
 494                 break;
 495         }
 496         *(unsigned char *)val = data;
 497         pic_unlock(s);
 498 }
 499
 500 /*
 501  * callback when PIC0 irq status changed
 502  */
 503 static void pic_irq_request(void *opaque, int level)
 504 {
 505         struct kvm *kvm = opaque;
 506         struct kvm_vcpu *vcpu = kvm->vcpus[0];
 507         struct kvm_pic *s = pic_irqchip(kvm);
 508         int irq = pic_get_irq(&s->pics[0]);
 509
 510         s->output = level;
 511         if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
 512                 s->pics[0].isr_ack &= ~(1 << irq);
 513                 s->wakeup_needed = true;
 514         }
 515 }
 516
 517 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
 518 {
 519         struct kvm_pic *s;
 520         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
 521         if (!s)
 522                 return NULL;
 523         spin_lock_init(&s->lock);
 524         s->kvm = kvm;
 525         s->pics[0].elcr_mask = 0xf8;
 526         s->pics[1].elcr_mask = 0xde;
 527         s->irq_request = pic_irq_request;
 528         s->irq_request_opaque = kvm;
 529         s->pics[0].pics_state = s;
 530         s->pics[1].pics_state = s;
 531
 532         /*
 533          * Initialize PIO device
 534          */
 535         s->dev.read = picdev_read;
 536         s->dev.write = picdev_write;
 537         s->dev.in_range = picdev_in_range;
 538         s->dev.private = s;
 539         kvm_io_bus_register_dev(&kvm->pio_bus, &s->dev);
 540         return s;
 541 }