3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <linux/atomic.h>
37 #include <linux/jump_label.h>
38 #include "kvm_cache_regs.h"
45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #define mod_64(x, y) ((x) % (y))
55 #define APIC_BUS_CYCLE_NS 1
57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58 #define apic_debug(fmt, arg...)
60 #define APIC_LVT_NUM 6
61 /* 14 is the version for Xeon and Pentium 8.4.8*/
62 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63 #define LAPIC_MMIO_LENGTH (1 << 12)
64 /* followed define is not in apicdef.h */
65 #define APIC_SHORT_MASK 0xc0000
66 #define APIC_DEST_NOSHORT 0x0
67 #define APIC_DEST_MASK 0x800
68 #define MAX_APIC_VECTOR 256
69 #define APIC_VECTORS_PER_REG 32
71 #define VEC_POS(v) ((v) & (32 - 1))
72 #define REG_POS(v) (((v) >> 5) << 4)
74 static inline void apic_set_reg(struct kvm_lapic
*apic
, int reg_off
, u32 val
)
76 *((u32
*) (apic
->regs
+ reg_off
)) = val
;
79 static inline int apic_test_vector(int vec
, void *bitmap
)
81 return test_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
84 bool kvm_apic_pending_eoi(struct kvm_vcpu
*vcpu
, int vector
)
86 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
88 return apic_test_vector(vector
, apic
->regs
+ APIC_ISR
) ||
89 apic_test_vector(vector
, apic
->regs
+ APIC_IRR
);
92 static inline void apic_set_vector(int vec
, void *bitmap
)
94 set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
97 static inline void apic_clear_vector(int vec
, void *bitmap
)
99 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
102 static inline int __apic_test_and_set_vector(int vec
, void *bitmap
)
104 return __test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
107 static inline int __apic_test_and_clear_vector(int vec
, void *bitmap
)
109 return __test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
112 struct static_key_deferred apic_hw_disabled __read_mostly
;
113 struct static_key_deferred apic_sw_disabled __read_mostly
;
115 static inline void apic_set_spiv(struct kvm_lapic
*apic
, u32 val
)
117 if ((kvm_apic_get_reg(apic
, APIC_SPIV
) ^ val
) & APIC_SPIV_APIC_ENABLED
) {
118 if (val
& APIC_SPIV_APIC_ENABLED
)
119 static_key_slow_dec_deferred(&apic_sw_disabled
);
121 static_key_slow_inc(&apic_sw_disabled
.key
);
123 apic_set_reg(apic
, APIC_SPIV
, val
);
126 static inline int apic_enabled(struct kvm_lapic
*apic
)
128 return kvm_apic_sw_enabled(apic
) && kvm_apic_hw_enabled(apic
);
132 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
135 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
136 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
138 static inline int kvm_apic_id(struct kvm_lapic
*apic
)
140 return (kvm_apic_get_reg(apic
, APIC_ID
) >> 24) & 0xff;
143 #define KVM_X2APIC_CID_BITS 0
145 static void recalculate_apic_map(struct kvm
*kvm
)
147 struct kvm_apic_map
*new, *old
= NULL
;
148 struct kvm_vcpu
*vcpu
;
151 new = kzalloc(sizeof(struct kvm_apic_map
), GFP_KERNEL
);
153 mutex_lock(&kvm
->arch
.apic_map_lock
);
159 /* flat mode is default */
162 new->lid_mask
= 0xff;
164 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
165 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
169 if (!kvm_apic_present(vcpu
))
173 * All APICs have to be configured in the same mode by an OS.
174 * We take advatage of this while building logical id loockup
175 * table. After reset APICs are in xapic/flat mode, so if we
176 * find apic with different setting we assume this is the mode
177 * OS wants all apics to be in; build lookup table accordingly.
179 if (apic_x2apic_mode(apic
)) {
182 new->cid_mask
= (1 << KVM_X2APIC_CID_BITS
) - 1;
183 new->lid_mask
= 0xffff;
184 } else if (kvm_apic_sw_enabled(apic
) &&
185 !new->cid_mask
/* flat mode */ &&
186 kvm_apic_get_reg(apic
, APIC_DFR
) == APIC_DFR_CLUSTER
) {
192 new->phys_map
[kvm_apic_id(apic
)] = apic
;
194 ldr
= kvm_apic_get_reg(apic
, APIC_LDR
);
195 cid
= apic_cluster_id(new, ldr
);
196 lid
= apic_logical_id(new, ldr
);
199 new->logical_map
[cid
][ffs(lid
) - 1] = apic
;
202 old
= rcu_dereference_protected(kvm
->arch
.apic_map
,
203 lockdep_is_held(&kvm
->arch
.apic_map_lock
));
204 rcu_assign_pointer(kvm
->arch
.apic_map
, new);
205 mutex_unlock(&kvm
->arch
.apic_map_lock
);
210 kvm_vcpu_request_scan_ioapic(kvm
);
213 static inline void kvm_apic_set_id(struct kvm_lapic
*apic
, u8 id
)
215 apic_set_reg(apic
, APIC_ID
, id
<< 24);
216 recalculate_apic_map(apic
->vcpu
->kvm
);
219 static inline void kvm_apic_set_ldr(struct kvm_lapic
*apic
, u32 id
)
221 apic_set_reg(apic
, APIC_LDR
, id
);
222 recalculate_apic_map(apic
->vcpu
->kvm
);
225 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
227 return !(kvm_apic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
230 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
232 return kvm_apic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
235 static inline int apic_lvtt_oneshot(struct kvm_lapic
*apic
)
237 return ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
238 apic
->lapic_timer
.timer_mode_mask
) == APIC_LVT_TIMER_ONESHOT
);
241 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
243 return ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
244 apic
->lapic_timer
.timer_mode_mask
) == APIC_LVT_TIMER_PERIODIC
);
247 static inline int apic_lvtt_tscdeadline(struct kvm_lapic
*apic
)
249 return ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
250 apic
->lapic_timer
.timer_mode_mask
) ==
251 APIC_LVT_TIMER_TSCDEADLINE
);
254 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
256 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
259 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
261 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
262 struct kvm_cpuid_entry2
*feat
;
263 u32 v
= APIC_VERSION
;
265 if (!kvm_vcpu_has_lapic(vcpu
))
268 feat
= kvm_find_cpuid_entry(apic
->vcpu
, 0x1, 0);
269 if (feat
&& (feat
->ecx
& (1 << (X86_FEATURE_X2APIC
& 31))))
270 v
|= APIC_LVR_DIRECTED_EOI
;
271 apic_set_reg(apic
, APIC_LVR
, v
);
274 static const unsigned int apic_lvt_mask
[APIC_LVT_NUM
] = {
275 LVT_MASK
, /* part LVTT mask, timer mode mask added at runtime */
276 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
277 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
278 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
279 LVT_MASK
/* LVTERR */
282 static int find_highest_vector(void *bitmap
)
287 for (vec
= MAX_APIC_VECTOR
- APIC_VECTORS_PER_REG
;
288 vec
>= 0; vec
-= APIC_VECTORS_PER_REG
) {
289 reg
= bitmap
+ REG_POS(vec
);
291 return fls(*reg
) - 1 + vec
;
297 static u8
count_vectors(void *bitmap
)
303 for (vec
= 0; vec
< MAX_APIC_VECTOR
; vec
+= APIC_VECTORS_PER_REG
) {
304 reg
= bitmap
+ REG_POS(vec
);
305 count
+= hweight32(*reg
);
311 void kvm_apic_update_irr(struct kvm_vcpu
*vcpu
, u32
*pir
)
314 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
316 for (i
= 0; i
<= 7; i
++) {
317 pir_val
= xchg(&pir
[i
], 0);
319 *((u32
*)(apic
->regs
+ APIC_IRR
+ i
* 0x10)) |= pir_val
;
322 EXPORT_SYMBOL_GPL(kvm_apic_update_irr
);
324 static inline void apic_set_irr(int vec
, struct kvm_lapic
*apic
)
326 apic
->irr_pending
= true;
327 apic_set_vector(vec
, apic
->regs
+ APIC_IRR
);
330 static inline int apic_search_irr(struct kvm_lapic
*apic
)
332 return find_highest_vector(apic
->regs
+ APIC_IRR
);
335 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
340 * Note that irr_pending is just a hint. It will be always
341 * true with virtual interrupt delivery enabled.
343 if (!apic
->irr_pending
)
346 kvm_x86_ops
->sync_pir_to_irr(apic
->vcpu
);
347 result
= apic_search_irr(apic
);
348 ASSERT(result
== -1 || result
>= 16);
353 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
355 struct kvm_vcpu
*vcpu
;
359 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
360 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
)))
361 /* try to update RVI */
362 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
364 vec
= apic_search_irr(apic
);
365 apic
->irr_pending
= (vec
!= -1);
369 static inline void apic_set_isr(int vec
, struct kvm_lapic
*apic
)
371 struct kvm_vcpu
*vcpu
;
373 if (__apic_test_and_set_vector(vec
, apic
->regs
+ APIC_ISR
))
379 * With APIC virtualization enabled, all caching is disabled
380 * because the processor can modify ISR under the hood. Instead
383 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
)))
384 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, vec
);
387 BUG_ON(apic
->isr_count
> MAX_APIC_VECTOR
);
389 * ISR (in service register) bit is set when injecting an interrupt.
390 * The highest vector is injected. Thus the latest bit set matches
391 * the highest bit in ISR.
393 apic
->highest_isr_cache
= vec
;
397 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
402 * Note that isr_count is always 1, and highest_isr_cache
403 * is always -1, with APIC virtualization enabled.
405 if (!apic
->isr_count
)
407 if (likely(apic
->highest_isr_cache
!= -1))
408 return apic
->highest_isr_cache
;
410 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
411 ASSERT(result
== -1 || result
>= 16);
416 static inline void apic_clear_isr(int vec
, struct kvm_lapic
*apic
)
418 struct kvm_vcpu
*vcpu
;
419 if (!__apic_test_and_clear_vector(vec
, apic
->regs
+ APIC_ISR
))
425 * We do get here for APIC virtualization enabled if the guest
426 * uses the Hyper-V APIC enlightenment. In this case we may need
427 * to trigger a new interrupt delivery by writing the SVI field;
428 * on the other hand isr_count and highest_isr_cache are unused
429 * and must be left alone.
431 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
)))
432 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
,
433 apic_find_highest_isr(apic
));
436 BUG_ON(apic
->isr_count
< 0);
437 apic
->highest_isr_cache
= -1;
441 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
445 /* This may race with setting of irr in __apic_accept_irq() and
446 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
447 * will cause vmexit immediately and the value will be recalculated
448 * on the next vmentry.
450 if (!kvm_vcpu_has_lapic(vcpu
))
452 highest_irr
= apic_find_highest_irr(vcpu
->arch
.apic
);
457 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
458 int vector
, int level
, int trig_mode
,
459 unsigned long *dest_map
);
461 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
,
462 unsigned long *dest_map
)
464 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
466 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
467 irq
->level
, irq
->trig_mode
, dest_map
);
470 static int pv_eoi_put_user(struct kvm_vcpu
*vcpu
, u8 val
)
473 return kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, &val
,
477 static int pv_eoi_get_user(struct kvm_vcpu
*vcpu
, u8
*val
)
480 return kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, val
,
484 static inline bool pv_eoi_enabled(struct kvm_vcpu
*vcpu
)
486 return vcpu
->arch
.pv_eoi
.msr_val
& KVM_MSR_ENABLED
;
489 static bool pv_eoi_get_pending(struct kvm_vcpu
*vcpu
)
492 if (pv_eoi_get_user(vcpu
, &val
) < 0)
493 apic_debug("Can't read EOI MSR value: 0x%llx\n",
494 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
498 static void pv_eoi_set_pending(struct kvm_vcpu
*vcpu
)
500 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_ENABLED
) < 0) {
501 apic_debug("Can't set EOI MSR value: 0x%llx\n",
502 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
505 __set_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
508 static void pv_eoi_clr_pending(struct kvm_vcpu
*vcpu
)
510 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_DISABLED
) < 0) {
511 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
512 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
515 __clear_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
518 void kvm_apic_update_tmr(struct kvm_vcpu
*vcpu
, u32
*tmr
)
520 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
523 for (i
= 0; i
< 8; i
++)
524 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, tmr
[i
]);
527 static void apic_update_ppr(struct kvm_lapic
*apic
)
529 u32 tpr
, isrv
, ppr
, old_ppr
;
532 old_ppr
= kvm_apic_get_reg(apic
, APIC_PROCPRI
);
533 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
);
534 isr
= apic_find_highest_isr(apic
);
535 isrv
= (isr
!= -1) ? isr
: 0;
537 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
542 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
543 apic
, ppr
, isr
, isrv
);
545 if (old_ppr
!= ppr
) {
546 apic_set_reg(apic
, APIC_PROCPRI
, ppr
);
548 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
552 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
554 apic_set_reg(apic
, APIC_TASKPRI
, tpr
);
555 apic_update_ppr(apic
);
558 int kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u16 dest
)
560 return dest
== 0xff || kvm_apic_id(apic
) == dest
;
563 int kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u8 mda
)
568 if (apic_x2apic_mode(apic
)) {
569 logical_id
= kvm_apic_get_reg(apic
, APIC_LDR
);
570 return logical_id
& mda
;
573 logical_id
= GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic
, APIC_LDR
));
575 switch (kvm_apic_get_reg(apic
, APIC_DFR
)) {
577 if (logical_id
& mda
)
580 case APIC_DFR_CLUSTER
:
581 if (((logical_id
>> 4) == (mda
>> 0x4))
582 && (logical_id
& mda
& 0xf))
586 apic_debug("Bad DFR vcpu %d: %08x\n",
587 apic
->vcpu
->vcpu_id
, kvm_apic_get_reg(apic
, APIC_DFR
));
594 int kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
595 int short_hand
, int dest
, int dest_mode
)
598 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
600 apic_debug("target %p, source %p, dest 0x%x, "
601 "dest_mode 0x%x, short_hand 0x%x\n",
602 target
, source
, dest
, dest_mode
, short_hand
);
605 switch (short_hand
) {
606 case APIC_DEST_NOSHORT
:
609 result
= kvm_apic_match_physical_addr(target
, dest
);
612 result
= kvm_apic_match_logical_addr(target
, dest
);
615 result
= (target
== source
);
617 case APIC_DEST_ALLINC
:
620 case APIC_DEST_ALLBUT
:
621 result
= (target
!= source
);
624 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
632 bool kvm_irq_delivery_to_apic_fast(struct kvm
*kvm
, struct kvm_lapic
*src
,
633 struct kvm_lapic_irq
*irq
, int *r
, unsigned long *dest_map
)
635 struct kvm_apic_map
*map
;
636 unsigned long bitmap
= 1;
637 struct kvm_lapic
**dst
;
643 if (irq
->shorthand
== APIC_DEST_SELF
) {
644 *r
= kvm_apic_set_irq(src
->vcpu
, irq
, dest_map
);
652 map
= rcu_dereference(kvm
->arch
.apic_map
);
657 if (irq
->dest_mode
== 0) { /* physical mode */
658 if (irq
->delivery_mode
== APIC_DM_LOWEST
||
659 irq
->dest_id
== 0xff)
661 dst
= &map
->phys_map
[irq
->dest_id
& 0xff];
663 u32 mda
= irq
->dest_id
<< (32 - map
->ldr_bits
);
665 dst
= map
->logical_map
[apic_cluster_id(map
, mda
)];
667 bitmap
= apic_logical_id(map
, mda
);
669 if (irq
->delivery_mode
== APIC_DM_LOWEST
) {
671 for_each_set_bit(i
, &bitmap
, 16) {
676 else if (kvm_apic_compare_prio(dst
[i
]->vcpu
, dst
[l
]->vcpu
) < 0)
680 bitmap
= (l
>= 0) ? 1 << l
: 0;
684 for_each_set_bit(i
, &bitmap
, 16) {
689 *r
+= kvm_apic_set_irq(dst
[i
]->vcpu
, irq
, dest_map
);
699 * Add a pending IRQ into lapic.
700 * Return 1 if successfully added and 0 if discarded.
702 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
703 int vector
, int level
, int trig_mode
,
704 unsigned long *dest_map
)
707 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
709 switch (delivery_mode
) {
711 vcpu
->arch
.apic_arb_prio
++;
713 /* FIXME add logic for vcpu on reset */
714 if (unlikely(!apic_enabled(apic
)))
720 __set_bit(vcpu
->vcpu_id
, dest_map
);
722 if (kvm_x86_ops
->deliver_posted_interrupt
)
723 kvm_x86_ops
->deliver_posted_interrupt(vcpu
, vector
);
725 apic_set_irr(vector
, apic
);
727 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
730 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
731 trig_mode
, vector
, false);
736 vcpu
->arch
.pv
.pv_unhalted
= 1;
737 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
742 apic_debug("Ignoring guest SMI\n");
747 kvm_inject_nmi(vcpu
);
752 if (!trig_mode
|| level
) {
754 /* assumes that there are only KVM_APIC_INIT/SIPI */
755 apic
->pending_events
= (1UL << KVM_APIC_INIT
);
756 /* make sure pending_events is visible before sending
759 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
762 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
767 case APIC_DM_STARTUP
:
768 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
769 vcpu
->vcpu_id
, vector
);
771 apic
->sipi_vector
= vector
;
772 /* make sure sipi_vector is visible for the receiver */
774 set_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
775 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
781 * Should only be called by kvm_apic_local_deliver() with LVT0,
782 * before NMI watchdog was enabled. Already handled by
783 * kvm_apic_accept_pic_intr().
788 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
795 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
797 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
800 static void kvm_ioapic_send_eoi(struct kvm_lapic
*apic
, int vector
)
802 if (!(kvm_apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_DIRECTED_EOI
) &&
803 kvm_ioapic_handles_vector(apic
->vcpu
->kvm
, vector
)) {
805 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
))
806 trigger_mode
= IOAPIC_LEVEL_TRIG
;
808 trigger_mode
= IOAPIC_EDGE_TRIG
;
809 kvm_ioapic_update_eoi(apic
->vcpu
, vector
, trigger_mode
);
813 static int apic_set_eoi(struct kvm_lapic
*apic
)
815 int vector
= apic_find_highest_isr(apic
);
817 trace_kvm_eoi(apic
, vector
);
820 * Not every write EOI will has corresponding ISR,
821 * one example is when Kernel check timer on setup_IO_APIC
826 apic_clear_isr(vector
, apic
);
827 apic_update_ppr(apic
);
829 kvm_ioapic_send_eoi(apic
, vector
);
830 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
835 * this interface assumes a trap-like exit, which has already finished
836 * desired side effect including vISR and vPPR update.
838 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu
*vcpu
, int vector
)
840 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
842 trace_kvm_eoi(apic
, vector
);
844 kvm_ioapic_send_eoi(apic
, vector
);
845 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
847 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated
);
849 static void apic_send_ipi(struct kvm_lapic
*apic
)
851 u32 icr_low
= kvm_apic_get_reg(apic
, APIC_ICR
);
852 u32 icr_high
= kvm_apic_get_reg(apic
, APIC_ICR2
);
853 struct kvm_lapic_irq irq
;
855 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
856 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
857 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
858 irq
.level
= icr_low
& APIC_INT_ASSERT
;
859 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
860 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
861 if (apic_x2apic_mode(apic
))
862 irq
.dest_id
= icr_high
;
864 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
866 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
868 apic_debug("icr_high 0x%x, icr_low 0x%x, "
869 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
870 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
871 icr_high
, icr_low
, irq
.shorthand
, irq
.dest_id
,
872 irq
.trig_mode
, irq
.level
, irq
.dest_mode
, irq
.delivery_mode
,
875 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
, NULL
);
878 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
884 ASSERT(apic
!= NULL
);
886 /* if initial count is 0, current count should also be 0 */
887 if (kvm_apic_get_reg(apic
, APIC_TMICT
) == 0 ||
888 apic
->lapic_timer
.period
== 0)
891 remaining
= hrtimer_get_remaining(&apic
->lapic_timer
.timer
);
892 if (ktime_to_ns(remaining
) < 0)
893 remaining
= ktime_set(0, 0);
895 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
896 tmcct
= div64_u64(ns
,
897 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
902 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
904 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
905 struct kvm_run
*run
= vcpu
->run
;
907 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS
, vcpu
);
908 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
909 run
->tpr_access
.is_write
= write
;
912 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
914 if (apic
->vcpu
->arch
.tpr_access_reporting
)
915 __report_tpr_access(apic
, write
);
918 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
922 if (offset
>= LAPIC_MMIO_LENGTH
)
927 if (apic_x2apic_mode(apic
))
928 val
= kvm_apic_id(apic
);
930 val
= kvm_apic_id(apic
) << 24;
933 apic_debug("Access APIC ARBPRI register which is for P6\n");
936 case APIC_TMCCT
: /* Timer CCR */
937 if (apic_lvtt_tscdeadline(apic
))
940 val
= apic_get_tmcct(apic
);
943 apic_update_ppr(apic
);
944 val
= kvm_apic_get_reg(apic
, offset
);
947 report_tpr_access(apic
, false);
950 val
= kvm_apic_get_reg(apic
, offset
);
957 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
959 return container_of(dev
, struct kvm_lapic
, dev
);
962 static int apic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
965 unsigned char alignment
= offset
& 0xf;
967 /* this bitmask has a bit cleared for each reserved register */
968 static const u64 rmask
= 0x43ff01ffffffe70cULL
;
970 if ((alignment
+ len
) > 4) {
971 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
976 if (offset
> 0x3f0 || !(rmask
& (1ULL << (offset
>> 4)))) {
977 apic_debug("KVM_APIC_READ: read reserved register %x\n",
982 result
= __apic_read(apic
, offset
& ~0xf);
984 trace_kvm_apic_read(offset
, result
);
990 memcpy(data
, (char *)&result
+ alignment
, len
);
993 printk(KERN_ERR
"Local APIC read with len = %x, "
994 "should be 1,2, or 4 instead\n", len
);
1000 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
1002 return kvm_apic_hw_enabled(apic
) &&
1003 addr
>= apic
->base_address
&&
1004 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
1007 static int apic_mmio_read(struct kvm_io_device
*this,
1008 gpa_t address
, int len
, void *data
)
1010 struct kvm_lapic
*apic
= to_lapic(this);
1011 u32 offset
= address
- apic
->base_address
;
1013 if (!apic_mmio_in_range(apic
, address
))
1016 apic_reg_read(apic
, offset
, len
, data
);
1021 static void update_divide_count(struct kvm_lapic
*apic
)
1023 u32 tmp1
, tmp2
, tdcr
;
1025 tdcr
= kvm_apic_get_reg(apic
, APIC_TDCR
);
1027 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
1028 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
1030 apic_debug("timer divide count is 0x%x\n",
1031 apic
->divide_count
);
1034 static void start_apic_timer(struct kvm_lapic
*apic
)
1037 atomic_set(&apic
->lapic_timer
.pending
, 0);
1039 if (apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
)) {
1040 /* lapic timer in oneshot or periodic mode */
1041 now
= apic
->lapic_timer
.timer
.base
->get_time();
1042 apic
->lapic_timer
.period
= (u64
)kvm_apic_get_reg(apic
, APIC_TMICT
)
1043 * APIC_BUS_CYCLE_NS
* apic
->divide_count
;
1045 if (!apic
->lapic_timer
.period
)
1048 * Do not allow the guest to program periodic timers with small
1049 * interval, since the hrtimers are not throttled by the host
1052 if (apic_lvtt_period(apic
)) {
1053 s64 min_period
= min_timer_period_us
* 1000LL;
1055 if (apic
->lapic_timer
.period
< min_period
) {
1056 pr_info_ratelimited(
1057 "kvm: vcpu %i: requested %lld ns "
1058 "lapic timer period limited to %lld ns\n",
1059 apic
->vcpu
->vcpu_id
,
1060 apic
->lapic_timer
.period
, min_period
);
1061 apic
->lapic_timer
.period
= min_period
;
1065 hrtimer_start(&apic
->lapic_timer
.timer
,
1066 ktime_add_ns(now
, apic
->lapic_timer
.period
),
1069 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
1071 "timer initial count 0x%x, period %lldns, "
1072 "expire @ 0x%016" PRIx64
".\n", __func__
,
1073 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
1074 kvm_apic_get_reg(apic
, APIC_TMICT
),
1075 apic
->lapic_timer
.period
,
1076 ktime_to_ns(ktime_add_ns(now
,
1077 apic
->lapic_timer
.period
)));
1078 } else if (apic_lvtt_tscdeadline(apic
)) {
1079 /* lapic timer in tsc deadline mode */
1080 u64 guest_tsc
, tscdeadline
= apic
->lapic_timer
.tscdeadline
;
1082 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1083 unsigned long this_tsc_khz
= vcpu
->arch
.virtual_tsc_khz
;
1084 unsigned long flags
;
1086 if (unlikely(!tscdeadline
|| !this_tsc_khz
))
1089 local_irq_save(flags
);
1091 now
= apic
->lapic_timer
.timer
.base
->get_time();
1092 guest_tsc
= kvm_x86_ops
->read_l1_tsc(vcpu
, native_read_tsc());
1093 if (likely(tscdeadline
> guest_tsc
)) {
1094 ns
= (tscdeadline
- guest_tsc
) * 1000000ULL;
1095 do_div(ns
, this_tsc_khz
);
1097 hrtimer_start(&apic
->lapic_timer
.timer
,
1098 ktime_add_ns(now
, ns
), HRTIMER_MODE_ABS
);
1100 local_irq_restore(flags
);
1104 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
1106 int nmi_wd_enabled
= apic_lvt_nmi_mode(kvm_apic_get_reg(apic
, APIC_LVT0
));
1108 if (apic_lvt_nmi_mode(lvt0_val
)) {
1109 if (!nmi_wd_enabled
) {
1110 apic_debug("Receive NMI setting on APIC_LVT0 "
1111 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
1112 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
++;
1114 } else if (nmi_wd_enabled
)
1115 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
--;
1118 static int apic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
1122 trace_kvm_apic_write(reg
, val
);
1125 case APIC_ID
: /* Local APIC ID */
1126 if (!apic_x2apic_mode(apic
))
1127 kvm_apic_set_id(apic
, val
>> 24);
1133 report_tpr_access(apic
, true);
1134 apic_set_tpr(apic
, val
& 0xff);
1142 if (!apic_x2apic_mode(apic
))
1143 kvm_apic_set_ldr(apic
, val
& APIC_LDR_MASK
);
1149 if (!apic_x2apic_mode(apic
)) {
1150 apic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
1151 recalculate_apic_map(apic
->vcpu
->kvm
);
1158 if (kvm_apic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
1159 mask
|= APIC_SPIV_DIRECTED_EOI
;
1160 apic_set_spiv(apic
, val
& mask
);
1161 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
1165 for (i
= 0; i
< APIC_LVT_NUM
; i
++) {
1166 lvt_val
= kvm_apic_get_reg(apic
,
1167 APIC_LVTT
+ 0x10 * i
);
1168 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
1169 lvt_val
| APIC_LVT_MASKED
);
1171 atomic_set(&apic
->lapic_timer
.pending
, 0);
1177 /* No delay here, so we always clear the pending bit */
1178 apic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
1179 apic_send_ipi(apic
);
1183 if (!apic_x2apic_mode(apic
))
1185 apic_set_reg(apic
, APIC_ICR2
, val
);
1189 apic_manage_nmi_watchdog(apic
, val
);
1194 /* TODO: Check vector */
1195 if (!kvm_apic_sw_enabled(apic
))
1196 val
|= APIC_LVT_MASKED
;
1198 val
&= apic_lvt_mask
[(reg
- APIC_LVTT
) >> 4];
1199 apic_set_reg(apic
, reg
, val
);
1204 if ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
1205 apic
->lapic_timer
.timer_mode_mask
) !=
1206 (val
& apic
->lapic_timer
.timer_mode_mask
))
1207 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1209 if (!kvm_apic_sw_enabled(apic
))
1210 val
|= APIC_LVT_MASKED
;
1211 val
&= (apic_lvt_mask
[0] | apic
->lapic_timer
.timer_mode_mask
);
1212 apic_set_reg(apic
, APIC_LVTT
, val
);
1216 if (apic_lvtt_tscdeadline(apic
))
1219 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1220 apic_set_reg(apic
, APIC_TMICT
, val
);
1221 start_apic_timer(apic
);
1226 apic_debug("KVM_WRITE:TDCR %x\n", val
);
1227 apic_set_reg(apic
, APIC_TDCR
, val
);
1228 update_divide_count(apic
);
1232 if (apic_x2apic_mode(apic
) && val
!= 0) {
1233 apic_debug("KVM_WRITE:ESR not zero %x\n", val
);
1239 if (apic_x2apic_mode(apic
)) {
1240 apic_reg_write(apic
, APIC_ICR
, 0x40000 | (val
& 0xff));
1249 apic_debug("Local APIC Write to read-only register %x\n", reg
);
1253 static int apic_mmio_write(struct kvm_io_device
*this,
1254 gpa_t address
, int len
, const void *data
)
1256 struct kvm_lapic
*apic
= to_lapic(this);
1257 unsigned int offset
= address
- apic
->base_address
;
1260 if (!apic_mmio_in_range(apic
, address
))
1264 * APIC register must be aligned on 128-bits boundary.
1265 * 32/64/128 bits registers must be accessed thru 32 bits.
1268 if (len
!= 4 || (offset
& 0xf)) {
1269 /* Don't shout loud, $infamous_os would cause only noise. */
1270 apic_debug("apic write: bad size=%d %lx\n", len
, (long)address
);
1276 /* too common printing */
1277 if (offset
!= APIC_EOI
)
1278 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1279 "0x%x\n", __func__
, offset
, len
, val
);
1281 apic_reg_write(apic
, offset
& 0xff0, val
);
1286 void kvm_lapic_set_eoi(struct kvm_vcpu
*vcpu
)
1288 if (kvm_vcpu_has_lapic(vcpu
))
1289 apic_reg_write(vcpu
->arch
.apic
, APIC_EOI
, 0);
1291 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi
);
1293 /* emulate APIC access in a trap manner */
1294 void kvm_apic_write_nodecode(struct kvm_vcpu
*vcpu
, u32 offset
)
1298 /* hw has done the conditional check and inst decode */
1301 apic_reg_read(vcpu
->arch
.apic
, offset
, 4, &val
);
1303 /* TODO: optimize to just emulate side effect w/o one more write */
1304 apic_reg_write(vcpu
->arch
.apic
, offset
, val
);
1306 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode
);
1308 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
1310 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1312 if (!vcpu
->arch
.apic
)
1315 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1317 if (!(vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
))
1318 static_key_slow_dec_deferred(&apic_hw_disabled
);
1320 if (!(kvm_apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_APIC_ENABLED
))
1321 static_key_slow_dec_deferred(&apic_sw_disabled
);
1324 free_page((unsigned long)apic
->regs
);
1330 *----------------------------------------------------------------------
1332 *----------------------------------------------------------------------
1335 u64
kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
)
1337 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1339 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1340 apic_lvtt_period(apic
))
1343 return apic
->lapic_timer
.tscdeadline
;
1346 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
, u64 data
)
1348 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1350 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1351 apic_lvtt_period(apic
))
1354 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1355 apic
->lapic_timer
.tscdeadline
= data
;
1356 start_apic_timer(apic
);
1359 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
1361 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1363 if (!kvm_vcpu_has_lapic(vcpu
))
1366 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
1367 | (kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 4));
1370 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
1374 if (!kvm_vcpu_has_lapic(vcpu
))
1377 tpr
= (u64
) kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_TASKPRI
);
1379 return (tpr
& 0xf0) >> 4;
1382 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
1384 u64 old_value
= vcpu
->arch
.apic_base
;
1385 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1388 value
|= MSR_IA32_APICBASE_BSP
;
1389 vcpu
->arch
.apic_base
= value
;
1393 if (!kvm_vcpu_is_bsp(apic
->vcpu
))
1394 value
&= ~MSR_IA32_APICBASE_BSP
;
1395 vcpu
->arch
.apic_base
= value
;
1397 /* update jump label if enable bit changes */
1398 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
) {
1399 if (value
& MSR_IA32_APICBASE_ENABLE
)
1400 static_key_slow_dec_deferred(&apic_hw_disabled
);
1402 static_key_slow_inc(&apic_hw_disabled
.key
);
1403 recalculate_apic_map(vcpu
->kvm
);
1406 if ((old_value
^ value
) & X2APIC_ENABLE
) {
1407 if (value
& X2APIC_ENABLE
) {
1408 u32 id
= kvm_apic_id(apic
);
1409 u32 ldr
= ((id
>> 4) << 16) | (1 << (id
& 0xf));
1410 kvm_apic_set_ldr(apic
, ldr
);
1411 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, true);
1413 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, false);
1416 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
1417 MSR_IA32_APICBASE_BASE
;
1419 /* with FSB delivery interrupt, we can restart APIC functionality */
1420 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
1421 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
1425 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
)
1427 struct kvm_lapic
*apic
;
1430 apic_debug("%s\n", __func__
);
1433 apic
= vcpu
->arch
.apic
;
1434 ASSERT(apic
!= NULL
);
1436 /* Stop the timer in case it's a reset to an active apic */
1437 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1439 kvm_apic_set_id(apic
, vcpu
->vcpu_id
);
1440 kvm_apic_set_version(apic
->vcpu
);
1442 for (i
= 0; i
< APIC_LVT_NUM
; i
++)
1443 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
1444 apic_set_reg(apic
, APIC_LVT0
,
1445 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
1447 apic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
1448 apic_set_spiv(apic
, 0xff);
1449 apic_set_reg(apic
, APIC_TASKPRI
, 0);
1450 kvm_apic_set_ldr(apic
, 0);
1451 apic_set_reg(apic
, APIC_ESR
, 0);
1452 apic_set_reg(apic
, APIC_ICR
, 0);
1453 apic_set_reg(apic
, APIC_ICR2
, 0);
1454 apic_set_reg(apic
, APIC_TDCR
, 0);
1455 apic_set_reg(apic
, APIC_TMICT
, 0);
1456 for (i
= 0; i
< 8; i
++) {
1457 apic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
1458 apic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
1459 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
1461 apic
->irr_pending
= kvm_apic_vid_enabled(vcpu
->kvm
);
1462 apic
->isr_count
= kvm_apic_vid_enabled(vcpu
->kvm
);
1463 apic
->highest_isr_cache
= -1;
1464 update_divide_count(apic
);
1465 atomic_set(&apic
->lapic_timer
.pending
, 0);
1466 if (kvm_vcpu_is_bsp(vcpu
))
1467 kvm_lapic_set_base(vcpu
,
1468 vcpu
->arch
.apic_base
| MSR_IA32_APICBASE_BSP
);
1469 vcpu
->arch
.pv_eoi
.msr_val
= 0;
1470 apic_update_ppr(apic
);
1472 vcpu
->arch
.apic_arb_prio
= 0;
1473 vcpu
->arch
.apic_attention
= 0;
1475 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1476 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
1477 vcpu
, kvm_apic_id(apic
),
1478 vcpu
->arch
.apic_base
, apic
->base_address
);
1482 *----------------------------------------------------------------------
1484 *----------------------------------------------------------------------
1487 static bool lapic_is_periodic(struct kvm_lapic
*apic
)
1489 return apic_lvtt_period(apic
);
1492 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
1494 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1496 if (kvm_vcpu_has_lapic(vcpu
) && apic_enabled(apic
) &&
1497 apic_lvt_enabled(apic
, APIC_LVTT
))
1498 return atomic_read(&apic
->lapic_timer
.pending
);
1503 int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
1505 u32 reg
= kvm_apic_get_reg(apic
, lvt_type
);
1506 int vector
, mode
, trig_mode
;
1508 if (kvm_apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
1509 vector
= reg
& APIC_VECTOR_MASK
;
1510 mode
= reg
& APIC_MODE_MASK
;
1511 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
1512 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
,
1518 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
1520 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1523 kvm_apic_local_deliver(apic
, APIC_LVT0
);
1526 static const struct kvm_io_device_ops apic_mmio_ops
= {
1527 .read
= apic_mmio_read
,
1528 .write
= apic_mmio_write
,
1531 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
1533 struct kvm_timer
*ktimer
= container_of(data
, struct kvm_timer
, timer
);
1534 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
, lapic_timer
);
1535 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1536 wait_queue_head_t
*q
= &vcpu
->wq
;
1539 * There is a race window between reading and incrementing, but we do
1540 * not care about potentially losing timer events in the !reinject
1541 * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked
1542 * in vcpu_enter_guest.
1544 if (!atomic_read(&ktimer
->pending
)) {
1545 atomic_inc(&ktimer
->pending
);
1546 /* FIXME: this code should not know anything about vcpus */
1547 kvm_make_request(KVM_REQ_PENDING_TIMER
, vcpu
);
1550 if (waitqueue_active(q
))
1551 wake_up_interruptible(q
);
1553 if (lapic_is_periodic(apic
)) {
1554 hrtimer_add_expires_ns(&ktimer
->timer
, ktimer
->period
);
1555 return HRTIMER_RESTART
;
1557 return HRTIMER_NORESTART
;
1560 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
1562 struct kvm_lapic
*apic
;
1564 ASSERT(vcpu
!= NULL
);
1565 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
1567 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
1571 vcpu
->arch
.apic
= apic
;
1573 apic
->regs
= (void *)get_zeroed_page(GFP_KERNEL
);
1575 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
1577 goto nomem_free_apic
;
1581 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
1583 apic
->lapic_timer
.timer
.function
= apic_timer_fn
;
1586 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1587 * thinking that APIC satet has changed.
1589 vcpu
->arch
.apic_base
= MSR_IA32_APICBASE_ENABLE
;
1590 kvm_lapic_set_base(vcpu
,
1591 APIC_DEFAULT_PHYS_BASE
| MSR_IA32_APICBASE_ENABLE
);
1593 static_key_slow_inc(&apic_sw_disabled
.key
); /* sw disabled at reset */
1594 kvm_lapic_reset(vcpu
);
1595 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
1604 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
1606 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1609 if (!kvm_vcpu_has_lapic(vcpu
) || !apic_enabled(apic
))
1612 apic_update_ppr(apic
);
1613 highest_irr
= apic_find_highest_irr(apic
);
1614 if ((highest_irr
== -1) ||
1615 ((highest_irr
& 0xF0) <= kvm_apic_get_reg(apic
, APIC_PROCPRI
)))
1620 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
1622 u32 lvt0
= kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
1625 if (!kvm_apic_hw_enabled(vcpu
->arch
.apic
))
1627 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
1628 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
1633 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
1635 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1637 if (!kvm_vcpu_has_lapic(vcpu
))
1640 if (atomic_read(&apic
->lapic_timer
.pending
) > 0) {
1641 kvm_apic_local_deliver(apic
, APIC_LVTT
);
1642 atomic_set(&apic
->lapic_timer
.pending
, 0);
1646 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
1648 int vector
= kvm_apic_has_interrupt(vcpu
);
1649 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1655 * We get here even with APIC virtualization enabled, if doing
1656 * nested virtualization and L1 runs with the "acknowledge interrupt
1657 * on exit" mode. Then we cannot inject the interrupt via RVI,
1658 * because the process would deliver it through the IDT.
1661 apic_set_isr(vector
, apic
);
1662 apic_update_ppr(apic
);
1663 apic_clear_irr(vector
, apic
);
1667 void kvm_apic_post_state_restore(struct kvm_vcpu
*vcpu
,
1668 struct kvm_lapic_state
*s
)
1670 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1672 kvm_lapic_set_base(vcpu
, vcpu
->arch
.apic_base
);
1673 /* set SPIV separately to get count of SW disabled APICs right */
1674 apic_set_spiv(apic
, *((u32
*)(s
->regs
+ APIC_SPIV
)));
1675 memcpy(vcpu
->arch
.apic
->regs
, s
->regs
, sizeof *s
);
1676 /* call kvm_apic_set_id() to put apic into apic_map */
1677 kvm_apic_set_id(apic
, kvm_apic_id(apic
));
1678 kvm_apic_set_version(vcpu
);
1680 apic_update_ppr(apic
);
1681 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1682 update_divide_count(apic
);
1683 start_apic_timer(apic
);
1684 apic
->irr_pending
= true;
1685 apic
->isr_count
= kvm_apic_vid_enabled(vcpu
->kvm
) ?
1686 1 : count_vectors(apic
->regs
+ APIC_ISR
);
1687 apic
->highest_isr_cache
= -1;
1688 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, apic_find_highest_isr(apic
));
1689 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1690 kvm_rtc_eoi_tracking_restore_one(vcpu
);
1693 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
1695 struct hrtimer
*timer
;
1697 if (!kvm_vcpu_has_lapic(vcpu
))
1700 timer
= &vcpu
->arch
.apic
->lapic_timer
.timer
;
1701 if (hrtimer_cancel(timer
))
1702 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS
);
1706 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1708 * Detect whether guest triggered PV EOI since the
1709 * last entry. If yes, set EOI on guests's behalf.
1710 * Clear PV EOI in guest memory in any case.
1712 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu
*vcpu
,
1713 struct kvm_lapic
*apic
)
1718 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1719 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1721 * KVM_APIC_PV_EOI_PENDING is unset:
1722 * -> host disabled PV EOI.
1723 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1724 * -> host enabled PV EOI, guest did not execute EOI yet.
1725 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1726 * -> host enabled PV EOI, guest executed EOI.
1728 BUG_ON(!pv_eoi_enabled(vcpu
));
1729 pending
= pv_eoi_get_pending(vcpu
);
1731 * Clear pending bit in any case: it will be set again on vmentry.
1732 * While this might not be ideal from performance point of view,
1733 * this makes sure pv eoi is only enabled when we know it's safe.
1735 pv_eoi_clr_pending(vcpu
);
1738 vector
= apic_set_eoi(apic
);
1739 trace_kvm_pv_eoi(apic
, vector
);
1742 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
1746 if (test_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
))
1747 apic_sync_pv_eoi_from_guest(vcpu
, vcpu
->arch
.apic
);
1749 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1752 kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1755 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
1759 * apic_sync_pv_eoi_to_guest - called before vmentry
1761 * Detect whether it's safe to enable PV EOI and
1764 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu
*vcpu
,
1765 struct kvm_lapic
*apic
)
1767 if (!pv_eoi_enabled(vcpu
) ||
1768 /* IRR set or many bits in ISR: could be nested. */
1769 apic
->irr_pending
||
1770 /* Cache not set: could be safe but we don't bother. */
1771 apic
->highest_isr_cache
== -1 ||
1772 /* Need EOI to update ioapic. */
1773 kvm_ioapic_handles_vector(vcpu
->kvm
, apic
->highest_isr_cache
)) {
1775 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1776 * so we need not do anything here.
1781 pv_eoi_set_pending(apic
->vcpu
);
1784 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
1787 int max_irr
, max_isr
;
1788 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1790 apic_sync_pv_eoi_to_guest(vcpu
, apic
);
1792 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1795 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
1796 max_irr
= apic_find_highest_irr(apic
);
1799 max_isr
= apic_find_highest_isr(apic
);
1802 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
1804 kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1808 int kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
1811 if (kvm_gfn_to_hva_cache_init(vcpu
->kvm
,
1812 &vcpu
->arch
.apic
->vapic_cache
,
1813 vapic_addr
, sizeof(u32
)))
1815 __set_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1817 __clear_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1820 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
1824 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
1826 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1827 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
1829 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1832 /* if this is ICR write vector before command */
1834 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1835 return apic_reg_write(apic
, reg
, (u32
)data
);
1838 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
1840 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1841 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
1843 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1846 if (apic_reg_read(apic
, reg
, 4, &low
))
1849 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1851 *data
= (((u64
)high
) << 32) | low
;
1856 int kvm_hv_vapic_msr_write(struct kvm_vcpu
*vcpu
, u32 reg
, u64 data
)
1858 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1860 if (!kvm_vcpu_has_lapic(vcpu
))
1863 /* if this is ICR write vector before command */
1864 if (reg
== APIC_ICR
)
1865 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1866 return apic_reg_write(apic
, reg
, (u32
)data
);
1869 int kvm_hv_vapic_msr_read(struct kvm_vcpu
*vcpu
, u32 reg
, u64
*data
)
1871 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1874 if (!kvm_vcpu_has_lapic(vcpu
))
1877 if (apic_reg_read(apic
, reg
, 4, &low
))
1879 if (reg
== APIC_ICR
)
1880 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1882 *data
= (((u64
)high
) << 32) | low
;
1887 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu
*vcpu
, u64 data
)
1889 u64 addr
= data
& ~KVM_MSR_ENABLED
;
1890 if (!IS_ALIGNED(addr
, 4))
1893 vcpu
->arch
.pv_eoi
.msr_val
= data
;
1894 if (!pv_eoi_enabled(vcpu
))
1896 return kvm_gfn_to_hva_cache_init(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
,
1900 void kvm_apic_accept_events(struct kvm_vcpu
*vcpu
)
1902 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1903 unsigned int sipi_vector
;
1906 if (!kvm_vcpu_has_lapic(vcpu
) || !apic
->pending_events
)
1909 pe
= xchg(&apic
->pending_events
, 0);
1911 if (test_bit(KVM_APIC_INIT
, &pe
)) {
1912 kvm_lapic_reset(vcpu
);
1913 kvm_vcpu_reset(vcpu
);
1914 if (kvm_vcpu_is_bsp(apic
->vcpu
))
1915 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
1917 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
1919 if (test_bit(KVM_APIC_SIPI
, &pe
) &&
1920 vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
1921 /* evaluate pending_events before reading the vector */
1923 sipi_vector
= apic
->sipi_vector
;
1924 apic_debug("vcpu %d received sipi with vector # %x\n",
1925 vcpu
->vcpu_id
, sipi_vector
);
1926 kvm_vcpu_deliver_sipi_vector(vcpu
, sipi_vector
);
1927 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
1931 void kvm_lapic_init(void)
1933 /* do not patch jump label more than once per second */
1934 jump_label_rate_limit(&apic_hw_disabled
, HZ
);
1935 jump_label_rate_limit(&apic_sw_disabled
, HZ
);