3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <linux/atomic.h>
37 #include <linux/jump_label.h>
38 #include "kvm_cache_regs.h"
45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #define mod_64(x, y) ((x) % (y))
55 #define APIC_BUS_CYCLE_NS 1
57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58 #define apic_debug(fmt, arg...)
60 #define APIC_LVT_NUM 6
61 /* 14 is the version for Xeon and Pentium 8.4.8*/
62 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63 #define LAPIC_MMIO_LENGTH (1 << 12)
64 /* followed define is not in apicdef.h */
65 #define APIC_SHORT_MASK 0xc0000
66 #define APIC_DEST_NOSHORT 0x0
67 #define APIC_DEST_MASK 0x800
68 #define MAX_APIC_VECTOR 256
69 #define APIC_VECTORS_PER_REG 32
71 #define APIC_BROADCAST 0xFF
72 #define X2APIC_BROADCAST 0xFFFFFFFFul
74 #define VEC_POS(v) ((v) & (32 - 1))
75 #define REG_POS(v) (((v) >> 5) << 4)
77 static inline void apic_set_reg(struct kvm_lapic
*apic
, int reg_off
, u32 val
)
79 *((u32
*) (apic
->regs
+ reg_off
)) = val
;
82 static inline int apic_test_vector(int vec
, void *bitmap
)
84 return test_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
87 bool kvm_apic_pending_eoi(struct kvm_vcpu
*vcpu
, int vector
)
89 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
91 return apic_test_vector(vector
, apic
->regs
+ APIC_ISR
) ||
92 apic_test_vector(vector
, apic
->regs
+ APIC_IRR
);
95 static inline void apic_set_vector(int vec
, void *bitmap
)
97 set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
100 static inline void apic_clear_vector(int vec
, void *bitmap
)
102 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
105 static inline int __apic_test_and_set_vector(int vec
, void *bitmap
)
107 return __test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
110 static inline int __apic_test_and_clear_vector(int vec
, void *bitmap
)
112 return __test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
115 struct static_key_deferred apic_hw_disabled __read_mostly
;
116 struct static_key_deferred apic_sw_disabled __read_mostly
;
118 static inline int apic_enabled(struct kvm_lapic
*apic
)
120 return kvm_apic_sw_enabled(apic
) && kvm_apic_hw_enabled(apic
);
124 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
127 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
128 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130 static inline int kvm_apic_id(struct kvm_lapic
*apic
)
132 return (kvm_apic_get_reg(apic
, APIC_ID
) >> 24) & 0xff;
135 #define KVM_X2APIC_CID_BITS 0
137 static void recalculate_apic_map(struct kvm
*kvm
)
139 struct kvm_apic_map
*new, *old
= NULL
;
140 struct kvm_vcpu
*vcpu
;
143 new = kzalloc(sizeof(struct kvm_apic_map
), GFP_KERNEL
);
145 mutex_lock(&kvm
->arch
.apic_map_lock
);
151 /* flat mode is default */
154 new->lid_mask
= 0xff;
155 new->broadcast
= APIC_BROADCAST
;
157 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
158 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
162 if (!kvm_apic_present(vcpu
))
166 * All APICs have to be configured in the same mode by an OS.
167 * We take advatage of this while building logical id loockup
168 * table. After reset APICs are in xapic/flat mode, so if we
169 * find apic with different setting we assume this is the mode
170 * OS wants all apics to be in; build lookup table accordingly.
172 if (apic_x2apic_mode(apic
)) {
175 new->cid_mask
= (1 << KVM_X2APIC_CID_BITS
) - 1;
176 new->lid_mask
= 0xffff;
177 new->broadcast
= X2APIC_BROADCAST
;
178 } else if (kvm_apic_sw_enabled(apic
) &&
179 !new->cid_mask
/* flat mode */ &&
180 kvm_apic_get_reg(apic
, APIC_DFR
) == APIC_DFR_CLUSTER
) {
186 new->phys_map
[kvm_apic_id(apic
)] = apic
;
188 ldr
= kvm_apic_get_reg(apic
, APIC_LDR
);
189 cid
= apic_cluster_id(new, ldr
);
190 lid
= apic_logical_id(new, ldr
);
193 new->logical_map
[cid
][ffs(lid
) - 1] = apic
;
196 old
= rcu_dereference_protected(kvm
->arch
.apic_map
,
197 lockdep_is_held(&kvm
->arch
.apic_map_lock
));
198 rcu_assign_pointer(kvm
->arch
.apic_map
, new);
199 mutex_unlock(&kvm
->arch
.apic_map_lock
);
204 kvm_vcpu_request_scan_ioapic(kvm
);
207 static inline void apic_set_spiv(struct kvm_lapic
*apic
, u32 val
)
209 u32 prev
= kvm_apic_get_reg(apic
, APIC_SPIV
);
211 apic_set_reg(apic
, APIC_SPIV
, val
);
212 if ((prev
^ val
) & APIC_SPIV_APIC_ENABLED
) {
213 if (val
& APIC_SPIV_APIC_ENABLED
) {
214 static_key_slow_dec_deferred(&apic_sw_disabled
);
215 recalculate_apic_map(apic
->vcpu
->kvm
);
217 static_key_slow_inc(&apic_sw_disabled
.key
);
221 static inline void kvm_apic_set_id(struct kvm_lapic
*apic
, u8 id
)
223 apic_set_reg(apic
, APIC_ID
, id
<< 24);
224 recalculate_apic_map(apic
->vcpu
->kvm
);
227 static inline void kvm_apic_set_ldr(struct kvm_lapic
*apic
, u32 id
)
229 apic_set_reg(apic
, APIC_LDR
, id
);
230 recalculate_apic_map(apic
->vcpu
->kvm
);
233 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
235 return !(kvm_apic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
238 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
240 return kvm_apic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
243 static inline int apic_lvtt_oneshot(struct kvm_lapic
*apic
)
245 return ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
246 apic
->lapic_timer
.timer_mode_mask
) == APIC_LVT_TIMER_ONESHOT
);
249 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
251 return ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
252 apic
->lapic_timer
.timer_mode_mask
) == APIC_LVT_TIMER_PERIODIC
);
255 static inline int apic_lvtt_tscdeadline(struct kvm_lapic
*apic
)
257 return ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
258 apic
->lapic_timer
.timer_mode_mask
) ==
259 APIC_LVT_TIMER_TSCDEADLINE
);
262 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
264 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
267 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
269 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
270 struct kvm_cpuid_entry2
*feat
;
271 u32 v
= APIC_VERSION
;
273 if (!kvm_vcpu_has_lapic(vcpu
))
276 feat
= kvm_find_cpuid_entry(apic
->vcpu
, 0x1, 0);
277 if (feat
&& (feat
->ecx
& (1 << (X86_FEATURE_X2APIC
& 31))))
278 v
|= APIC_LVR_DIRECTED_EOI
;
279 apic_set_reg(apic
, APIC_LVR
, v
);
282 static const unsigned int apic_lvt_mask
[APIC_LVT_NUM
] = {
283 LVT_MASK
, /* part LVTT mask, timer mode mask added at runtime */
284 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
285 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
286 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
287 LVT_MASK
/* LVTERR */
290 static int find_highest_vector(void *bitmap
)
295 for (vec
= MAX_APIC_VECTOR
- APIC_VECTORS_PER_REG
;
296 vec
>= 0; vec
-= APIC_VECTORS_PER_REG
) {
297 reg
= bitmap
+ REG_POS(vec
);
299 return fls(*reg
) - 1 + vec
;
305 static u8
count_vectors(void *bitmap
)
311 for (vec
= 0; vec
< MAX_APIC_VECTOR
; vec
+= APIC_VECTORS_PER_REG
) {
312 reg
= bitmap
+ REG_POS(vec
);
313 count
+= hweight32(*reg
);
319 void kvm_apic_update_irr(struct kvm_vcpu
*vcpu
, u32
*pir
)
322 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
324 for (i
= 0; i
<= 7; i
++) {
325 pir_val
= xchg(&pir
[i
], 0);
327 *((u32
*)(apic
->regs
+ APIC_IRR
+ i
* 0x10)) |= pir_val
;
330 EXPORT_SYMBOL_GPL(kvm_apic_update_irr
);
332 static inline void apic_set_irr(int vec
, struct kvm_lapic
*apic
)
334 apic
->irr_pending
= true;
335 apic_set_vector(vec
, apic
->regs
+ APIC_IRR
);
338 static inline int apic_search_irr(struct kvm_lapic
*apic
)
340 return find_highest_vector(apic
->regs
+ APIC_IRR
);
343 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
348 * Note that irr_pending is just a hint. It will be always
349 * true with virtual interrupt delivery enabled.
351 if (!apic
->irr_pending
)
354 kvm_x86_ops
->sync_pir_to_irr(apic
->vcpu
);
355 result
= apic_search_irr(apic
);
356 ASSERT(result
== -1 || result
>= 16);
361 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
363 struct kvm_vcpu
*vcpu
;
367 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
368 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
)))
369 /* try to update RVI */
370 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
372 vec
= apic_search_irr(apic
);
373 apic
->irr_pending
= (vec
!= -1);
377 static inline void apic_set_isr(int vec
, struct kvm_lapic
*apic
)
379 struct kvm_vcpu
*vcpu
;
381 if (__apic_test_and_set_vector(vec
, apic
->regs
+ APIC_ISR
))
387 * With APIC virtualization enabled, all caching is disabled
388 * because the processor can modify ISR under the hood. Instead
391 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
)))
392 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, vec
);
395 BUG_ON(apic
->isr_count
> MAX_APIC_VECTOR
);
397 * ISR (in service register) bit is set when injecting an interrupt.
398 * The highest vector is injected. Thus the latest bit set matches
399 * the highest bit in ISR.
401 apic
->highest_isr_cache
= vec
;
405 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
410 * Note that isr_count is always 1, and highest_isr_cache
411 * is always -1, with APIC virtualization enabled.
413 if (!apic
->isr_count
)
415 if (likely(apic
->highest_isr_cache
!= -1))
416 return apic
->highest_isr_cache
;
418 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
419 ASSERT(result
== -1 || result
>= 16);
424 static inline void apic_clear_isr(int vec
, struct kvm_lapic
*apic
)
426 struct kvm_vcpu
*vcpu
;
427 if (!__apic_test_and_clear_vector(vec
, apic
->regs
+ APIC_ISR
))
433 * We do get here for APIC virtualization enabled if the guest
434 * uses the Hyper-V APIC enlightenment. In this case we may need
435 * to trigger a new interrupt delivery by writing the SVI field;
436 * on the other hand isr_count and highest_isr_cache are unused
437 * and must be left alone.
439 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
)))
440 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
,
441 apic_find_highest_isr(apic
));
444 BUG_ON(apic
->isr_count
< 0);
445 apic
->highest_isr_cache
= -1;
449 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
453 /* This may race with setting of irr in __apic_accept_irq() and
454 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
455 * will cause vmexit immediately and the value will be recalculated
456 * on the next vmentry.
458 if (!kvm_vcpu_has_lapic(vcpu
))
460 highest_irr
= apic_find_highest_irr(vcpu
->arch
.apic
);
465 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
466 int vector
, int level
, int trig_mode
,
467 unsigned long *dest_map
);
469 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
,
470 unsigned long *dest_map
)
472 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
474 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
475 irq
->level
, irq
->trig_mode
, dest_map
);
478 static int pv_eoi_put_user(struct kvm_vcpu
*vcpu
, u8 val
)
481 return kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, &val
,
485 static int pv_eoi_get_user(struct kvm_vcpu
*vcpu
, u8
*val
)
488 return kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, val
,
492 static inline bool pv_eoi_enabled(struct kvm_vcpu
*vcpu
)
494 return vcpu
->arch
.pv_eoi
.msr_val
& KVM_MSR_ENABLED
;
497 static bool pv_eoi_get_pending(struct kvm_vcpu
*vcpu
)
500 if (pv_eoi_get_user(vcpu
, &val
) < 0)
501 apic_debug("Can't read EOI MSR value: 0x%llx\n",
502 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
506 static void pv_eoi_set_pending(struct kvm_vcpu
*vcpu
)
508 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_ENABLED
) < 0) {
509 apic_debug("Can't set EOI MSR value: 0x%llx\n",
510 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
513 __set_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
516 static void pv_eoi_clr_pending(struct kvm_vcpu
*vcpu
)
518 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_DISABLED
) < 0) {
519 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
520 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
523 __clear_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
526 void kvm_apic_update_tmr(struct kvm_vcpu
*vcpu
, u32
*tmr
)
528 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
531 for (i
= 0; i
< 8; i
++)
532 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, tmr
[i
]);
535 static void apic_update_ppr(struct kvm_lapic
*apic
)
537 u32 tpr
, isrv
, ppr
, old_ppr
;
540 old_ppr
= kvm_apic_get_reg(apic
, APIC_PROCPRI
);
541 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
);
542 isr
= apic_find_highest_isr(apic
);
543 isrv
= (isr
!= -1) ? isr
: 0;
545 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
550 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
551 apic
, ppr
, isr
, isrv
);
553 if (old_ppr
!= ppr
) {
554 apic_set_reg(apic
, APIC_PROCPRI
, ppr
);
556 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
560 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
562 apic_set_reg(apic
, APIC_TASKPRI
, tpr
);
563 apic_update_ppr(apic
);
566 static int kvm_apic_broadcast(struct kvm_lapic
*apic
, u32 dest
)
568 return dest
== (apic_x2apic_mode(apic
) ?
569 X2APIC_BROADCAST
: APIC_BROADCAST
);
572 int kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u32 dest
)
574 return kvm_apic_id(apic
) == dest
|| kvm_apic_broadcast(apic
, dest
);
577 int kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u32 mda
)
582 if (kvm_apic_broadcast(apic
, mda
))
585 if (apic_x2apic_mode(apic
)) {
586 logical_id
= kvm_apic_get_reg(apic
, APIC_LDR
);
587 return logical_id
& mda
;
590 logical_id
= GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic
, APIC_LDR
));
592 switch (kvm_apic_get_reg(apic
, APIC_DFR
)) {
594 if (logical_id
& mda
)
597 case APIC_DFR_CLUSTER
:
598 if (((logical_id
>> 4) == (mda
>> 0x4))
599 && (logical_id
& mda
& 0xf))
603 apic_debug("Bad DFR vcpu %d: %08x\n",
604 apic
->vcpu
->vcpu_id
, kvm_apic_get_reg(apic
, APIC_DFR
));
611 int kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
612 int short_hand
, unsigned int dest
, int dest_mode
)
615 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
617 apic_debug("target %p, source %p, dest 0x%x, "
618 "dest_mode 0x%x, short_hand 0x%x\n",
619 target
, source
, dest
, dest_mode
, short_hand
);
622 switch (short_hand
) {
623 case APIC_DEST_NOSHORT
:
626 result
= kvm_apic_match_physical_addr(target
, dest
);
629 result
= kvm_apic_match_logical_addr(target
, dest
);
632 result
= (target
== source
);
634 case APIC_DEST_ALLINC
:
637 case APIC_DEST_ALLBUT
:
638 result
= (target
!= source
);
641 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
649 bool kvm_irq_delivery_to_apic_fast(struct kvm
*kvm
, struct kvm_lapic
*src
,
650 struct kvm_lapic_irq
*irq
, int *r
, unsigned long *dest_map
)
652 struct kvm_apic_map
*map
;
653 unsigned long bitmap
= 1;
654 struct kvm_lapic
**dst
;
660 if (irq
->shorthand
== APIC_DEST_SELF
) {
661 *r
= kvm_apic_set_irq(src
->vcpu
, irq
, dest_map
);
669 map
= rcu_dereference(kvm
->arch
.apic_map
);
674 if (irq
->dest_id
== map
->broadcast
)
677 if (irq
->dest_mode
== 0) { /* physical mode */
678 if (irq
->delivery_mode
== APIC_DM_LOWEST
)
680 dst
= &map
->phys_map
[irq
->dest_id
& 0xff];
682 u32 mda
= irq
->dest_id
<< (32 - map
->ldr_bits
);
684 dst
= map
->logical_map
[apic_cluster_id(map
, mda
)];
686 bitmap
= apic_logical_id(map
, mda
);
688 if (irq
->delivery_mode
== APIC_DM_LOWEST
) {
690 for_each_set_bit(i
, &bitmap
, 16) {
695 else if (kvm_apic_compare_prio(dst
[i
]->vcpu
, dst
[l
]->vcpu
) < 0)
699 bitmap
= (l
>= 0) ? 1 << l
: 0;
703 for_each_set_bit(i
, &bitmap
, 16) {
708 *r
+= kvm_apic_set_irq(dst
[i
]->vcpu
, irq
, dest_map
);
718 * Add a pending IRQ into lapic.
719 * Return 1 if successfully added and 0 if discarded.
721 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
722 int vector
, int level
, int trig_mode
,
723 unsigned long *dest_map
)
726 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
728 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
730 switch (delivery_mode
) {
732 vcpu
->arch
.apic_arb_prio
++;
734 /* FIXME add logic for vcpu on reset */
735 if (unlikely(!apic_enabled(apic
)))
741 __set_bit(vcpu
->vcpu_id
, dest_map
);
743 if (kvm_x86_ops
->deliver_posted_interrupt
)
744 kvm_x86_ops
->deliver_posted_interrupt(vcpu
, vector
);
746 apic_set_irr(vector
, apic
);
748 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
755 vcpu
->arch
.pv
.pv_unhalted
= 1;
756 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
761 apic_debug("Ignoring guest SMI\n");
766 kvm_inject_nmi(vcpu
);
771 if (!trig_mode
|| level
) {
773 /* assumes that there are only KVM_APIC_INIT/SIPI */
774 apic
->pending_events
= (1UL << KVM_APIC_INIT
);
775 /* make sure pending_events is visible before sending
778 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
781 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
786 case APIC_DM_STARTUP
:
787 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
788 vcpu
->vcpu_id
, vector
);
790 apic
->sipi_vector
= vector
;
791 /* make sure sipi_vector is visible for the receiver */
793 set_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
794 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
800 * Should only be called by kvm_apic_local_deliver() with LVT0,
801 * before NMI watchdog was enabled. Already handled by
802 * kvm_apic_accept_pic_intr().
807 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
814 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
816 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
819 static void kvm_ioapic_send_eoi(struct kvm_lapic
*apic
, int vector
)
821 if (!(kvm_apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_DIRECTED_EOI
) &&
822 kvm_ioapic_handles_vector(apic
->vcpu
->kvm
, vector
)) {
824 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
))
825 trigger_mode
= IOAPIC_LEVEL_TRIG
;
827 trigger_mode
= IOAPIC_EDGE_TRIG
;
828 kvm_ioapic_update_eoi(apic
->vcpu
, vector
, trigger_mode
);
832 static int apic_set_eoi(struct kvm_lapic
*apic
)
834 int vector
= apic_find_highest_isr(apic
);
836 trace_kvm_eoi(apic
, vector
);
839 * Not every write EOI will has corresponding ISR,
840 * one example is when Kernel check timer on setup_IO_APIC
845 apic_clear_isr(vector
, apic
);
846 apic_update_ppr(apic
);
848 kvm_ioapic_send_eoi(apic
, vector
);
849 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
854 * this interface assumes a trap-like exit, which has already finished
855 * desired side effect including vISR and vPPR update.
857 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu
*vcpu
, int vector
)
859 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
861 trace_kvm_eoi(apic
, vector
);
863 kvm_ioapic_send_eoi(apic
, vector
);
864 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
866 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated
);
868 static void apic_send_ipi(struct kvm_lapic
*apic
)
870 u32 icr_low
= kvm_apic_get_reg(apic
, APIC_ICR
);
871 u32 icr_high
= kvm_apic_get_reg(apic
, APIC_ICR2
);
872 struct kvm_lapic_irq irq
;
874 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
875 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
876 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
877 irq
.level
= icr_low
& APIC_INT_ASSERT
;
878 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
879 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
880 if (apic_x2apic_mode(apic
))
881 irq
.dest_id
= icr_high
;
883 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
885 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
887 apic_debug("icr_high 0x%x, icr_low 0x%x, "
888 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
889 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
890 icr_high
, icr_low
, irq
.shorthand
, irq
.dest_id
,
891 irq
.trig_mode
, irq
.level
, irq
.dest_mode
, irq
.delivery_mode
,
894 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
, NULL
);
897 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
903 ASSERT(apic
!= NULL
);
905 /* if initial count is 0, current count should also be 0 */
906 if (kvm_apic_get_reg(apic
, APIC_TMICT
) == 0 ||
907 apic
->lapic_timer
.period
== 0)
910 remaining
= hrtimer_get_remaining(&apic
->lapic_timer
.timer
);
911 if (ktime_to_ns(remaining
) < 0)
912 remaining
= ktime_set(0, 0);
914 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
915 tmcct
= div64_u64(ns
,
916 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
921 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
923 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
924 struct kvm_run
*run
= vcpu
->run
;
926 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS
, vcpu
);
927 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
928 run
->tpr_access
.is_write
= write
;
931 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
933 if (apic
->vcpu
->arch
.tpr_access_reporting
)
934 __report_tpr_access(apic
, write
);
937 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
941 if (offset
>= LAPIC_MMIO_LENGTH
)
946 if (apic_x2apic_mode(apic
))
947 val
= kvm_apic_id(apic
);
949 val
= kvm_apic_id(apic
) << 24;
952 apic_debug("Access APIC ARBPRI register which is for P6\n");
955 case APIC_TMCCT
: /* Timer CCR */
956 if (apic_lvtt_tscdeadline(apic
))
959 val
= apic_get_tmcct(apic
);
962 apic_update_ppr(apic
);
963 val
= kvm_apic_get_reg(apic
, offset
);
966 report_tpr_access(apic
, false);
969 val
= kvm_apic_get_reg(apic
, offset
);
976 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
978 return container_of(dev
, struct kvm_lapic
, dev
);
981 static int apic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
984 unsigned char alignment
= offset
& 0xf;
986 /* this bitmask has a bit cleared for each reserved register */
987 static const u64 rmask
= 0x43ff01ffffffe70cULL
;
989 if ((alignment
+ len
) > 4) {
990 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
995 if (offset
> 0x3f0 || !(rmask
& (1ULL << (offset
>> 4)))) {
996 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1001 result
= __apic_read(apic
, offset
& ~0xf);
1003 trace_kvm_apic_read(offset
, result
);
1009 memcpy(data
, (char *)&result
+ alignment
, len
);
1012 printk(KERN_ERR
"Local APIC read with len = %x, "
1013 "should be 1,2, or 4 instead\n", len
);
1019 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
1021 return kvm_apic_hw_enabled(apic
) &&
1022 addr
>= apic
->base_address
&&
1023 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
1026 static int apic_mmio_read(struct kvm_io_device
*this,
1027 gpa_t address
, int len
, void *data
)
1029 struct kvm_lapic
*apic
= to_lapic(this);
1030 u32 offset
= address
- apic
->base_address
;
1032 if (!apic_mmio_in_range(apic
, address
))
1035 apic_reg_read(apic
, offset
, len
, data
);
1040 static void update_divide_count(struct kvm_lapic
*apic
)
1042 u32 tmp1
, tmp2
, tdcr
;
1044 tdcr
= kvm_apic_get_reg(apic
, APIC_TDCR
);
1046 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
1047 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
1049 apic_debug("timer divide count is 0x%x\n",
1050 apic
->divide_count
);
1053 static void apic_timer_expired(struct kvm_lapic
*apic
)
1055 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1056 wait_queue_head_t
*q
= &vcpu
->wq
;
1059 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1062 if (atomic_read(&apic
->lapic_timer
.pending
))
1065 atomic_inc(&apic
->lapic_timer
.pending
);
1066 /* FIXME: this code should not know anything about vcpus */
1067 kvm_make_request(KVM_REQ_PENDING_TIMER
, vcpu
);
1069 if (waitqueue_active(q
))
1070 wake_up_interruptible(q
);
1073 static void start_apic_timer(struct kvm_lapic
*apic
)
1076 atomic_set(&apic
->lapic_timer
.pending
, 0);
1078 if (apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
)) {
1079 /* lapic timer in oneshot or periodic mode */
1080 now
= apic
->lapic_timer
.timer
.base
->get_time();
1081 apic
->lapic_timer
.period
= (u64
)kvm_apic_get_reg(apic
, APIC_TMICT
)
1082 * APIC_BUS_CYCLE_NS
* apic
->divide_count
;
1084 if (!apic
->lapic_timer
.period
)
1087 * Do not allow the guest to program periodic timers with small
1088 * interval, since the hrtimers are not throttled by the host
1091 if (apic_lvtt_period(apic
)) {
1092 s64 min_period
= min_timer_period_us
* 1000LL;
1094 if (apic
->lapic_timer
.period
< min_period
) {
1095 pr_info_ratelimited(
1096 "kvm: vcpu %i: requested %lld ns "
1097 "lapic timer period limited to %lld ns\n",
1098 apic
->vcpu
->vcpu_id
,
1099 apic
->lapic_timer
.period
, min_period
);
1100 apic
->lapic_timer
.period
= min_period
;
1104 hrtimer_start(&apic
->lapic_timer
.timer
,
1105 ktime_add_ns(now
, apic
->lapic_timer
.period
),
1108 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
1110 "timer initial count 0x%x, period %lldns, "
1111 "expire @ 0x%016" PRIx64
".\n", __func__
,
1112 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
1113 kvm_apic_get_reg(apic
, APIC_TMICT
),
1114 apic
->lapic_timer
.period
,
1115 ktime_to_ns(ktime_add_ns(now
,
1116 apic
->lapic_timer
.period
)));
1117 } else if (apic_lvtt_tscdeadline(apic
)) {
1118 /* lapic timer in tsc deadline mode */
1119 u64 guest_tsc
, tscdeadline
= apic
->lapic_timer
.tscdeadline
;
1121 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1122 unsigned long this_tsc_khz
= vcpu
->arch
.virtual_tsc_khz
;
1123 unsigned long flags
;
1125 if (unlikely(!tscdeadline
|| !this_tsc_khz
))
1128 local_irq_save(flags
);
1130 now
= apic
->lapic_timer
.timer
.base
->get_time();
1131 guest_tsc
= kvm_x86_ops
->read_l1_tsc(vcpu
, native_read_tsc());
1132 if (likely(tscdeadline
> guest_tsc
)) {
1133 ns
= (tscdeadline
- guest_tsc
) * 1000000ULL;
1134 do_div(ns
, this_tsc_khz
);
1136 hrtimer_start(&apic
->lapic_timer
.timer
,
1137 ktime_add_ns(now
, ns
), HRTIMER_MODE_ABS
);
1139 local_irq_restore(flags
);
1143 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
1145 int nmi_wd_enabled
= apic_lvt_nmi_mode(kvm_apic_get_reg(apic
, APIC_LVT0
));
1147 if (apic_lvt_nmi_mode(lvt0_val
)) {
1148 if (!nmi_wd_enabled
) {
1149 apic_debug("Receive NMI setting on APIC_LVT0 "
1150 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
1151 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
++;
1153 } else if (nmi_wd_enabled
)
1154 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
--;
1157 static int apic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
1161 trace_kvm_apic_write(reg
, val
);
1164 case APIC_ID
: /* Local APIC ID */
1165 if (!apic_x2apic_mode(apic
))
1166 kvm_apic_set_id(apic
, val
>> 24);
1172 report_tpr_access(apic
, true);
1173 apic_set_tpr(apic
, val
& 0xff);
1181 if (!apic_x2apic_mode(apic
))
1182 kvm_apic_set_ldr(apic
, val
& APIC_LDR_MASK
);
1188 if (!apic_x2apic_mode(apic
)) {
1189 apic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
1190 recalculate_apic_map(apic
->vcpu
->kvm
);
1197 if (kvm_apic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
1198 mask
|= APIC_SPIV_DIRECTED_EOI
;
1199 apic_set_spiv(apic
, val
& mask
);
1200 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
1204 for (i
= 0; i
< APIC_LVT_NUM
; i
++) {
1205 lvt_val
= kvm_apic_get_reg(apic
,
1206 APIC_LVTT
+ 0x10 * i
);
1207 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
1208 lvt_val
| APIC_LVT_MASKED
);
1210 atomic_set(&apic
->lapic_timer
.pending
, 0);
1216 /* No delay here, so we always clear the pending bit */
1217 apic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
1218 apic_send_ipi(apic
);
1222 if (!apic_x2apic_mode(apic
))
1224 apic_set_reg(apic
, APIC_ICR2
, val
);
1228 apic_manage_nmi_watchdog(apic
, val
);
1233 /* TODO: Check vector */
1234 if (!kvm_apic_sw_enabled(apic
))
1235 val
|= APIC_LVT_MASKED
;
1237 val
&= apic_lvt_mask
[(reg
- APIC_LVTT
) >> 4];
1238 apic_set_reg(apic
, reg
, val
);
1243 if ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
1244 apic
->lapic_timer
.timer_mode_mask
) !=
1245 (val
& apic
->lapic_timer
.timer_mode_mask
))
1246 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1248 if (!kvm_apic_sw_enabled(apic
))
1249 val
|= APIC_LVT_MASKED
;
1250 val
&= (apic_lvt_mask
[0] | apic
->lapic_timer
.timer_mode_mask
);
1251 apic_set_reg(apic
, APIC_LVTT
, val
);
1255 if (apic_lvtt_tscdeadline(apic
))
1258 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1259 apic_set_reg(apic
, APIC_TMICT
, val
);
1260 start_apic_timer(apic
);
1265 apic_debug("KVM_WRITE:TDCR %x\n", val
);
1266 apic_set_reg(apic
, APIC_TDCR
, val
);
1267 update_divide_count(apic
);
1271 if (apic_x2apic_mode(apic
) && val
!= 0) {
1272 apic_debug("KVM_WRITE:ESR not zero %x\n", val
);
1278 if (apic_x2apic_mode(apic
)) {
1279 apic_reg_write(apic
, APIC_ICR
, 0x40000 | (val
& 0xff));
1288 apic_debug("Local APIC Write to read-only register %x\n", reg
);
1292 static int apic_mmio_write(struct kvm_io_device
*this,
1293 gpa_t address
, int len
, const void *data
)
1295 struct kvm_lapic
*apic
= to_lapic(this);
1296 unsigned int offset
= address
- apic
->base_address
;
1299 if (!apic_mmio_in_range(apic
, address
))
1303 * APIC register must be aligned on 128-bits boundary.
1304 * 32/64/128 bits registers must be accessed thru 32 bits.
1307 if (len
!= 4 || (offset
& 0xf)) {
1308 /* Don't shout loud, $infamous_os would cause only noise. */
1309 apic_debug("apic write: bad size=%d %lx\n", len
, (long)address
);
1315 /* too common printing */
1316 if (offset
!= APIC_EOI
)
1317 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1318 "0x%x\n", __func__
, offset
, len
, val
);
1320 apic_reg_write(apic
, offset
& 0xff0, val
);
1325 void kvm_lapic_set_eoi(struct kvm_vcpu
*vcpu
)
1327 if (kvm_vcpu_has_lapic(vcpu
))
1328 apic_reg_write(vcpu
->arch
.apic
, APIC_EOI
, 0);
1330 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi
);
1332 /* emulate APIC access in a trap manner */
1333 void kvm_apic_write_nodecode(struct kvm_vcpu
*vcpu
, u32 offset
)
1337 /* hw has done the conditional check and inst decode */
1340 apic_reg_read(vcpu
->arch
.apic
, offset
, 4, &val
);
1342 /* TODO: optimize to just emulate side effect w/o one more write */
1343 apic_reg_write(vcpu
->arch
.apic
, offset
, val
);
1345 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode
);
1347 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
1349 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1351 if (!vcpu
->arch
.apic
)
1354 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1356 if (!(vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
))
1357 static_key_slow_dec_deferred(&apic_hw_disabled
);
1359 if (!(kvm_apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_APIC_ENABLED
))
1360 static_key_slow_dec_deferred(&apic_sw_disabled
);
1363 free_page((unsigned long)apic
->regs
);
1369 *----------------------------------------------------------------------
1371 *----------------------------------------------------------------------
1374 u64
kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
)
1376 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1378 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1379 apic_lvtt_period(apic
))
1382 return apic
->lapic_timer
.tscdeadline
;
1385 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
, u64 data
)
1387 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1389 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1390 apic_lvtt_period(apic
))
1393 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1394 /* Inject here so clearing tscdeadline won't override new value */
1395 if (apic_has_pending_timer(vcpu
))
1396 kvm_inject_apic_timer_irqs(vcpu
);
1397 apic
->lapic_timer
.tscdeadline
= data
;
1398 start_apic_timer(apic
);
1401 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
1403 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1405 if (!kvm_vcpu_has_lapic(vcpu
))
1408 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
1409 | (kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 4));
1412 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
1416 if (!kvm_vcpu_has_lapic(vcpu
))
1419 tpr
= (u64
) kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_TASKPRI
);
1421 return (tpr
& 0xf0) >> 4;
1424 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
1426 u64 old_value
= vcpu
->arch
.apic_base
;
1427 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1430 value
|= MSR_IA32_APICBASE_BSP
;
1431 vcpu
->arch
.apic_base
= value
;
1435 if (!kvm_vcpu_is_bsp(apic
->vcpu
))
1436 value
&= ~MSR_IA32_APICBASE_BSP
;
1437 vcpu
->arch
.apic_base
= value
;
1439 /* update jump label if enable bit changes */
1440 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
) {
1441 if (value
& MSR_IA32_APICBASE_ENABLE
)
1442 static_key_slow_dec_deferred(&apic_hw_disabled
);
1444 static_key_slow_inc(&apic_hw_disabled
.key
);
1445 recalculate_apic_map(vcpu
->kvm
);
1448 if ((old_value
^ value
) & X2APIC_ENABLE
) {
1449 if (value
& X2APIC_ENABLE
) {
1450 u32 id
= kvm_apic_id(apic
);
1451 u32 ldr
= ((id
>> 4) << 16) | (1 << (id
& 0xf));
1452 kvm_apic_set_ldr(apic
, ldr
);
1453 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, true);
1455 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, false);
1458 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
1459 MSR_IA32_APICBASE_BASE
;
1461 /* with FSB delivery interrupt, we can restart APIC functionality */
1462 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
1463 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
1467 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
)
1469 struct kvm_lapic
*apic
;
1472 apic_debug("%s\n", __func__
);
1475 apic
= vcpu
->arch
.apic
;
1476 ASSERT(apic
!= NULL
);
1478 /* Stop the timer in case it's a reset to an active apic */
1479 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1481 kvm_apic_set_id(apic
, vcpu
->vcpu_id
);
1482 kvm_apic_set_version(apic
->vcpu
);
1484 for (i
= 0; i
< APIC_LVT_NUM
; i
++)
1485 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
1486 apic_set_reg(apic
, APIC_LVT0
,
1487 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
1489 apic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
1490 apic_set_spiv(apic
, 0xff);
1491 apic_set_reg(apic
, APIC_TASKPRI
, 0);
1492 kvm_apic_set_ldr(apic
, 0);
1493 apic_set_reg(apic
, APIC_ESR
, 0);
1494 apic_set_reg(apic
, APIC_ICR
, 0);
1495 apic_set_reg(apic
, APIC_ICR2
, 0);
1496 apic_set_reg(apic
, APIC_TDCR
, 0);
1497 apic_set_reg(apic
, APIC_TMICT
, 0);
1498 for (i
= 0; i
< 8; i
++) {
1499 apic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
1500 apic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
1501 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
1503 apic
->irr_pending
= kvm_apic_vid_enabled(vcpu
->kvm
);
1504 apic
->isr_count
= kvm_apic_vid_enabled(vcpu
->kvm
);
1505 apic
->highest_isr_cache
= -1;
1506 update_divide_count(apic
);
1507 atomic_set(&apic
->lapic_timer
.pending
, 0);
1508 if (kvm_vcpu_is_bsp(vcpu
))
1509 kvm_lapic_set_base(vcpu
,
1510 vcpu
->arch
.apic_base
| MSR_IA32_APICBASE_BSP
);
1511 vcpu
->arch
.pv_eoi
.msr_val
= 0;
1512 apic_update_ppr(apic
);
1514 vcpu
->arch
.apic_arb_prio
= 0;
1515 vcpu
->arch
.apic_attention
= 0;
1517 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1518 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
1519 vcpu
, kvm_apic_id(apic
),
1520 vcpu
->arch
.apic_base
, apic
->base_address
);
1524 *----------------------------------------------------------------------
1526 *----------------------------------------------------------------------
1529 static bool lapic_is_periodic(struct kvm_lapic
*apic
)
1531 return apic_lvtt_period(apic
);
1534 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
1536 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1538 if (kvm_vcpu_has_lapic(vcpu
) && apic_enabled(apic
) &&
1539 apic_lvt_enabled(apic
, APIC_LVTT
))
1540 return atomic_read(&apic
->lapic_timer
.pending
);
1545 int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
1547 u32 reg
= kvm_apic_get_reg(apic
, lvt_type
);
1548 int vector
, mode
, trig_mode
;
1550 if (kvm_apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
1551 vector
= reg
& APIC_VECTOR_MASK
;
1552 mode
= reg
& APIC_MODE_MASK
;
1553 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
1554 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
,
1560 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
1562 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1565 kvm_apic_local_deliver(apic
, APIC_LVT0
);
1568 static const struct kvm_io_device_ops apic_mmio_ops
= {
1569 .read
= apic_mmio_read
,
1570 .write
= apic_mmio_write
,
1573 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
1575 struct kvm_timer
*ktimer
= container_of(data
, struct kvm_timer
, timer
);
1576 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
, lapic_timer
);
1578 apic_timer_expired(apic
);
1580 if (lapic_is_periodic(apic
)) {
1581 hrtimer_add_expires_ns(&ktimer
->timer
, ktimer
->period
);
1582 return HRTIMER_RESTART
;
1584 return HRTIMER_NORESTART
;
1587 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
1589 struct kvm_lapic
*apic
;
1591 ASSERT(vcpu
!= NULL
);
1592 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
1594 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
1598 vcpu
->arch
.apic
= apic
;
1600 apic
->regs
= (void *)get_zeroed_page(GFP_KERNEL
);
1602 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
1604 goto nomem_free_apic
;
1608 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
1610 apic
->lapic_timer
.timer
.function
= apic_timer_fn
;
1613 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1614 * thinking that APIC satet has changed.
1616 vcpu
->arch
.apic_base
= MSR_IA32_APICBASE_ENABLE
;
1617 kvm_lapic_set_base(vcpu
,
1618 APIC_DEFAULT_PHYS_BASE
| MSR_IA32_APICBASE_ENABLE
);
1620 static_key_slow_inc(&apic_sw_disabled
.key
); /* sw disabled at reset */
1621 kvm_lapic_reset(vcpu
);
1622 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
1631 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
1633 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1636 if (!kvm_vcpu_has_lapic(vcpu
) || !apic_enabled(apic
))
1639 apic_update_ppr(apic
);
1640 highest_irr
= apic_find_highest_irr(apic
);
1641 if ((highest_irr
== -1) ||
1642 ((highest_irr
& 0xF0) <= kvm_apic_get_reg(apic
, APIC_PROCPRI
)))
1647 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
1649 u32 lvt0
= kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
1652 if (!kvm_apic_hw_enabled(vcpu
->arch
.apic
))
1654 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
1655 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
1660 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
1662 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1664 if (!kvm_vcpu_has_lapic(vcpu
))
1667 if (atomic_read(&apic
->lapic_timer
.pending
) > 0) {
1668 kvm_apic_local_deliver(apic
, APIC_LVTT
);
1669 if (apic_lvtt_tscdeadline(apic
))
1670 apic
->lapic_timer
.tscdeadline
= 0;
1671 atomic_set(&apic
->lapic_timer
.pending
, 0);
1675 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
1677 int vector
= kvm_apic_has_interrupt(vcpu
);
1678 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1684 * We get here even with APIC virtualization enabled, if doing
1685 * nested virtualization and L1 runs with the "acknowledge interrupt
1686 * on exit" mode. Then we cannot inject the interrupt via RVI,
1687 * because the process would deliver it through the IDT.
1690 apic_set_isr(vector
, apic
);
1691 apic_update_ppr(apic
);
1692 apic_clear_irr(vector
, apic
);
1696 void kvm_apic_post_state_restore(struct kvm_vcpu
*vcpu
,
1697 struct kvm_lapic_state
*s
)
1699 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1701 kvm_lapic_set_base(vcpu
, vcpu
->arch
.apic_base
);
1702 /* set SPIV separately to get count of SW disabled APICs right */
1703 apic_set_spiv(apic
, *((u32
*)(s
->regs
+ APIC_SPIV
)));
1704 memcpy(vcpu
->arch
.apic
->regs
, s
->regs
, sizeof *s
);
1705 /* call kvm_apic_set_id() to put apic into apic_map */
1706 kvm_apic_set_id(apic
, kvm_apic_id(apic
));
1707 kvm_apic_set_version(vcpu
);
1709 apic_update_ppr(apic
);
1710 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1711 update_divide_count(apic
);
1712 start_apic_timer(apic
);
1713 apic
->irr_pending
= true;
1714 apic
->isr_count
= kvm_apic_vid_enabled(vcpu
->kvm
) ?
1715 1 : count_vectors(apic
->regs
+ APIC_ISR
);
1716 apic
->highest_isr_cache
= -1;
1717 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, apic_find_highest_isr(apic
));
1718 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1719 kvm_rtc_eoi_tracking_restore_one(vcpu
);
1722 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
1724 struct hrtimer
*timer
;
1726 if (!kvm_vcpu_has_lapic(vcpu
))
1729 timer
= &vcpu
->arch
.apic
->lapic_timer
.timer
;
1730 if (hrtimer_cancel(timer
))
1731 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS
);
1735 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1737 * Detect whether guest triggered PV EOI since the
1738 * last entry. If yes, set EOI on guests's behalf.
1739 * Clear PV EOI in guest memory in any case.
1741 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu
*vcpu
,
1742 struct kvm_lapic
*apic
)
1747 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1748 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1750 * KVM_APIC_PV_EOI_PENDING is unset:
1751 * -> host disabled PV EOI.
1752 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1753 * -> host enabled PV EOI, guest did not execute EOI yet.
1754 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1755 * -> host enabled PV EOI, guest executed EOI.
1757 BUG_ON(!pv_eoi_enabled(vcpu
));
1758 pending
= pv_eoi_get_pending(vcpu
);
1760 * Clear pending bit in any case: it will be set again on vmentry.
1761 * While this might not be ideal from performance point of view,
1762 * this makes sure pv eoi is only enabled when we know it's safe.
1764 pv_eoi_clr_pending(vcpu
);
1767 vector
= apic_set_eoi(apic
);
1768 trace_kvm_pv_eoi(apic
, vector
);
1771 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
1775 if (test_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
))
1776 apic_sync_pv_eoi_from_guest(vcpu
, vcpu
->arch
.apic
);
1778 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1781 kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1784 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
1788 * apic_sync_pv_eoi_to_guest - called before vmentry
1790 * Detect whether it's safe to enable PV EOI and
1793 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu
*vcpu
,
1794 struct kvm_lapic
*apic
)
1796 if (!pv_eoi_enabled(vcpu
) ||
1797 /* IRR set or many bits in ISR: could be nested. */
1798 apic
->irr_pending
||
1799 /* Cache not set: could be safe but we don't bother. */
1800 apic
->highest_isr_cache
== -1 ||
1801 /* Need EOI to update ioapic. */
1802 kvm_ioapic_handles_vector(vcpu
->kvm
, apic
->highest_isr_cache
)) {
1804 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1805 * so we need not do anything here.
1810 pv_eoi_set_pending(apic
->vcpu
);
1813 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
1816 int max_irr
, max_isr
;
1817 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1819 apic_sync_pv_eoi_to_guest(vcpu
, apic
);
1821 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1824 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
1825 max_irr
= apic_find_highest_irr(apic
);
1828 max_isr
= apic_find_highest_isr(apic
);
1831 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
1833 kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1837 int kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
1840 if (kvm_gfn_to_hva_cache_init(vcpu
->kvm
,
1841 &vcpu
->arch
.apic
->vapic_cache
,
1842 vapic_addr
, sizeof(u32
)))
1844 __set_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1846 __clear_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1849 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
1853 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
1855 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1856 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
1858 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1861 /* if this is ICR write vector before command */
1863 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1864 return apic_reg_write(apic
, reg
, (u32
)data
);
1867 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
1869 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1870 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
1872 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1875 if (apic_reg_read(apic
, reg
, 4, &low
))
1878 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1880 *data
= (((u64
)high
) << 32) | low
;
1885 int kvm_hv_vapic_msr_write(struct kvm_vcpu
*vcpu
, u32 reg
, u64 data
)
1887 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1889 if (!kvm_vcpu_has_lapic(vcpu
))
1892 /* if this is ICR write vector before command */
1893 if (reg
== APIC_ICR
)
1894 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1895 return apic_reg_write(apic
, reg
, (u32
)data
);
1898 int kvm_hv_vapic_msr_read(struct kvm_vcpu
*vcpu
, u32 reg
, u64
*data
)
1900 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1903 if (!kvm_vcpu_has_lapic(vcpu
))
1906 if (apic_reg_read(apic
, reg
, 4, &low
))
1908 if (reg
== APIC_ICR
)
1909 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1911 *data
= (((u64
)high
) << 32) | low
;
1916 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu
*vcpu
, u64 data
)
1918 u64 addr
= data
& ~KVM_MSR_ENABLED
;
1919 if (!IS_ALIGNED(addr
, 4))
1922 vcpu
->arch
.pv_eoi
.msr_val
= data
;
1923 if (!pv_eoi_enabled(vcpu
))
1925 return kvm_gfn_to_hva_cache_init(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
,
1929 void kvm_apic_accept_events(struct kvm_vcpu
*vcpu
)
1931 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1932 unsigned int sipi_vector
;
1935 if (!kvm_vcpu_has_lapic(vcpu
) || !apic
->pending_events
)
1938 pe
= xchg(&apic
->pending_events
, 0);
1940 if (test_bit(KVM_APIC_INIT
, &pe
)) {
1941 kvm_lapic_reset(vcpu
);
1942 kvm_vcpu_reset(vcpu
);
1943 if (kvm_vcpu_is_bsp(apic
->vcpu
))
1944 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
1946 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
1948 if (test_bit(KVM_APIC_SIPI
, &pe
) &&
1949 vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
1950 /* evaluate pending_events before reading the vector */
1952 sipi_vector
= apic
->sipi_vector
;
1953 apic_debug("vcpu %d received sipi with vector # %x\n",
1954 vcpu
->vcpu_id
, sipi_vector
);
1955 kvm_vcpu_deliver_sipi_vector(vcpu
, sipi_vector
);
1956 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
1960 void kvm_lapic_init(void)
1962 /* do not patch jump label more than once per second */
1963 jump_label_rate_limit(&apic_hw_disabled
, HZ
);
1964 jump_label_rate_limit(&apic_sw_disabled
, HZ
);