3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <linux/atomic.h>
37 #include <linux/jump_label.h>
38 #include "kvm_cache_regs.h"
45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #define mod_64(x, y) ((x) % (y))
55 #define APIC_BUS_CYCLE_NS 1
57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58 #define apic_debug(fmt, arg...)
60 #define APIC_LVT_NUM 6
61 /* 14 is the version for Xeon and Pentium 8.4.8*/
62 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63 #define LAPIC_MMIO_LENGTH (1 << 12)
64 /* followed define is not in apicdef.h */
65 #define APIC_SHORT_MASK 0xc0000
66 #define APIC_DEST_NOSHORT 0x0
67 #define APIC_DEST_MASK 0x800
68 #define MAX_APIC_VECTOR 256
69 #define APIC_VECTORS_PER_REG 32
71 #define APIC_BROADCAST 0xFF
72 #define X2APIC_BROADCAST 0xFFFFFFFFul
74 #define VEC_POS(v) ((v) & (32 - 1))
75 #define REG_POS(v) (((v) >> 5) << 4)
77 static inline void apic_set_reg(struct kvm_lapic
*apic
, int reg_off
, u32 val
)
79 *((u32
*) (apic
->regs
+ reg_off
)) = val
;
82 static inline int apic_test_vector(int vec
, void *bitmap
)
84 return test_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
87 bool kvm_apic_pending_eoi(struct kvm_vcpu
*vcpu
, int vector
)
89 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
91 return apic_test_vector(vector
, apic
->regs
+ APIC_ISR
) ||
92 apic_test_vector(vector
, apic
->regs
+ APIC_IRR
);
95 static inline void apic_set_vector(int vec
, void *bitmap
)
97 set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
100 static inline void apic_clear_vector(int vec
, void *bitmap
)
102 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
105 static inline int __apic_test_and_set_vector(int vec
, void *bitmap
)
107 return __test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
110 static inline int __apic_test_and_clear_vector(int vec
, void *bitmap
)
112 return __test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
115 struct static_key_deferred apic_hw_disabled __read_mostly
;
116 struct static_key_deferred apic_sw_disabled __read_mostly
;
118 static inline int apic_enabled(struct kvm_lapic
*apic
)
120 return kvm_apic_sw_enabled(apic
) && kvm_apic_hw_enabled(apic
);
124 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
127 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
128 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130 static inline int kvm_apic_id(struct kvm_lapic
*apic
)
132 return (kvm_apic_get_reg(apic
, APIC_ID
) >> 24) & 0xff;
135 #define KVM_X2APIC_CID_BITS 0
137 static void recalculate_apic_map(struct kvm
*kvm
)
139 struct kvm_apic_map
*new, *old
= NULL
;
140 struct kvm_vcpu
*vcpu
;
143 new = kzalloc(sizeof(struct kvm_apic_map
), GFP_KERNEL
);
145 mutex_lock(&kvm
->arch
.apic_map_lock
);
151 /* flat mode is default */
154 new->lid_mask
= 0xff;
155 new->broadcast
= APIC_BROADCAST
;
157 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
158 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
160 if (!kvm_apic_present(vcpu
))
163 if (apic_x2apic_mode(apic
)) {
166 new->cid_mask
= (1 << KVM_X2APIC_CID_BITS
) - 1;
167 new->lid_mask
= 0xffff;
168 new->broadcast
= X2APIC_BROADCAST
;
169 } else if (kvm_apic_get_reg(apic
, APIC_LDR
)) {
170 if (kvm_apic_get_reg(apic
, APIC_DFR
) ==
178 new->lid_mask
= 0xff;
183 * All APICs have to be configured in the same mode by an OS.
184 * We take advatage of this while building logical id loockup
185 * table. After reset APICs are in software disabled mode, so if
186 * we find apic with different setting we assume this is the mode
187 * OS wants all apics to be in; build lookup table accordingly.
189 if (kvm_apic_sw_enabled(apic
))
193 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
194 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
198 new->phys_map
[kvm_apic_id(apic
)] = apic
;
200 ldr
= kvm_apic_get_reg(apic
, APIC_LDR
);
201 cid
= apic_cluster_id(new, ldr
);
202 lid
= apic_logical_id(new, ldr
);
205 new->logical_map
[cid
][ffs(lid
) - 1] = apic
;
208 old
= rcu_dereference_protected(kvm
->arch
.apic_map
,
209 lockdep_is_held(&kvm
->arch
.apic_map_lock
));
210 rcu_assign_pointer(kvm
->arch
.apic_map
, new);
211 mutex_unlock(&kvm
->arch
.apic_map_lock
);
216 kvm_vcpu_request_scan_ioapic(kvm
);
219 static inline void apic_set_spiv(struct kvm_lapic
*apic
, u32 val
)
221 bool enabled
= val
& APIC_SPIV_APIC_ENABLED
;
223 apic_set_reg(apic
, APIC_SPIV
, val
);
225 if (enabled
!= apic
->sw_enabled
) {
226 apic
->sw_enabled
= enabled
;
228 static_key_slow_dec_deferred(&apic_sw_disabled
);
229 recalculate_apic_map(apic
->vcpu
->kvm
);
231 static_key_slow_inc(&apic_sw_disabled
.key
);
235 static inline void kvm_apic_set_id(struct kvm_lapic
*apic
, u8 id
)
237 apic_set_reg(apic
, APIC_ID
, id
<< 24);
238 recalculate_apic_map(apic
->vcpu
->kvm
);
241 static inline void kvm_apic_set_ldr(struct kvm_lapic
*apic
, u32 id
)
243 apic_set_reg(apic
, APIC_LDR
, id
);
244 recalculate_apic_map(apic
->vcpu
->kvm
);
247 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
249 return !(kvm_apic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
252 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
254 return kvm_apic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
257 static inline int apic_lvtt_oneshot(struct kvm_lapic
*apic
)
259 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_ONESHOT
;
262 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
264 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_PERIODIC
;
267 static inline int apic_lvtt_tscdeadline(struct kvm_lapic
*apic
)
269 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_TSCDEADLINE
;
272 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
274 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
277 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
279 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
280 struct kvm_cpuid_entry2
*feat
;
281 u32 v
= APIC_VERSION
;
283 if (!kvm_vcpu_has_lapic(vcpu
))
286 feat
= kvm_find_cpuid_entry(apic
->vcpu
, 0x1, 0);
287 if (feat
&& (feat
->ecx
& (1 << (X86_FEATURE_X2APIC
& 31))))
288 v
|= APIC_LVR_DIRECTED_EOI
;
289 apic_set_reg(apic
, APIC_LVR
, v
);
292 static const unsigned int apic_lvt_mask
[APIC_LVT_NUM
] = {
293 LVT_MASK
, /* part LVTT mask, timer mode mask added at runtime */
294 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
295 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
296 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
297 LVT_MASK
/* LVTERR */
300 static int find_highest_vector(void *bitmap
)
305 for (vec
= MAX_APIC_VECTOR
- APIC_VECTORS_PER_REG
;
306 vec
>= 0; vec
-= APIC_VECTORS_PER_REG
) {
307 reg
= bitmap
+ REG_POS(vec
);
309 return fls(*reg
) - 1 + vec
;
315 static u8
count_vectors(void *bitmap
)
321 for (vec
= 0; vec
< MAX_APIC_VECTOR
; vec
+= APIC_VECTORS_PER_REG
) {
322 reg
= bitmap
+ REG_POS(vec
);
323 count
+= hweight32(*reg
);
329 void kvm_apic_update_irr(struct kvm_vcpu
*vcpu
, u32
*pir
)
332 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
334 for (i
= 0; i
<= 7; i
++) {
335 pir_val
= xchg(&pir
[i
], 0);
337 *((u32
*)(apic
->regs
+ APIC_IRR
+ i
* 0x10)) |= pir_val
;
340 EXPORT_SYMBOL_GPL(kvm_apic_update_irr
);
342 static inline void apic_set_irr(int vec
, struct kvm_lapic
*apic
)
344 apic_set_vector(vec
, apic
->regs
+ APIC_IRR
);
346 * irr_pending must be true if any interrupt is pending; set it after
347 * APIC_IRR to avoid race with apic_clear_irr
349 apic
->irr_pending
= true;
352 static inline int apic_search_irr(struct kvm_lapic
*apic
)
354 return find_highest_vector(apic
->regs
+ APIC_IRR
);
357 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
362 * Note that irr_pending is just a hint. It will be always
363 * true with virtual interrupt delivery enabled.
365 if (!apic
->irr_pending
)
368 kvm_x86_ops
->sync_pir_to_irr(apic
->vcpu
);
369 result
= apic_search_irr(apic
);
370 ASSERT(result
== -1 || result
>= 16);
375 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
377 struct kvm_vcpu
*vcpu
;
381 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
))) {
382 /* try to update RVI */
383 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
384 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
386 apic
->irr_pending
= false;
387 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
388 if (apic_search_irr(apic
) != -1)
389 apic
->irr_pending
= true;
393 static inline void apic_set_isr(int vec
, struct kvm_lapic
*apic
)
395 struct kvm_vcpu
*vcpu
;
397 if (__apic_test_and_set_vector(vec
, apic
->regs
+ APIC_ISR
))
403 * With APIC virtualization enabled, all caching is disabled
404 * because the processor can modify ISR under the hood. Instead
407 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
)))
408 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, vec
);
411 BUG_ON(apic
->isr_count
> MAX_APIC_VECTOR
);
413 * ISR (in service register) bit is set when injecting an interrupt.
414 * The highest vector is injected. Thus the latest bit set matches
415 * the highest bit in ISR.
417 apic
->highest_isr_cache
= vec
;
421 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
426 * Note that isr_count is always 1, and highest_isr_cache
427 * is always -1, with APIC virtualization enabled.
429 if (!apic
->isr_count
)
431 if (likely(apic
->highest_isr_cache
!= -1))
432 return apic
->highest_isr_cache
;
434 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
435 ASSERT(result
== -1 || result
>= 16);
440 static inline void apic_clear_isr(int vec
, struct kvm_lapic
*apic
)
442 struct kvm_vcpu
*vcpu
;
443 if (!__apic_test_and_clear_vector(vec
, apic
->regs
+ APIC_ISR
))
449 * We do get here for APIC virtualization enabled if the guest
450 * uses the Hyper-V APIC enlightenment. In this case we may need
451 * to trigger a new interrupt delivery by writing the SVI field;
452 * on the other hand isr_count and highest_isr_cache are unused
453 * and must be left alone.
455 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
)))
456 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
,
457 apic_find_highest_isr(apic
));
460 BUG_ON(apic
->isr_count
< 0);
461 apic
->highest_isr_cache
= -1;
465 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
469 /* This may race with setting of irr in __apic_accept_irq() and
470 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
471 * will cause vmexit immediately and the value will be recalculated
472 * on the next vmentry.
474 if (!kvm_vcpu_has_lapic(vcpu
))
476 highest_irr
= apic_find_highest_irr(vcpu
->arch
.apic
);
481 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
482 int vector
, int level
, int trig_mode
,
483 unsigned long *dest_map
);
485 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
,
486 unsigned long *dest_map
)
488 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
490 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
491 irq
->level
, irq
->trig_mode
, dest_map
);
494 static int pv_eoi_put_user(struct kvm_vcpu
*vcpu
, u8 val
)
497 return kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, &val
,
501 static int pv_eoi_get_user(struct kvm_vcpu
*vcpu
, u8
*val
)
504 return kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, val
,
508 static inline bool pv_eoi_enabled(struct kvm_vcpu
*vcpu
)
510 return vcpu
->arch
.pv_eoi
.msr_val
& KVM_MSR_ENABLED
;
513 static bool pv_eoi_get_pending(struct kvm_vcpu
*vcpu
)
516 if (pv_eoi_get_user(vcpu
, &val
) < 0)
517 apic_debug("Can't read EOI MSR value: 0x%llx\n",
518 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
522 static void pv_eoi_set_pending(struct kvm_vcpu
*vcpu
)
524 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_ENABLED
) < 0) {
525 apic_debug("Can't set EOI MSR value: 0x%llx\n",
526 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
529 __set_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
532 static void pv_eoi_clr_pending(struct kvm_vcpu
*vcpu
)
534 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_DISABLED
) < 0) {
535 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
536 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
539 __clear_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
542 void kvm_apic_update_tmr(struct kvm_vcpu
*vcpu
, u32
*tmr
)
544 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
547 for (i
= 0; i
< 8; i
++)
548 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, tmr
[i
]);
551 static void apic_update_ppr(struct kvm_lapic
*apic
)
553 u32 tpr
, isrv
, ppr
, old_ppr
;
556 old_ppr
= kvm_apic_get_reg(apic
, APIC_PROCPRI
);
557 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
);
558 isr
= apic_find_highest_isr(apic
);
559 isrv
= (isr
!= -1) ? isr
: 0;
561 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
566 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
567 apic
, ppr
, isr
, isrv
);
569 if (old_ppr
!= ppr
) {
570 apic_set_reg(apic
, APIC_PROCPRI
, ppr
);
572 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
576 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
578 apic_set_reg(apic
, APIC_TASKPRI
, tpr
);
579 apic_update_ppr(apic
);
582 static int kvm_apic_broadcast(struct kvm_lapic
*apic
, u32 dest
)
584 return dest
== (apic_x2apic_mode(apic
) ?
585 X2APIC_BROADCAST
: APIC_BROADCAST
);
588 int kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u32 dest
)
590 return kvm_apic_id(apic
) == dest
|| kvm_apic_broadcast(apic
, dest
);
593 int kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u32 mda
)
598 if (kvm_apic_broadcast(apic
, mda
))
601 if (apic_x2apic_mode(apic
)) {
602 logical_id
= kvm_apic_get_reg(apic
, APIC_LDR
);
603 return logical_id
& mda
;
606 logical_id
= GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic
, APIC_LDR
));
608 switch (kvm_apic_get_reg(apic
, APIC_DFR
)) {
610 if (logical_id
& mda
)
613 case APIC_DFR_CLUSTER
:
614 if (((logical_id
>> 4) == (mda
>> 0x4))
615 && (logical_id
& mda
& 0xf))
619 apic_debug("Bad DFR vcpu %d: %08x\n",
620 apic
->vcpu
->vcpu_id
, kvm_apic_get_reg(apic
, APIC_DFR
));
627 int kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
628 int short_hand
, unsigned int dest
, int dest_mode
)
631 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
633 apic_debug("target %p, source %p, dest 0x%x, "
634 "dest_mode 0x%x, short_hand 0x%x\n",
635 target
, source
, dest
, dest_mode
, short_hand
);
638 switch (short_hand
) {
639 case APIC_DEST_NOSHORT
:
642 result
= kvm_apic_match_physical_addr(target
, dest
);
645 result
= kvm_apic_match_logical_addr(target
, dest
);
648 result
= (target
== source
);
650 case APIC_DEST_ALLINC
:
653 case APIC_DEST_ALLBUT
:
654 result
= (target
!= source
);
657 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
665 bool kvm_irq_delivery_to_apic_fast(struct kvm
*kvm
, struct kvm_lapic
*src
,
666 struct kvm_lapic_irq
*irq
, int *r
, unsigned long *dest_map
)
668 struct kvm_apic_map
*map
;
669 unsigned long bitmap
= 1;
670 struct kvm_lapic
**dst
;
676 if (irq
->shorthand
== APIC_DEST_SELF
) {
677 *r
= kvm_apic_set_irq(src
->vcpu
, irq
, dest_map
);
685 map
= rcu_dereference(kvm
->arch
.apic_map
);
690 if (irq
->dest_id
== map
->broadcast
)
693 if (irq
->dest_mode
== 0) { /* physical mode */
694 if (irq
->delivery_mode
== APIC_DM_LOWEST
)
696 dst
= &map
->phys_map
[irq
->dest_id
& 0xff];
698 u32 mda
= irq
->dest_id
<< (32 - map
->ldr_bits
);
700 dst
= map
->logical_map
[apic_cluster_id(map
, mda
)];
702 bitmap
= apic_logical_id(map
, mda
);
704 if (irq
->delivery_mode
== APIC_DM_LOWEST
) {
706 for_each_set_bit(i
, &bitmap
, 16) {
711 else if (kvm_apic_compare_prio(dst
[i
]->vcpu
, dst
[l
]->vcpu
) < 0)
715 bitmap
= (l
>= 0) ? 1 << l
: 0;
719 for_each_set_bit(i
, &bitmap
, 16) {
724 *r
+= kvm_apic_set_irq(dst
[i
]->vcpu
, irq
, dest_map
);
734 * Add a pending IRQ into lapic.
735 * Return 1 if successfully added and 0 if discarded.
737 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
738 int vector
, int level
, int trig_mode
,
739 unsigned long *dest_map
)
742 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
744 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
746 switch (delivery_mode
) {
748 vcpu
->arch
.apic_arb_prio
++;
750 /* FIXME add logic for vcpu on reset */
751 if (unlikely(!apic_enabled(apic
)))
757 __set_bit(vcpu
->vcpu_id
, dest_map
);
759 if (kvm_x86_ops
->deliver_posted_interrupt
)
760 kvm_x86_ops
->deliver_posted_interrupt(vcpu
, vector
);
762 apic_set_irr(vector
, apic
);
764 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
771 vcpu
->arch
.pv
.pv_unhalted
= 1;
772 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
777 apic_debug("Ignoring guest SMI\n");
782 kvm_inject_nmi(vcpu
);
787 if (!trig_mode
|| level
) {
789 /* assumes that there are only KVM_APIC_INIT/SIPI */
790 apic
->pending_events
= (1UL << KVM_APIC_INIT
);
791 /* make sure pending_events is visible before sending
794 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
797 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
802 case APIC_DM_STARTUP
:
803 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
804 vcpu
->vcpu_id
, vector
);
806 apic
->sipi_vector
= vector
;
807 /* make sure sipi_vector is visible for the receiver */
809 set_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
810 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
816 * Should only be called by kvm_apic_local_deliver() with LVT0,
817 * before NMI watchdog was enabled. Already handled by
818 * kvm_apic_accept_pic_intr().
823 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
830 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
832 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
835 static void kvm_ioapic_send_eoi(struct kvm_lapic
*apic
, int vector
)
837 if (!(kvm_apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_DIRECTED_EOI
) &&
838 kvm_ioapic_handles_vector(apic
->vcpu
->kvm
, vector
)) {
840 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
))
841 trigger_mode
= IOAPIC_LEVEL_TRIG
;
843 trigger_mode
= IOAPIC_EDGE_TRIG
;
844 kvm_ioapic_update_eoi(apic
->vcpu
, vector
, trigger_mode
);
848 static int apic_set_eoi(struct kvm_lapic
*apic
)
850 int vector
= apic_find_highest_isr(apic
);
852 trace_kvm_eoi(apic
, vector
);
855 * Not every write EOI will has corresponding ISR,
856 * one example is when Kernel check timer on setup_IO_APIC
861 apic_clear_isr(vector
, apic
);
862 apic_update_ppr(apic
);
864 kvm_ioapic_send_eoi(apic
, vector
);
865 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
870 * this interface assumes a trap-like exit, which has already finished
871 * desired side effect including vISR and vPPR update.
873 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu
*vcpu
, int vector
)
875 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
877 trace_kvm_eoi(apic
, vector
);
879 kvm_ioapic_send_eoi(apic
, vector
);
880 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
882 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated
);
884 static void apic_send_ipi(struct kvm_lapic
*apic
)
886 u32 icr_low
= kvm_apic_get_reg(apic
, APIC_ICR
);
887 u32 icr_high
= kvm_apic_get_reg(apic
, APIC_ICR2
);
888 struct kvm_lapic_irq irq
;
890 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
891 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
892 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
893 irq
.level
= icr_low
& APIC_INT_ASSERT
;
894 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
895 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
896 if (apic_x2apic_mode(apic
))
897 irq
.dest_id
= icr_high
;
899 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
901 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
903 apic_debug("icr_high 0x%x, icr_low 0x%x, "
904 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
905 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
906 icr_high
, icr_low
, irq
.shorthand
, irq
.dest_id
,
907 irq
.trig_mode
, irq
.level
, irq
.dest_mode
, irq
.delivery_mode
,
910 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
, NULL
);
913 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
919 ASSERT(apic
!= NULL
);
921 /* if initial count is 0, current count should also be 0 */
922 if (kvm_apic_get_reg(apic
, APIC_TMICT
) == 0 ||
923 apic
->lapic_timer
.period
== 0)
926 remaining
= hrtimer_get_remaining(&apic
->lapic_timer
.timer
);
927 if (ktime_to_ns(remaining
) < 0)
928 remaining
= ktime_set(0, 0);
930 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
931 tmcct
= div64_u64(ns
,
932 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
937 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
939 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
940 struct kvm_run
*run
= vcpu
->run
;
942 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS
, vcpu
);
943 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
944 run
->tpr_access
.is_write
= write
;
947 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
949 if (apic
->vcpu
->arch
.tpr_access_reporting
)
950 __report_tpr_access(apic
, write
);
953 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
957 if (offset
>= LAPIC_MMIO_LENGTH
)
962 if (apic_x2apic_mode(apic
))
963 val
= kvm_apic_id(apic
);
965 val
= kvm_apic_id(apic
) << 24;
968 apic_debug("Access APIC ARBPRI register which is for P6\n");
971 case APIC_TMCCT
: /* Timer CCR */
972 if (apic_lvtt_tscdeadline(apic
))
975 val
= apic_get_tmcct(apic
);
978 apic_update_ppr(apic
);
979 val
= kvm_apic_get_reg(apic
, offset
);
982 report_tpr_access(apic
, false);
985 val
= kvm_apic_get_reg(apic
, offset
);
992 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
994 return container_of(dev
, struct kvm_lapic
, dev
);
997 static int apic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
1000 unsigned char alignment
= offset
& 0xf;
1002 /* this bitmask has a bit cleared for each reserved register */
1003 static const u64 rmask
= 0x43ff01ffffffe70cULL
;
1005 if ((alignment
+ len
) > 4) {
1006 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1011 if (offset
> 0x3f0 || !(rmask
& (1ULL << (offset
>> 4)))) {
1012 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1017 result
= __apic_read(apic
, offset
& ~0xf);
1019 trace_kvm_apic_read(offset
, result
);
1025 memcpy(data
, (char *)&result
+ alignment
, len
);
1028 printk(KERN_ERR
"Local APIC read with len = %x, "
1029 "should be 1,2, or 4 instead\n", len
);
1035 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
1037 return kvm_apic_hw_enabled(apic
) &&
1038 addr
>= apic
->base_address
&&
1039 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
1042 static int apic_mmio_read(struct kvm_io_device
*this,
1043 gpa_t address
, int len
, void *data
)
1045 struct kvm_lapic
*apic
= to_lapic(this);
1046 u32 offset
= address
- apic
->base_address
;
1048 if (!apic_mmio_in_range(apic
, address
))
1051 apic_reg_read(apic
, offset
, len
, data
);
1056 static void update_divide_count(struct kvm_lapic
*apic
)
1058 u32 tmp1
, tmp2
, tdcr
;
1060 tdcr
= kvm_apic_get_reg(apic
, APIC_TDCR
);
1062 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
1063 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
1065 apic_debug("timer divide count is 0x%x\n",
1066 apic
->divide_count
);
1069 static void apic_timer_expired(struct kvm_lapic
*apic
)
1071 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1072 wait_queue_head_t
*q
= &vcpu
->wq
;
1075 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1078 if (atomic_read(&apic
->lapic_timer
.pending
))
1081 atomic_inc(&apic
->lapic_timer
.pending
);
1082 /* FIXME: this code should not know anything about vcpus */
1083 kvm_make_request(KVM_REQ_PENDING_TIMER
, vcpu
);
1085 if (waitqueue_active(q
))
1086 wake_up_interruptible(q
);
1089 static void start_apic_timer(struct kvm_lapic
*apic
)
1092 atomic_set(&apic
->lapic_timer
.pending
, 0);
1094 if (apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
)) {
1095 /* lapic timer in oneshot or periodic mode */
1096 now
= apic
->lapic_timer
.timer
.base
->get_time();
1097 apic
->lapic_timer
.period
= (u64
)kvm_apic_get_reg(apic
, APIC_TMICT
)
1098 * APIC_BUS_CYCLE_NS
* apic
->divide_count
;
1100 if (!apic
->lapic_timer
.period
)
1103 * Do not allow the guest to program periodic timers with small
1104 * interval, since the hrtimers are not throttled by the host
1107 if (apic_lvtt_period(apic
)) {
1108 s64 min_period
= min_timer_period_us
* 1000LL;
1110 if (apic
->lapic_timer
.period
< min_period
) {
1111 pr_info_ratelimited(
1112 "kvm: vcpu %i: requested %lld ns "
1113 "lapic timer period limited to %lld ns\n",
1114 apic
->vcpu
->vcpu_id
,
1115 apic
->lapic_timer
.period
, min_period
);
1116 apic
->lapic_timer
.period
= min_period
;
1120 hrtimer_start(&apic
->lapic_timer
.timer
,
1121 ktime_add_ns(now
, apic
->lapic_timer
.period
),
1124 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
1126 "timer initial count 0x%x, period %lldns, "
1127 "expire @ 0x%016" PRIx64
".\n", __func__
,
1128 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
1129 kvm_apic_get_reg(apic
, APIC_TMICT
),
1130 apic
->lapic_timer
.period
,
1131 ktime_to_ns(ktime_add_ns(now
,
1132 apic
->lapic_timer
.period
)));
1133 } else if (apic_lvtt_tscdeadline(apic
)) {
1134 /* lapic timer in tsc deadline mode */
1135 u64 guest_tsc
, tscdeadline
= apic
->lapic_timer
.tscdeadline
;
1137 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1138 unsigned long this_tsc_khz
= vcpu
->arch
.virtual_tsc_khz
;
1139 unsigned long flags
;
1141 if (unlikely(!tscdeadline
|| !this_tsc_khz
))
1144 local_irq_save(flags
);
1146 now
= apic
->lapic_timer
.timer
.base
->get_time();
1147 guest_tsc
= kvm_x86_ops
->read_l1_tsc(vcpu
, native_read_tsc());
1148 if (likely(tscdeadline
> guest_tsc
)) {
1149 ns
= (tscdeadline
- guest_tsc
) * 1000000ULL;
1150 do_div(ns
, this_tsc_khz
);
1151 hrtimer_start(&apic
->lapic_timer
.timer
,
1152 ktime_add_ns(now
, ns
), HRTIMER_MODE_ABS
);
1154 apic_timer_expired(apic
);
1156 local_irq_restore(flags
);
1160 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
1162 int nmi_wd_enabled
= apic_lvt_nmi_mode(kvm_apic_get_reg(apic
, APIC_LVT0
));
1164 if (apic_lvt_nmi_mode(lvt0_val
)) {
1165 if (!nmi_wd_enabled
) {
1166 apic_debug("Receive NMI setting on APIC_LVT0 "
1167 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
1168 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
++;
1170 } else if (nmi_wd_enabled
)
1171 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
--;
1174 static int apic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
1178 trace_kvm_apic_write(reg
, val
);
1181 case APIC_ID
: /* Local APIC ID */
1182 if (!apic_x2apic_mode(apic
))
1183 kvm_apic_set_id(apic
, val
>> 24);
1189 report_tpr_access(apic
, true);
1190 apic_set_tpr(apic
, val
& 0xff);
1198 if (!apic_x2apic_mode(apic
))
1199 kvm_apic_set_ldr(apic
, val
& APIC_LDR_MASK
);
1205 if (!apic_x2apic_mode(apic
)) {
1206 apic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
1207 recalculate_apic_map(apic
->vcpu
->kvm
);
1214 if (kvm_apic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
1215 mask
|= APIC_SPIV_DIRECTED_EOI
;
1216 apic_set_spiv(apic
, val
& mask
);
1217 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
1221 for (i
= 0; i
< APIC_LVT_NUM
; i
++) {
1222 lvt_val
= kvm_apic_get_reg(apic
,
1223 APIC_LVTT
+ 0x10 * i
);
1224 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
1225 lvt_val
| APIC_LVT_MASKED
);
1227 atomic_set(&apic
->lapic_timer
.pending
, 0);
1233 /* No delay here, so we always clear the pending bit */
1234 apic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
1235 apic_send_ipi(apic
);
1239 if (!apic_x2apic_mode(apic
))
1241 apic_set_reg(apic
, APIC_ICR2
, val
);
1245 apic_manage_nmi_watchdog(apic
, val
);
1250 /* TODO: Check vector */
1251 if (!kvm_apic_sw_enabled(apic
))
1252 val
|= APIC_LVT_MASKED
;
1254 val
&= apic_lvt_mask
[(reg
- APIC_LVTT
) >> 4];
1255 apic_set_reg(apic
, reg
, val
);
1260 u32 timer_mode
= val
& apic
->lapic_timer
.timer_mode_mask
;
1262 if (apic
->lapic_timer
.timer_mode
!= timer_mode
) {
1263 apic
->lapic_timer
.timer_mode
= timer_mode
;
1264 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1267 if (!kvm_apic_sw_enabled(apic
))
1268 val
|= APIC_LVT_MASKED
;
1269 val
&= (apic_lvt_mask
[0] | apic
->lapic_timer
.timer_mode_mask
);
1270 apic_set_reg(apic
, APIC_LVTT
, val
);
1275 if (apic_lvtt_tscdeadline(apic
))
1278 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1279 apic_set_reg(apic
, APIC_TMICT
, val
);
1280 start_apic_timer(apic
);
1285 apic_debug("KVM_WRITE:TDCR %x\n", val
);
1286 apic_set_reg(apic
, APIC_TDCR
, val
);
1287 update_divide_count(apic
);
1291 if (apic_x2apic_mode(apic
) && val
!= 0) {
1292 apic_debug("KVM_WRITE:ESR not zero %x\n", val
);
1298 if (apic_x2apic_mode(apic
)) {
1299 apic_reg_write(apic
, APIC_ICR
, 0x40000 | (val
& 0xff));
1308 apic_debug("Local APIC Write to read-only register %x\n", reg
);
1312 static int apic_mmio_write(struct kvm_io_device
*this,
1313 gpa_t address
, int len
, const void *data
)
1315 struct kvm_lapic
*apic
= to_lapic(this);
1316 unsigned int offset
= address
- apic
->base_address
;
1319 if (!apic_mmio_in_range(apic
, address
))
1323 * APIC register must be aligned on 128-bits boundary.
1324 * 32/64/128 bits registers must be accessed thru 32 bits.
1327 if (len
!= 4 || (offset
& 0xf)) {
1328 /* Don't shout loud, $infamous_os would cause only noise. */
1329 apic_debug("apic write: bad size=%d %lx\n", len
, (long)address
);
1335 /* too common printing */
1336 if (offset
!= APIC_EOI
)
1337 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1338 "0x%x\n", __func__
, offset
, len
, val
);
1340 apic_reg_write(apic
, offset
& 0xff0, val
);
1345 void kvm_lapic_set_eoi(struct kvm_vcpu
*vcpu
)
1347 if (kvm_vcpu_has_lapic(vcpu
))
1348 apic_reg_write(vcpu
->arch
.apic
, APIC_EOI
, 0);
1350 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi
);
1352 /* emulate APIC access in a trap manner */
1353 void kvm_apic_write_nodecode(struct kvm_vcpu
*vcpu
, u32 offset
)
1357 /* hw has done the conditional check and inst decode */
1360 apic_reg_read(vcpu
->arch
.apic
, offset
, 4, &val
);
1362 /* TODO: optimize to just emulate side effect w/o one more write */
1363 apic_reg_write(vcpu
->arch
.apic
, offset
, val
);
1365 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode
);
1367 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
1369 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1371 if (!vcpu
->arch
.apic
)
1374 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1376 if (!(vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
))
1377 static_key_slow_dec_deferred(&apic_hw_disabled
);
1379 if (!apic
->sw_enabled
)
1380 static_key_slow_dec_deferred(&apic_sw_disabled
);
1383 free_page((unsigned long)apic
->regs
);
1389 *----------------------------------------------------------------------
1391 *----------------------------------------------------------------------
1394 u64
kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
)
1396 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1398 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1399 apic_lvtt_period(apic
))
1402 return apic
->lapic_timer
.tscdeadline
;
1405 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
, u64 data
)
1407 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1409 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1410 apic_lvtt_period(apic
))
1413 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1414 apic
->lapic_timer
.tscdeadline
= data
;
1415 start_apic_timer(apic
);
1418 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
1420 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1422 if (!kvm_vcpu_has_lapic(vcpu
))
1425 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
1426 | (kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 4));
1429 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
1433 if (!kvm_vcpu_has_lapic(vcpu
))
1436 tpr
= (u64
) kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_TASKPRI
);
1438 return (tpr
& 0xf0) >> 4;
1441 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
1443 u64 old_value
= vcpu
->arch
.apic_base
;
1444 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1447 value
|= MSR_IA32_APICBASE_BSP
;
1448 vcpu
->arch
.apic_base
= value
;
1452 if (!kvm_vcpu_is_bsp(apic
->vcpu
))
1453 value
&= ~MSR_IA32_APICBASE_BSP
;
1454 vcpu
->arch
.apic_base
= value
;
1456 /* update jump label if enable bit changes */
1457 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
) {
1458 if (value
& MSR_IA32_APICBASE_ENABLE
)
1459 static_key_slow_dec_deferred(&apic_hw_disabled
);
1461 static_key_slow_inc(&apic_hw_disabled
.key
);
1462 recalculate_apic_map(vcpu
->kvm
);
1465 if ((old_value
^ value
) & X2APIC_ENABLE
) {
1466 if (value
& X2APIC_ENABLE
) {
1467 u32 id
= kvm_apic_id(apic
);
1468 u32 ldr
= ((id
>> 4) << 16) | (1 << (id
& 0xf));
1469 kvm_apic_set_ldr(apic
, ldr
);
1470 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, true);
1472 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, false);
1475 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
1476 MSR_IA32_APICBASE_BASE
;
1478 if ((value
& MSR_IA32_APICBASE_ENABLE
) &&
1479 apic
->base_address
!= APIC_DEFAULT_PHYS_BASE
)
1480 pr_warn_once("APIC base relocation is unsupported by KVM");
1482 /* with FSB delivery interrupt, we can restart APIC functionality */
1483 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
1484 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
1488 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
)
1490 struct kvm_lapic
*apic
;
1493 apic_debug("%s\n", __func__
);
1496 apic
= vcpu
->arch
.apic
;
1497 ASSERT(apic
!= NULL
);
1499 /* Stop the timer in case it's a reset to an active apic */
1500 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1502 kvm_apic_set_id(apic
, vcpu
->vcpu_id
);
1503 kvm_apic_set_version(apic
->vcpu
);
1505 for (i
= 0; i
< APIC_LVT_NUM
; i
++)
1506 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
1507 apic
->lapic_timer
.timer_mode
= 0;
1508 apic_set_reg(apic
, APIC_LVT0
,
1509 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
1511 apic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
1512 apic_set_spiv(apic
, 0xff);
1513 apic_set_reg(apic
, APIC_TASKPRI
, 0);
1514 kvm_apic_set_ldr(apic
, 0);
1515 apic_set_reg(apic
, APIC_ESR
, 0);
1516 apic_set_reg(apic
, APIC_ICR
, 0);
1517 apic_set_reg(apic
, APIC_ICR2
, 0);
1518 apic_set_reg(apic
, APIC_TDCR
, 0);
1519 apic_set_reg(apic
, APIC_TMICT
, 0);
1520 for (i
= 0; i
< 8; i
++) {
1521 apic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
1522 apic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
1523 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
1525 apic
->irr_pending
= kvm_apic_vid_enabled(vcpu
->kvm
);
1526 apic
->isr_count
= kvm_apic_vid_enabled(vcpu
->kvm
);
1527 apic
->highest_isr_cache
= -1;
1528 update_divide_count(apic
);
1529 atomic_set(&apic
->lapic_timer
.pending
, 0);
1530 if (kvm_vcpu_is_bsp(vcpu
))
1531 kvm_lapic_set_base(vcpu
,
1532 vcpu
->arch
.apic_base
| MSR_IA32_APICBASE_BSP
);
1533 vcpu
->arch
.pv_eoi
.msr_val
= 0;
1534 apic_update_ppr(apic
);
1536 vcpu
->arch
.apic_arb_prio
= 0;
1537 vcpu
->arch
.apic_attention
= 0;
1539 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1540 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
1541 vcpu
, kvm_apic_id(apic
),
1542 vcpu
->arch
.apic_base
, apic
->base_address
);
1546 *----------------------------------------------------------------------
1548 *----------------------------------------------------------------------
1551 static bool lapic_is_periodic(struct kvm_lapic
*apic
)
1553 return apic_lvtt_period(apic
);
1556 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
1558 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1560 if (kvm_vcpu_has_lapic(vcpu
) && apic_enabled(apic
) &&
1561 apic_lvt_enabled(apic
, APIC_LVTT
))
1562 return atomic_read(&apic
->lapic_timer
.pending
);
1567 int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
1569 u32 reg
= kvm_apic_get_reg(apic
, lvt_type
);
1570 int vector
, mode
, trig_mode
;
1572 if (kvm_apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
1573 vector
= reg
& APIC_VECTOR_MASK
;
1574 mode
= reg
& APIC_MODE_MASK
;
1575 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
1576 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
,
1582 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
1584 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1587 kvm_apic_local_deliver(apic
, APIC_LVT0
);
1590 static const struct kvm_io_device_ops apic_mmio_ops
= {
1591 .read
= apic_mmio_read
,
1592 .write
= apic_mmio_write
,
1595 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
1597 struct kvm_timer
*ktimer
= container_of(data
, struct kvm_timer
, timer
);
1598 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
, lapic_timer
);
1600 apic_timer_expired(apic
);
1602 if (lapic_is_periodic(apic
)) {
1603 hrtimer_add_expires_ns(&ktimer
->timer
, ktimer
->period
);
1604 return HRTIMER_RESTART
;
1606 return HRTIMER_NORESTART
;
1609 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
1611 struct kvm_lapic
*apic
;
1613 ASSERT(vcpu
!= NULL
);
1614 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
1616 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
1620 vcpu
->arch
.apic
= apic
;
1622 apic
->regs
= (void *)get_zeroed_page(GFP_KERNEL
);
1624 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
1626 goto nomem_free_apic
;
1630 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
1632 apic
->lapic_timer
.timer
.function
= apic_timer_fn
;
1635 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1636 * thinking that APIC satet has changed.
1638 vcpu
->arch
.apic_base
= MSR_IA32_APICBASE_ENABLE
;
1639 kvm_lapic_set_base(vcpu
,
1640 APIC_DEFAULT_PHYS_BASE
| MSR_IA32_APICBASE_ENABLE
);
1642 static_key_slow_inc(&apic_sw_disabled
.key
); /* sw disabled at reset */
1643 kvm_lapic_reset(vcpu
);
1644 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
1653 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
1655 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1658 if (!kvm_vcpu_has_lapic(vcpu
) || !apic_enabled(apic
))
1661 apic_update_ppr(apic
);
1662 highest_irr
= apic_find_highest_irr(apic
);
1663 if ((highest_irr
== -1) ||
1664 ((highest_irr
& 0xF0) <= kvm_apic_get_reg(apic
, APIC_PROCPRI
)))
1669 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
1671 u32 lvt0
= kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
1674 if (!kvm_apic_hw_enabled(vcpu
->arch
.apic
))
1676 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
1677 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
1682 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
1684 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1686 if (!kvm_vcpu_has_lapic(vcpu
))
1689 if (atomic_read(&apic
->lapic_timer
.pending
) > 0) {
1690 kvm_apic_local_deliver(apic
, APIC_LVTT
);
1691 if (apic_lvtt_tscdeadline(apic
))
1692 apic
->lapic_timer
.tscdeadline
= 0;
1693 atomic_set(&apic
->lapic_timer
.pending
, 0);
1697 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
1699 int vector
= kvm_apic_has_interrupt(vcpu
);
1700 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1706 * We get here even with APIC virtualization enabled, if doing
1707 * nested virtualization and L1 runs with the "acknowledge interrupt
1708 * on exit" mode. Then we cannot inject the interrupt via RVI,
1709 * because the process would deliver it through the IDT.
1712 apic_set_isr(vector
, apic
);
1713 apic_update_ppr(apic
);
1714 apic_clear_irr(vector
, apic
);
1718 void kvm_apic_post_state_restore(struct kvm_vcpu
*vcpu
,
1719 struct kvm_lapic_state
*s
)
1721 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1723 kvm_lapic_set_base(vcpu
, vcpu
->arch
.apic_base
);
1724 /* set SPIV separately to get count of SW disabled APICs right */
1725 apic_set_spiv(apic
, *((u32
*)(s
->regs
+ APIC_SPIV
)));
1726 memcpy(vcpu
->arch
.apic
->regs
, s
->regs
, sizeof *s
);
1727 /* call kvm_apic_set_id() to put apic into apic_map */
1728 kvm_apic_set_id(apic
, kvm_apic_id(apic
));
1729 kvm_apic_set_version(vcpu
);
1731 apic_update_ppr(apic
);
1732 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1733 update_divide_count(apic
);
1734 start_apic_timer(apic
);
1735 apic
->irr_pending
= true;
1736 apic
->isr_count
= kvm_apic_vid_enabled(vcpu
->kvm
) ?
1737 1 : count_vectors(apic
->regs
+ APIC_ISR
);
1738 apic
->highest_isr_cache
= -1;
1739 if (kvm_x86_ops
->hwapic_irr_update
)
1740 kvm_x86_ops
->hwapic_irr_update(vcpu
,
1741 apic_find_highest_irr(apic
));
1742 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, apic_find_highest_isr(apic
));
1743 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1744 kvm_rtc_eoi_tracking_restore_one(vcpu
);
1747 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
1749 struct hrtimer
*timer
;
1751 if (!kvm_vcpu_has_lapic(vcpu
))
1754 timer
= &vcpu
->arch
.apic
->lapic_timer
.timer
;
1755 if (hrtimer_cancel(timer
))
1756 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS
);
1760 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1762 * Detect whether guest triggered PV EOI since the
1763 * last entry. If yes, set EOI on guests's behalf.
1764 * Clear PV EOI in guest memory in any case.
1766 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu
*vcpu
,
1767 struct kvm_lapic
*apic
)
1772 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1773 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1775 * KVM_APIC_PV_EOI_PENDING is unset:
1776 * -> host disabled PV EOI.
1777 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1778 * -> host enabled PV EOI, guest did not execute EOI yet.
1779 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1780 * -> host enabled PV EOI, guest executed EOI.
1782 BUG_ON(!pv_eoi_enabled(vcpu
));
1783 pending
= pv_eoi_get_pending(vcpu
);
1785 * Clear pending bit in any case: it will be set again on vmentry.
1786 * While this might not be ideal from performance point of view,
1787 * this makes sure pv eoi is only enabled when we know it's safe.
1789 pv_eoi_clr_pending(vcpu
);
1792 vector
= apic_set_eoi(apic
);
1793 trace_kvm_pv_eoi(apic
, vector
);
1796 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
1800 if (test_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
))
1801 apic_sync_pv_eoi_from_guest(vcpu
, vcpu
->arch
.apic
);
1803 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1806 kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1809 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
1813 * apic_sync_pv_eoi_to_guest - called before vmentry
1815 * Detect whether it's safe to enable PV EOI and
1818 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu
*vcpu
,
1819 struct kvm_lapic
*apic
)
1821 if (!pv_eoi_enabled(vcpu
) ||
1822 /* IRR set or many bits in ISR: could be nested. */
1823 apic
->irr_pending
||
1824 /* Cache not set: could be safe but we don't bother. */
1825 apic
->highest_isr_cache
== -1 ||
1826 /* Need EOI to update ioapic. */
1827 kvm_ioapic_handles_vector(vcpu
->kvm
, apic
->highest_isr_cache
)) {
1829 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1830 * so we need not do anything here.
1835 pv_eoi_set_pending(apic
->vcpu
);
1838 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
1841 int max_irr
, max_isr
;
1842 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1844 apic_sync_pv_eoi_to_guest(vcpu
, apic
);
1846 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1849 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
1850 max_irr
= apic_find_highest_irr(apic
);
1853 max_isr
= apic_find_highest_isr(apic
);
1856 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
1858 kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1862 int kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
1865 if (kvm_gfn_to_hva_cache_init(vcpu
->kvm
,
1866 &vcpu
->arch
.apic
->vapic_cache
,
1867 vapic_addr
, sizeof(u32
)))
1869 __set_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1871 __clear_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1874 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
1878 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
1880 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1881 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
1883 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1886 if (reg
== APIC_ICR2
)
1889 /* if this is ICR write vector before command */
1890 if (reg
== APIC_ICR
)
1891 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1892 return apic_reg_write(apic
, reg
, (u32
)data
);
1895 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
1897 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1898 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
1900 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1903 if (reg
== APIC_DFR
|| reg
== APIC_ICR2
) {
1904 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1909 if (apic_reg_read(apic
, reg
, 4, &low
))
1911 if (reg
== APIC_ICR
)
1912 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1914 *data
= (((u64
)high
) << 32) | low
;
1919 int kvm_hv_vapic_msr_write(struct kvm_vcpu
*vcpu
, u32 reg
, u64 data
)
1921 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1923 if (!kvm_vcpu_has_lapic(vcpu
))
1926 /* if this is ICR write vector before command */
1927 if (reg
== APIC_ICR
)
1928 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1929 return apic_reg_write(apic
, reg
, (u32
)data
);
1932 int kvm_hv_vapic_msr_read(struct kvm_vcpu
*vcpu
, u32 reg
, u64
*data
)
1934 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1937 if (!kvm_vcpu_has_lapic(vcpu
))
1940 if (apic_reg_read(apic
, reg
, 4, &low
))
1942 if (reg
== APIC_ICR
)
1943 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1945 *data
= (((u64
)high
) << 32) | low
;
1950 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu
*vcpu
, u64 data
)
1952 u64 addr
= data
& ~KVM_MSR_ENABLED
;
1953 if (!IS_ALIGNED(addr
, 4))
1956 vcpu
->arch
.pv_eoi
.msr_val
= data
;
1957 if (!pv_eoi_enabled(vcpu
))
1959 return kvm_gfn_to_hva_cache_init(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
,
1963 void kvm_apic_accept_events(struct kvm_vcpu
*vcpu
)
1965 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1969 if (!kvm_vcpu_has_lapic(vcpu
) || !apic
->pending_events
)
1972 pe
= xchg(&apic
->pending_events
, 0);
1974 if (test_bit(KVM_APIC_INIT
, &pe
)) {
1975 kvm_lapic_reset(vcpu
);
1976 kvm_vcpu_reset(vcpu
);
1977 if (kvm_vcpu_is_bsp(apic
->vcpu
))
1978 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
1980 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
1982 if (test_bit(KVM_APIC_SIPI
, &pe
) &&
1983 vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
1984 /* evaluate pending_events before reading the vector */
1986 sipi_vector
= apic
->sipi_vector
;
1987 apic_debug("vcpu %d received sipi with vector # %x\n",
1988 vcpu
->vcpu_id
, sipi_vector
);
1989 kvm_vcpu_deliver_sipi_vector(vcpu
, sipi_vector
);
1990 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
1994 void kvm_lapic_init(void)
1996 /* do not patch jump label more than once per second */
1997 jump_label_rate_limit(&apic_hw_disabled
, HZ
);
1998 jump_label_rate_limit(&apic_sw_disabled
, HZ
);